Semiconductor device manufacturing method and manufacturing apparatus

Abstract

This semiconductor device manufacturing method involves: a step for preparing a template substrate having a primary substrate and a mask pattern that is positioned above the primary substrate and that includes a mask part and an opening part; a step for using ELO to form a first semiconductor part on the mask pattern; a step for removing the part of the primary substrate that overlaps the opening in planar view; and a step for removing the part of the first semiconductor part that overlaps with the opening in planar view.

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method of forming a through hole in a sapphire substrate and a GaN buffer layer grown thereon, and extending an electrode that contacts a GaN contact layer through the through hole to the underside of the sapphire substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-45892 Summary of the Invention

[0004] A manufacturing method for a semiconductor device according to the present disclosure includes the steps of preparing a template substrate having a main substrate and a mask pattern located above the main substrate and including a mask portion and an opening, forming a first semiconductor portion on the mask pattern using an ELO method, removing a portion of the main substrate that overlaps with the opening in a planar view, and removing a portion of the first semiconductor portion that overlaps with the opening in a planar view. [Brief description of the drawings]

[0005] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 2] 4 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the embodiment. [Diagram 3] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment of the present invention. [Diagram 5]1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view showing a configuration of an electronic device according to a first embodiment. [Figure 7] 4 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 9] 1A to 1C are plan views showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 10] 1A to 1C are plan views showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 11] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 12] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 13] 1A to 1C are plan views showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 14] 5A to 5C are cross-sectional views showing another example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 5A to 5C are cross-sectional views showing another example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 10 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 17] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] 10A to 10C are cross-sectional views showing another example of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 19] 10A to 10C are cross-sectional views showing another example of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 20] 10 is a flowchart showing another example of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 21] 10A to 10C are cross-sectional views showing another example of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 22]10 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 23] 11A to 11C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Semiconductor Devices] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment. As shown in FIG. 1, a semiconductor device 20 according to this embodiment includes a first semiconductor portion 8 and a second semiconductor portion 9 located in a layer (above) higher than the first semiconductor portion 8 and including an active layer. The first semiconductor portion 8 may be a first semiconductor layer including a nitride semiconductor (e.g., a GaN-based semiconductor), and the second semiconductor portion 9 may be a second semiconductor layer including a nitride semiconductor. The first semiconductor portion 8 includes an upper surface 8a that is a (0001) plane and a lower surface 8b that is a (000-1) plane. The semiconductor device 20 can be configured such that the length of the upper surface 8a in the <11-20> direction is greater than the length of the lower surface 8b in the <11-20> direction. This facilitates the manufacturing process of the semiconductor device 20.

[0007] [Semiconductor device manufacturing] FIG. 2 is a flow chart showing an example of a method for manufacturing a semiconductor device according to this embodiment. FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to this embodiment. In the method for manufacturing a semiconductor device shown in FIG. 2 and FIG. 3, after a step of preparing a template substrate (substrate for ELO growth) 7, a first semiconductor portion 8 is formed on the template substrate 7 including a mask pattern 6 including a mask portion 5 and an opening K by using an ELO method. Next, a step of forming a second semiconductor portion 9 is performed. Thereafter, a step of removing a portion of the main substrate 1 that overlaps with the opening K of the mask pattern 6 in a plan view by etching the main substrate 1 from its back surface is performed. Thereafter, a step of removing a portion of the first semiconductor portion 8 that overlaps with the opening K of the mask pattern 6 in a plan view is performed. This makes it easier to separate the semiconductor device from the template substrate 7. Note that "two members overlap in a plan view" means that "at least a part of one member overlaps with the other member in a plan view (including a perspective plan view) viewed in a normal direction of the main substrate 1".

[0008] Fig. 4 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment. The semiconductor device manufacturing apparatus 70 in Fig. 4 includes a forming unit 72 that forms a first semiconductor portion 8 and a second semiconductor portion 9 on a template substrate 7, a processing unit 73 that performs etching on the main substrate 1 from its back surface, and a control unit 74 that controls the forming unit 72 and the processing unit 73.

[0009] The forming unit 72 may include an MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the forming unit 72 and the processing unit 73 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network. The above-mentioned program and a recording medium on which the above-mentioned program is stored are also included in this embodiment.

[0010] Example 1 (Overall composition) FIG. 5 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment. As shown in FIG. 5, the semiconductor device 20 according to the first embodiment includes a first semiconductor portion 8, a second semiconductor portion 9 located on the first semiconductor portion 8 and including an n-type semiconductor layer 9N, an active layer 9E, and a p-type semiconductor layer 9P, a first electrode E1 located on the p-type semiconductor layer 9P, and a second electrode E2 located on the first semiconductor portion 8. The active layer 9E is, for example, a light-emitting layer. The first electrode E1 is an anode. The second semiconductor portion 9 is provided on the first semiconductor portion 8, but the second semiconductor portion 9 is not formed above a part of the first semiconductor portion 8, and the second electrode E2, which is a cathode, may be provided so as to contact a part of the first semiconductor portion 8.

[0011] The first semiconductor portion 8 includes a nitride semiconductor (for example, a GaN-based semiconductor). The nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include a GaN-based semiconductor, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor that includes gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. In FIG. 5, a GaN-based semiconductor <0001> The Z-direction can be taken as the thickness direction, the c-axis direction, the <11-20> direction (a-axis direction) of the GaN-based semiconductor, and the <1-100> direction (m-axis direction) of the GaN-based semiconductor.

[0012] The first semiconductor portion 8 can be formed by an ELO (Epitaxial Lateral Overgrowth) method. The first semiconductor portion 8 may contain an n-type dopant such as Si. The first semiconductor portion 8 includes an upper surface 8a that is a (0001) plane and a lower surface 8b that is a (000-1) plane. The second semiconductor portion 9 includes an upper surface 9a that is a (0001) plane and a lower surface 9b that is a (000-1) plane.

[0013] In the semiconductor device 20, the length of the upper surface 8a of the first semiconductor portion 8 in the <11-20> direction (X direction) may be greater than the length of the lower surface 8b in the <11-20> direction (X direction). Also, the length of the upper surface 9a of the second semiconductor portion 9 (p-type semiconductor layer 9P) in the <11-20> direction (X direction) may be greater than the length of the lower surface 9b of the second semiconductor portion 9 (n-type semiconductor layer 9N) in the <11-20> direction (X direction). This facilitates the manufacturing process of the semiconductor device 20 (described later).

[0014] Specific examples of the semiconductor device 20 include a light emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, and a transistor (including a power transistor and a high electron mobility transistor).

[0015] [Electronic equipment] FIG. 6 is a cross-sectional view showing the configuration of an electronic device according to the first embodiment. As shown in FIG. 6, a micro LED display 30 (electronic device) includes the above-mentioned semiconductor devices 20 fabricated as a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B. The micro LED display 30 also includes a drive substrate 23 on which these semiconductor devices 20 are mounted, a control circuit 25 for controlling the drive substrate 23, and a driver circuit 29 for driving the semiconductor devices 20. The red micro LED 20R, the green micro LED 20G, and the blue micro LED 20B are mounted on a plurality of pixel circuits 27 of the drive substrate 23 by conductive resin (e.g., anisotropic conductive resin) or the like. A part of the driver circuit 29 may be included in the drive substrate 23.

[0016] Examples of electronic devices include, in addition to the micro LED display 30, display devices, laser emission devices (including Fabry-Perot type and surface emission type), lighting devices, communication devices, information processing devices, sensing devices, power control devices, and the like.

[0017] Fig. 7 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to Example 1. Fig. 8 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to Example 1. Figs. 9 and 10 are plan views illustrating an example of a method for manufacturing a semiconductor device according to Example 1.

[0018] 7 and 8, a step of preparing a template substrate (substrate for ELO growth) 7 is performed. The template substrate 7 includes a main substrate 1, a base portion 4, and a mask pattern 6 in this order, and the mask pattern 6 includes a mask portion 5 and an opening K. Then, a first semiconductor portion 8 is formed on the template substrate 7 using the ELO method. Next, a step of forming a second semiconductor portion 9 and first and second electrodes E1 and E2 is performed. As a result, a semiconductor substrate 10 is formed.

[0019] Thereafter, a process is performed in which the main substrate 1 is etched from its rear surface (deep etching) to remove the portions of the main substrate 1 that overlap with the openings K of the mask pattern 6 in a plan view. Note that before etching the main substrate 1, the thickness of the main substrate 1 may be reduced by polishing the rear surface of the main substrate 1, for example. This reduces the etching depth and improves the etching accuracy.

[0020] Thereafter, using the remaining portion of the main substrate 1 as an etching mask, the portions of the base portion 4, the first semiconductor portion 8, and the second semiconductor portion 9 that overlap the opening portion K of the mask pattern 6 in a plan view are removed to form a trench TY extending in the Y direction. In this step, the joint portion between the base portion 4 (seed portion 3) and the first semiconductor portion 8 is removed. The second semiconductor portion 9 may be partially removed following (continuously with) the partial removal of the first semiconductor portion 8. The etching in this step may be dry etching or wet etching. In the case of dry etching, side etching can be suppressed. Phosphoric acid or a phosphoric acid mixture may be used for the wet etching.

[0021] A GaN-based semiconductor has polar N-face (lower face) and Ga-face (upper face) in the c-axis direction, and has a characteristic that the etching rate from the lower N-face ((000-1) face) is higher than the etching rate from the upper Ga-face ((0001) face). By performing etching (particularly dry etching) from the rear face (lower face) of the first semiconductor portion 8, the etching speed and accuracy can be improved. Note that the rear face (lower face) of the first semiconductor portion 8 is not limited to a polar face. It may be a semi-polar face tilted from the c-face. It may be a combination of a polar face and a semi-polar face. In FIG. 9, a trench TY extending in the Y-direction is formed, but as shown in FIG. 10, a trench TX extending in the X-direction may be formed in the same process as the formation of the trench TY.

[0022] Thereafter, a process of separating the template substrate 7 from the first semiconductor portion 8 is performed. Since the adhesive force between the mask portion 5 and the first semiconductor portion 8 is weak (mainly due to von der Waals force), for example, the first and second semiconductor portions 8 and 9 can be peeled off from the mask portion 5 while they are attached to a flexible adhesive sheet. In other words, the template substrate 7 and the first semiconductor portion 8 are easily separated. As a result, the first and second semiconductor portions 8 and 9 are separated into individual pieces, and a plurality of semiconductor devices 20 are formed. Since the trench TY has a tapered shape that tapers upward (from the main substrate 1 to the mask pattern 6), in the semiconductor device 20, the length of the first semiconductor portion upper surface 8a in the <11-20> direction (X direction) is greater than the length of the first semiconductor portion lower surface 8b in the <11-20> direction (X direction). Moreover, the length of the second semiconductor portion upper surface 9a in the <11-20> direction (X direction) is greater than the length of the second semiconductor portion lower surface 9b in the <11-20> direction (X direction).

[0023] 11 and 12 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. The step of removing the portion of the first semiconductor portion 8 that overlaps with the opening K of the mask pattern 6 in a plan view may be performed in a state in which the main substrate 1 is vertically upward as shown in FIG. 11. In that case, as shown in FIG. 12, an anchor film AF (e.g., an inorganic insulating film such as a silicon oxide film or a silicon nitride film) may be formed in contact with the upper surface ((0001) surface) and side surface of the first semiconductor portion 8 and the mask portion 5. This reduces the risk that the first semiconductor portion 8 will fall off the mask pattern 6 when the joint portion between the first semiconductor portion 8 and the base portion 4 is removed.

[0024] Fig. 13 is a plan view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. In Figs. 8 and 9 and the like, the first and second electrodes E1 and E2 are arranged in the X direction, but this is not limiting. As shown in Fig. 13, the first and second electrodes E1 and E2 may be arranged in the Y direction. The area of ​​the first electrode E1 may be larger than that of the second electrode E2.

[0025] (Main board) The main substrate 1 may be a heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor. Examples of heterogeneous substrates include a single crystal silicon (Si) substrate, a sapphire (Al2O3) substrate, and a silicon carbide (SiC, silicon carbide) substrate. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, and the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any main substrate and surface orientation that allows the first semiconductor portion 8 to be grown by the ELO method may be used. The main substrate 1 is not limited to a heterogeneous substrate, and may be a GaN substrate (bulk).

[0026] (Base part) As the base portion 4, as shown in Fig. 8, a buffer portion 2 and a seed portion 3 can be provided in this order from the main substrate 1 side. The base portion 4 may be a base layer. The buffer portion 2 may be a buffer layer. The seed portion 3 may be a seed layer.

[0027] The buffer section 2 has a function of reducing the melting of the main substrate 1 and the seed section 3 due to direct contact between them. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed section 3, the two (the main substrate and the seed layer) melt together, so by providing the buffer section 2 including at least one of an AlN layer and a SiC (silicon carbide) layer, for example, the melting can be reduced.

[0028] An AlN layer, which is an example of the buffer portion 2, can be formed to a thickness of about 10 nm to about 5 μm using, for example, an MOCVD apparatus. The buffer portion 2 may have at least one of the effects of increasing the crystallinity of the seed portion 3 and alleviating the internal stress of the first semiconductor portion 8 (alleviating warpage of the semiconductor substrate 10). When a main substrate 1 that does not melt with the seed portion 3 is used, a configuration without providing the buffer portion 2 is also possible.

[0029] At least one of the buffer portion 2 (for example, aluminum nitride) and the seed portion 3 (for example, GaN-based semiconductor) can be deposited using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).

[0030] (Mask pattern) The opening K of the mask pattern 6 functions as a growth initiation hole that exposes the seed portion 3 and initiates the growth of the first semiconductor portion 8, and the mask portion 5 functions as a selective growth mask that causes the first semiconductor portion 8 to grow laterally. The mask pattern 6 may be a mask layer 6. The opening K may be a portion where the mask portion 5 is not present, and the opening K does not have to be surrounded by the mask portion 5.

[0031] The mask portion 5 may be, for example, a single layer film including any one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000°C or higher), or a laminated film including at least two of these.

[0032] For example, a silicon oxide film having a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed on the entire surface of the base portion 4 by sputtering, and a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned by photolithography to form a resist having a plurality of stripe-shaped openings. Parts of the silicon oxide film are then removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings (including K), and the resist is removed by organic cleaning to form the mask pattern 6.

[0033] The openings K have an elongated shape (slit shape) and are periodically arranged in the a-axis direction (X direction) of the first semiconductor portion 8. The width of the openings K is about 0.1 μm to 20 μm. The smaller the width of each opening K, the smaller the number of threading dislocations propagating from each opening K to the first semiconductor portion 8. Also, the low defect portion in the first semiconductor portion 8 can be enlarged.

[0034] A small amount of silicon oxide film may decompose and evaporate during the formation of the first semiconductor portion 8 and be incorporated into the first semiconductor portion 8, but a silicon nitride film and a silicon oxynitride film have the advantage of being less susceptible to decomposition and evaporation at high temperatures.

[0035] Therefore, the mask portion 5 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order on the base portion 4, or may be a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order on the base portion 4, or may be a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on the base layer.

[0036] Pinholes and other abnormalities in the mask portion 5 can be eliminated by performing organic cleaning after film formation, and then re-introducing the mask into the film formation device to form a film of the same type. A good quality mask pattern 6 can also be formed by using a general silicon oxide film (single layer) and using such a film re-formation method.

[0037] (template substrate) The main substrate 1 is a silicon substrate having a (111) surface, and the buffer portion 2 of the base portion 4 is an AlN layer (for example, 30 nm). 0.6 Ga 0.4 A graded layer was formed in which an N layer (eg, 300 nm) and a GaN layer (eg, 1 to 2 μm) as a second layer were formed in this order.

[0038] A laminated body in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) are formed in this order is used for the mask portion 5. The silicon oxide film has a thickness of, for example, 0.3 μm, and the silicon nitride film has a thickness of, for example, 70 nm. The silicon oxide film and the silicon nitride film are each formed by a plasma chemical vapor deposition (CVD) method.

[0039] (First semiconductor part) The first semiconductor portion 8 is formed by an ELO (Epitaxial Lateral Overgrowth) method, and includes low dislocation portions SD that overlap the mask portion 5 in a plan view and have relatively few threading dislocations, and high dislocation portions HD that overlap the openings K of the mask pattern 6 in a plan view and have relatively more threading dislocations than the low dislocation portions (see FIG. 8 ). The threading dislocation density of the low dislocation portions SD may be 1 / 5 or less of the threading dislocation density of the high dislocation portions HD. The threading dislocation density of the low dislocation portions SD may be 5×10 6 / cm 2 In the low dislocation portion SD, the non-threading dislocation density may be greater than the threading dislocation density.

[0040] Threading dislocations are dislocations (defects) that extend from the lower surface or interior of the first semiconductor portion 8 to its surface or surface layer along the thickness direction (Z direction) of the first semiconductor portion 8. Threading dislocations can be observed by performing CL (cathode luminescence) measurement on the surface layer (parallel to the c-plane) of the first semiconductor portion 8. Non-threading dislocations are dislocations that are measured by CL in a cross section along a plane parallel to the thickness direction (for example, the m-plane), and are mainly basal plane (c-plane) dislocations.

[0041] The light emitting efficiency of the active layer 9E can be improved by overlapping the light emitting region (portion under the anode) of the active layer 9E with the low dislocation portion SD in a planar view. This is because the portion of the second semiconductor portion 9 that overlaps with the low dislocation portion SD in a planar view inherits the low dislocation property of the first semiconductor portion 8.

[0042] In Example 1, the first semiconductor portion 8 was a GaN layer, and ELO deposition of gallium nitride (GaN) was performed on the above-mentioned template substrate 7 using the MOCVD apparatus provided in the formation portion 72. As an example of the ELO deposition conditions, the following can be adopted: substrate temperature: 1120° C., growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, and V / III=6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied).

[0043] In this case, the first semiconductor portion 8 is selectively grown (vertical growth) on the seed portion 3 (the GaN layer which is the second layer) exposed in the opening portion K, and then grows laterally on the mask portion 5. Then, the lateral growth of the first semiconductor portions 8 growing laterally from both sides of the mask portion 5 is stopped before they meet.

[0044] The width Wm of the mask portion 5 was 50 μm, the width of the opening K was 5 μm, the lateral width of the first semiconductor portion 8 was 53 μm, the width of the low defect portion (size in the X direction) was 24 μm, and the layer thickness of the first semiconductor portion 8 was 5 μm. The aspect ratio of the first semiconductor portion 8 was 53 μm / 5 μm=10.6, which is an extremely high aspect ratio.

[0045] In the formation of the first semiconductor portion 8 in the first embodiment, the lateral film formation rate is increased. The method for increasing the lateral film formation rate is as follows. First, a vertically grown layer that grows in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the opening K, and then a laterally grown layer that grows in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertically grown layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the laterally grown layer can be kept low and the lateral film formation rate can be increased.

[0046] (Second semiconductor portion and electrode) 5, the second semiconductor portion 9 includes, in order from the bottom side, an n-type semiconductor layer 9N, an active layer 9E, and a p-type semiconductor layer 9P. The active layer 9E has, for example, an MQW (Multi-Quantum Well) structure and includes, for example, InGaN or GaN. The n-type semiconductor layer 9N is, for example, an AlGaN layer. The p-type semiconductor layer 9P is, for example, a p-type GaN layer. The first electrode E1, which is an anode, is disposed so as to be in contact with the p-type semiconductor layer 9P.

[0047] The first and second semiconductor portions 8 and 9 may be formed consecutively in the same apparatus (for example, an MOCVD apparatus), or the substrate may be removed from the apparatus once after the formation of the first semiconductor portion 8, and the second semiconductor portion 9 may be formed after performing surface polishing or the like on the first semiconductor portion 8. In addition to the MOCVD apparatus, a sputtering apparatus, a remote plasma CVD apparatus (RPCVD), a PSD (Pulse Sputter Deposition) apparatus, or the like may be used to form the second semiconductor portion 9. The remote plasma CVD apparatus and the PSD apparatus do not use hydrogen as a carrier gas, and therefore a low-resistance p-type GaN-based semiconductor can be formed.

[0048] The MQW structure of the active layer 9E may be, for example, a 5-6 period structure of InGaN / GaN. The In composition varies depending on the target emission wavelength, and may be about 15-20% In concentration for blue (near 450 nm) and about 30% In concentration for green (near 530 nm). If necessary, an electron blocking layer (for example, an AlGaN layer) may be formed on the active layer 9E. In addition, in order to reduce resistance, the surface (about 10 nm) of the p-type semiconductor layer 9P may be a highly doped p-type layer.

[0049] The first and second electrodes E1 and E2 may have a single layer structure or a multi-layer structure containing at least one of Au, Ag, Pd, Pt, Ni, Ti, V, W, Cr, Al, Cu, Zn, Sn, and In, for example.

[0050] 14 and 15 are cross-sectional views showing another example of the method for manufacturing the semiconductor device according to the first embodiment. In FIG. 8, the base portion 4 is formed over the entire surface of the main substrate 1, but this is not limiting. As shown in FIG. 14, the base portion 4 can also be formed locally so as to overlap with the opening K of the mask pattern 6 in a plan view. Also, as shown in FIG. 15, by using, for example, a GaN substrate (bulk crystal of GaN) or a 6H-SiC substrate as the main substrate 1, the first semiconductor portion 8 can be grown using the upper surface of the main substrate 1 as a seed without providing the base portion 4.

[0051] When the first semiconductor portion 8 is formed using the ELO method, a template substrate 7 including a main substrate 1 and a mask pattern 6 on the main substrate 1 may be used. The template substrate 7 may have a growth-inhibiting region (e.g., a region that inhibits crystal growth in the Z direction) corresponding to the mask portion 5, and a seed region corresponding to the opening K. For example, the growth-inhibiting region and the seed region may be formed on the main substrate 1, and the first semiconductor portion 8 may be formed on the growth-inhibiting region and the seed region using the ELO method.

[0052] Example 2 FIG. 16 is a flowchart showing an example of a method for manufacturing a semiconductor device according to Example 2. FIG. 17 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 2. In the method for manufacturing a semiconductor device shown in FIG. 16 and FIG. 17, a step of preparing a template substrate (substrate for ELO growth) 7 is performed. The template substrate includes a main substrate 1, a base portion 4, and a mask pattern 6 in this order, and the mask pattern 6 includes a mask portion 5 and an opening K. Thereafter, a first semiconductor portion 8 is formed on the template substrate 7 using the ELO method. Next, a step of forming a second semiconductor portion 9 and first and second electrodes E1 and E2 is performed.

[0053] Then, a step of removing the entire main substrate 1 and a step of removing the entire base portion 4 are performed. Then, a step of using (functioning as) the mask portion 5, which is a selective growth mask, as an etching mask to remove the portions of the first and second semiconductor portions 8 and 9 that overlap with the openings K of the mask pattern 6 in a planar view is performed. Then, a step of removing the mask portion 5 using, for example, hydrogen fluoride (HF) is performed. This makes it possible to easily separate the template substrate 7 and the first semiconductor portion 8. The first and second semiconductor portions 8 and 9, etc. are separated into individual pieces, and a plurality of semiconductor devices 20 are formed.

[0054] 18 and 19 are cross-sectional views showing another example of the method for manufacturing a semiconductor device according to the second embodiment. In FIG. 17, the base portion 4 is formed over the entire surface of the main substrate 1, but this is not limiting. As shown in FIG. 18, the base portion 4 can also be formed locally so as to overlap with the opening K of the mask pattern 6 in a plan view. Also, as shown in FIG. 19, by using, for example, a GaN substrate (bulk crystal of GaN) or a 6H-SiC substrate as the main substrate 1, the first semiconductor portion 8 can be grown using the upper surface of the main substrate 1 as a seed without providing the base portion 4.

[0055] FIG. 20 is a flow chart showing another example of the method for manufacturing a semiconductor device according to the second embodiment. FIG. 21 is a cross-sectional view showing another example of the method for manufacturing a semiconductor device according to the second embodiment. In the method for manufacturing a semiconductor device shown in FIGS. 20 and 21, after forming a semiconductor substrate 10 including the first and second semiconductor portions 8·9, a support substrate FK is bonded to the opposite side of the main substrate 1. As a result, the first and second semiconductor portions 8·9 and the first and second electrodes E·E2 are held by the support substrate FK. Then, the entire main substrate 1 is removed. This makes it easier to handle after removing the main substrate 1. In this case, the support substrate FK is used as a mounting substrate (submount substrate or drive substrate), thereby making it possible to omit the mounting process. The first and second semiconductor portions 8·9 and the like may be transferred from the support substrate FK to another mounting substrate.

[0056] Example 3 FIG. 22 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the third embodiment. FIG. 23 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. In the method for manufacturing a semiconductor device shown in FIG. 22 and FIG. 23, a step of preparing a template substrate (substrate for ELO growth) 7 is performed. Then, a first semiconductor portion 8 is formed on the template substrate 7 by using the ELO method. Next, a step of forming a second semiconductor portion 9 and first and second electrodes E1 and E2 is performed. Then, a step of removing a portion of the main substrate 1 that overlaps with the opening K of the mask pattern 6 in a plan view by etching (deep etching) the main substrate 1 from its rear surface is performed. Then, a step of removing a portion of the base portion 4, the first semiconductor portion 8, and the second semiconductor portion 9 that overlaps with the opening K of the mask pattern 6 in a plan view is performed by using the remaining portion of the main substrate 1 as an etching mask to form a trench TY extending in the Y direction. Then, a step of removing the entire main substrate 1 and a step of isolating the first semiconductor portion 8 from the mask pattern 6 are performed.

[0057] The above-described embodiments and examples are for the purpose of illustration and description, not for the purpose of limitation. Based on these examples and descriptions, it will be apparent to those skilled in the art that many variations are possible.

[0058] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-mentioned embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0059] 1 Main Board 3 Seed Section 4 Base 5 Mask section 6 Mask Pattern 7 Template Substrate 8 First Semiconductor Department 9. Second Semiconductor Department 9E active layer 20 Semiconductor Devices 30 Micro LED Display (Electronic Devices) 70 Manufacturing equipment 72 Formation part 73 Processing Department E1 1st electrode E2 2nd electrode K opening FK support board

Claims

1. A step of preparing a semiconductor substrate including a main substrate, a template substrate including a seed region and a growth inhibition region located above the main substrate, and a first semiconductor portion located above the template substrate, the template substrate including a mask portion corresponding to the growth inhibition region; removing the main substrate; and removing a portion of the first semiconductor portion that overlaps with the seed region in a planar view using the mask portion as an etching mask.

2. forming a second semiconductor portion above the first semiconductor portion; The method for manufacturing a semiconductor device according to claim 1 , further comprising removing a portion of the second semiconductor portion that overlaps with the seed region in a plan view.

3. The method for manufacturing a semiconductor device according to claim 2 , further comprising the step of partially removing the second semiconductor portion, followed by partially removing the first semiconductor portion.

4. The template substrate has an underlayer located above the main substrate, The method for manufacturing a semiconductor device according to claim 1 , further comprising removing at least a portion of the underlayer that overlaps with the seed region in a plan view.

5. the first semiconductor portion includes a nitride semiconductor; 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of partially removing the first semiconductor portion, etching is performed from a (000-1) plane of the first semiconductor portion.

6. The method for manufacturing a semiconductor device according to claim 1 , further comprising supporting the first semiconductor portion by a support substrate.

7. The method for manufacturing a semiconductor device according to claim 6 , wherein the support substrate is a mounting substrate.

8. The first semiconductor portion includes a GaN-based semiconductor, The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the main substrate is a silicon substrate or a silicon carbide substrate.

9. the template substrate includes a seed portion having the seed region; 8. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of partially removing the first semiconductor portion, a bonded portion between the seed portion and the first semiconductor portion is removed.

10. A method for manufacturing a semiconductor substrate comprising: a main substrate; a template substrate including a seed region and a growth inhibition region located above the main substrate; and a first semiconductor portion located above the template substrate, the template substrate including a mask portion corresponding to the growth inhibition region; removing a portion of the main substrate that overlaps with the seed region in a plan view; removing a portion of the first semiconductor portion that overlaps with the seed region in a plan view; A method for manufacturing a semiconductor device, comprising forming an anchor film in contact with the mask portion and an upper surface and a side surface of the first semiconductor portion before the step of partially removing the first semiconductor portion.

11. A semiconductor device manufacturing apparatus that performs each step according to claim 1.

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