Systems and methods for adaptive semiconductor testing using in-line defect portion average testing

Abstract

The adaptive semiconductor test system and method uses an online defective portion average test configured to receive a plurality of online defective portion average test scores (I-PAT) from an I-PAT system, the plurality of I-PAT scores being generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies. The semiconductor die data includes characterization measurements for the plurality of semiconductor dies, and each I-PAT score of the plurality of I-PAT scores represents a weighted defect rate determined by the I-PAT system as a function of the characterization measurements for a corresponding semiconductor die of the plurality of semiconductor dies. Apply one or more rules to the plurality of I-PAT scores during a dynamic decision process. Generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies in response to the dynamic decision process.

Description

[Technical field]

[0001] REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Application No. 63 / 184,793 (May 6, 2021), which is incorporated by reference herein in its entirety.

[0002] "Technology field" The present disclosure relates generally to semiconductor devices, and more particularly to a system and method for semiconductor adaptive testing using in-line defective part average testing. [Background technology]

[0003] The manufacture of semiconductor devices may typically require tens of thousands or more of processing steps to form a functioning device. During the course of these processing steps, various characterization measurements (e.g., inspection and / or metrology measurements) may be performed to identify defects and / or monitor various parameters on the device. Electrical testing may be performed in lieu of, or in addition to, the various characterization measurements to verify or evaluate the functionality of the device. However, while some detected defects and metrology errors may be significant enough to clearly indicate device failure, smaller variations may cause premature reliability failure of the device after exposure to the working environment. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,761,128 Summary of the Invention [Problem to be solved by the invention]

[0005] Hazardous users of semiconductor devices (e.g., automotive, military, aviation, and medical applications) are now looking for failure rates in the parts per billion (PPB) range beyond the parts per million (PPM) level. Evaluating the reliability of semiconductor die is critical to meeting the requirements of these industries as the need for semiconductor devices in automotive, military, aviation, and medical applications continues to increase. [Means for solving the problem]

[0006] A system is disclosed according to one or more embodiments of the present disclosure. In an exemplary embodiment, the system includes an adaptive test controller communicatively coupled to an in-line defective part average testing (I-PAT) system. In another exemplary embodiment, the adaptive test controller includes one or more processors and a memory. In another exemplary embodiment, the memory is configured to store a set of program instructions. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to receive a plurality of I-PAT scores from the I-PAT system. In another exemplary embodiment, the plurality of I-PAT scores are generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies. In another exemplary embodiment, the semiconductor die data includes characterization measurements for the plurality of semiconductor dies. In another exemplary embodiment, each I-PAT score of the plurality of I-PAT scores represents a weighted defect rate (detection rate) determined by the I-PAT system based on characterization measurements for a corresponding semiconductor die of the plurality of semiconductor dies. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process. In another illustrative embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to generate, based on the dynamic decision-making process, one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies.

[0007] A method is disclosed according to one or more embodiments of the present disclosure. In an exemplary embodiment, the method includes, but is not limited to, receiving a plurality of in-line defective part average test (I-PAT) scores from an I-PAT system via an adaptive test controller. In another exemplary embodiment, the plurality of I-PAT scores are generated by the I-PAT system based on semiconductor die data of the plurality of semiconductor dies. In another exemplary embodiment, the semiconductor die data includes characterization measurements of the plurality of semiconductor dies. In another exemplary embodiment, each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on characterization measurements of a corresponding semiconductor die of the plurality of semiconductor dies. In another exemplary embodiment, the method may include, but is not limited to, applying one or more rules to the plurality of I-PAT scores via an adaptive test controller during a dynamic decision-making process. In another exemplary embodiment, the method may include, but is not limited to, generating one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies via an adaptive test controller based on a dynamic decision-making process.

[0008] A system is disclosed according to one or more embodiments of the present disclosure. In one exemplary embodiment, the system includes an In-line Defective Part Average Test (I-PAT) system. In another exemplary embodiment, the I-PAT system is configured to receive semiconductor die data for a plurality of semiconductor dies and generate a plurality of I-PAT scores based on the semiconductor die data. In another exemplary embodiment, the semiconductor die data includes characterization measurements of the plurality of semiconductor dies. In another exemplary embodiment, each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on the characterization measurements of a corresponding semiconductor die of the plurality of semiconductor dies. In another exemplary embodiment, the system includes an adaptive test controller communicatively coupled to the I-PAT system. In another exemplary embodiment, the adaptive test controller includes one or more processors and a memory. In another exemplary embodiment, the memory is configured to store a set of program instructions. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to receive a plurality of I-PAT scores from the I-PAT system. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process. In another exemplary embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process. Effect of the Invention

[0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, are exemplary embodiments of the invention and, together with the general description, serve to explain the principles of the invention. [Brief description of the drawings]

[0010] Many advantages of the present disclosure may be better understood by those skilled in the art by reference to the following drawings. [Figure 1] FIG. 1 is a block diagram of a system for semiconductor adaptive testing using in-line defective part average testing (I-PAT) in accordance with one or more embodiments of the present disclosure. [Diagram 2] FIG. 2 is a conceptual diagram of a system for semiconductor adaptive testing using I-PAT in accordance with one or more embodiments of the present disclosure. [Diagram 3] FIG. 3 is a flow diagram illustrating steps performed in a method for semiconductor adaptive testing using I-PAT in accordance with one or more embodiments of the present disclosure. [Figure 4A] FIG. 4A is a block diagram of a system for manufacturing and characterizing semiconductor devices in accordance with one or more embodiments of the present disclosure. [Figure 4B] FIG. 4B is a block diagram of a system for manufacturing and characterizing semiconductor devices in accordance with one or more embodiments of the present disclosure. [Diagram 5] FIG. 5 is a flow diagram illustrating steps performed in a method for manufacturing and characterizing a semiconductor device in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings. The present disclosure has been specifically shown and described with respect to certain embodiments and certain features thereof. The embodiments described herein are to be construed as illustrative and not restrictive. It will be readily apparent to those skilled in the art that various changes and modifications in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

[0012] The fabrication of semiconductor devices may typically require tens of thousands or more processing steps to form a functioning device. During these processing steps, various characterization measurements (e.g., inspection and / or metrology measurements) may be performed to identify defects and / or monitor various parameters on the device. Electrical testing may be performed instead of or in addition to the various characterization measurements to verify or evaluate the functionality of the device.

[0013] However, while some detected defects and metrology errors may be significant enough to clearly indicate device failure, lesser variations may cause premature reliability failure of the device after exposure to the working environment. Defects occurring during the manufacturing process may have a wide-ranging effect on the performance of devices in the field. For example, "killer" defects occurring at known or unknown locations in the design may result in immediate device failure. For example, killer defects at unknown locations may be particularly problematic if they are susceptible to reliability escapes in the test gap and the semiconductor device may be functionally dead after processing, but the device manufacturer is unable to make this determination due to limitations in testing. As another example, minor defects may have little or no effect on device performance throughout the device's life. As another example, a class of defects known as latent reliability defects (LRDs) may not lead to failures during manufacturing / testing or may not lead to immediate device failure during operation, but may lead to premature end-of-life failure of the device during operation when used in the working environment. It should be noted that, as used herein, the terms "fabrication process" and "manufacturing process" may be considered equivalent for purposes of this disclosure, along with respective variations of the terms (e.g., "fabrication line" and "manufacturing line").

[0014] Hazardous users of semiconductor devices (e.g., automotive, military, aerospace, and medical applications) are now requiring failure rates in the parts per billion (PPB) range beyond the parts per million (PPM) level. Evaluating the reliability of semiconductor die is critical to meeting the requirements of these industries as the need for semiconductor devices in automotive, military, aerospace, and medical applications continues to increase.

[0015] In one example, semiconductor devices that play a quality-critical role may undergo extensive electrical testing during wafer sort and again at final test after singulation and packaging. This manufacturing stage is under conflicting pressures to reduce quality escapes and to lower costs by shortening test time. One way to accomplish both goals is through adaptive testing, where the variables of the test program for each device under test are dynamically adjusted using various a priori sources of information. The output or results of adaptive testing may change one or more of the test conditions, manufacturing flow, test content, or test limits or die placement after adaptive testing.

[0016] Known adaptive test techniques rely solely on preliminary electrical data from wafer sort or statistical predictions of electrical test trends and yield results from previous lots and adjacent dies to dynamically shape the test program. The resulting in-line process control information is too sparse to be used for shape testing at the individual device level, as sampling included only 1-2% of the production material. Furthermore, known adaptive test techniques lack metrology information to aid in die-level manufacturing defect and / or risk prediction. Furthermore, since non-activated LRDs are invisible to electrical testing, relying solely on electrical wafer sort data may overlook the potential presence of LRDs when shaping adaptive test. Furthermore, statistically-based predictive algorithms lack location data regarding the semiconductor die undergoing test and may miss individual outliers caused by local manufacturing deviations. Furthermore, predictive algorithms based on historical feedback loops that address test sets solely to electrical testing may fail to overlook the unpredictable nature of manufacturing process excursions and the unexpected failures they may result in. These shortcomings are particularly problematic in PPB test environments, as they may cause unacceptable risks.

[0017] Embodiments of the present disclosure are directed to systems and methods for semiconductor adaptive testing using in-line defect part average testing (I-PAT). Embodiments of the present disclosure are also directed to using in-line defect screening, or I-PAT, in conjunction with a semiconductor characterization process to identify semiconductor die outliers. Embodiments of the present disclosure also include evaluating the suitability of a particular adaptive test for a given semiconductor die. Embodiments of the present disclosure also include evaluating the suitability of a particular adaptive test parameter for a given semiconductor die.

[0018] 1 and 2 generally illustrate a block diagram of a system 100 for semiconductor adaptive testing using in-line defective part average testing (I-PAT), in accordance with one or more embodiments of the present disclosure.

[0019] In some embodiments, the system 100 includes an I-PAT system 102 and an adaptive test controller 104 (or adaptive test server 104). The adaptive test controller 104 may include one or more processors 106 configured to execute program instructions maintained or stored in a memory 108 (e.g., a storage medium, a storage device, etc.). It is noted herein that the one or more processors 106 of the adaptive test controller 104 may perform any of the various process steps described throughout this disclosure. For example, the one or more processors 106 may be configured to receive semiconductor die data, generate I-PAT scores for the semiconductor die from the semiconductor die data using the I-PAT system 102, generate adaptive tests for at least some of the semiconductor die based on the I-PAT scores from the I-PAT system 102, and determine adjustments based on the adaptive tests.

[0020] The system 100 may include a user interface 110 coupled (e.g., physically coupled, electrically coupled, communicatively coupled, etc.) to the adaptive test controller 104. For example, the user interface 110 may be a separate device coupled to the adaptive test controller 104. As another example, the user interface 110 and the adaptive test controller 104 may be located within a common or shared housing. However, it is noted herein that the adaptive test controller 104 may not include, require, or be coupled to the user interface 110.

[0021] In some embodiments, the system 100 includes a semiconductor manufacturing and characterization system 112 coupled (e.g., physically coupled, electrically coupled, communicatively coupled, etc.) to the I-PAT system 102. The semiconductor manufacturing and characterization system 112 may transmit semiconductor data 114 that may be received by the I-PAT system 102. For example, the semiconductor data 114 may be transmitted directly between the semiconductor manufacturing and characterization system 112 and the I-PAT system 102. As another example, the semiconductor data 114 may be transmitted between the semiconductor manufacturing and characterization system 112 and the I-PAT system 102 via one or more auxiliary controllers or servers. Thus, the examples of systems, subsystems, or controllers or servers described throughout this disclosure are provided merely for illustrative purposes and should not be construed as limiting.

[0022] The semiconductor data 114 may be uploaded to the I-PAT system 102 as a standardized data format shared by the semiconductor manufacturing and characterization system 112 and the I-PAT system 102. For example, the standardized data format may be formatted for use with different operating systems, including but not limited to Android, Apple iOS, Microsoft Windows, Apple macOS, Linux, ChromeOS, Unix, Ubuntu, etc. However, it is noted herein that the fabrication environment may use a first type of file format, while the I-PAT environment may use a different type of file format.

[0023] Thus, the semiconductor data 114 may be in a non-standardized manufacturing data format that requires conversion. For example, the semiconductor manufacturing and characterization system 112 may transmit the semiconductor data 114 to the I-PAT system 102 in a non-standardized manufacturing data format, which may convert the semiconductor data 114 to a standardized test data format upon receipt. As another example, the semiconductor manufacturing and characterization system 112 may convert the semiconductor data 114 to a standardized test data format prior to transmission to the I-PAT system 102. Additionally, the semiconductor data 114 may be uploaded to the I-PAT system 102 as a proprietary data format specific to the manufacturing and / or test environment. Additionally, the semiconductor data 114 may be shared using encrypted data (e.g., via a daemon), web or cloud interface, or other secure connection using die traceability to ensure that the semiconductor data 114 remains synchronized.

[0024] The I-PAT system 102 can receive semiconductor data 114 and perform one or more screening inspection processes 200 on the semiconductor data 114. The semiconductor data 114 can include information regarding a semiconductor wafer 202 of a plurality of semiconductor wafers 202, where each semiconductor wafer 202 of the plurality of semiconductor wafers 202 includes a plurality of (e.g., 1, 2, .... N number) layers that are fabricated according to a plurality of steps (e.g., tens of thousands) performed by a plurality of manufacturing processes, where each layer of the plurality of layers includes a plurality of semiconductor dies 204, and each semiconductor die 204 of the plurality of semiconductor dies 204 includes a plurality of blocks. In this regard, the semiconductor data 114 can include wafer-level data, layer-level data, die-level data, and / or block-level data. For purposes of this disclosure, "semiconductor data" should be understood to include "semiconductor die data," and "semiconductor data" and "semiconductor die data" can be considered equivalent. However, "semiconductor data" is not intended to include only "semiconductor die data."

[0025] The one or more screening inspection processes 200 can characterize the plurality of semiconductor dies 204. For example, each semiconductor die 204 of the plurality of semiconductor dies 204 can be characterized as either a low-defectivity (low defect rate) "good" semiconductor die 206, a medium-defectivity (medium defect rate) "at risk" semiconductor die 208, or a high-defectivity (high defect rate) semiconductor die 210.

[0026] It is noted herein that characterization of the plurality of semiconductor dies 204 may be performed on all (e.g., 100%) or a subset of the plurality of semiconductor dies 204 on a particular semiconductor wafer 202. Additionally, it is noted herein that characterization of the plurality of semiconductor dies 204 may occur on all (e.g., 100%) or a subset of the plurality of semiconductor layers on a particular semiconductor wafer 202. For example, the subset of the plurality of semiconductor layers may include, but is not limited to, one or more layers that are determined to be completely critical and / or include a critical aspect. Additionally, it is noted herein that characterization of the plurality of semiconductor dies 204 may be performed on all (e.g., 100%) or a subset of the plurality of semiconductor wafers 202.

[0027] With I-PAT scores potentially available for 100% of the wafer and 100% of the dies, significant information about the relative health or quality risk of each die is available that test engineers can use to adaptively shape their test programs. With the addition of I-PAT data, adaptive testing can dynamically customize test content with low latency to reduce escapes while simultaneously reducing the total cost of testing. Additionally, with the addition of I-PAT data, test adaptations can vary from die to die, potentially resulting in tailored test times, different test content, or different test limits for each semiconductor device being tested. Exemplary uses of the I-PAT method include U.S. Patent 10,761,128 (September 1, 2020), and U.S. Patent Application 17 / 101,856 (November 23, 2020), each of which is incorporated herein in its entirety.

[0028] In some embodiments, the I-PAT system 102 outputs a weighted aggregate score 116, or I-PAT score 116, to the adaptive test controller 104. The I-PAT score 116 may represent the amount and risk level of defects present in each semiconductor die 204 summed across each of the layers being inspected and screened, such that the I-PAT score 116 is a die-level score. The I-PAT score 116 may include the layer in which the defect occurred, including information about its x,y location within the semiconductor die 204. The I-PAT score 116 may describe the type of defect (e.g., is it a short, open, etc.), the size of the defect, its inclusion in a cluster, or its location on the wafer 202 (e.g., x,y location).

[0029] The weighted aggregate scores 116 may be binned at one or more pre-set or custom user-defined outlier thresholds before being output to the adaptive test controller 104. However, it is noted herein that the weighted aggregate scores 116 may be output to the adaptive test controller 104 in an organized format similar to that of the semiconductor die data 114.

[0030] The I-PAT scores 116 may be output directly, or indirectly via one or more auxiliary servers or controllers, to the adaptive test controller 104. Thus, the examples of systems, subsystems, or controllers or servers described throughout this disclosure are provided for illustrative purposes only and should not be construed as limiting.

[0031] The I-PAT scores 116 may be uploaded to the adaptive test controller 104 as a standardized data format shared by the I-PAT system 102 and the adaptive test controller 104. For example, the standardized data format may be formatted for use with different operating systems, including but not limited to Android, Apple iOS, Microsoft Windows, Apple macOS, Linux, ChromeOS, Unix, Ubuntu, etc. However, it is noted herein that while the manufacturing environment (including the I-PAT environment) may use a first type of file format (e.g., defect data format and KLARF file format), the test environment may use a different type of file format (e.g., STDF file format, BITdb file format, etc.).

[0032] Thus, the I-PAT scores 116 may be in a non-standardized manufacturing data format that requires conversion. For example, the I-PAT system 102 may transmit the I-PAT scores 116 to the adaptive test controller 104 in a non-standardized manufacturing data format, which may convert the I-PAT scores 116 to a standardized test data format upon receipt. As another example, the I-PAT system 102 may convert the I-PAT scores 116 to a standardized test data format prior to transmission to the adaptive test controller 104. Additionally, the I-PAT scores 116 may be uploaded to the adaptive test controller 104 as a proprietary data format specific to the manufacturing and / or test environment. Furthermore, the I-PAT scores 116 may be shared using encrypted data (e.g., via a daemon), web or cloud interface, or other secure connection using die traceability to ensure that the I-PAT scores 116 of each semiconductor die 204 remain synchronized.

[0033] It should be noted herein that the distinction between operating with a "standardized data format" and / or a "non-standardized data format" for the I-PAT system 102, the adaptive test controller 104, and / or the semiconductor manufacturing and characterization system 112 is provided for illustrative purposes only and should not be construed as limiting.

[0034] In some embodiments, the adaptive test controller 104 generates one or more adaptive tests 118 from the I-PAT scores 116 instead of using the I-PAT scores 116 to make decisions regarding immediately screening out highly defective die and / or merging the I-PAT scores 116 with electrical part average test data to make better informed go / no-go decisions for the semiconductor die 204 following final electrical testing.

[0035] Using user-defined or pre-defined rules for limits on the I-PAT score 116 (and / or contributing factors of the I-PAT score 116), the adaptive test controller 104 may use a dynamic rule-based decision-making process for the I-PAT score 116 for each semiconductor die 204. For example, the dynamic rule-based decision-making process may be used to make decisions regarding the content, duration, and limits of the test patterns executed on each device under test depending on the amount, type, location, or layer of defects present. It is noted herein that the "dynamic" nature of the decision-making may result from one or more of the following: receipt of user-defined rules and subsequent adjustment of the decision-making process, continuous operation of the decision-making process as the I-PAT score 116 is received. It is also noted that the adaptive tests 118 based on application of defined rules to generate one or more adaptive tests 118 may be continually modified.

[0036] The adaptive test controller 104 may use dynamic rule-based decision-making alone for the I-PAT score 116 of each semiconductor die 204, or may combine dynamic rule-based decision-making with other processes.

[0037] For example, the decision maker can receive die-level electrical sort data 212 from the electrical sort process 120. For example, the electrical sort data 212 can include, but is not limited to, wafer probe data or other electrical test data received from the semiconductor fabrication and characterization system 112 during or after a process of electrically evaluating device functionality at the end of a fabrication manufacturing process (e.g., an electrical wafer sort (EWS) process, etc.).

[0038] As another example, the decision maker may receive statistical prediction feedback 214 from the statistical prediction process 122. For example, the statistical prediction feedback 214 may be in the form of a data set or a table, graph, model, or other form of physical or graphical representation.

[0039] It is noted herein that dynamic rule-based decision making, the electronic sorting process 120, and / or the statistical prediction process 122 may be combined. For example, the combination may be based on user-defined priorities (e.g., weighting factors) that should be taken into account when determining the type of one or more adaptive tests 118.

[0040] The one or more adaptive tests 118 may include one or more of the following non-limiting examples: For example, the one or more adaptive tests 118 may be selected based on a threshold between a low defect rate (low detection rate) "good" semiconductor die 206 and a medium defect rate (medium detection rate) "at risk" semiconductor die 208, and / or based on a second threshold between a medium defect rate "at risk" semiconductor die 208 and a high defect rate (high detection rate) semiconductor die 210.

[0041] In one non-limiting example, the one or more adaptive tests 118 may include a nominal test 216. The nominal test 216 may be selected for a "good" semiconductor die 206 with a low defect rate. The nominal test 216 may include a baseline test program, where the baseline test program is at an optimized minimum (e.g., an optimized minimum with no changes in any of the test parameters would improve the operation of the baseline test program). However, it is noted herein that the nominal test 216 may be a test program that has been reduced (steps removed and simplified) from a baseline test program where the baseline test program is not optimized through an iterative process until optimization is achieved. For example, the nominal test 216 may be reduced in terms of the number and / or type of test vectors, amount of coverage, etc., throughout the iterative process until optimization is achieved. Thus, a "good" semiconductor die 206 with a low defect rate having a low I-PAT score 116 may be assigned a nominal test, saving time and cost.

[0042] In another non-limiting example, the one or more adaptive tests 118 may include adaptive tests 218. The adaptive tests 218 may be selected for a moderately defective “at risk” semiconductor die 208. The adaptive tests 218 may include modifications to a baseline test program including the addition of test program parameters to target known defects. For example, the modifications may include, but are not limited to, expanding test coverage, adding or adjusting fault models, modifying control limits, placing the moderately defective “at risk” semiconductor die 208 using a different binning process, or the like. Thus, a moderately defective “at risk” semiconductor die 208 with an I-PAT score indicating an elevated risk may be assigned an “adaptive” or “adaptable” test program with additional thoroughness to determine its fitness for purpose and improve the quality of results.

[0043] In another non-limiting example, the one or more adaptive tests 118 may include skip testing 220. Skip testing 220 may generate cost savings by not packaging and / or testing known non-good high defectivity semiconductor dies 210 as determined by the I-PAT system 102. Here, skip testing 220 may perform a reduced set of test patterns that do not test the non-selected set by recognizing the non-selected set as known outliers, such that the non-selected set is effectively treated as if it were sorted or ink-out. Thus, high defectivity (highly defective) semiconductor dies 210 with very high I-PAT scores 116 may be rejected and thus skip testing entirely, which may also result in cost savings.

[0044] In another non-limiting example, the one or more adaptive tests 118 can include deep test 222. Deep test 222 can be applied to high defect rate semiconductor die 210 that are potential candidates for full or complete characterization of defect detection and coverage. Thus, a high defect rate semiconductor die 210 with an I-PAT score that includes a target defect of interest can trigger the use of a unique set of test vectors that are known to best recognize the defect when that defect type is present. Additionally, a high defect rate semiconductor die 210 with an I-PAT score that indicates an excursion or new defect type can trigger a very complete test program that characterizes the impact of the defect and appropriate test vectors for efficient coverage.

[0045] It should be noted that the above non-limiting examples are provided herein merely for purposes of illustrating the types of adaptive tests 118 and should not be construed as limiting.

[0046] Although the I-PAT system 102 and the adaptive test controller 104 are shown as separate components of the system 100, it is noted herein that the I-PAT system 102 and the adaptive test controller 104 may be integrated together. For example, the I-PAT system 102 may be integrated into the adaptive test controller 104 (e.g., a process coded to operate on the adaptive test controller 104) such that the adaptive test controller 104 receives semiconductor die data 114 from the semiconductor manufacturing and characterization system 112. As another example, the adaptive test controller 104 may be integrated into the I-PAT system 102 (e.g., a process coded to operate on the I-PAT system 102) such that the I-PAT system 102 can generate one or more adaptive tests 118.

[0047] 3 illustrates a method or process 300 for semiconductor adaptive testing using in-line defect part average testing, according to one or more embodiments of the present disclosure. It is noted herein that the steps of the method or process 300 may be implemented in whole or in part by the system 100 illustrated in Figures 1 and 2. However, it is further recognized that the method or process 300 is not limited to the system 100 illustrated in Figures 1 and 2, in that additional or alternative system level embodiments may perform all or a portion of the steps of the method or process 300.

[0048] In step 302, semiconductor die data 114 is received. In some embodiments, the semiconductor die data 114 is received by the I-PAT system 102 from a semiconductor manufacturing and characterization system 112.

[0049] In step 304, an I-PAT score 116 is generated for the semiconductor die 204 from the semiconductor die data 114 using the I-PAT system 102. In some embodiments, the I-PAT score 116 separates the semiconductor die 204 into low defect rate "good" semiconductor die 206, medium defect rate "at risk" semiconductor die 208, or high defect rate semiconductor die 210.

[0050] In step 306, the defined rules are applied to the I-PAT scores 116 during the dynamic decision-making process. The defined rules may be user-defined and received by the adaptive test controller 104 (e.g., via the user interface 110). The defined rules may be pre-configured within the adaptive test controller 104. The defined rules may segregate the semiconductor dies 204 based on the corresponding I-PAT scores 116 and / or observed defects on the semiconductor dies 204.

[0051] In step 308, adaptive tests 118 for at least some of the semiconductor dies 204 are generated based on the dynamic decision-making process. In some embodiments, the adaptive tests 118 include, but are not limited to, nominal tests 216, adaptive tests 218, skip tests 220, and / or deep tests 222.

[0052] In step 310, adjustments are determined based on the adaptive tests 118. In some embodiments, the adjustments are transmitted to the manufacturing or characterization system 112 via either a feed-forward loop (e.g., to correct current semiconductor devices) or a feedback loop (e.g., to adjust future semiconductor devices) to adjust the manufacturing and / or characterization process. In this regard, the manufacturing and / or characterization process may be improved, leading to reduced costs (e.g., in time, money, etc.) for the manufacturer while maintaining a desired quality level (e.g., PPB failure rate).

[0053] Although the embodiments of the present disclosure depict steps of the method or process 300 as being performed by the adaptive test controller 104, it is noted herein that some or all of the steps of the method or process 300 may be performed by a server or controller communicatively coupled to the adaptive test controller 104. For example, the server or controller may include a processor and memory, and other communicatively coupled components as described throughout this disclosure.

[0054] 4A and 4B show block diagrams of a semiconductor fabrication and characterization system 112, or "system 112," according to one or more embodiments of the present disclosure. It is noted herein that system 112 may be configured to perform processing steps for fabricating and / or analyzing semiconductor devices and / or components on semiconductor devices (e.g., semiconductor dies), as described throughout this disclosure.

[0055] In some embodiments, system 112 includes one or more semiconductor characterization subsystems 400 configured to output characterization measurements within (or as) semiconductor die data 114 for semiconductor die 204. For example, the characterization measurements may include, but are not limited to, baseline inspection (e.g., sampling-based inspection), screening inspection at key semiconductor device layers, etc. For purposes of this disclosure, "characterization" may refer to in-line defect inspection and / or in-line metrology measurements.

[0056] In one non-limiting example, the one or more semiconductor characterization subsystems 400 may include at least one inspection tool 402 (e.g., an in-line sample analysis tool) for detecting defects in one or more layers of a sample 404 (e.g., a semiconductor wafer 202). The system 112 may generally include any number or type of inspection tools 402. For example, the inspection tool 402 may include an optical inspection tool configured to detect defects based on interrogation of the sample 404 with light from any source, such as, but not limited to, a laser source, a lamp source, an X-ray source, or a broadband plasma source. As another example, the inspection tool 402 may include a particle beam inspection tool configured to detect defects based on interrogation of the sample with one or more particle beams, such as, but not limited to, an electron beam, an ion beam, or a neutral particle beam. For example, the inspection tool 402 may include a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For purposes of this disclosure, it is noted that, as used herein, at least one inspection tool 402 may refer to a single inspection tool 402 or a group of inspection tools 402 .

[0057] It is noted herein that the specimen 404 may be a semiconductor wafer of a plurality of semiconductor wafers, each semiconductor wafer of the plurality of semiconductor wafers including a plurality of (e.g., 1, 2, ... N number) layers fabricated according to several (e.g., tens of thousands) steps performed by a plurality of manufacturing processes, each layer of the plurality of layers including a plurality of semiconductor dies, where each semiconductor die of the plurality of semiconductor dies includes a plurality of blocks. In addition, it is noted herein that the specimen (sample) 404 may be a semiconductor die package formed from a plurality of semiconductor dies arranged in a 2.5D lateral combination of bare dies on a substrate inside an advanced die package or a 3D die package.

[0058] For purposes of this disclosure, the term "defect" may refer to a physical defect found by an in-line inspection tool, a metrology measurement outlier, or other physical characteristic of a semiconductor device that is deemed to be abnormal. A defect may be considered to be any deviation of a fabricated layer or a fabricated pattern within a layer from a design characteristic, including but not limited to a physical, mechanical, chemical, or optical characteristic. In addition, a defect may be considered to be any deviation in the alignment or joining of components within a fabricated semiconductor die package. Furthermore, a defect may have any size relative to a semiconductor die or features thereon. In this manner, a defect may be smaller than a semiconductor die (e.g., at the scale of one or more patterned features) or larger than a semiconductor die (e.g., as a wafer-scale scratch or part of a pattern). For example, a defect may include a deviation in the thickness or composition of a sample layer before or after patterning. As another example, a defect may include a deviation in the size, shape, orientation, or position of a patterned feature. As another example, the defect may include defects associated with lithography and / or etching steps, such as, but not limited to, bridges (or lack thereof) between adjacent structures, pits, or holes. As another example, the defect may include damaged portions of the sample 404, such as, but not limited to, scratches or chips. For example, the severity of the defect (e.g., the length of the scratch, the depth of the pit, the measured size or polarity of the defect, etc.) may be important and considered. As another example, the defect may include foreign material introduced into the sample 404. As another example, the defect may be a misaligned and / or mismated package component on the sample 404. It should therefore be understood that the examples of defects in this disclosure are provided merely for illustrative purposes and should not be construed as limiting.

[0059] In another non-limiting example, the one or more semiconductor characterization subsystems 400 can include at least one metrology tool 406 (e.g., an in-line sample analysis tool) for measuring one or more properties of the sample 404 or one or more layers thereof. For example, the metrology tool 406 can characterize properties such as, but not limited to, layer thickness, layer composition, critical dimension (CD), overlay, or lithography processing parameters (e.g., intensity or dose of illumination during a lithography step). In this regard, the metrology tool 406 can provide information regarding the manufacturing of the sample 404, one or more layers of the sample 404, or one or more semiconductor dies of the sample 404, which information can relate to the probability of manufacturing defects that can lead to reliability issues in the resulting manufactured device. For purposes of this disclosure, it is noted herein that the at least one metrology tool 406 may be a single metrology tool 406 or may represent a group of metrology tools 406.

[0060] In some embodiments, the system 112 includes at least one semiconductor manufacturing tool or process tool 408. For example, the process tool 408 can include any tool known in the art, including, but not limited to, etchers, scanners, steppers, cleaners, and the like. For example, the manufacturing process can include fabricating a plurality of dies distributed across a surface of a specimen (e.g., a semiconductor wafer, etc.), each die including a plurality of patterned layers of material forming device components. Each patterned layer may be formed by the process tool 408 through a series of steps including material deposition, lithography, etching to generate a pattern of interest, and / or one or more exposure steps (e.g., performed by a scanner, stepper, etc.). As another example, the process tool 408 can include any tool known in the art configured to package and / or bond semiconductor dies into 2.5D and / or 3D semiconductor die packages. For example, the manufacturing process can include, but is not limited to, aligning semiconductor dies and / or electrical components on the semiconductor dies. Additionally, the manufacturing process may include, but is not limited to, joining the semiconductor die and / or electrical components on the semiconductor die via hybrid bonding (e.g., die-to-die, die-to-wafer, wafer-to-wafer, etc.), solder, adhesives, fasteners, or the like. For purposes of this disclosure, it is noted that, herein, at least one process tool 408 may be a single process tool 408 or may represent a group of process tools 408. It is noted that, herein, the terms "fabrication process" and "manufacturing process" may be considered equivalent for purposes of this disclosure, along with respective variations of the terms (e.g., "fabrication line" and "manufacturing line", "fabrication supplier" and "manufacturing supplier", etc.).

[0061] In some embodiments, the system 112 includes one or more test tool subsystems 410 for testing the functionality of one or more portions of a manufactured device.

[0062] In one non-limiting example, the one or more test tool subsystems 410 may include any number or type of electrical test tools 412 to complete pre-probing at the wafer level, for example, pre-probing is not designed to attempt to force failures at the wafer level.

[0063] In some embodiments, defects are identified using any combination of semiconductor characterization subsystems 400 (e.g., inspection tools 402, metrology tools 406, etc.), test tool subsystems 410 (e.g., including electrical test tools 412 and / or stress test tools 414, etc.) utilized before or after one or more processing steps (e.g., lithography, etching, alignment, bonding, etc.) performed by one or more process tools 408 on the semiconductor die and / or layers of interest within the semiconductor die package. In this regard, defect detection at various stages of the manufacturing process may be referred to as in-line defect detection.

[0064] In some embodiments, the system 112 includes a controller 416. The controller 416 can include one or more processors 418 configured to execute program instructions maintained on a memory 420 (e.g., a storage medium, a storage device, etc.). For example, the one or more processors 418 can be configured to obtain semiconductor die data 114 including characterization measurements of the semiconductor die 204, transmit the semiconductor die data 114 to the I-PAT system 102, and generate control signals for adjustments determined based on output from adaptive testing for at least some of the semiconductor die created based on the I-PAT scores 116 from the I-PAT system 102.

[0065] The controller 416 can be communicatively coupled to any of the components of the system 112, including, but not limited to, the semiconductor characterization subsystem 400, including the inspection tool 402 or metrology tool 406, the test tool subsystem 410, including the electrical test tool 412 or the stress test tool 414, and the like. It is noted herein that the embodiment shown in FIG. 4A and the embodiment shown in FIG. 4B may be considered as parts of the same manufacturing and characterization system 112 or parts of different manufacturing and characterization systems 112 for purposes of this disclosure. It is further noted herein that the components in the semiconductor manufacturing and characterization system 112 shown in FIG. 4A and the components in the semiconductor manufacturing and characterization system 112 shown in FIG. 4B may communicate directly or through the controller 416.

[0066] The one or more processors 106 or 418 may include any processor or processing element known in the art. For purposes of this disclosure, the term "processor" or "processing element" may be broadly defined to encompass any device having one or more processing or logic elements (e.g., one or more graphics processing units (GPUs), microprocessing units (MPUs), systems on chips (SoCs), one or more application specific integrated circuits (ASICs) devices, one or more field programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, the one or more processors 106 or 418 may include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in a memory). In an embodiment, the one or more processors 106 or 418 may be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a network computer, or any other computer system configured to execute programs that operate or are configured to operate with the components of the system 100 or 112 as described throughout this disclosure.

[0067] The memory 108 or 420 may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors 106 or 418, respectively. For example, the memory 108 or 420 may include a non-transitory memory medium. As another example, the memory 108 or 420 may include, but is not limited to, a read-only memory (ROM), a random access memory (RAM), a magnetic or optical memory device (e.g., disk), a magnetic tape, a solid-state drive, and the like. It is further noted that the memory 108 or 420 may be housed in a common controller housing with the one or more processors 106 or 418. In one embodiment, the memory 108 or 420 may be located remotely with respect to the physical location of the respective one or more processors 106 or 418. For example, the respective one or more processors 106 or 418 may access a remote memory (e.g., a server) accessible via a network (e.g., the Internet, an intranet, etc.).

[0068] In another embodiment, the system 112 includes a user interface 422 coupled (e.g., physically coupled, electrically coupled, communicatively coupled, etc.) to the controller 416. For example, the user interface 422 may be a separate device coupled to the controller 416. As another example, the user interface 422 and the controller 416 may be located within a common or shared housing. However, it is noted herein that the controller 416 may not include, require, or be coupled to the user interface 422.

[0069] The user interface 110 or 422 may include, but is not limited to, one or more desktops, laptops, tablets, etc. The user interface 110 or 422 may include a display used to display data of the system 100 or 112 to a user. The display of the user interface 110 or 422 may include any display known in the art. For example, the display may include, but is not limited to, a liquid crystal display (LCD), an organic light emitting diode (OLED) based display, or a CRT display. Those skilled in the art should recognize that any display device that can be integrated with the user interface 110 or 422 is suitable for implementation in the present disclosure. In another embodiment, a user may input selections and / or commands in response to data displayed to the user via a user input device of the user interface 110 or 422.

[0070] 5 illustrates a method or process 500 for semiconductor adaptive testing using in-line defective part average testing, according to one or more embodiments of the present disclosure. It is noted herein that the steps of the method or process 500 may be implemented in whole or in part by the system 112 illustrated in FIGs. 4A and 4B. However, it is further recognized that the method or process 500 is not limited to the system 112 illustrated in FIGs. 4A and 4B in that additional or alternative system level embodiments may perform all or a portion of the steps of the method or process 500.

[0071] In step 502, characterization measurements are obtained of the semiconductor die 204. In some embodiments, the characterization measurements are obtained by the semiconductor manufacturing and characterization system 112. It is noted herein that the die-level electrical sort data 212 may also be obtained directly or indirectly (e.g., after processing) from the semiconductor manufacturing and characterization system 112.

[0072] In step 504, the characterization measurements are transmitted to the I-PAT system 102. In some embodiments, the I-PAT system 102 generates an I-PAT score 116 based on the characterization measurements. In some embodiments, the adaptive test controller 104 determines one or more adaptive tests 118 based on the I-PAT score 116.

[0073] In step 506, one or more control signals are generated for adjustments determined based on output from adaptive testing 118 for at least some of the semiconductor dies 204 created based on the I-PAT scores 116 from the I-PAT system 102. In some embodiments, the one or more control signals are directed to at least one of manufacturing, characterizing, or testing one or more semiconductor devices. For example, the one or more control signals can adjust the semiconductor manufacturing and characterization system 112 and / or one or more manufacturing processes or methods or one or more characterization processes or methods used by the semiconductor manufacturing and characterization system 112. The adjustments can be made either via a feed-forward loop (e.g., to correct current semiconductor devices) or a feedback loop (e.g., to adjust future semiconductor devices).

[0074] Although embodiments of the present disclosure depict steps of method or process 500 as being performed by controller 416, it is noted herein that some or all of the steps of method or process 500 may be performed by a server or controller communicatively coupled to controller 416. For example, a server or controller may include a processor and memory, as well as other communicatively coupled components as described throughout this disclosure.

[0075] It should be noted herein that the methods or processes 300 and 500 are not limited to the steps and / or sub-steps provided. The methods or processes 300 and 500 may include more or fewer steps and / or sub-steps. The methods or processes 300 and 500 may perform the steps and / or sub-steps simultaneously. The methods or processes 300 and 500 may perform the steps and / or sub-steps sequentially, including in the order provided or in an order other than that provided. Thus, the above description should not be construed as a limitation on the scope of the present disclosure, but merely as an example.

[0076] In this regard, unique data from I-PAT screening in semiconductor manufacturing and characterization system 112 can help improve several important metrics with significant business impact, improve tester productivity by enabling reduced testing on low defect rate "good" semiconductor die 206 and skipped testing on outlier-screened high defect rate semiconductor die 210, improve quality (with associated benefits for sharing and pricing) by removing outliers and flagging "at risk" semiconductor die 208 for adaptive testing that more thoroughly evaluates their suitability for the purpose, improve yield by reducing over-destruction of low defect rate "good" semiconductor die 206, and improve performance by providing insight into the effectiveness of various failure models in detecting in-line defects.

[0077] Combining I-PAT and characterization processes with adaptive testing allows correlated but separate data sources to proactively shape test programs and reduce costs while ensuring quality of results. For example, a test engineer may be responsible for testing automotive semiconductor devices to meet requirements for part per billion (PPB) level quality. Achieving PPB levels of quality may require extensive semiconductor device coverage and multiple overlapping test patterns, resulting in long and expensive test times with some redundancy. Cost pressures to reduce test times make the use of adaptive testing 118 economically attractive; however, incomplete knowledge of device quality makes the implementation of adaptive testing 118 a potential risk when wafer sort data and predictive statistical algorithms are the only inputs resulting in potential exposure to manufacturing excursions, latent defects, and localized random failures. In general, manufacturing quality teams are likely to benefit from connecting front-end manufacturing with back-end testing as a differentiating capability to demonstrate continuous improvement toward PPB goals.

[0078] The availability of defect data on 100% of the die and 100% of the wafer represents an inflection in the available sources of quality data for decision making. Risk can also be mitigated by feeding I-PAT scores 116 and metrology data from manufacturing screening tests to the adaptive test controller 104, allowing customized adaptive test 118 shaping against tangible data from the manufacturing history of the semiconductor device.

[0079] In a non-limiting example, if the adaptive test controller 104 identifies a defect in a shallow trench module of a semiconductor device, the adaptive test 118 may trigger more leakage testing.

[0080] In another non-limiting example, if the adaptive test controller 104 identifies a defect in a metal interconnect module of a semiconductor device, the adaptive test 118 may trigger more delay testing.

[0081] In another non-limiting example, if the adaptive test controller 104 identifies a set of semiconductor dies 206 with very low levels of defects, the adaptive test 118 may begin sub-sampling the test content (e.g., begin running a particular test pattern on only one out of every tenth die until a failure is observed) or even trigger content skipping to reduce the test content.

[0082] In another non-limiting example, if the adaptive test controller 104 identifies a short in the high-voltage analog domain that is difficult to test, the adaptive test 118 may be triggered to run more tests, extend the parametric test range, or simply cause the device to fail.

[0083] In another non-limiting example, if the adaptive test controller 104 identifies a semiconductor die 204 that has thickness / overlay variations at the gate level, the adaptive test 118 may trigger additional tests to determine the correct speed bin.

[0084] In another non-limiting example, if the adaptive test controller 104 identifies a defect that occurs within a certain proximity to an “N Detect” value of <3 (three or less) (where “N Detect” is the number of times one failure occurs with different overlapping test patterns), the adaptive test 118 may trigger additional testing.

[0085] In another non-limiting example, if the system identifies a defect that occurs within a certain proximity to an "N Detect" value >50, where "N Detect" is the number of times a single fault occurs with different overlapping test patterns, adaptive test 118 may be instructed to ignore the defect.

[0086] It should be noted that the above non-limiting examples are provided herein only for illustrative purposes of types of adaptive tests 118 and / or modifications to adaptive tests 118 and should not be construed as limiting.

[0087] Advantages of the present disclosure relate to systems and methods for semiconductor adaptive testing using in-line defect part average testing. Advantages of the present disclosure are also directed to using in-line defect screening and / or in-line part average testing (I-PAT) in conjunction with a semiconductor characterization process to identify semiconductor die outliers. Advantages of the present disclosure also relate to evaluating the suitability of a particular adaptive test program for a given semiconductor die. Advantages of the present disclosure are also directed to evaluating the suitability of a particular adaptive test parameter for a given semiconductor die.

[0088] In particular, advantages of the present disclosure relate to evaluating the suitability of a nominal test program or the need for an alternative test program for a given die. Advantages of the present disclosure are also directed to evaluating which test vectors, test patterns, or fault models should be applied to a semiconductor device under test. Advantages of the present disclosure are also directed to appending additional test vectors, test patterns, or fault models to a baseline test program. Advantages of the present disclosure are also directed to deciding to skip testing of dies deemed unlikely to save time and cost. Advantages of the present disclosure are also directed to triggering fail-continuation testing of semiconductor dies that require further characterization with new defect types. Advantages of the present disclosure are also directed to adjusting test limits for acceptable device performance. Advantages of the present disclosure are also directed to supplementing predictive statistical algorithms and wafer test data in rule-based decisions regarding test reduction and risk management. Advantages of the present disclosure are also directed to directing additional test vectors, test patterns, or fault models to one or more cores within a multi-core graphics processing unit (GPU), microprocessing unit (MPU), or system-on-chip (SoC) that have outlier levels of defects.

[0089] The subject matter described herein illustrates different components that are sometimes included within or connected to other components. It should be understood that such depicted architectures are merely exemplary, and that in fact many other architectures that achieve the same functionality may be implemented. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Thus, any two components herein that are combined to achieve a particular functionality can be considered to be "associated" with each other such that the desired functionality is achieved, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered to be "connected" or "coupled" with each other to achieve the desired functionality, and any two components capable of being so associated can also be considered to be "couplable" with each other to achieve the desired functionality. Specific examples of components that can be coupled include, but are not limited to, physically interactable and / or physically interacting components and / or wirelessly interactable and / or wirelessly interacting components and / or logically interactable and / or logically interacting components.

[0090] It is believed that the present disclosure and many of its attendant advantages will be understood from the foregoing description, and it will be apparent that various changes can be made in the form, construction and arrangement of the elements without departing from the disclosed subject matter or sacrificing all of its material advantages. The forms described are merely illustrative, and it is the intent of the following claims to embrace and include such modifications. It is to be understood, further, that the invention is defined by the appended claims.

Claims

1. 1. A system including an adaptive test controller communicatively coupled to an in-line defective part average testing (I-PAT) system, the adaptive test controller including one or more processors and a memory, the memory configured to store a set of program instructions, the one or more processors configured to execute the program instructions, The one or more processors execute the program instructions to: receiving a plurality of I-PAT scores from an I-PAT system, the plurality of I-PAT scores being generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, the semiconductor die data including characterization measurements for the plurality of semiconductor dies, each I-PAT score of the plurality of I-PAT scores representing a weighted defectivity determined by the I-PAT system based on the characterization measurements for a corresponding semiconductor die of the plurality of semiconductor dies; applying one or more rules to the plurality of I-PAT scores during the dynamic decision-making process; generating one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process; system.

2. 2. The system of claim 1, The one or more processors: The one or more processors execute the program instructions to: determining one or more adjustments to a semiconductor manufacturing and characterization system based on the one or more adaptive tests, wherein the semiconductor manufacturing and characterization system is configured to obtain characterization measurements of the semiconductor die data; system.

3. 2. The system of claim 1, at least one I-PAT score of the plurality of I-PAT scores corresponds to a low defectivity semiconductor die defined by a selected threshold, and the one or more adaptive tests include an optimized baseline test for the low defectivity semiconductor die; system.

4. 2. The system of claim 1, At least one I-PAT score of the plurality of I-PAT scores corresponds to a semiconductor die with a medium defectivity defined by a selected threshold and a second selected threshold, and the one or more adaptive tests include an adaptive test configured to add one or more test program parameters to a baseline test program for the semiconductor die with a medium defectivity, the one or more test program parameters including at least one of additional test vectors, test patterns, or fault models. system.

5. 2. The system of claim 1, at least one I-PAT score of the plurality of I-PAT scores corresponds to a high defectivity semiconductor die defined by a second selected threshold, and the one or more adaptive tests include a skip test configured to not test the high defectivity semiconductor die. system.

6. 2. The system of claim 1, at least one I-PAT score of the plurality of I-PAT scores corresponds to a high defectivity semiconductor die defined by a second selected threshold, and the one or more adaptive tests include tests configured to apply a complete characterization of defect detection and coverage to the high defectivity semiconductor die. system.

7. 2. The system of claim 1, The one or more processors execute the program instructions to: the dynamic decision-making process; at least one of one or more die-level electrical sort data generated by one or more electrical sort processes and one or more statistical prediction feedback generated by one or more statistical prediction processes; generating one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on system.

8. receiving a plurality of in-line defective part average test (I-PAT) scores from an I-PAT system via an adaptive test controller, wherein the plurality of I-PAT scores are generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, the semiconductor die data including characterization measurements for the plurality of semiconductor dies, and each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on the characterization measurements for a corresponding semiconductor die of the plurality of semiconductor dies; applying one or more rules to the plurality of I-PAT scores via the adaptive test controller during a dynamic decision-making process; generating, via the adaptive test controller, one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process; method.

9. 9. The method of claim 8, determining one or more adjustments to a semiconductor manufacturing and characterization system based on the one or more adaptive tests, wherein the semiconductor manufacturing and characterization system is configured to obtain characterization measurements of the semiconductor die data; method.

10. 9. The method of claim 8, at least one I-PAT score of the plurality of I-PAT scores corresponds to a low defectivity semiconductor die defined by a selected threshold, and the one or more adaptive tests include an optimized baseline test for the low defectivity semiconductor die; method.

11. 9. The method of claim 8, At least one I-PAT score of the plurality of I-PAT scores corresponds to a semiconductor die with a medium defectivity defined by a selected threshold and a second selected threshold, and the one or more adaptive tests include an adaptive test configured to add one or more test program parameters to a baseline test program for the semiconductor die with a medium defectivity, the one or more test program parameters including at least one of additional test vectors, test patterns, or fault models. method.

12. The method according to claim 8. at least one I-PAT score of the plurality of I-PAT scores corresponds to a high defectivity semiconductor die defined by a second selected threshold, and the one or more adaptive tests include a skip test configured to not test the high defectivity semiconductor die; method.

13. 9. The method of claim 8, at least one I-PAT score of the plurality of I-PAT scores corresponds to a high defectivity semiconductor die defined by a second selected threshold, and the one or more adaptive tests include tests configured to apply a complete characterization of defect detection and coverage to the high defectivity semiconductor die; method.

14. 9. The method of claim 8, at least one of one or more die-level electrical sort data generated by one or more electrical sort processes and one or more statistical prediction feedback generated by one or more statistical prediction processes; generating one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on method.

15. an in-line defective part average testing (I-PAT) subsystem configured to receive semiconductor die data for a plurality of semiconductor dies and generate a plurality of I-PAT scores based on the semiconductor die data, the semiconductor die data including characterization measurements for the plurality of semiconductor dies, each I-PAT score of the plurality of I-PAT scores representing a weighted defect rate determined by the I-PAT subsystem based on characterization measurements for a corresponding semiconductor die of the plurality of semiconductor dies; an adaptive test controller communicatively coupled to the I-PAT system, the adaptive test controller including one or more processors and a memory, the memory configured to store a set of program instructions; Including, The one or more processors execute the program instructions to: receiving a plurality of I-PAT scores from the adaptive test controller and the I-PAT system; applying one or more rules to the plurality of I-PAT scores during the dynamic decision-making process; generating one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process; system.

16. 16. The system of claim 15, a semiconductor manufacturing and characterization system configured to obtain the characterization measurements of the semiconductor die data; The one or more processors execute the program instructions to determining one or more adjustments to the semiconductor manufacturing and characterization system based on the one or more adaptive tests; system.

17. 16. The system of claim 15, at least one I-PAT score of the plurality of I-PAT scores corresponds to a low defectivity semiconductor die defined by a selected threshold, and the one or more adaptive tests include an optimized baseline test for the low defectivity semiconductor die; system.

18. 16. The system of claim 15, At least one I-PAT score of the plurality of I-PAT scores corresponds to a semiconductor die with a medium defectivity defined by a selected threshold and a second selected threshold, and the one or more adaptive tests include an adaptive test configured to add one or more test program parameters to a baseline test program for the semiconductor die with a medium defectivity, the one or more test program parameters including at least one of additional test vectors, test patterns, or fault models. system.

19. 16. The system of claim 15, at least one I-PAT score of the plurality of I-PAT scores corresponds to a high defectivity semiconductor die defined by a second selected threshold, and the one or more adaptive tests include a skip test configured to not test the high defectivity semiconductor die; system.

20. 16. The system of claim 15, at least one I-PAT score of the plurality of I-PAT scores corresponds to a high defectivity semiconductor die defined by a second selected threshold, and the one or more adaptive tests include tests configured to apply a complete characterization of defect detection and coverage to the high defectivity semiconductor die; system.

21. 16. The system of claim 15, at least one of one or more die-level electrical sort data generated by one or more electrical sort processes and one or more statistical prediction feedback generated by one or more statistical prediction processes; generating one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on system.

22. 16. The system of claim 15, 16. The system of claim 15, wherein the I-PAT system is configured to bin the I-PAT scores before transmitting to an adaptive test controller.

23. 16. The system of claim 15, 16. The system of claim 15, wherein the I-PAT system is configured to receive the semiconductor die data in a first data format and transmit the I-PAT scores in a second data format.

24. 16. The system of claim 15, the I-PAT system converts the I-PAT scores into a standardized data format before transmitting the I-PAT scores to the adaptive test controller. system.

25. 16. The system of claim 15, the adaptive test controller converts the I-PAT scores into a standardized data format after receiving the I-PAT scores from the I-PAT system. system.

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