Method for manufacturing semiconductor device, template substrate, semiconductor device, electronic device, and semiconductor device manufacturing apparatus

Abstract

This semiconductor device manufacturing method comprises: a step for preparing a main substrate, a base semiconductor part formed above the main substrate, and a compound semiconductor part formed on the base semiconductor part; and a step for separating the base semiconductor part and the compound semiconductor part so as to form a resonator surface on at least the compound semiconductor part, and separating the base semiconductor part and the compound semiconductor part into a plurality of element parts.

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] When a semiconductor device such as a semiconductor laser element is made smaller, the semiconductor device becomes difficult to handle. Patent Document 1 describes a technique related to the handling of a semiconductor laser element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2008-252069 Summary of the Invention

[0004] A method for manufacturing a semiconductor device in one aspect of the present disclosure includes the steps of preparing a main substrate, a base semiconductor portion formed above the main substrate, and a compound semiconductor portion formed on the base semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion so as to form a resonator surface in at least the compound semiconductor portion, and separating the base semiconductor portion and the compound semiconductor portion into a plurality of element portions.

[0005] In addition, a method for manufacturing a semiconductor device according to an aspect of the present disclosure includes the steps of preparing a main substrate, a base semiconductor portion formed above the main substrate, and a compound semiconductor portion formed on the base semiconductor portion, and dividing the base semiconductor portion and the compound semiconductor portion to form a plurality of optical resonators, each of which includes a resonator surface. In the step of forming the plurality of optical resonators, the main substrate is not divided, or the main substrate is divided into a number of resonators less than the number of the plurality of optical resonators.

[0006] A template substrate according to an aspect of the present disclosure includes a main substrate, a seed portion, and a mask, the mask including an elongated opening and a mask portion, the opening being provided with a notch.

[0007] A semiconductor device according to an embodiment of the present disclosure includes a base semiconductor portion and a compound semiconductor portion located above the base semiconductor portion and having an optical resonator including a pair of resonator faces. The base semiconductor portion and the compound semiconductor portion include a GaN-based semiconductor. The base semiconductor portion includes an m-plane cleavage plane of the GaN-based semiconductor. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view illustrating a structure of a semiconductor laser element according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a perspective view for explaining an optical resonator included in the semiconductor laser element. [Diagram 3] 4 is a flowchart illustrating an example of a manufacturing method of a semiconductor laser device according to an embodiment of the present disclosure. [Figure 4] 1A and 1B are a plan view and a cross-sectional view illustrating a configuration of a template substrate according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a cross-sectional view for explaining a semiconductor substrate according to an embodiment of the present disclosure. [Figure 6A] FIG. 11 is a plan view for explaining an example of an element isolation process. [Figure 6B] FIG. 6B is a cross-sectional view taken along the line B-VI shown in FIG. 6A. [Figure 7] 1 is a flowchart showing an example of a mounting stage of a manufacturing method for a semiconductor laser device according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is a block diagram showing an example of a manufacturing apparatus. [Figure 9] 4 is a flowchart showing an example of a method for manufacturing the semiconductor laser device in the first embodiment. [Figure 10]1 is a cross-sectional view showing a configuration of a template substrate in Example 1. FIG. [Figure 11A] FIG. 11 is an enlarged view of a main part of FIG. [Figure 11B] FIG. 2 is a plan view showing an example of the initiation inducing part of the first embodiment. [Figure 11C] FIG. 4 is a plan view showing another example of the initiation inducing part of the first embodiment. [Figure 11D] FIG. 4 is a plan view showing another example of the initiation inducing part of the first embodiment. [Figure 11E] FIG. 4 is a plan view showing another example of the initiation inducing part of the first embodiment. [Figure 12] 3 is a cross-sectional view showing an example of lateral growth of a base semiconductor layer in Example 1. FIG. [Figure 13] 4 is a plan view for explaining a base semiconductor layer in the first embodiment. FIG. [Figure 14] 4 is an enlarged view for explaining the growth of a base semiconductor layer around a triggering portion in Example 1. FIG. [Figure 15] 2 is a cross-sectional view showing a configuration of a compound semiconductor layer in Example 1. FIG. [Figure 16] FIG. 2 is a plan view for explaining a compound semiconductor layer in the first embodiment. [Figure 17] FIG. 2 is a plan view for explaining an example of an element isolation process in the first embodiment. [Figure 18] FIG. 2 is an exploded perspective view for explaining the configuration of a half element portion in the first embodiment. [Figure 19] FIG. 2 is a perspective view for explaining a configuration of an element portion in the first embodiment. [Figure 20] 2 is a cross-sectional view showing the configuration of an element portion in Example 1. FIG. [Figure 21] 4A to 4C are cross-sectional views that typically show a step of separating an element portion from a template substrate in the manufacturing method of the semiconductor laser element of Example 1. [Figure 22] FIG. 2 is a perspective view showing a state in which an element portion is bonded to a support substrate. [Figure 23]1 is a cross-sectional view showing a schematic state in which a device portion DS is bonded to a support substrate SK. [Figure 24] 4A to 4C are cross-sectional views illustrating a process of forming a reflective film on a cavity facet in a manufacturing method of the semiconductor laser device of Example 1. [Diagram 25] FIG. 2 is a plan view showing the configuration of the compound semiconductor layer after a reflector film is formed. [Figure 26] 4A to 4C are cross-sectional views that typically show a step of dividing a support substrate in a manufacturing method for the semiconductor laser device of Example 1. [Figure 27] 4 is a plan view for explaining another example of the base semiconductor layer in Example 1. FIG. [Figure 28] 13 is an exploded perspective view for explaining another configuration example of the half element portion in the first embodiment. FIG. [Figure 29] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor laser element in Example 2. [Diagram 30] 5A to 5C are schematic cross-sectional views showing an example of a manufacturing method for the semiconductor laser device in Example 2. [Diagram 31] 10 is a flowchart showing an example of a method for manufacturing a semiconductor laser device in Example 3. [Diagram 32] 11 is a plan view showing a configuration of a semiconductor substrate on which a base semiconductor layer is formed in Example 3. FIG. [Diagram 33] 13 is a plan view showing a configuration of a semiconductor substrate on which an element structure is formed in Example 3. FIG. [Diagram 34] 34 is a cross-sectional view showing the configuration of the semiconductor substrate of FIG. 33. [Diagram 35] FIG. 13 is a plan view showing an example of element isolation in the fourth embodiment. [Diagram 36] FIG. 13 is a schematic diagram illustrating a configuration of an electronic device in a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings. Note that the following description is for better understanding of the gist of the present disclosure, and does not limit the present disclosure unless otherwise specified. Unless otherwise specified in this specification, "A to B" representing a numerical range means "A or more and B or less." In addition, the shapes and dimensions (length, width, etc.) of the configurations shown in each drawing in this application do not necessarily reflect the actual shapes and dimensions, and have been appropriately changed for the clarity and simplification of the drawings.

[0010] In the embodiment of the present disclosure, a semiconductor laser (Laser Diode; LD) element will be described as an example of a semiconductor device, but the semiconductor device of the present disclosure is not necessarily limited to this. The semiconductor device of the present disclosure may be, for example, a sensor having an optical resonator or a sensor on which a resonator surface is formed.

[0011] In the following description, first, a structure of a semiconductor laser element according to an embodiment of the present disclosure will be generally described, and then a manufacturing method of the semiconductor laser element according to an embodiment of the present disclosure will be described in detail.

[0012] [Semiconductor laser element] A semiconductor laser element 20 according to an embodiment of the present disclosure will be described below with reference to Fig. 1 and Fig. 2. Fig. 1 is a perspective view for explaining the structure of the semiconductor laser element 20. Fig. 2 is a perspective view for explaining an optical resonator LK of the semiconductor laser element 20. Note that Fig. 1 is merely an example, and the semiconductor laser element 20 may have a shape in which the depth direction in the perspective view shown in Fig. 1 is the longitudinal direction.

[0013] The semiconductor laser element 20 in one embodiment of the present disclosure has a structure having electrodes on the upper and lower sides (hereinafter referred to as a "double-sided electrode structure"), but is not limited thereto, and may have, for example, a structure having two electrodes (anode and cathode) on the upper side (hereinafter referred to as a "single-sided two-electrode structure"). The semiconductor laser element 20 may be mounted on a support substrate (also referred to as a submount), and the support substrate is omitted in FIG. 1.

[0014] 1 and 2, a semiconductor laser element (semiconductor device) 20 in this embodiment includes a base semiconductor portion 8, a compound semiconductor portion 9 located above the base semiconductor portion 8 and including an optical resonator LK, a first electrode E1, a second electrode E2, and an insulating film DF. In the optical resonator LK, a surface from which a laser beam is emitted is defined as an emission surface F1, and a surface facing the emission surface F1 is defined as an opposing surface F2. The emission surface F1 and the opposing surface F2 are a pair of resonator surfaces in the optical resonator LK. Note that the specific aspect (element structure) of the optical resonator LK is not particularly limited.

[0015] The base semiconductor portion 8 and the compound semiconductor portion 9 are typically layered. Therefore, the base semiconductor portion 8 can also be called a base semiconductor layer 8, and the compound semiconductor portion 9 can also be called a compound semiconductor layer 9. In the following description, they will be referred to as the base semiconductor layer 8 and the compound semiconductor layer 9, but the base semiconductor layer 8 and the compound semiconductor layer 9 are not necessarily limited to being layered.

[0016] The base semiconductor layer 8 may include, for example, a nitride semiconductor. The nitride semiconductor can be expressed as, for example, AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include gallium nitride (GaN)-based semiconductor, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor layer 8 may be a doped type (e.g., n-type containing a donor) layer, or a non-doped type layer.

[0017] Moreover, the compound semiconductor layer 9 may include, for example, the above-mentioned nitride semiconductor. Here, it is generally difficult to reduce the defect density of a nitride semiconductor. If the base semiconductor layer 8 has few surface defects, the dislocations (defects) inherited from the base semiconductor layer 8 to the compound semiconductor layer 9 are reduced. This makes it possible to reduce the defect density of the compound semiconductor layer 9. The semiconductor laser element 20 in this embodiment may have, as the base semiconductor layer 8, a semiconductor layer formed by an ELO (Epitaxial Lateral Overgrowth) method (hereinafter, sometimes referred to as an ELO semiconductor layer). Note that the base semiconductor layer 8 is not limited to an ELO semiconductor layer as long as it can reduce the defect density of the optical resonator LK of the compound semiconductor layer 9.

[0018] The method for manufacturing the base semiconductor layer 8 is not particularly limited, and the base semiconductor layer 8 may be, for example, a general semiconductor layer including a nitride semiconductor. The "general semiconductor layer" means a semiconductor layer epitaxially grown in the vertical direction on a growth substrate. In this specification, such a general semiconductor layer may be referred to as a "GE semiconductor layer" for convenience of explanation. The GE semiconductor layer can be formed by a known method, and therefore explanation thereof will be omitted.

[0019] In this specification, a substrate used for growing various semiconductor layers of a semiconductor laser element may be referred to as a "growth substrate".

[0020] In this embodiment, a semiconductor laser device 20 in which the base semiconductor layer 8 is an ELO semiconductor layer, as shown in Fig. 1, will be described. A method for manufacturing the base semiconductor layer 8 using the ELO method will be described later.

[0021] The base semiconductor layer 8, which is an ELO semiconductor layer, includes a first part (first portion) B1, and a second part (second portion) B2 and a third part (third portion) B3 in which the density (threading dislocation density) of threading dislocations KD extending in the thickness direction (Z direction) is smaller than that of the first part B1. The second part B2, the first part B1, and the third part B3 are arranged in this order in the X direction, and the first part B1 is located between the second part B2 and the third part B3. The threading dislocations KD are dislocations (defects) that extend from the lower surface or the inside of the base semiconductor layer 8 to its surface or surface layer along the thickness direction of the base semiconductor layer 8. The threading dislocation density of the second part B2 and the third part B3 is 1 / 5 or less (e.g., 5×10) of the threading dislocation density of the first part B1. 6 / cm 2 (see below).

[0022] In the semiconductor laser element 20, a compound semiconductor layer 9 including a plurality of layers is stacked on a base semiconductor layer 8, and the stacking direction can be referred to as the "upper direction". Hereinafter, the Z-axis positive side of the XYZ coordinate system shown in FIG. 1 may be referred to as the "upper side", and the Z-axis negative side may be referred to as the "lower side". In addition, the surface of each member on the Z-axis positive side may be referred to as the "upper surface", and the surface of each member on the Z-axis negative side may be referred to as the "lower surface". For a substrate-like or substantially substrate-like object such as the semiconductor laser element 20, viewing the object with a line of sight parallel to the normal direction of the upper surface can be referred to as a "planar view". Although not described again below, the up-down direction is defined in the same manner in other figures, and the expression "in a planar view" may be used.

[0023] The compound semiconductor layer 9 includes, from the base semiconductor layer 8 upward, an n-type semiconductor portion (first type semiconductor portion) 9N, an active portion 9K, and a p-type semiconductor portion (second type semiconductor portion) 9P, in this order. The n-type semiconductor portion 9N, the active portion 9K, and the p-type semiconductor portion 9P are typically layered. Therefore, the n-type semiconductor portion 9N can also be called an n-type semiconductor layer 9N. The active portion 9K can also be called an active layer 9K. The p-type semiconductor portion 9P can also be called a p-type semiconductor layer 9P. In the following description, the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P are referred to as the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P, but they are not necessarily limited to being layered.

[0024] The p-type semiconductor layer 9P may have a ridge portion RJ. The n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P may contain the above-mentioned nitride semiconductors. The various layers included in the compound semiconductor layer 9 will be described in detail later. The compound semiconductor layer 9 may have a high threading dislocation density above the first portion B1 due to the influence of the first portion B1 of the base semiconductor layer 8.

[0025] The compound semiconductor layer 9 has an optical resonator LK at a position overlapping with the second portion B2 in a plan view. The optical resonator LK includes a waveguide extending between an emission face F1 and an opposing face F2 that constitute a pair of resonator faces. The distance between the emission face F1 and the opposing face F2 can be set as a resonator length (resonance length) L1 of the optical resonator LK. An end face of the active layer 9K included in the emission face F1 and an end face of the active layer 9K included in the opposing face F2 may each be coated with a reflective film (e.g., a dielectric film).

[0026] At least one of the emission surface F1 and the opposing surface F2 of the semiconductor laser element 20 may be an m-plane or a c-plane of the compound semiconductor layer 9 containing a nitride semiconductor. In FIG. 1 and other figures, the positive X-axis direction in the XYZ coordinate system can be the [11-20] direction of the nitride semiconductor, the positive Y-axis direction can be the [-1100] direction of the nitride semiconductor, and the positive Z-axis direction (thickness direction) can be the

[0001] direction of the nitride semiconductor. The m-plane that at least one of the emission surface F1 and the opposing surface F2 can have is a plane parallel to the (1-100) plane (or the (-1100) plane) of the nitride semiconductor. The c-plane that at least one of the emission surface F1 and the opposing surface F2 can have is a plane parallel to the (0001) plane of the nitride semiconductor.

[0027] In the semiconductor laser element 20, at least one of the emission surface F1 and the opposing surface F2 may be included in a cleavage surface of the compound semiconductor layer 9. Each of the emission surface F1 and the opposing surface F2 may be included in a cleavage surface of the compound semiconductor layer 9. The semiconductor laser element 20 may also be configured such that the cavity length L1 is 200 [μm] or less.

[0028] The semiconductor laser element 20 is provided with a first electrode E1 and a second electrode E2 for supplying a current to the optical resonator LK. The first electrode E1 can be disposed so as to overlap with the optical resonator LK in a plan view seen in the thickness direction of the base semiconductor layer 8. Note that "two members overlap" in a plan view means that at least a part of one member overlaps the other member in a plan view (including a perspective plan view) seen in the thickness direction of each member, and these members may or may not be in contact with each other.

[0029] The first electrode E1 may be located above the compound semiconductor layer 9, overlap at least a part of the ridge portion RJ in a plan view, and have a shape extending along the longitudinal direction of the optical resonator LK. The first electrode E1 is electrically connected to the ridge portion RJ in the p-type semiconductor layer 9P and functions as an anode. The first electrode E1 and the ridge portion RJ may be in contact with each other or may be connected via another layer.

[0030] The second electrode E2 may be located below the compound semiconductor layer 9, and is disposed, for example, on the lower surface of the base semiconductor layer 8. The second electrode E2 may have a shape that overlaps at least a part of the first electrode E1 in a plan view. The second electrode E2 is electrically connected to the base semiconductor layer 8 and functions as a cathode. The second electrode E2 and the base semiconductor layer 8 may be in contact with each other or may be connected via another layer. The second electrode E2 may be in contact with the compound semiconductor portion 9 (for example, the n-type semiconductor layer 9N).

[0031] The insulating film DF is located above the compound semiconductor layer 9. The insulating film DF may cover the upper surface of the p-type semiconductor layer 9P except for the contact portion between the first electrode E1 and the ridge portion RJ.

[0032] [Manufacture of Semiconductor Laser Device] A semiconductor laser may be manufactured from a stack including multiple semiconductor layers (called the conventional CT method). In the conventional CT method, multiple semiconductor lasers are formed on a growth substrate, and the multiple semiconductor lasers are then separated together with the growth substrate.

[0033] The present inventors have conducted extensive research into techniques different from the conventional technique CT and have arrived at the method for manufacturing a semiconductor laser device according to the present disclosure. In general, the semiconductor laser device 20 in this embodiment is manufactured by a technique including a step of forming an optical resonator on a growth substrate (at least forming a resonator facet in the compound semiconductor layer 9).

[0034] Hereinafter, a method for manufacturing a semiconductor laser element (a semiconductor laser element in which the base semiconductor layer 8 is an ELO semiconductor layer) according to an embodiment of the present disclosure will be described. Fig. 3 is a flowchart showing an example of a method for manufacturing the semiconductor laser element according to this embodiment. Fig. 4 is a plan view and a cross-sectional view showing the configuration of a template substrate according to this embodiment.

[0035] (Process for preparing a template substrate) As shown in Fig. 3, in the method for manufacturing a semiconductor laser device according to an embodiment of the present disclosure, first, a template substrate is prepared. As shown in Fig. 4, the template substrate 7 according to this embodiment has a main substrate 1, an underlayer 4 located above the main substrate 1, and a mask 6 located above the main substrate 1 and having an opening KS and a mask portion 5. Hereinafter, the main substrate 1 and the underlayer 4 may be collectively referred to as the underlayer substrate UK. The underlayer substrate UK and the template substrate 7 are an example of the growth substrate described above.

[0036] The base portion 4 and the mask 6 are typically layered. Therefore, the base portion 4 can also be called the base layer 4, and the mask 6 can also be called the mask layer 6. In the following description, they are referred to as the base layer 4 and the mask layer 6, but the base layer 4 and the mask layer 6 are not necessarily limited to being layered. The mask 6 may be a mask pattern including a mask portion 5 and an opening KS. The opening KS is a region where the mask portion 5 does not exist, and the opening KS does not necessarily have to be surrounded by the mask portion 5.

[0037] The main substrate 1 may be a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor. Examples of heterogeneous substrates include a silicon (Si) substrate, a sapphire (Al2O3) substrate, and a silicon carbide (SiC) substrate. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a Si substrate, the (0001) surface of an Al2O3 substrate, or the 6H-SiC (0001) surface of a SiC substrate. However, these are merely examples, and the main substrate 1 is not particularly limited as long as it is a substrate and has a surface orientation on which the base semiconductor layer 8 can be grown by the ELO method.

[0038] The template substrate 7 may have, as the underlayer 4, a buffer portion 2 and a seed portion 3 in this order from the main substrate 1 side. The buffer portion 2 and the seed portion 3 are typically layered. Therefore, the buffer portion 2 can also be called a buffer layer 2, and the seed portion 3 can also be called a seed layer 3. In the following description, they are referred to as the buffer layer 2 and the seed layer 3, but the buffer layer 2 and the seed layer 3 are not necessarily limited to being layered.

[0039] The buffer layer 2 is a melting suppression layer that can reduce the possibility that the main substrate 1 and the seed layer 3 come into direct contact with each other and melt. It also has the effect of increasing the crystallinity of the seed layer 3. The seed layer 3 is a layer that is a growth starting point of the base semiconductor layer 8 when the base semiconductor layer 8 described later is formed. In addition, when the main substrate 1 that does not melt with the seed layer 3, which is a GaN-based semiconductor, is used, it is possible to configure without providing the buffer layer 2. On the other hand, when a Si substrate or the like is used for the main substrate 1, the GaN-based semiconductor and the Si substrate may melt with each other when the GaN-based semiconductor contained in the seed layer 3 comes into contact with the Si substrate. Therefore, for example, a buffer layer 2 such as an AlN layer or a SiC layer is provided. This can reduce the possibility that the GaN-based semiconductor and the Si substrate melt.

[0040] The mask layer 6 formed on the base substrate UK has a plurality of mask portions 5 and a plurality of openings KS. The mask portions 5 and the openings KS may each have a longitudinal shape with the first direction (X direction) as the width direction and the second direction (Y direction) as the length direction. The openings KS may have a tapered shape (a shape in which the width narrows downward). The mask layer 6 may be an inorganic insulating film such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride film (SiON), or a titanium nitride (TiNx) film. The mask layer 6 may be a laminated film containing the above materials, for example, a laminated film containing a silicon oxide film and a silicon nitride film.

[0041] The mask layer 6 may be formed, for example, as follows. That is, a SiO2 film is formed on the entire surface of the base substrate UK by sputtering, and then wet-etched while being partially protected by resist. A part of the SiO2 film is removed to form the mask portion 5 and the opening KS.

[0042] The opening KS of the mask layer 6 functions as a growth initiation hole that exposes the seed layer 3 and starts the growth of the base semiconductor layer 8, and the mask portion 5 of the mask layer 6 functions as a selective growth mask that laterally grows the base semiconductor layer 8. The width WK of the opening KS may be, for example, about 0.1 μm to 20 μm. The smaller the width of the opening KS, the smaller the number of threading dislocations that propagate from the opening KS to the base semiconductor layer 8. In addition, the peeling of the base semiconductor layer 8 in a later process may be facilitated. Furthermore, the areas of the second portion B2 and the third portion B3 with fewer surface defects can be increased. The width WM of the mask portion 5 may be, for example, about 25 μm to 200 μm.

[0043] In the method for manufacturing the semiconductor laser device in this embodiment, for example, in the step of preparing the template substrate 7, the mask layer 6 may be formed so that the opening KS has a notched shape, in other words, so that the mask portion 5 has a shape that partially protrudes in the X direction. Hereinafter, the part of the mask portion 5 that partially protrudes in the X direction is referred to as an origin inducing portion. By having the origin inducing portion in the mask layer 6, the base semiconductor layer 8 and the compound semiconductor layer 9 can be formed on the template substrate 7 so as to have an origin portion that becomes the origin of cleavage. This will be described in detail in Example 1 below.

[0044] (Step of forming a semiconductor layer) 5 is a cross-sectional view for explaining the semiconductor substrate in this embodiment. A method for manufacturing a semiconductor laser device in one aspect of the present disclosure may include a step of forming a semiconductor layer (see FIG. 3). In the step of forming the semiconductor layer, for example, a base semiconductor layer 8 is formed on a template substrate 7 by an ELO method, and then a compound semiconductor layer 9 is formed above the base semiconductor layer 8.

[0045] In the ELO method, for example, a seed layer 3 containing a GaN-based semiconductor is used, and an inorganic compound film such as a SiO2 film is used as the mask layer 6, and the base semiconductor layer 8 can be grown laterally on the mask portion 5. The thickness direction (Z direction) of the base semiconductor layer 8 formed by the ELO method is the thickness direction (Z direction) of the GaN-based crystal. <0001> The direction (c-axis direction) of the aperture KS can be the <11-20> direction (a-axis direction) of the GaN-based crystal, and the longitudinal direction (Y direction) of the aperture KS can be the <1-100> direction (m-axis direction) of the GaN-based crystal.

[0046] As shown in FIG. 5, the base semiconductor layer 8 includes a second portion B2 and a third portion B3 that overlap the mask portion 5 in a plan view and have relatively few threading dislocations KD, and a first portion B1 that overlaps the opening KS in a plan view and has more threading dislocations KD than the second portion B2 and the third portion B3. The compound semiconductor layer 9 includes many threading dislocations KD above the first portion B1 due to the influence of the threading dislocations KD present on the surface of the first portion B1. The optical resonator LK can be provided so as to overlap the second portion B2 in a plan view. This reduces the possibility that the performance of the optical resonator LK will be deteriorated due to the influence of the threading dislocations KD. This is because the compound semiconductor layer 9 on the second portion B2 has a relatively small amount of dislocations (defects) introduced due to surface defects of the second portion B2 during the deposition of the compound semiconductor layer 9.

[0047] The threading dislocations KD are dislocations (defects) that extend from the lower surface or the inside of the base semiconductor layer 8 to the surface or surface layer of the base semiconductor layer 8 along the thickness direction of the base semiconductor layer 8. The threading dislocations KD can be observed by, for example, performing CL (cathode luminescence) measurement on the surface (parallel to the c-plane) of the base semiconductor layer 8.

[0048] Part 2 B2 or Part 3 B3: <0001> The non-threading dislocation density in a cross section parallel to the thickness direction may be greater than the threading dislocation density on the top surface. The non-threading dislocations are dislocations measured by CL in a cross section along a plane parallel to the thickness direction, and are primarily basal plane (c-plane) dislocations.

[0049] The semiconductor substrate 10 in this embodiment may have a template substrate 7 and a base semiconductor layer 8 formed on the template substrate 7. The semiconductor substrate 10 may also have the template substrate 7, the base semiconductor layer 8, and a compound semiconductor layer 9 formed above the base semiconductor layer 8.

[0050] In the semiconductor substrate 10 of this embodiment, a plurality of base semiconductor layers 8 are formed so as to have a gap Gp between different base semiconductor layers 8. The width WG of the gap Gp may be 4 μm or less, or may be 3 μm or less. Note that the semiconductor substrate 10 is not limited to having the gap Gp, and the base semiconductor layers 8 grown laterally from the seed layer 3 exposed in two adjacent openings KS may be in contact (meet) with each other on the mask portion 5.

[0051] When the base semiconductor layer 8 is formed using the ELO method, a template substrate 7 including the main substrate 1 and the mask layer 6 on the main substrate 1 may be used, and the template substrate 7 may have a growth inhibition region (e.g., a region that inhibits crystal growth in the Z direction) corresponding to the mask portion 5, and a seed region corresponding to the opening KS. For example, the growth inhibition region and the seed region may be formed on the main substrate 1, and the base semiconductor layer 8 may be formed on the growth inhibition region and the seed region using the ELO method.

[0052] (Process of isolating elements on a template substrate) Fig. 6A is a plan view for explaining an example of an element isolation process, and Fig. 6B is a cross-sectional view taken along line B-VI shown in Fig. 6A.

[0053] In the manufacturing method of the semiconductor laser device in this embodiment, the base semiconductor layer 8 and the compound semiconductor layer 9 may be separated into a plurality of half-element portions (first element portions) sDS on the template substrate 7 so as to form a resonator surface at least in the compound semiconductor layer 9. Here, the "half-element portion sDS" means a portion (laminated body) including one piece 8V of the base semiconductor layer 8 and one piece 9V of the compound semiconductor layer 9 located above the one piece 8V of the base semiconductor layer 8, among a plurality of pieces aligned along the Y-axis direction formed by dividing the base semiconductor layer 8 and the compound semiconductor layer 9 on the template substrate 7. The half-element portion sDS can be said to be a kind of element portion, but since it does not have members such as electrodes for driving as an element, it can be positioned as a state in the middle of manufacturing the element portion as a product, that is, a semi-finished product. Such a half-element portion sDS also falls within the category of the semiconductor device of the present disclosure. The boundary between adjacent half-element portions sDS is called a division portion PS, and the division portion PS is indicated by a thick black line in FIG. 6A and FIG. 6B.

[0054] In this specification, separation of the base semiconductor layer 8 and the compound semiconductor layer 9 on the template substrate 7 into a plurality of semi-element portions sDS may be referred to as “element isolation.” “Element isolation” refers to the following (i) and (ii). (i) At the time when the base semiconductor layer 8 and the compound semiconductor layer 9 are separated on the template substrate 7, each of the multiple semi-element portions sDS has an optical resonator LK individually (in other words, each of the multiple semi-element portions sDS has a resonator surface formed in at least the compound semiconductor layer 9 individually). (ii) Until the half element portion sDS becomes an element portion (second element portion) DS through a later process, the piece 8V of the base semiconductor layer 8 and the piece 9V of the compound semiconductor layer 9 of the half element portion sDS are not further divided.

[0055] In Fig. 6B, various forms of the division portion PS are illustrated, but are not limited thereto. As shown in Fig. 6B, in the process of isolating elements on the template substrate 7, in the division portion PS, a part or all of the mask portion 5 in the thickness direction of the semiconductor substrate 10 may be divided, the mask portion 5 may not be divided, or the mask portion 5 and the underlayer 4 may be divided. In this process, the main substrate 1 may not be divided at all in the thickness direction. Note that a crack may occur in a part of the main substrate 1 in the thickness direction.

[0056] In the manufacturing method of the semiconductor laser device of this embodiment, the specific method of the step of separating elements on the template substrate 7 is not particularly limited. For example, as described above, the mask layer 6 may be formed so that the mask portion 5 has an origin inducing portion, and then the base semiconductor layer 8 may be formed. In this case, the base semiconductor layer 8 may have an origin portion that is a portion that is likely to become the origin of cleavage. In addition, like the base semiconductor layer 8, the compound semiconductor layer 9 may also have an origin portion of cleavage. A plurality of half element portions sDS may be formed by cleavage occurring from the origin portion due to thermal stress or physical external force. Note that cleavage may be caused in the base semiconductor layer 8 before the compound semiconductor layer 9 is formed. In this case, the compound semiconductor layer 9 may be formed on each of the plurality of pieces of the base semiconductor layer 8 after cleaving the base semiconductor layer 8. The compound semiconductor layer 9 can be separated into a plurality of half element portions sDS by cleaving or dividing the compound semiconductor layer 9.

[0057] Also, for example, the mask portion 5 may not have an initiation point inducing portion, and in this case, an initiation point of cleavage may be formed in the base semiconductor layer 8 or the compound semiconductor layer 9 by processing such as scribing. Cleavage may be caused from the initiation point by applying an external force to at least one of the base semiconductor layer 8 and the compound semiconductor layer 9. Furthermore, cleavage may be naturally caused to proceed by internal stress of the base semiconductor layer 8 and the compound semiconductor layer 9 by scribing the compound semiconductor layer 9.

[0058] Also, for example, the base semiconductor layer 8 or the compound semiconductor layer 9 can be etched to separate the device into a plurality of semi-device portions sDS. In this case, the separation portions PS may be grooves (trench) formed by etching.

[0059] As described above, the method for manufacturing the semiconductor laser device in this embodiment may include (i) a step of preparing the main substrate 1, the base semiconductor portion 8 formed above the main substrate 1, and the compound semiconductor portion 9 formed on the base semiconductor portion 8, and (ii) a step of separating the base semiconductor portion 8 and the compound semiconductor portion 9 so as to form a resonator surface in at least the compound semiconductor portion 9, and separating the base semiconductor portion 8 and the compound semiconductor portion 9 into a plurality of element portions (e.g., half element portions sDS). In the step of separating into a plurality of element portions, the device may be separated into a plurality of half element portions sDS having resonator surfaces (e.g., emission surface F1 and opposing surface F2) on a growth substrate (e.g., on a template substrate 7). By separating the base semiconductor layer 8 and the compound semiconductor layer 9 into a plurality of element portions (e.g., half element portions sDS), an optical resonator LK including resonator surfaces (e.g., emission surface F1 and opposing surface F2) may be formed.

[0060] The method for manufacturing the semiconductor laser element in this embodiment includes the steps of (i) preparing a main substrate 1, a base semiconductor portion 8 formed above the main substrate 1, and a compound semiconductor portion 9 formed on the base semiconductor portion 8, and (ii) dividing the base semiconductor portion 8 and the compound semiconductor portion 9 to form a plurality of optical resonators LK, each of which includes a resonator surface (e.g., an emission surface F1 and an opposing surface F2). For example, the base semiconductor layer 8 and the compound semiconductor layer 9 may be divided on a growth substrate (e.g., on a template substrate 7) to form a plurality of optical resonators LK, each of which includes a resonator surface. In the step of forming the plurality of optical resonators LK, the main substrate 1 may not be divided, or the main substrate 1 may be divided into a number of pieces less than the number of optical resonators LK. For example, the main substrate 1 may be divided so that one of the pieces formed by dividing the main substrate 1 has a plurality of semi-element portions sDS.

[0061] According to the method for manufacturing the semiconductor laser device in this embodiment, the resonator facet can be easily formed even when the semiconductor laser device 20 is miniaturized. Therefore, the optical resonator LK can be easily formed. Then, by peeling the formed device portion DS from the growth substrate as described below, the device portion DS can be mounted on a support substrate to manufacture the semiconductor laser device 20. This improves handling. Also, a substrate suitable for mounting can be used as the support substrate.

[0062] (Process for forming element structure) In the method for manufacturing the semiconductor laser device in this embodiment, a step of forming an element structure for the half element portion sDS on the template substrate 7 is performed. This forms the element portion DS. At this stage, the base semiconductor layer 8 included in the element portion DS is van der Waals bonded to the mask portion 5, and the element portion DS may be a part of the semiconductor substrate 10.

[0063] In the step of forming the element structure, for example, after forming a ridge portion RJ in the p-type semiconductor layer 9P in the compound semiconductor layer 9, an insulating film DF is formed, and then a first electrode E1 (anode) is formed at a position in contact with the ridge portion RJ. Then, for example, in the case where the semiconductor laser element 20 has a one-sided two-electrode structure, a part of the upper surface of the base semiconductor layer 8 may be exposed by etching or the like, and then a second electrode E2 may be formed on the upper surface of the base semiconductor layer 8. This can form the element portion DS. By providing the ridge portion RJ and the insulating film DF, the element portion DS can narrow the current path between the first electrode E1 and the base semiconductor layer 8 on the anode side, and can efficiently emit light in the resonator LK. Moreover, the ridge portion RJ may overlap the second portion B2 (low dislocation portion) of the base semiconductor portion 8 in a plan view, and may not overlap the first portion B1. The second electrode E2 may overlap the second portion B2 (low dislocation portion) of the base semiconductor portion 8 in a plan view. As a result, a current path from the first electrode E1 through the compound semiconductor portion 9 and the base semiconductor portion 8 to the second electrode E2 is formed in a portion (portion with few threading dislocations) that overlaps with the second portion B2 in a planar view, and the light emission efficiency in the active layer 9K is improved. This is because the threading dislocations act as non-radiative recombination centers. The second electrode E2 may also overlap with the second portion B2 and the third portion B3 (low-dislocation portions) of the base semiconductor portion 8 in a planar view, in which case the efficiency of electron injection from the second electrode E2 to the base semiconductor portion 8 is improved.

[0064] In the case where the semiconductor laser element 20 has a double-sided electrode structure, the second electrode E2 may be formed in a later step. In this specification, an element having an element structure not having the second electrode E2 obtained by the step of forming an element structure is also referred to as an element portion DS.

[0065] (Process for mounting element part) FIG. 7 is a flow chart showing an example of a mounting stage in a manufacturing method for a semiconductor laser device according to this embodiment.

[0066] As shown in FIG. 7, first, a step of separating the element portion DS from the template substrate 7 is performed. For example, after bonding the first electrode E1 to a pad of a support substrate, the element portion DS can be separated from the template substrate 7 using the support substrate. Then, a step of coating an end face of the optical resonator LK of the element portion DS may be performed to form the semiconductor laser element 20. The support substrate on which the element portion DS is mounted may be divided to form the semiconductor laser element 20. The support substrate may function as a submount, and thus a chip on which the semiconductor laser element 20 is mounted can be formed on the divided support substrate. A specific example of the support substrate will be described later.

[0067] According to the manufacturing method of the semiconductor laser device 20 in this embodiment, the template substrate 7 or the base substrate UK can be reused. Moreover, the semiconductor laser device 20 can be formed by transferring the device portion DS from a substrate unsuitable for mounting to a substrate (support substrate) suitable for mounting.

[0068] [Manufacturing equipment] Fig. 8 is a block diagram showing an example of a manufacturing apparatus. As shown in Fig. 8, a manufacturing apparatus 70 includes a semiconductor layer forming section 72 that forms a base semiconductor layer 8 and a compound semiconductor layer 9 on a template substrate 7, a processing section 73 that forms an element structure, and a control section 74 that controls the semiconductor layer forming section 72 and the processing section 73.

[0069] The semiconductor layer forming unit 72 may include, for example, an MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus, and forms a base semiconductor layer 8 by using an ELO method, and forms a compound semiconductor layer 9 on the base semiconductor layer 8. When the processing object is removed from a processing apparatus (film forming apparatus) such as an MOCVD apparatus, an element isolation process may be performed. The semiconductor layer forming unit 72 may be controlled so that after forming the base semiconductor layer 8, the processing object is temporarily removed from the processing apparatus, and then the processing object is again loaded into the processing apparatus to form the compound semiconductor layer 9 on the base semiconductor layer 8. The semiconductor layer forming unit 72 may have a function of manufacturing the template substrate 7.

[0070] The processing unit 73 may perform a process of isolating elements to form the semi-element portion sDS. The processing unit 73 performs various processes on the semi-element portion sDS located on the template substrate 7 to form the element portion DS. The processing unit 73 may perform a process of isolating the element portion DS from the template substrate 7 by using a support substrate, or may perform a process of coating the end face of the optical resonator LK.

[0071] The control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the semiconductor layer forming unit 72 and the processing unit 73 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network. The above program and a recording medium on which the above program is stored are also included in this embodiment.

[0072] Other Embodiments (a) In the manufacturing method of the semiconductor laser device 20 according to another embodiment of the present disclosure, a GaN substrate may be used as a growth substrate instead of the base substrate UK, in which case the main substrate 1 may be a GaN substrate. That is, the main substrate 1 may be a growth substrate. A semiconductor substrate in which a semiconductor layer containing a nitride semiconductor (the above-mentioned GE semiconductor layer) is formed on a GaN substrate without forming a mask layer 6 may also be used.

[0073] For example, by removing a part of the GE semiconductor layer in the semiconductor substrate by etching, it is possible to form a plurality of island-shaped semiconductor layers having a shape as shown in Fig. 5. Then, after forming a compound semiconductor layer on this semiconductor layer, a device isolation process is performed to form a plurality of half-element portions sDS.

[0074] (b) In the manufacturing method of the semiconductor laser device 20 according to another embodiment of the present disclosure, the method is not limited to using a template substrate 7 in which the seed layer 3 overlaps the entire mask portion 5. Since the seed layer 3 only needs to be exposed from the opening KS, a template substrate 7 in which the seed layer 3 is locally formed so as not to overlap a part or all of the mask portion 5 may be used. For example, the buffer layer 2 may be located on the main substrate 1, and the seed layer 3 may be locally provided on the buffer layer 2 so as to overlap the opening KS of the mask layer 6.

[0075] (c) In the manufacturing method of the semiconductor laser device 20 according to another embodiment of the present disclosure, a base substrate UK having no buffer layer 2 between the main substrate 1 and the seed layer 3 may be used as the growth substrate. That is, a template substrate 7 including a base substrate UK having the main substrate 1 and the seed layer 3, and a mask layer 6 formed on the base substrate UK may be used. The template substrate 7 may be configured without the buffer layer 2 when the main substrate 1 made of a material that does not melt with the seed layer 3 is used, or when the seed layer 3 made of a material that is less reactive with the main substrate 1 is used. This omits the film formation process of the buffer layer 2, thereby reducing the cost of the film formation process.

[0076] For example, the seed layer 3 may be formed of a material that has low reactivity with the main substrate 1 and can serve as a growth starting point for the base semiconductor layer 8. The seed layer 3 may be, for example, an AlN layer or a SiC layer, or may be a layer containing at least one of AlN and SiC.

[0077] (d) In another embodiment of the present disclosure, the semiconductor laser device 20 may have a configuration in which the base semiconductor layer 8 does not have the first portion B1, that is, the base semiconductor layer 8 may have one second portion B2. For example, before separating the device portion DS from the template substrate 7, the first portion B1 may be removed by etching or the like.

[0078] Example 1 The manufacturing method of the semiconductor device of the present disclosure will be described in more detail below with reference to examples, but the present disclosure is not limited to the configurations described below, and various modifications are possible within the scope of the claims. In addition, the configurations of the multiple examples of the present disclosure will be described below with the same reference numerals assigned to the same or corresponding parts in the drawings, but unless otherwise specified, the technical scope of the present disclosure also includes forms obtained by appropriately combining the technical means disclosed in the above-mentioned embodiment and multiple different examples described below.

[0079] 9 is a flowchart showing an example of a method for manufacturing the semiconductor laser device 20 in Example 1. In Example 1, the mask layer 6 of the template substrate 7 includes a mask portion 5 having an origin induction portion. Then, an ELO semiconductor layer having an origin induction portion is formed on the template substrate 7. As shown in FIG. 9, in Example 1, first, the template substrate 7 including the origin induction portion in the mask layer 6 is prepared, and then a semiconductor layer (base semiconductor layer 8 and compound semiconductor layer 9) including the origin induction portion is formed on the template substrate 7.

[0080] (Process for preparing a template substrate) FIG. 10 is a cross-sectional view showing the configuration of the template substrate 7 in the first embodiment. FIG. 11A is an enlarged view of a main part of FIG. 10. A heterogeneous substrate having a lattice constant different from that of the nitride semiconductor can be used as the main substrate 1 in the template substrate 7. By using a Si substrate as the main substrate 1, the manufacturing cost of the template substrate 7 can be reduced. As a result, the manufacturing cost of the semiconductor laser element 20 can be reduced. The main substrate 1 may be an Al2O3 substrate or a SiC substrate that can reduce reactivity with Ga. The main substrate 1 may be made of a material and has a surface orientation that allows the ELO semiconductor layer to be grown, and the material and surface orientation of the main substrate 1 are not particularly limited.

[0081] In the first embodiment, the base substrate UK may be manufactured by forming the base layer 4 (see FIG. 4) on the main substrate 1, or a base substrate UK prepared in advance may be used. When a base substrate UK prepared in advance is used, it is easy to stably grow the base semiconductor layer 8 and the like. This is because when a process for forming the base layer 4 is performed, the process may affect the base semiconductor layer 8 and the like.

[0082] The template substrate 7 may include, for example, a seed layer 3 as the underlayer 4. The seed layer 3 is a layer that serves as a growth starting point for the base semiconductor layer 8 when the base semiconductor layer 8 is formed. The seed layer 3 may include a GaN-based semiconductor, aluminum nitride (AlN), SiC, graphene, or the like. The silicon carbide used for the seed layer 3 may be hexagonal 6H-SiC or 4H-SiC. The seed layer 3 may be, for example, an AlGaN layer, or a graded layer in which the Al composition gradually increases to approach GaN. The seed layer 3 may include a GaN layer. In this case, the seed layer 3 may be a GaN single layer, or the top layer of the graded layer that is the seed layer 3 may be a GaN layer. The seed layer 3 may be of any material and have any plane orientation that allows the base semiconductor layer 8 including a nitride semiconductor to grow.

[0083] The template substrate 7 may include, as the underlayer 4, a buffer layer 2 (see FIG. 4) located between the main substrate 1 and the seed layer 3. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed layer 3, the buffer layer 2 provided between the silicon substrate and the GaN-based semiconductor can reduce mutual melting of the silicon substrate and the GaN-based semiconductor. The buffer layer 2 may have at least one of the effects of increasing the crystallinity of the seed layer 3 and the effect of alleviating the internal stress of the seed layer 3.

[0084] The buffer layer 2 may typically be an AlN layer or a SiC layer. The SiC used in the buffer layer 2 may be hexagonal (6H-SiC, 4H-SiC) or cubic (3C-SiC). The buffer layer 2 may be a multilayer film including at least one of an AlN film and a SiC film. The buffer layer 2 may include a strain relaxation layer. Examples of the strain relaxation layer include a superlattice structure of AlGaN and a graded structure in which the Al composition of AlGaN changes stepwise. The strain relaxation layer can relax the longitudinal stress of the base semiconductor layer 8. The AlN layer, which is an example of the buffer layer 2, can be formed to a thickness of about 10 nm to about 5 μm using, for example, an MOCVD apparatus.

[0085] The underlayer 4 can be formed by stacking various layers on the main substrate 1 using an MOCVD apparatus or a sputtering apparatus. For example, at least one of the buffer layer 2 (e.g., aluminum nitride) and the seed layer 3 (e.g., GaN-based semiconductor) can be formed on the main substrate 1 using a sputtering apparatus (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). This allows the undersubstrate UK to be manufactured.

[0086] A mask layer 6 is formed on the base substrate UK to manufacture a template substrate 7. As the mask layer 6, for example, a single layer film including any one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (for example, 1000° C. or higher), or a laminated film including at least two of these can be used.

[0087] In the first embodiment, the mask layer 6 is formed on the undersubstrate UK so that the mask portion 5 has the origin inducing portion 5Y in a part thereof. The origin inducing portion 5Y in the first embodiment has a triangular shape in a plan view. The origin inducing portion 5Y has a vertex 5P and two sides 5A and 5B that intersect at the vertex 5P in a plan view. In a plan view, a virtual line segment that connects the end of the side 5A and the end of the side 5B on the opposite side to the vertex 5P is called a side 5C. A virtual triangle is formed by the sides 5A, 5B, and 5C. The side 5C can also be called the base of the virtual triangle. The angle between the side 5A and the side 5B is called θ1, and the angle between the side 5B and the side 5C is called θ2. The distance from the side 5C to the vertex 5P is called the protruding length H1 of the origin inducing portion 5Y.

[0088] The origin inducing part 5Y may have the same thickness as the other parts of the mask part 5. The angle θ1 may be 30° or approximately 30°, for example, about 20° to 40°. In this specification, "approximately" means within a variation range of ±10%. The angles θ1 and θ2 may be the same or approximately the same. The side 5A may have a length of, for example, about 0.1 μm to 20 μm. The sides 5A and 5B may have the same or approximately the same length. In this specification, "approximately the same" means within a range of 10% difference based on the larger numerical value. The origin inducing part 5Y may have a protruding length H1 of, for example, about 0.1 μm to 10 μm.

[0089] The specific shape of the initiation point inducing portion 5Y is not particularly limited as long as it can form a portion that becomes the initiation point of cleavage in the base semiconductor layer 8 as described later. The initiation point inducing portion 5Y is not limited to a shape in which the tip of the apex 5P is pointed in a plan view, and the apex 5P may have a rounded shape. The angle θ1 and the angle θ2 of the initiation point inducing portion 5Y may be different from each other. In addition, the initiation point inducing portion 5Y may have a rectangular shape in a plan view, or may have other shapes. The portion other than the initiation point inducing portion 5Y in the mask portion 5 is referred to as a main portion, and the initiation point inducing portion 5Y and the main portion may have different thicknesses from each other. In addition, the initiation point inducing portion 5Y and the main portion may be formed integrally, or the initiation point inducing portion 5Y may be formed after the main portion is formed.

[0090] The opening KS has an elongated shape except for the portion where the origin inducing portion 5Y is provided, and the width is relatively narrow in the portion where the origin inducing portion 5Y is provided. In the first embodiment, the mask layer 6 is formed so that the opening KS has a notch by providing the origin inducing portion 5Y. The multiple openings KS may be periodically arranged with a first period in the X direction. The width of the openings KS may be about 0.1 μm to 20 μm. The smaller the width of the openings KS, the smaller the number of threading dislocations propagating from the openings KS to the base semiconductor layer 8. In addition, the base semiconductor layer 8 is easily peeled off in a later process. Furthermore, the area of ​​the second portion B2 with fewer surface defects can be increased.

[0091] In the first embodiment, the mask layer 6 having the mask portion 5 may be formed, for example, as follows. First, a silicon oxide film having a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed on the entire surface of the underlayer 4 by using a sputtering method. Then, a resist is applied to the entire surface of the silicon oxide film. After that, the resist is patterned by using a photolithography method to form a resist having a plurality of stripe-shaped openings. At this time, in the first embodiment, the resist is not removed at the position corresponding to the origin inducing portion 5Y. Then, a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF), thereby forming the mask portion 5 including the plurality of openings KS and the origin inducing portion 5Y. Next, the resist is removed by organic cleaning to form the mask layer 6.

[0092] In the mask layer 6, for example, in one mask portion 5, the protruding direction of the multiple origin induction portions 5Y, in other words, the direction of the multiple notches of the opening KS may be aligned in one direction. As a result, as described later, the semiconductor laser element 20 manufactured using the template substrate 7 can form a pair of cavity faces (emission face F1 and opposing face F2) in the second part B2 (see FIG. 1, etc.) located farther from the origin induction portion 5Y out of the second part B2 and the third part B3. The second part B2 is less likely to be affected by the origin induction portion 5Y. As a result, the possibility of the quality of the pair of cavity faces being degraded can be reduced. However, it is of course possible to form the mask layer 6 by appropriately changing the direction of the origin induction portion 5Y.

[0093] (Example of the shape of the inducing part) Another example of a specific shape of the origin inducing part 5Y will be described below.

[0094] 11B is a plan view showing an example of the origin inducing part 5Y. As shown in FIG. 11B, the origin inducing part 5Y may have a shape in which the apex 5P does not exceed the center of the opening KS. That is, the origin inducing part 5Y may have a protruding length H1 of, for example, 0.1 μm or more and less than (WK / 2) (WK: width of the opening KS). The origin inducing part 5Y may have, for example, an isosceles triangle shape or an equilateral triangle shape in a plan view.

[0095] 11C is a plan view showing another example of the trigger point inducing part 5Y. As shown in FIG. 11C, the trigger point inducing part 5Y may have a shape in which the apex 5P exceeds the center of the opening KS. That is, the trigger point inducing part 5Y may have a protruding length H1 that is, for example, equal to or greater than (WK / 2) and less than WK. Also, for example, the angle θ1 and the angle θ2 may exceed 40°.

[0096] FIG. 11D is a plan view showing another example of the origin inducing part 5Y. As shown in FIG. 11D, the origin inducing part 5Y may have a virtual pentagonal shape in plan view by combining a virtual triangle 5Y1 and a virtual rectangle 5Y2. The virtual rectangle 5Y2 may be a square shape or a rectangle. The virtual rectangle 5Y2 may have a virtual side 5D whose length direction is the width direction of the opening KS, and the length may be, for example, about 0.1 μm to 10 μm. The side 5D may be a line segment extending parallel or approximately parallel to the width direction of the opening KS. The virtual rectangle 5Y2 may be, for example, a trapezoid. The vertex 5P of the virtual triangle 5Y1 may be located beyond the center of the opening KS, or may not be located beyond the center.

[0097] FIG. 11E is a plan view showing another example of the origin inducing part 5Y. As shown in FIG. 11E, the origin inducing part 5Y may have a quadrangular shape in plan view. In this case, the origin inducing part 5Y does not have a vertex 5P, and the distance between the side 5E, whose length direction is the longitudinal direction of the opening KS, and the main part of the mask part 5 is defined as the protruding length H1. The side 5E may have a length of, for example, about 0.1 μm to 10 μm. The origin inducing part 5Y may have a trapezoidal shape or a parallelogram shape in plan view. The side 5E may be located at a position that exceeds the center of the opening KS, or may not exceed the center. That is, the side 5D may have a length of, for example, about 0.1 μm to 20 μm.

[0098] (Step of forming a semiconductor layer) Next, the base semiconductor layer 8 is formed on the template substrate 7. In Example 1, for example, the template substrate 7 is loaded into an MOCVD apparatus, and a GaN-based semiconductor layer is formed by the ELO method. FIG. 12 is a cross-sectional view showing an example of lateral growth of the base semiconductor layer 8 in Example 1. The base semiconductor layer 8 in Example 1 is a nitride semiconductor (for example, a GaN-based semiconductor layer), and is obtained by c-plane deposition on the template substrate 7. The base semiconductor layer 8 may be an n-type semiconductor layer having a donor. In FIG. 12 and other figures, the [-1100] direction of the GaN-based semiconductor is the Y-axis positive direction, the [11-20] direction of the GaN-based semiconductor is the X-axis positive direction, and the

[0001] direction of the GaN-based semiconductor is the Z-axis positive direction (thickness direction).

[0099] 12, in the ELO method, first, an initial growth layer SL is formed on a seed layer 3, and then a base semiconductor layer 8 can be grown laterally from the initial growth layer SL. The initial growth layer SL is a starting point of the lateral growth of the base semiconductor layer 8, and is a part of the first part B1. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the base semiconductor layer 8 in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0100] Here, the ELO deposition conditions may be controlled so that deposition of the initial growth layer SL is stopped just before the edge of the initial growth layer SL rises onto the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or just after it rises onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions are switched from the c-axis direction deposition conditions to the a-axis direction deposition conditions). In this way, lateral deposition is performed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that material is less likely to be consumed in the growth of the base semiconductor layer 8 in the thickness direction, and the base semiconductor layer 8 can be grown laterally at a high speed. The initial growth layer SL may be formed to a thickness of, for example, 2.0 μm or more and 3.0 μm or less.

[0101] In Example 1, the base semiconductor layer 8 was an n-type GaN layer, and an MOCVD apparatus was used to perform ELO deposition of Si-doped GaN on the template substrate 7. As an example of ELO deposition conditions, the following can be adopted: substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, V / III=6000 (ratio of the amount of V-group raw material supplied to the amount of III-group raw material supplied). An initial growth layer SL is selectively grown on the seed layer 3 (the GaN layer that is the top layer of the seed layer 3) exposed in the opening KS, and then grows laterally on the mask portion 5. Then, the lateral growth of the base semiconductor layer 8 growing laterally from both sides on the mask portion 5 was stopped before they met.

[0102] Here, in the first embodiment, since the mask layer 6 includes the initiation site inducing portion 5Y, disturbance may occur in the lateral growth of the base semiconductor layer 8 in the portion where the initiation site inducing portion 5Y exists. Fig. 13 is a plan view for explaining the base semiconductor layer 8 in the first embodiment.

[0103] As shown in FIG. 13, in Example 1, the base semiconductor layer 8 has an origin portion 8K which becomes the origin of cleavage, and the origin portion 8K is naturally formed in the base semiconductor layer 8 by growing the base semiconductor layer 8 from an opening KS having a notch shape. The relationship between the shape of the origin inducing portion 5Y and the shape of the origin portion 8K may vary depending on the growth conditions of the base semiconductor layer 8. The origin portion 8K may be smaller or larger than the shape of the origin inducing portion 5Y, or may be approximately the same as the shape of the origin inducing portion 5Y. An example of the origin portion 8K will be described below.

[0104] For example, the base semiconductor layer 8 may have an oblique meeting portion 8N extending from the position of the initiation point inducing portion 5Y of the mask layer 6 to the position of the initiation point portion 8K of the base semiconductor layer 8 in a plan view. The oblique meeting portion 8N is a portion where semiconductor layers grown in a direction oblique to the X direction (a-axis direction) meet each other. The oblique meeting portion 8N may be, for example, a grain boundary, or may be a portion where the crystal structure is more disturbed (i.e., has more lattice defects) than other portions in the base semiconductor layer 8. In FIG. 13, the oblique meeting portion 8N is illustrated by a solid line. When the base semiconductor layer 8 has the oblique meeting portion 8N, the oblique meeting portion 8N can be observed by, for example, performing a CL measurement.

[0105] FIG. 14 is an enlarged view for explaining the growth of the base semiconductor layer 8 around the origin induction portion 5Y in Example 1. As shown in FIG. 14, first, an initial growth layer SL is formed from the opening KS. At this time, in the portion other than the periphery of the origin induction portion 5Y in the opening KS, the initial growth layer SL is formed so as to climb up onto the upper surface of the mask portion 5 by lateral growth of the GaN-based semiconductor in the <11-20> direction (i.e., the a-axis direction). In contrast, in the peripheral portion of the origin induction portion 5Y in the opening KS, a notch may be generated in a part of the initial growth layer SL that has grown from the opening KS to climb up onto the upper surface of the mask portion 5 due to the presence of the origin induction portion 5Y. For example, in a plan view, the direction perpendicular to the side 5A of the origin induction portion 5Y may be the m-plane direction of the GaN-based semiconductor (for example, the [10-10] direction), and the direction perpendicular to the side 5B may be another m-plane direction of the GaN-based semiconductor (for example, the [01-10] direction). The growth rate in the m-plane direction of a GaN-based semiconductor is slower than the growth rate in the a-plane direction. The base semiconductor layer 8 can grow so as to maintain the notch formed in the initially grown layer SL.

[0106] The oblique meeting portion 8N may be generated, for example, by the meeting of semiconductor layers grown in the [10-10] direction and the [01-10] direction. After being generated in the vicinity of the mask portion 5, the oblique meeting portion 8N may affect (propagate) to the surface of the base semiconductor layer 8 after film formation, and may also exist on the surface of the base semiconductor layer 8. The starting point portion 8K may have a tapered shape such as a triangular shape in a plan view. This makes it easier for stress to concentrate at one point during cleavage. As a result, it is easier to obtain a good cleavage surface. The starting point portion 8K may have an end face that is an m-plane of a GaN-based semiconductor. Note that the end face of the starting point portion 8K does not have to be an m-plane of a GaN-based semiconductor.

[0107] If the interval between the multiple starting points 8K in the base semiconductor layer 8 (the distance between the tips of each of the two starting points 8K) is L2 (see FIG. 17), this interval L2 corresponds to the cavity length L1 (see FIG. 2). The length of the interval L2 may be about 20 μm to 200 μm. If the interval L2 is short, there are many locations where internal stress is released by cleavage. Therefore, it is possible to reduce the possibility that element separation occurs at unintended locations during cleavage during cooling, which will be described later. The interval L2 may be 300 μm or more. If the interval L2 is long, it is possible to reduce the possibility that there are starting points 8K that do not cleave during cleavage during cooling, which will be described later, and the manufacturing yield of semiconductor devices can be improved.

[0108] In forming the base semiconductor layer 8, it is preferable to reduce mutual reaction between the base semiconductor layer 8 and the mask portion 5 and maintain a state in which the base semiconductor layer 8 and the mask portion 5 are in contact with each other through van der Waals forces. That is, the base semiconductor layer 8 and the mask portion 5 may be in contact with each other mainly through van der Waals forces.

[0109] (Process for forming compound semiconductor layer) In Example 1, a semiconductor substrate 10 having a base semiconductor layer 8 formed on a template substrate 7 is manufactured using an MOCVD apparatus, and then, without removing the semiconductor substrate 10 from the MOCVD apparatus once, a compound semiconductor layer 9 is formed on the base semiconductor layer 8 using the MOCVD apparatus. In addition, without removing the compound semiconductor layer 9 from the MOCVD apparatus during the formation of the layered structure, the film formation process of the layered structure is continuously performed using the MOCVD apparatus. The compound semiconductor layer 9 includes a nitride semiconductor layer (for example, a GaN-based semiconductor layer).

[0110] FIG. 15 is a cross-sectional view showing the configuration of the compound semiconductor layer 9 in Example 1. As shown in FIG. 15, the compound semiconductor layer 9 is formed by forming an n-type semiconductor layer 9N having a donor, an active layer 9K, and a p-type semiconductor layer 9P having an acceptor in this order. The n-type semiconductor layer 9N is formed by forming a first contact layer 9A, a first cladding layer 9B, and a first optical guide layer 9C in this order. The p-type semiconductor layer 9P is formed by forming a second optical guide layer 9D, an electron blocking layer 9E, a second cladding layer 9F, and a second contact layer 9G in this order. Note that the compound semiconductor section 9 may be arranged such that the second optical guide layer 9D and the electron blocking layer 9E are interchanged in the p-type semiconductor layer 9P. For example, the p-type semiconductor layer 9P may be formed by forming an electron blocking layer 9E, a second optical guide layer 9D, a second cladding layer 9F, and a second contact layer 9G in this order.

[0111] For example, an n-type GaN layer can be used for the first contact layer 9A, and for example, an n-type AlGaN layer can be used for the first cladding layer 9B. The first cladding layer 9B may be an n-type GaN-based semiconductor layer, an n-type AlGaN-based semiconductor layer, or an n-type AlInGaN-based semiconductor layer, and may have a thickness of, for example, about 0.8 μm to 2 μm. When GaN not containing Al is used for the first cladding layer 9B, deposition of a GaN-based semiconductor on the surface of the mask portion 5 can be suppressed, and the yield during peeling (in the step of separating the element portion DS from the template substrate 7, which will be described later) is improved. For example, an n-type GaN layer can be used for the first optical guide layer 9C, and may be an InGaN layer with an In composition of about 3 to 10%. The first optical guide layer 9C may have a thickness of about 50 nm.

[0112] The active layer 9K may have a multi-quantum well (MQW) structure including an InGaN layer, for example. The active layer 9K may typically have a 5-6 period structure. The In composition varies depending on the target emission wavelength. For example, for blue light emission (wavelength around 450 nm), the In concentration may be about 15-20%. For green light emission (wavelength around 530 nm), the In concentration may be about 30%.

[0113] The second optical guide layer 9D may be, for example, a p-type AlGaN layer. The second optical guide layer 9D may have an Al composition of, for example, about 15 to 25%, and may have a layer thickness of, for example, about 5 to 25 nm. The electron blocking layer 9E may be, for example, a p-type GaN layer, and may be an InGaN layer having an In composition of, for example, about 3 to 10%. The electron blocking layer 9E may have a layer thickness of, for example, about 50 nm. The second cladding layer 9F may be, for example, a p-type AlGaN layer. The second cladding layer 9F may be a p-type GaN-based semiconductor layer, an AlGaN-based semiconductor layer, or an AlInGaN-based semiconductor layer, and may have a layer thickness of, for example, about 0.1 μm to 1 μm. The second contact layer 9G may be, for example, a p-type GaN layer. The second contact layer 9G may have a layer thickness of, for example, about 0.1 μm to 0.3 μm. Although not shown, a highly doped layer with a thickness of about 10 nm and containing Mg as a dopant may be formed on the surface of the second contact layer 9G.

[0114] The thickness of each layer in the compound semiconductor layer 9 can be expressed as: base semiconductor layer 8>first cladding layer 9B>first optical guide layer 9C>active layer 9K, and base semiconductor layer 8>second cladding layer 9F>second optical guide layer 9D>active layer 9K. The refractive index of each layer in the compound semiconductor layer 9 (refractive index of light generated in the active layer 9K) can be expressed as:first cladding layer 9B<first optical guide layer 9C<active layer 9K, and insulating film DF<second cladding layer 9F<second optical guide layer 9D<active layer 9K.

[0115] Fig. 16 is a plan view for explaining the compound semiconductor layer 9 in Example 1. As shown in Fig. 16, the compound semiconductor layer 9 is formed in a shape having an origin portion 9T corresponding to the origin portion 8K of the base semiconductor layer 8. This is because it is difficult to form the compound semiconductor layer 9 at the position of the origin portion 8K of the base semiconductor layer 8. The origin portion 9T may have an end face that is an m-plane of a GaN-based semiconductor by being formed in a shape that corresponds to the origin portion 8K. Note that the end face of the origin portion 9T does not have to be an m-plane of a GaN-based semiconductor.

[0116] The above-described steps can be summarized as follows. That is, in Example 1, first, a step of preparing a main substrate 1, a base semiconductor layer 8 formed above the main substrate 1, and a compound semiconductor layer 9 formed on the base semiconductor layer 8 is performed. A notch is formed at the opening KS of the mask layer 6. As a result, an origin portion 8K is naturally formed in the base semiconductor layer 8. Then, a compound semiconductor layer 9 is formed on the base semiconductor layer 8 having the origin portion 8K. As a result, an origin portion 9T is naturally formed in the compound semiconductor layer 9.

[0117] (Process of isolating elements on a template substrate) Next, the semiconductor substrate 10 on which the compound semiconductor layer 9 is formed is cooled, thereby isolating the device into a plurality of half-device portions sDS on the template substrate 7. Fig. 17 is a plan view for explaining an example of a device isolation process in Example 1.

[0118] The compound semiconductor layer 9 may be formed under high temperature conditions using an MOCVD apparatus, in which case a cooling step is performed within the MOCVD apparatus.

[0119] Here, in Example 1, the thermal expansion coefficients of the base semiconductor layer 8 and the compound semiconductor layer 9 may be different from the thermal expansion coefficient of the main substrate 1. In this case, the difference in the thermal expansion coefficients between the base semiconductor layer 8 and the compound semiconductor layer 9 and the main substrate 1 generates internal stress in the base semiconductor layer 8 and the compound semiconductor layer 9.

[0120] In addition, in the first embodiment, the main substrate 1 and the base semiconductor layer 8 may have different lattice constants. In this case, an internal stress is generated in the base semiconductor layer 8 due to the difference in lattice constants between the main substrate 1 and the base semiconductor layer 8. An internal stress may also be generated in the compound semiconductor layer 9 due to the influence of the internal stress of the base semiconductor layer 8. By using a heterogeneous substrate (e.g., a Si substrate) different from a GaN-based semiconductor as the main substrate 1, it is possible to easily generate internal stress in the base semiconductor layer 8 and the compound semiconductor layer 9.

[0121] 17, when the semiconductor substrate 10 is cooled, the base semiconductor layer 8 and the compound semiconductor layer 9 may be cleaved from the notched starting point portions 8K and 9T due to internal stresses of the base semiconductor layer 8 and the compound semiconductor layer 9, thereby generating split portions PS. That is, in the first embodiment, cleavage may occur naturally while the base semiconductor layer 8 and the compound semiconductor layer 9 are being cooled.

[0122] The base semiconductor layer 8 and the compound semiconductor layer 9 may have the initiation points 8K and 9T, respectively, each having a tapered notch shape, in which case stress tends to concentrate at one point, making it easier to produce a high-quality cleavage surface by cleavage. The shapes of the initiation points 8K and 9T are influenced by the shape of the initiation inducing portion 5Y of the mask portion 5 in the mask layer 6. The shape of the initiation inducing portion 5Y may affect the quality of the cleavage surface.

[0123] In addition, tensile stress may occur as an internal stress in the base semiconductor layer 8. For example, if the thermal expansion coefficient of the main substrate 1 is larger than that of the base semiconductor layer 8, compressive stress occurs in the base semiconductor layer 8, and if the thermal expansion coefficient of the main substrate 1 is smaller than that of the base semiconductor layer 8, tensile stress occurs in the base semiconductor layer 8. When the base semiconductor layer 8 in which tensile stress occurs is cleaved, the possibility that the individual pieces of the divided base semiconductor layer 8 come into contact with each other can be reduced. Therefore, the possibility that the end face of the divided base semiconductor layer 8 is scratched can be reduced. Furthermore, when cleavage occurs in the base semiconductor layer 8 so as to tear it from the starting point 8K, the cleavage surface is likely to be smooth.

[0124] In the first embodiment, when the semiconductor substrate 10 is cooled, the base semiconductor layer 8 and the compound semiconductor layer 9 may be cleaved to separate the semiconductor laser device 20 into a plurality of half-element portions sDS each having an optical resonator LK on the template substrate 7. In this case, there is no need to perform a separate process for cleaving the base semiconductor layer 8 and the compound semiconductor layer 9, and the manufacturing cost of the semiconductor laser device 20 can be reduced. Also, a half-element portion sDS having an optical resonator LK with a short resonator length can be manufactured. For example, the length of the interval L2 can be set to about 20 μm to 200 μm, and therefore the resonator length L1 can be set to about 20 μm to 200 μm.

[0125] In addition, after cooling the semiconductor substrate 10, if there is a portion where the division portion PS is not generated from the starting point portion 9T, that is, the starting point portion 9T where no cleavage has occurred, a process of cleaving the starting point portion 9T may be further performed. For example, a blade may be applied to the starting point portion 9T and a force may be applied in a direction perpendicular to the surface direction to cause cleavage to occur in the starting point portion 9T. In this case, cleavage can be relatively reliably caused in the starting point portion 9T, so that the yield can be improved. Alternatively, cleavage can be caused in the starting point portion 9T by applying vibration to the starting point portion 9T. In this case, the process can be relatively easily performed, so that the manufacturing process can be simplified. In addition, the temperature of the semiconductor substrate 10 may be raised or lowered from room temperature to apply thermal stress to the starting point portion 9T by utilizing the difference in thermal expansion coefficient between the main substrate 1 and the base semiconductor layer 8, so that cleavage occurs.

[0126] Fig. 18 is an exploded perspective view for explaining the configuration of the half-element portion sDS in Example 1. In Fig. 18, for convenience of explanation, the template substrate 7 and the base semiconductor layer 8 are virtually separated from each other, but in reality, the base semiconductor layer 8 and the mask portion 5 are in contact with each other. In addition, the base semiconductor layer 8 has a junction 8S corresponding to the initial growth layer SL on the lower surface, and the junction 8S and the seed layer 3 are bonded to each other. In addition, Fig. 18 shows only a part of the template substrate 7, not the whole of it.

[0127] As shown in FIG. 18, the base semiconductor layer 8 in the half-element portion sDS has a first base end surface 8X and a second base end surface 8Y adjacent to the first base end surface 8X at an angle. The base semiconductor layer 8 may have a third base end surface 8Z adjacent to the second base end surface 8Y at an angle and corresponding to the a-plane of the GaN-based semiconductor (for example, parallel to the a-plane). The second base end surface 8Y may be located between the first base end surface 8X and the third base end surface 8Z. The half-element portion sDS may have two first base end surfaces 8X and two second base end surfaces 8Y as end surfaces of the third portion B3.

[0128] The first base end surface 8X may include a first partial surface 8X1, a second partial surface 8X2, and a third partial surface 8X3. The first partial surface 8X1 is a part of the first base end surface 8X and is a surface at a position corresponding to the first portion B1 of the base semiconductor layer 8. The second partial surface 8X2 is a partial surface at a position corresponding to the second portion B2 of the first base end surface 8X. The third partial surface 8X3 is a partial surface at a position corresponding to the third portion B3 of the first base end surface 8X. The first partial surface 8X1 is located between the second partial surface 8X2 and the third partial surface 8X3.

[0129] The third partial surface 8X3 may be a surface where a portion corresponding to the oblique meeting portion 8N described above is divided, and may be an m-plane cleavage surface formed by cleaving the base semiconductor layer 8 starting from the starting point portion 8K. The second partial surface 8X2 may be an m-plane cleavage surface formed by cleaving the base semiconductor layer 8 starting from the starting point portion 8K, and may be flush with the emission surface F1 of the optical resonator LK. In addition, the first partial surface 8X1, the second partial surface 8X2, and the third partial surface 8X3 may be flush with each other. The surface roughness of the second partial surface 8X2 may be smaller than that of the third partial surface 8X3. The density of dislocations (dislocations measured by CL on the cleavage surface, mainly basal plane dislocations) in the second partial surface 8X2 may be equal to or greater than the threading dislocation density of the second portion B2.

[0130] The second base end face 8Y is a surface included in the notch-shaped initiation point portion 8K in the base semiconductor layer 8 before cleavage, and is not a cleavage surface formed by cleavage. Depending on the shape of the initiation point inducing portion 5Y of the mask portion 5, the initiation point portion 8K may have an end face of an ELO semiconductor layer grown in the m-axis direction. In this case, the second base end face 8Y may be an m-plane of a GaN-based semiconductor, although it is not a cleavage surface. The compound semiconductor portion 9 may have a side face 9S located above the second base end face 8Y. The surface roughness of at least one of the pair of resonator faces (the emission face F1 and the opposing face F2) can be made smaller than the surface roughness of the side face 9S.

[0131] The angle (interior angle) formed between the first base end surface 8X and the second base end surface 8Y is referred to as θ3. The angle θ3 may be an obtuse angle, for example, 120° or approximately 120°, for example, about 110° to 130°.

[0132] As described above, in the first embodiment, the base semiconductor layer 8 and the compound semiconductor layer 9 are separated into a plurality of first element portions (semi-element portions sDS) to form an optical resonator LK (see FIGS. 1 and 2) including a resonator surface. In FIG. 18, the optical resonator LK is exemplarily illustrated at a position overlapping the second portion B2 in a plan view, but the position of the optical resonator LK in the X direction is not necessarily limited in the semi-element portion sDS. The optical resonator LK will be described in more detail later.

[0133] In addition, in the first embodiment, it can be said that the optical resonator LK including the resonator surface is formed by dividing the base semiconductor layer 8 and the compound semiconductor layer 9 so that the main substrate 1 is not entirely divided in the thickness direction.

[0134] The emission surface F1 and the opposing surface F2 of the optical resonator LK may each be an m-plane of the compound semiconductor layer 9, and may be included in the cleavage plane of the compound semiconductor layer 9. The emission surface F1 and the opposing surface F2 may each be formed by m-plane cleavage of the compound semiconductor layer 9, which is a nitride semiconductor layer (e.g., a GaN-based semiconductor layer). The semi-element portion sDS may have a trace of a cleavage starting point for cleavage (e.g., the second base end surface 8Y) in at least one of the base semiconductor layer 8 and the compound semiconductor layer 9. The emission surface F1 and the opposing surface F2 are m-planes, so that the reflectance of the resonator facets of the optical resonator LK can be improved.

[0135] (Process for forming element structure) Next, a process of forming an element structure is performed on the semiconductor substrate 10 having a plurality of half element portions sDS. For example, a ridge portion RJ is formed in the p-type semiconductor layer 9P, and then an insulating film DF and a first electrode E1 are formed to form the element portion DS. In the first embodiment, a semiconductor laser element 20 having a double-sided electrode structure is manufactured. Therefore, the element portion DS does not include the second electrode E2, and the second electrode E2 may be provided in a later process.

[0136] Fig. 19 is a perspective view for explaining the configuration of the element portion DS in Example 1. The template substrate 7 is omitted in Fig. 19. Fig. 20 is a cross-sectional view showing the configuration of the element portion DS in Example 1.

[0137] As shown in FIGS. 19 and 20, the compound semiconductor layer 9 may include a ridge portion (ridge portion) RJ overlapping with the first electrode E1 in plan view. The ridge portion RJ may include a part (a part overlapping with the first electrode E1 in plan view) of the second cladding layer 9F and the electron blocking layer 9E (see FIG. 15). The ridge portion RJ has a shape with the Y direction as the longitudinal direction, and an insulating film DF may be provided so as to cover the side surface of the ridge portion RJ. The insulating film DF may be a single layer film or a multilayer film including, for example, an oxide or nitride of Si, Al, Zr, Ti, Nb, or Ta. The insulating film DF may have a thickness of about 10 to 500 nm.

[0138] The refractive index of the insulating film DF is smaller than the refractive indexes of the second optical guide layer 9D and the second cladding layer 9F. By providing the ridge portion RJ and the insulating film DF, the current path between the first electrode E1 and the base semiconductor layer 8 is narrowed on the anode side, allowing efficient light emission within the resonator LK.

[0139] The first electrode E1 is provided on, for example, the upper surface of the ridge portion RJ and functions as an anode. Examples of materials for the first electrode E1 include a single layer film or a multilayer film of a conductive oxide containing at least one selected from metals or alloys such as Ni, Rh, Cr, Au, W, Pt, Ti, and Al, Zn, In, and Sn. Examples of conductive oxides include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and GZO (Gallium-doped Zinc Oxide). The thickness of the first electrode E1 may be, for example, about 0.1 to 2 μm.

[0140] The optical resonator LK includes a portion (portion overlapping with the first electrode E1 in a plan view) of each of the n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P. For example, the optical resonator LK includes a portion (portion overlapping with the first electrode E1 in a plan view) of each of the first cladding layer 9B, the first optical guide layer 9C, the active layer 9K, the second optical guide layer 9D, the electron blocking layer 9E, and the second cladding layer 9F.

[0141] In the optical resonator LK, the refractive index (optical refractive index) decreases in the order of the active layer 9K, the first optical guide layer 9C, and the first cladding layer 9B, and the refractive index decreases in the order of the active layer 9K, the second optical guide layer 9D, and the second cladding layer 9F. Therefore, light generated by the combination of holes supplied from the first electrode E1 and electrons supplied from the second electrode E2 in the active layer 9K is confined in the optical resonator LK (particularly, the active layer 9K), and laser oscillation occurs due to stimulated emission and feedback action in the active layer 9K. The laser light generated by the laser oscillation is emitted from a light emission region EA of the emission surface F1.

[0142] The emission surface F1 and the opposing surface F2 of the optical resonator LK are formed by m-plane cleavage, and therefore have excellent planarity and perpendicularity to the c-plane (parallelism between the emission surface F1 and the opposing surface F2), and have high optical reflectance. This allows the reflection loss to be reduced, and stable laser oscillation is possible even with a short cavity length of 200 μm or less where the optical gain is small. The emission surface F1 and the opposing surface F2 are formed above the second portion B2, which is a low-dislocation portion, and therefore have excellent planarity of the cleavage surface, and a high optical reflectance is achieved.

[0143] In the first embodiment, the sum T1 of the thickness of the base semiconductor layer 8 and the thickness of the compound semiconductor layer 9 can be 50 μm or less. If the sum T1 of the thicknesses is too large, it may be difficult to cleave the base semiconductor layer 8 so that the resonator length is 200 μm or less. The ratio of the resonator length L1 (see FIG. 2) to the thickness of the second portion B2 of the base semiconductor layer 8 can be 1 to 20. In addition, the direction perpendicular to the direction of the resonator length L1 is the first direction (X direction), the size of the second portion B2 in the X direction is the width W2 of the second portion B2, and the ratio of the resonator length L1 to the width W2 of the second portion B2 can be 1 to 10. In addition, the size of the first portion B1 in the X direction is the width W1 of the first portion B1, and the ratio of the resonator length L1 to the width W1 of the first portion can be 1 to 200.

[0144] (Step of isolating the element portion from the template substrate) Next, a step of separating the element portion DS from the template substrate 7 is performed. Fig. 21 is a cross-sectional view that typically shows a step of separating the element portion DS from the template substrate 7 in the manufacturing method of the semiconductor laser device of Example 1. Although Fig. 21 shows one element portion DS, it goes without saying that a process of separating a plurality of element portions DS from the template substrate 7 may be performed. Also, in Fig. 21, the illustration of the ridge portion RJ is simplified.

[0145] As shown in FIG. 21, first, the mask portion 5 of the template substrate 7 may be removed by etching using hydrofluoric acid, buffered hydrofluoric acid, or the like. The insulating film DF may be protected by a resist or the like so that it is not removed together with the mask portion 5. In the first embodiment, the mask portion 5 may be removed after the element portion DS is formed on the template substrate 7. In this case, since the mask portion 5 can be removed while the element portion DS is fixed to the template substrate 7, the yield in the manufacture of the semiconductor laser element 20 can be improved. By removing the mask portion 5, the base semiconductor layer 8 and the base substrate UK are bonded via the bonding portion 8S (weak portion), and the element portion DS can be easily separated from the base substrate UK.

[0146] Next, for example, a step of separating the element portion DS from the template substrate 7 may be performed so as to also serve as a step of bonding the element portion DS to the support substrate SK. The specific shape of the support substrate SK is not particularly limited, but the support substrate SK in Example 1 will be described below with reference to Figs. 22 and 23. Fig. 22 is a perspective view that typically shows a state in which the element portion DS is bonded to the support substrate SK. Fig. 23 is a cross-sectional view that typically shows a state in which the element portion DS is bonded to the support substrate SK.

[0147] As shown in FIG. 21 to FIG. 23, the support substrate SK includes a conductive first pad P1 and a second pad P2, and for example, the first electrode E1 may be connected to the first pad P1 via a first bonding portion A1. By bonding at least the first electrode E1 and the first bonding portion A1, the element portion DS is supported by the support substrate SK. As a result, the bonding portion 8S (weak portion) protruding downward on the rear surface of the base semiconductor layer 8 is broken, and the element portion DS can be separated from the template substrate 7. The insulating film DF and the second pad P2 may be bonded to each other via a second bonding portion A2 (not shown), and in this case, the stability of the state in which the element portion DS is supported by the support substrate SK can be improved. The rear surface of the base semiconductor layer 8 may be planarized by polishing or CMP (Chemical Mechanical Polishing). Then, the second electrode E2 can be formed on the lower surface of the base semiconductor layer 8 of the element portion DS in a state in which it is supported by the support substrate SK.

[0148] Next, (i) an insulating film D1 covering the side surfaces of the base semiconductor layer 8 and the compound semiconductor layer 9, and (ii) a conductive film MF are formed. The conductive film MF electrically connects the second electrode E2 to the second joint A2 or the second pad P2. The material of the conductive film MF is not particularly limited. The first pad P1 and the second pad P2 may be provided spaced apart from each other. The conductive film MF may be in contact with the second electrode E2, the insulating film D1, and at least one of the second joint A2 and the second pad P2.

[0149] In the first embodiment, the second electrode E2 is located on the back surface of the base semiconductor portion 8, and the compound semiconductor portion 9 and the first electrode E1 are closer to the support substrate SK than the base semiconductor portion 8 (junction-down type).

[0150] A plurality of element portions DS are arranged on a support substrate SK in a direction (X direction) perpendicular to the direction defining the cavity length so that the cavity length directions are aligned, and the support substrate SK may be provided with first and second pads P1 and P2 corresponding to each of the plurality of element portions DS.

[0151] The support substrate SK can be formed, for example, as follows. That is, the support substrate SK can be formed by providing a plurality of recesses HL (rectangular in plan view) in a matrix on a Si substrate, a SiC substrate, an AlN substrate, or the like, and providing a plurality of first pads P1, a plurality of second pads P2, and a plurality of first bonding portions A1 in the non-recessed portions. Note that a plurality of second bonding portions A2 may also be provided. The material constituting the main body portion of the support substrate SK is not particularly limited, and the support substrate SK may be formed, for example, of an insulator or semi-insulator, or may be formed of a conductive material. Examples of conductive materials include metal materials containing Cu, Al, and the like. When the support substrate SK is formed of a conductive material, an insulating layer can be disposed on the upper surface of the support substrate SK, and wiring can be disposed on the insulating layer.

[0152] The shape of the support substrate SK is not particularly limited, and may be a substantially quadrangular prism (substantially rectangular parallelepiped), a substantially pentagonal prism, a substantially hexagonal prism, or other shape. In the first embodiment, the shape of the support substrate SK is a substantially rectangular parallelepiped.

[0153] The first pad P1 and the second pad P2 may have a metal layer containing, for example, Au, Ti, Ni, etc. The first bonding portion A1 and the second bonding portion A2 may be made of a single metal layer or may be made of a multi-layer metal layer. When the first bonding portion A1 and the second bonding portion A2 are made of a multi-layer metal layer, the outermost surface may be a metal layer made of Au. This can suppress corrosion of the first bonding portion A1 and the second bonding portion A2. The first bonding portion A1 is, for example, a solder material such as AuSi or AuSn. The first pad P1 and the first electrode E1 may be bonded by metal-metal bonding without providing the first bonding portion A1, and the second pad P2 and the second electrode E2 may be bonded by metal-metal bonding without providing the second bonding portion A2. In that case, for example, Au-Au bonding can be used.

[0154] The first pad P1 and the second pad P2 may be located on the same plane. The second bonding portion A2 may not be provided in the first embodiment. The first bonding portion A1 may be, for example, a solder material, and the element portion DS may be held by the first bonding portion A1 and placed on the support substrate SK.

[0155] (Process for forming a reflective film on the cavity surface) Next, a reflector film UF is formed on the emission surface F1 and the opposing surface F2 of the optical resonator LK in the device portion DS mounted on the support substrate SK. This allows the semiconductor laser device 20 to be manufactured. Fig. 24 is a cross-sectional view that typically shows a step of forming a reflector film on the resonator facet in the manufacturing method of the semiconductor laser device of Example 1. Fig. 25 is a plan view showing the configuration of the compound semiconductor layer 9 after the reflector film UF is formed.

[0156] As shown in Figs. 24 and 25, a reflector film UF (e.g., a dielectric film) is formed on a first end face including an end face of the base semiconductor layer 8 and an end face of the compound semiconductor layer 9. The first end face includes an emission face F1 of the optical resonator LK. Examples of materials for the reflector film UF include dielectric materials such as SiO2, Al2O3, AlN, AlON, Nb2O5, Ta2O5, and ZrO2. The reflector film UF may be a multilayer film. The reflector film UF may be formed by electron beam evaporation, electron cyclotron resonance sputtering, chemical vapor deposition, or the like.

[0157] The semiconductor laser element 20 may be configured such that at least one of a pair of cavity facets (emission facet F1 and opposing facet F2) has an optical reflectance of 98% or more, and the cavity length L1 is 200 μm or less. The difference between the emission facet F1 and the opposing facet F2 may be the reflectance. The cavity facet with the lower reflectance may be the emission facet F1. The reflectance may be controlled by the type, structure, film thickness, etc. of the reflecting mirror film UF.

[0158] A reflector film UF may be provided so as to cover the opposing surface F2. The light reflectance of each of the exit surface F1 and the opposing surface F2 may be 98% or more. The light reflectance of the opposing surface F2 on the light reflecting surface side is greater than the light reflectance of the exit surface F1. The reflector film UF may be formed on the entire cleavage surface (m-plane) of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0159] As described above, the element portion DS can be electrically connected to the support substrate SK and mechanically fixed. As a result, the element portion DS is disposed on the support substrate SK with its end face exposed. Therefore, in the next process, it becomes possible to form a reflective film on the emission surface F1 and the opposing surface F2 of the optical resonator LK at the end face of the element portion DS. In other words, in the state where the element portion DS is disposed on the template substrate 7 (the state before the element portion DS is separated from the template substrate 7), the resonator surface is not exposed to the outside in the divided portion PS, so it is difficult to form a reflective film on the emission surface F1 and the opposing surface F2 of the optical resonator LK.

[0160] In general, in the manufacture of semiconductor laser devices, a dielectric layer can be formed (facet coating) so that the resonator facets of a plurality of devices have a desired reflectance.

[0161] In contrast, by using the support substrate SK, it is possible to appropriately coat the resonator facet of the element portion DS after element separation. The support substrate SK serves as a tool when coating the end face of the optical resonator LK, and also functions as a submount in the final device (semiconductor laser element 20). In the first embodiment, by performing a coating process on the element portion DS fixed to the support substrate SK, it is possible to increase the reflection efficiency at the opposing surface F2 and provide a semiconductor laser element 20 with excellent light emission efficiency. In addition, it is possible to suppress optical damage to the end face of the emission surface F1 and provide a semiconductor laser element 20 with excellent reliability.

[0162] In the conventional method CT, when the resonator facet of the optical resonator is formed by cleavage, both the growth substrate and the structure formed on the growth substrate are cleaved, so there is a limit to the extent to which the resonator length can be shortened. As far as the inventors recognize, the resonator length of a semiconductor laser that has been put to practical use and is manufactured by a method of forming the resonator facet by cleavage is about 300 μm for the semiconductor laser with the shortest resonator length. In contrast, the semiconductor laser element 20 can have an ultra-short resonator of 20 to 200 μm. Since at least one of the resonator faces (the emission surface F1 and the opposing surface F2) has a high optical reflectance and a small reflection loss, stable laser oscillation is possible even with a short resonator length of 200 μm or less where the optical gain is small. The short resonator allows low power consumption in low light output applications such as wearable devices.

[0163] (Step of dividing the support substrate) Next, the support substrate SK may be divided into a plurality of supports ST. This makes it possible to obtain a semiconductor laser chip 21 in which one or more semiconductor laser elements 20 are held by the supports ST. Fig. 26 is a cross-sectional view that typically shows a step of dividing the support substrate SK in the manufacturing method for the semiconductor laser element of Example 1.

[0164] 26, the support substrate SK is divided to form a plurality of semiconductor laser chips 21, each of which has a semiconductor laser element 20 disposed thereon. The support ST can be used as a substrate (also called a submount) for the semiconductor laser chip 21. The semiconductor laser chip 21 functions as a COS (Chip on Submount).

[0165] The support substrate SK may be divided into supports ST by using a known cutting method such as dicing or scribing. Any portion of the support substrate SK may be cut while avoiding damage to the semiconductor laser element 20. The support substrate ST may include one semiconductor laser element 20, or may include two or more semiconductor laser elements 20.

[0166] In the above-described first embodiment, the base semiconductor layer 8 and the compound semiconductor layer 9 are spontaneously cleaved on the template substrate 7 to separate the semiconductor laser device into a plurality of half-element portions sDS, so that there is no need to add a separate process for cleaving the base semiconductor layer 8 and the compound semiconductor layer 9. As a result, the manufacturing cost of the semiconductor laser device 20 can be reduced.

[0167] [Another configuration example 1] (1A) The ELO method is not limited to forming a plurality of base semiconductor layers 8 in an island shape, and the base semiconductor layers 8 may be grown for a relatively long time to allow adjacent base semiconductor layers 8 to meet. In this case, the upper surface of the base semiconductor layer 8 may be polished. The compound semiconductor layer 9 can be formed on the flat base semiconductor layer 8. The base semiconductor layer 8 and the compound semiconductor layer 9 may be dry-etched to form a compound semiconductor layer 9 having a starting point 9T. The base semiconductor layer 8 may be formed to have a starting point 8K. This allows the semiconductor substrate 10 to be isolated on the template substrate 7. For example, the semiconductor substrate 10 may have a base semiconductor layer 8 and a compound semiconductor layer 9 in the form shown in FIG. 16.

[0168] (1B) After the base semiconductor layer 8 is grown on the template substrate 7 in the MOCVD apparatus, the semiconductor substrate 10 may be temporarily removed from the MOCVD apparatus before the compound semiconductor layer 9 is formed. In this case, cleavage may occur in the base semiconductor layer 8 by removing the semiconductor substrate 10 from the MOCVD apparatus. Then, the semiconductor substrate 10 having the cleaved base semiconductor layer 8 may be loaded into the MOCVD apparatus, and the compound semiconductor layer 9 having the starting point portion 9T may be formed. In this case, the emission surface F1 and the facing surface F2 are included in the end surface of the epitaxially grown compound semiconductor layer 9. By epitaxially growing the compound semiconductor layer 9 on the base semiconductor layer 8 having a high-quality cleavage surface, the end surface of the compound semiconductor layer 9 can be made high quality. Therefore, the end surface of the epitaxially grown compound semiconductor layer 9 can be used as a resonator surface.

[0169] (1C) In the first embodiment, the mask portion 5 is removed after the element portion DS is formed on the template substrate 7, but in another configuration example, the mask portion 5 may be removed before the step of forming the element portion DS. For example, after the semi-element portion sDS is formed by isolating elements on the template substrate 7, the mask portion 5 may be removed before the element portion DS is formed. In this case, there is an advantage that it is not necessary to protect the insulating film DF so that the insulating film DF is not removed when removing the mask portion 5.

[0170] (1D) In another configuration example, the semiconductor laser element 20 may be mounted on the support substrate SK after forming the second electrode E2 and the reflector film UF with the element portion DS supported by a temporary substrate. In addition, both the temporary substrate DK and the support substrate SK may be divided with the semiconductor laser element 20 sandwiched between the temporary substrate and the support substrate SK. In this case, the individual pieces of the divided temporary substrate DK may be removed.

[0171] Also, a first support substrate having wiring may be used instead of the temporary substrate DK, and in this case, both the first support substrate and the support substrate SK (second support substrate) may be cut in a state in which the semiconductor laser element 20 is sandwiched between them. This may result in a semiconductor laser chip 21 including an individual piece of the first support substrate and the support ST.

[0172] (1E) FIG. 27 is a plan view for explaining another example of the base semiconductor layer 8 in the first embodiment. As shown in FIG. 27, the base semiconductor layer 8 of the example may have an origin portion 8K in which a notch is formed up to a position close to the origin induction portion 5Y in a plan view. The tip of the origin portion 8K is referred to as the tip portion 8P. For example, the origin portion 8K may be located at a position where the tip portion 8P overlaps with the origin induction portion 5Y in a plan view. The origin portion 8K may have a virtual triangular shape in a plan view. In this virtual triangle, a virtual line segment corresponding to the base when the tip portion 8P is the apex is referred to as the side 8C. The distance from the side 8C to the tip portion 8P is referred to as the cutout length H2 of the origin portion 8K. The cutout length H2 may be WM / 4 or more, or WM / 3 or more, using the width WM of the mask portion 5 (see FIG. 4). The cutout length H2 may be WM / 2 or less.

[0173] By forming the compound semiconductor layer 9 on the base semiconductor layer 8, the compound semiconductor layer 9 is formed into a shape having an origin portion (not shown) corresponding to the origin portion 8K. The origin portion formed in the compound semiconductor layer 9 may have an end face which is an m-plane of a GaN-based semiconductor by being formed into a shape corresponding to the origin portion 8K. The end face of the origin portion formed in the compound semiconductor layer 9 does not have to be an m-plane of a GaN-based semiconductor.

[0174] Fig. 28 is an exploded perspective view for explaining the configuration of the half-element portion sDS formed by isolating the base semiconductor layer 8 and the compound semiconductor layer 9. In Fig. 28, for convenience of explanation, the template substrate 7 and the base semiconductor layer 8 are virtually separated from each other, but in reality, the base semiconductor layer 8 and the mask portion 5 are in contact with each other. In addition, the base semiconductor layer 8 has a bonding portion 8S corresponding to the initial growth layer SL on the lower surface, and the bonding portion 8S and the seed layer 3 are bonded to each other. In addition, in Fig. 28, the template substrate 7 is illustrated not in its entirety but in part with the omitted portions.

[0175] 28, in the base semiconductor layer 8 in the half element portion sDS of the example, the first base end surface 8X may not have the third partial surface 8X3. The angle (interior angle) between the second base end surface 8Y and the third base end surface 8Z is referred to as θ4. θ4 may be an obtuse angle, for example, 120° or approximately 120°, for example, about 110° to 130°. Alternatively, θ4 may exceed 130°. The second base end surface 8Y may be an m-plane of a GaN-based semiconductor.

[0176] (1F) In another configuration example of the first embodiment, the element portion DS may have a part of the compound semiconductor layer 9 removed by etching or the like, or the compound semiconductor layer 9 may be partially formed on the base semiconductor layer 8. In this case, the first electrode E1 may be connected to the first pad P1 via the first joint A1, and the second electrode E2 may be connected to the second pad P2 via the conductive film MF and the second joint A2. In this example, the element portion DS can be mounted on the support substrate SK without the need to form the insulating film D1 covering the side surfaces of the base semiconductor layer 8 and the compound semiconductor layer 9.

[0177] Example 2 In the first embodiment, the semiconductor laser device 20 has a double-sided electrode structure, but in the second embodiment, the semiconductor laser device 20 may have a single-sided two-electrode structure. Fig. 29 is a cross-sectional view showing the configuration of the semiconductor laser device 20 in the second embodiment.

[0178] 29, the semiconductor laser device 20 in the second embodiment may include a device portion DS including a base semiconductor layer 8 and a compound semiconductor layer 9, and a support substrate SK that holds the device portion DS. Examples of materials for the support substrate SK include Si, SiC, and AlN. The support substrate SK is disposed such that the compound semiconductor layer 9, the first electrode E1, and the second electrode E2 are located between the support substrate SK and the base semiconductor layer 8.

[0179] The first electrode E1 overlaps the optical resonator LK (not shown) in a plan view and also overlaps the second portion B2 of the base semiconductor layer 8. The second electrode E2 is provided on the same side as the first electrode E1 with respect to the base semiconductor layer 8. The second electrode E2 is in contact with the base semiconductor layer 8, and the first electrode E1 and the second electrode E2 do not overlap each other in a plan view. Specifically, the base semiconductor layer 8 has a width in the X direction larger than that of the compound semiconductor layer 9, and the second electrode E2 is formed in an exposed portion where the compound semiconductor layer 9 is not formed. The exposed portion may be formed by removing a part of the compound semiconductor layer 9 by reactive ion etching (RIE) or the like, or may be formed by partially depositing the compound semiconductor layer 9 on the base semiconductor layer 8. Although not shown, the compound semiconductor layer 9 may have an optical resonator LK, and a pair of resonator faces of the optical resonator LK may be covered with a reflecting mirror film UF.

[0180] The support substrate SK includes a conductive first pad P1 and a second pad P2, the first electrode E1 is connected to the first pad P1 via a first joint A1, and the second electrode E2 is connected to the second pad P2 via a second joint A2. In the second embodiment, the second joint A2 is thicker than the first joint A1, and the difference in thickness between the first joint A1 and the second joint A2 is equal to or greater than the thickness of the compound semiconductor layer 9. This enables the first and second electrodes E1 and E2 to be connected to the first and second pads P1 and P2 located on the same plane.

[0181] The support substrate SK may be divided into support members ST, in which case the semiconductor laser element 20 may be a semiconductor laser chip 21. The support member ST can be used as a substrate (also called a submount) for the semiconductor laser chip 21. The semiconductor laser chip 21 functions as a COS (Chip on Submount).

[0182] FIG. 30 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor laser element 20 in Example 2. As shown in FIG. 30, Example 2 includes a step of preparing a template substrate 7 including a base substrate UK and a mask layer 6, a step of forming a first semiconductor layer S1 (and a third semiconductor layer S3) that will be the origin of a base semiconductor layer 8 by an ELO method (described later), and a step of forming a second semiconductor layer S2 (and a fourth semiconductor layer S4) that will be the origin of a compound semiconductor layer 9. A mask layer 6 having an origin inducing portion 5Y may be formed in the mask portion 5, and in this case, the first semiconductor layer S1 (and the third semiconductor layer S3) has an origin portion 8K. In addition, when the second semiconductor layer S2 is formed at a position including the origin portion 8K on the first semiconductor layer S1, it can be formed to have an origin portion 9T.

[0183] The starting point 8K may be formed in the third portion B3, and the second semiconductor layer S2 may be provided above the second portion B2. In this case, the optical resonator LK is provided at a position overlapping the second portion B2 in a plan view. The second semiconductor layer S2 may not have the starting point 9T, and a starting point for cleavage may be formed by scribing as described later (Example 3, etc.).

[0184] Next, a half-element portion sDS is formed by isolating elements on the template substrate 7. Thereafter, a ridge portion RJ is formed in the first semiconductor layer S1, and a first electrode E1, a second electrode E2, etc. are formed. In this way, an element portion DS having a one-sided two-electrode structure is formed on the template substrate 7.

[0185] Then, the element portion DS is bonded to the support substrate SK, and the first semiconductor layer S1 is separated from the template substrate 7. For example, after the element portion DS is formed, the mask portion 5 is etched away, and the first and second bonding portions A1 and A2 (e.g., solder) of the support substrate SK are heated and melted, and the element portion DS is bonded to the support substrate SK. Then, one or both of the support substrate SK and the base substrate UK are displaced so that the support substrate SK and the base substrate UK move away from each other. This breaks the bonding portion (downward protruding portion) between the back surface of the first semiconductor layer S1 and the base substrate UK, and the first semiconductor layer S1 is separated from the template substrate 7. As a result, a two-dimensionally arranged semiconductor laser substrate (see FIG. 22) is formed.

[0186] The two-dimensionally arranged semiconductor laser substrate may be divided into rows to form one-dimensionally arranged (rod-shaped) semiconductor laser substrates, and then a reflector film UF may be formed on each of the emission surface F1 and the opposing surface F2. Next, a step of dividing the support substrate SK into a plurality of supports ST may be performed. By having each support ST hold one or more semiconductor laser elements 20, a plurality of semiconductor laser chips 21 can be formed.

[0187] Example 3 In the third embodiment, a template substrate 7 that does not have the origin inducing portion 5Y in the mask portion 5 may be used. In the third embodiment, a semiconductor laser element 20 having a one-side two-electrode structure is manufactured. Fig. 31 is a flowchart showing an example of a manufacturing method of the semiconductor laser element in the third embodiment.

[0188] As shown in FIG. 31, in Example 3, first, a template substrate 7 (see FIG. 4) having no origin inducing portion in a mask layer 6 is prepared, and then a base semiconductor layer 8 and a compound semiconductor layer 9 are formed on the template substrate 7.

[0189] In the third embodiment, the template substrate 7 may be prepared, for example, as follows. First, a silicon oxide film having a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed on the entire surface of the underlayer 4 by using a sputtering method, a CVD method, a deposition method, or the like. Then, a resist is applied to the entire surface of the silicon oxide film. After that, the resist is patterned by using a photolithography method to form a resist having a plurality of stripe-shaped openings. Then, a plurality of openings KS and a mask portion 5 are formed by removing a part of the silicon oxide film by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF). Next, the resist is removed by organic cleaning to form a mask layer 6. As a result, the template substrate 7 as shown in FIG. 4 can be obtained.

[0190] Next, the template substrate 7 is loaded into the MOCVD apparatus, and a GaN-based semiconductor layer is formed by the ELO method. In Example 3, the base semiconductor layer 8 is an n-type GaN layer, and the ELO formation of Si-doped GaN is performed on the template substrate 7 using the MOCVD apparatus. As an example of the ELO film formation conditions, the following can be adopted: substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, V / III=6000 (ratio of the supply amount of V-group raw material to the supply amount of III-group raw material). An initial growth layer SL is selectively grown on the seed layer 3 (the GaN layer that is the top layer of the seed layer 3) exposed in the opening KS, and then grows laterally on the mask portion 5. Then, the lateral growth of the base semiconductor layer 8 growing laterally from both sides on the mask portion 5 is stopped before they meet.

[0191] The deposition time may be further extended to cause adjacent base semiconductor layers 8 to meet. In this case, after the compound semiconductor layer 9 is formed on the base semiconductor layer 8, the meeting portion of the base semiconductor layer 8 may be removed by dry etching or the like.

[0192] Fig. 32 is a plan view showing the configuration of a semiconductor substrate 10 on which a base semiconductor layer 8 is formed in Example 3. As shown in Fig. 32, in Example 3, the base semiconductor layer 8 does not have a starting point portion 8K.

[0193] Next, a step of forming a compound semiconductor layer 9, a step of forming an element structure, and a step of forming a cleavage starting point are performed. Fig. 33 is a plan view showing the configuration of a semiconductor substrate 10 on which an element structure in Example 3 is formed. Fig. 34 is a cross-sectional view showing the configuration of the semiconductor substrate 10 in Fig. 33. In Fig. 34, the template substrate 7 is omitted.

[0194] The compound semiconductor layer 9 may be formed on the entire surface of the base semiconductor layer 8, in which case a part of the base semiconductor layer 8 may be exposed by reactive ion etching. Alternatively, the compound semiconductor layer 9 may be partially formed on the upper surface of the base semiconductor layer 8. A second electrode E2 may be formed on the exposed part of the base semiconductor layer 8. Then, a ridge portion RJ is formed in the compound semiconductor layer 9, and an insulating film DF and a first electrode E1 are formed. In this way, a semiconductor substrate 10 having the template substrate 7 and the element structure 22 formed on the template substrate 7 can be obtained.

[0195] Next, a cleavage starting point is formed in the element structure 22. The cleavage starting point may be formed in the base semiconductor layer 8 or in the compound semiconductor layer 9. The method of forming the cleavage starting point is not particularly limited. For example, the cleavage starting point may be formed by diamond scribing. In this case, the cleavage starting point can be formed in a thin shape, so that the cleavage starting point is likely to be concentrated in one place. Therefore, a smooth cleavage surface can be easily obtained. Since the insulating film DF formed on the compound semiconductor layer 9 is thin, the cleavage starting point can be formed in the compound semiconductor layer 9 while ignoring the presence of the insulating film DF. The insulating film DF does not need to be formed in the compound semiconductor layer 9 in the portion where the cleavage starting point is to be formed. In other words, the compound semiconductor layer 9 may be exposed in the portion of the insulating film DF where the cleavage starting point is to be formed.

[0196] Also, for example, the starting point for cleavage may be formed by laser scribing, in which case the variation in the length of the scribe can be reduced, thereby improving the yield. The length of the laser scribe is the scanning distance of the laser. Also, the starting point for cleavage may be formed by dry etching or wet etching, in which case the cleavage proceeds without deviating from the cleavage plane, making it easier to obtain a smooth cleavage plane.

[0197] The starting point for cleavage may be formed by combining the above methods. In this case, the advantages of each method can be enjoyed at the same time. The starting point formed by diamond scribing or laser scribing may be further wet etched, in which case the shape of the starting point for cleavage can be shaped. Also, the starting point formed by dry etching may be further wet etched, in which case the shape of the starting point for cleavage can be shaped.

[0198] Next, the element structure 22 having the cleavage starting point formed therein is cleaved. For example, cleavage may be generated at the cleavage starting point by applying a blade to the cleavage starting point and applying a force in a direction perpendicular to the surface direction. In this case, a strong force can be applied to the cleavage starting point, improving the yield. Alternatively, cleavage may be generated at the cleavage starting point by applying vibration to the cleavage starting point. In this case, the processing can be performed relatively easily, simplifying the manufacturing process.

[0199] Also, by raising or lowering the temperature of the semiconductor substrate 10 from room temperature, a thermal stress may be applied to the starting point to generate cleavage by utilizing the difference in thermal expansion coefficient between the main substrate 1 and the base semiconductor layer 8. When the difference in thermal expansion coefficient is utilized, the force is applied evenly across the surface, improving the yield.

[0200] Alternatively, the template substrate 7 may be curved by thinning the main substrate 1 by polishing or the like, thereby applying stress to the element structures 22 on the template substrate 7 to perform cleavage, in which case the element structures 22 can be separated into elements to form a plurality of element portions DS at once, thereby reducing the manufacturing cost.

[0201] The element structure 22 may be cleaved by a combination of the above cleavage techniques, in which case the advantages of each technique can be enjoyed simultaneously.

[0202] In the third embodiment, the timing for removing the mask portion 5 to separate the element portion DS from the template substrate 7 is preferably after the formation of the starting point portions for cleavage or after cleavage, which allows the formation of the starting point portions or cleavage to be performed stably, improving the yield.

[0203] In the third embodiment, a difference in thermal expansion coefficient between the template substrate 7 and the base semiconductor layer 8 may cause internal stress in the base semiconductor layer 8. Also, a difference in lattice constant between the template substrate 7 and the base semiconductor layer 8 may cause internal stress in the base semiconductor layer 8. The occurrence of internal stress in the base semiconductor layer 8 can make cleavage occur more easily.

[0204] For example, internal stress is generated in the base semiconductor layer 8 and the compound semiconductor layer 9 due to the difference in thermal expansion coefficient between the base semiconductor layer 8 and the compound semiconductor layer 9 and the main substrate 1. For example, when the base semiconductor layer 8 is formed by the ELO method on a heterogeneous substrate such as a Si substrate, the film formation temperature may be as high as 1000° C. or more. Therefore, when the temperature is lowered to room temperature, stress is generated in the base semiconductor layer 8. In addition, strain is generated in the base semiconductor layer 8 due to the difference in lattice constant between the main substrate 1 and the base semiconductor layer 8.

[0205] Here, if the thermal expansion coefficient of the main substrate 1 is larger than that of the base semiconductor layer 8, a compressive stress is generated in the base semiconductor layer 8, and if the thermal expansion coefficient of the main substrate 1 is smaller than that of the base semiconductor layer 8, a tensile stress is generated in the base semiconductor layer 8. Due to the tensile stress generated in the base semiconductor layer 8, cleavage may occur by scribing the compound semiconductor layer 9. When the base semiconductor layer 8 in which a tensile stress is generated is cleaved, the possibility that the individual pieces of the divided base semiconductor layer 8 come into contact with each other can be reduced. Therefore, the possibility that the end face of the divided base semiconductor layer 8 is scratched can be reduced. In addition, since cleavage occurs in the element structure 22 as if it is torn from the starting point due to the application of a tensile stress, the cleavage surface is likely to be smooth.

[0206] For example, the internal stress of the base semiconductor layer 8 may be released by scribing the base semiconductor layer 8, and the cleavage of the element structure 22 may proceed naturally. Alternatively, the internal stress of the base semiconductor layer 8 may be released by scribing the compound semiconductor layer 9, and the cleavage of the element structure 22 may proceed naturally. "Natural cleavage proceeds by scribing" means that scribing and cleavage occur at the same or almost the same timing (spontaneous cleavage occurs with scribing). This makes it possible to omit the step of forming the starting point portion (scribing step) and the step of cleaving the starting point portion (breaking step). This makes it possible to reduce the manufacturing cost of the semiconductor laser element 20.

[0207] Next, the element portion DS is separated from the template substrate 7. The subsequent steps are similar to those in the first and second embodiments, and therefore a description thereof will be omitted.

[0208] As described above, in the third embodiment, after the element structure is formed, the cleavage starting point can be formed at any position. Therefore, the position where the cleavage starting point is formed can be controlled. As a result, the position where the cleavage occurs can be controlled, and the cavity length L1 can be adjusted. Therefore, the yield can be easily improved.

[0209] [Alternative Configuration Example 3] In the above-described third embodiment, the step of forming an element structure is performed, followed by the step of forming an origin portion and the step of isolating elements on the template substrate 7, but the order is not limited to this. The step of forming an element structure may be performed after the step of forming an origin portion, and then the step of isolating elements on the template substrate 7 may be performed.

[0210] Example 4 In the fourth embodiment, element isolation may be performed by etching instead of cleavage. Fig. 35 is a plan view showing an example of element isolation in the fourth embodiment.

[0211] 35, after a base semiconductor layer 8 and a compound semiconductor layer 9 are formed on a template substrate 7, etching is performed to form a plurality of trenches TR (separation grooves) in a semiconductor substrate 10. This may separate the template substrate 7 into a plurality of half-element units sDS each having an optical resonator LK. The trenches TR penetrate the compound semiconductor layer 9 and the base semiconductor layer 8. The mask unit 5 and the seed layer 3 or the main substrate 1 may be exposed in the trenches TR.

[0212] In addition, the etching may cause a taper angle on the end face of the compound semiconductor layer 9 (the end face may deviate from the vertical). For this reason, for example, element separation may be performed as follows. That is, first, the semiconductor substrate 10 is set in a slightly tilted state in an etching apparatus. Next, a trench TR corresponding to one side in the Y direction of the half element portion sDS to be formed by the following etching process is formed by etching. This forms one of the pair of resonator surfaces of the half element portion sDS (e.g., the emission surface F1). As a result, for example, the emission surface F1 can be formed vertically or approximately vertically. Next, the semiconductor substrate 10 is set in a slightly tilted state on the opposite side (the opposite side to the side in which the trench TR was formed) in an etching apparatus. Then, a trench TR corresponding to one side in the Y direction of the half element portion sDS is formed by etching. This forms the other of the pair of resonator surfaces of the half element portion sDS (e.g., the opposing surface F2). As a result, for example, the opposing surface F2 can be formed vertically or approximately vertically.

[0213] Example 5 Fig. 36 is a schematic diagram showing the configuration of an electronic device according to Example 5. An electronic device 50 in Fig. 36 includes a semiconductor laser device ZD (semiconductor laser element 20 or semiconductor laser chip 21) and a control unit 80 including a processor and controlling the semiconductor laser device ZD. Examples of the electronic device 50 include a lighting device, a display device, a communication device, an information processing device, a medical device, an electric vehicle (EV), and the like.

[0214] Example 6 In the first embodiment, the compound semiconductor section 9 is provided on the c-plane of the base semiconductor section 8, and the pair of cavity faces are the m-planes of a nitride semiconductor, but this is not limiting. For example, the compound semiconductor section 9 may be provided on the m-plane ((1-100) plane) of the base semiconductor section 8, and the pair of cavity faces may be the c-plane ((0001) plane) of a nitride semiconductor. The cavity length L1 is the length in the c-axis direction. The emission surface F1 and the opposing surface F2 may be formed, for example, by c-plane cleavage of a nitride semiconductor.

[0215] [Additional notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-mentioned embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0216] 1 Main Board 5 Mask section 5Y Origin Inducer 6 Mask layer (mask) 7 Template Substrate 8 Base semiconductor layer (base semiconductor part) 8K, 9T starting point (starting point) 9 Compound semiconductor layer (compound semiconductor section) 20 Semiconductor laser element (semiconductor device) 21 Semiconductor laser chip 70 Manufacturing equipment B1 Part 1 B2 Part 2 B3 Part 3 DS element part E1 1st electrode E2 2nd electrode F1 Output surface (resonator surface) F2 Opposite surface (resonator surface) LK optical resonator RJ Ridge sDS Semi-element part (element part) SK support board

Claims

1. preparing a main substrate, a base semiconductor portion formed above the main substrate, and a compound semiconductor portion formed on the base semiconductor portion; dividing the base semiconductor portion and the compound semiconductor portion on the main substrate to form a plurality of optical resonators, each of which includes a resonator surface; In the step of forming the plurality of optical resonators, the main substrate is not divided, or the main substrate is divided into a number of pieces fewer than the number of the optical resonators; the base semiconductor portion and the compound semiconductor portion include nitride semiconductors, the resonator facets are formed by cleaving the base semiconductor portion and the compound semiconductor portion.

2. A method of manufacturing a semiconductor device, comprising: preparing a main substrate; a base semiconductor portion formed above the main substrate; and a compound semiconductor portion formed on the base semiconductor portion; dividing the base semiconductor portion and the compound semiconductor portion on the main substrate to form a plurality of optical resonators, each of which includes a resonator surface; In the step of forming the plurality of optical resonators, the main substrate is not divided, or the main substrate is divided into a number of pieces fewer than the number of the optical resonators; The base semiconductor portion includes a first portion and a second portion having a threading dislocation density that is 1 / 5 or less of that of the first portion.

3. The method for manufacturing a semiconductor device according to claim 2 , wherein the resonator facets are formed by etching the base semiconductor portion and the compound semiconductor portion.

4. A method of manufacturing a semiconductor device comprising the steps of: preparing a main substrate; a base semiconductor portion formed above the main substrate; and a compound semiconductor portion formed on the base semiconductor portion; dividing the base semiconductor portion and the compound semiconductor portion on the main substrate to form a plurality of optical resonators, each of which includes a resonator surface; In the step of forming the plurality of optical resonators, the main substrate is not divided, or the main substrate is divided into a number of pieces fewer than the number of the optical resonators; The method for manufacturing a semiconductor device further comprises, after forming the resonator facet, isolating an element portion having the resonator facet from the main substrate.

5. a mask between the main substrate and the base semiconductor portion; The mask includes a mask portion and an elongated opening, The method for manufacturing a semiconductor device according to claim 1 , further comprising forming a notch in the opening.

6. By forming a notch in the opening, a notch is naturally formed in the base semiconductor portion, The method for manufacturing a semiconductor device according to claim 5 , wherein a notch in the base semiconductor portion serves as a starting point for the cleavage.

7. The method of claim 1 , wherein the base semiconductor portion and the compound semiconductor portion have thermal expansion coefficients different from a thermal expansion coefficient of the main substrate.

8. The method of claim 7 , wherein the cleaving occurs spontaneously during cooling of the base semiconductor portion and the compound semiconductor portion.

9. The method for manufacturing a semiconductor device according to claim 1 , further comprising forming a starting point for the cleavage in the base semiconductor portion after forming the base semiconductor portion.

10. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of forming the compound semiconductor portion and forming the starting point of the cleavage in the compound semiconductor portion after the compound semiconductor portion is formed.

11. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the starting points are formed by diamond scribing.

12. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the starting points are formed by laser scribing.

13. The method for manufacturing a semiconductor device according to claim 11 , further comprising wet etching the starting points.

14. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the starting points are formed by etching.

15. The etching is a dry etching, The method for manufacturing a semiconductor device according to claim 14 , further comprising wet etching the starting points.

16. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the cleavage occurs from the starting point by changing temperatures of the base semiconductor portion and the compound semiconductor portion.

17. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the cleavage occurs from the starting point by applying an external force to at least one of the base semiconductor portion and the compound semiconductor portion.

18. The method of claim 1 , wherein the cleaving occurs by scribing the compound semiconductor portion.

19. the compound semiconductor portion includes a GaN-based semiconductor, The method for manufacturing a semiconductor device according to claim 1 , wherein the cavity facet is an m-plane of the compound semiconductor portion.

20. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the main substrate and the base semiconductor portion have different lattice constants.

21. The method of claim 20, wherein the primary substrate is a silicon substrate.

22. The method of claim 20 , wherein the base semiconductor portion comprises a GaN-based semiconductor.

23. The method for manufacturing a semiconductor device according to claim 1, further comprising forming a first electrode and a second electrode located above the compound semiconductor portion.

24. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the main substrate is not divided in the process of forming the multiple optical resonators.

25. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein the compound semiconductor section includes a first type semiconductor section, an active section, and a second type semiconductor section in this order.

26. The method for manufacturing a semiconductor device according to claim 2 , wherein the element portion having the cavity facets includes a ridge structure overlapping the second portion in a plan view.

27. The threading dislocation density of the second portion is 5×10 ６ / cm ２ 3. The method of claim 2, wherein:

28. A method of manufacturing a semiconductor device, comprising: preparing a main substrate; a base semiconductor portion formed above the main substrate; and a compound semiconductor portion formed on the base semiconductor portion; dividing the base semiconductor portion and the compound semiconductor portion on the main substrate to form a plurality of optical resonators, each of which includes a resonator surface; In the step of forming the plurality of optical resonators, the main substrate is not divided, or the main substrate is divided into a number of pieces fewer than the number of the optical resonators; A method for manufacturing a semiconductor device, comprising forming the base semiconductor portion by an ELO method.

29. A template substrate comprising a main substrate, a seed portion, and a mask, The mask includes an elongated opening and a mask portion, A template substrate, the template substrate having a notch in the opening.

30. A base semiconductor portion; a compound semiconductor portion located above the base semiconductor portion and having an optical resonator including a pair of resonator faces; the base semiconductor portion and the compound semiconductor portion include a GaN-based semiconductor; the base semiconductor portion includes an m-plane cleavage surface of the GaN-based semiconductor, a first base end facet including an m-plane cleavage plane of the GaN-based semiconductor; and a second base end facet adjacent to the first base end facet at an angle thereto, the second base end facet being a non-cleavage plane.

31. 31. The semiconductor device of claim 30, wherein an interior angle between the first base end surface and the second base end surface is obtuse.

32. The semiconductor device according to claim 30 , wherein the base semiconductor portion has a third base end face adjacent to the second base end face at an angle and parallel to an a-plane of the GaN-based semiconductor.

33. An electronic device comprising the semiconductor device according to any one of claims 30 to 32.

34. A semiconductor device manufacturing apparatus which performs each process described in any one of claims 1, 2, 4, or 28.

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