System and method for calibrating a digital phase-locked loop - Patents.com

Abstract

The clock generator calibration system includes a phase-locked loop (PLL) and a correction circuit. The PLL is capable of generating an output clock signal, and the correction circuit is capable of adjusting a frequency signal of the PLL based on a digital signal of the PLL. The digital signal is generated based on the frequency signal being adjusted.

Description

[Technical field]

[0001] Aspects described herein relate generally to digital phase-locked loops (PLLs), including systems and methods for estimating and calibrating integral nonlinearity of a digital-to-time converter (DTC). [Background technology]

[0002] Wireless communication and radar systems with increased data rates require highly accurate synchronized clock generation. Such systems may use one or more PLLs. Traditional PLLs require a dedicated full-range time-to-digital converter (TDC), a dedicated short-TDC with high resolution and a configurable delay element, and dedicated feedback. Traditional systems also require dedicated hardware such as a TDC, an analog-to-digital converter (ADC), and / or feedback to the digital domain. [Brief description of the drawings]

[0003] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of those aspects and to enable one of ordinary skill in the relevant art to make and use those aspects.

[0004] [Figure 1] 1 illustrates a communication device according to an exemplary aspect of the present disclosure. [Figure 2A]1 illustrates a clock generator according to an exemplary embodiment of the present disclosure. [Figure 2B] 1 illustrates a clock generator according to an exemplary embodiment of the present disclosure. [Diagram 3] 1 illustrates a number of histogram distributions according to example aspects of the present disclosure. [Figure 4] 1 illustrates a flowchart of a coarse correction method according to an exemplary embodiment of the present disclosure. [Diagram 5] 1 illustrates a flowchart of a fine correction method according to an exemplary embodiment of the present disclosure.

[0005] Exemplary aspects of the present disclosure are described with reference to the accompanying drawings, in which the drawing in which an element first appears is typically indicated by one or more leftmost digits in the corresponding reference number. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the aspects of the present disclosure. However, it will be apparent to those skilled in the art that the aspects, including structures, systems, and methods, can be practiced without the use of these specific details. The descriptions and representations herein are the general means used by those skilled in the art or those familiar with the technical field of the present disclosure to most effectively convey the substance of their work to others skilled in the art. In other instances, well-known methods, procedures, components, and circuits have not been described in detail to avoid unnecessarily obscuring the aspects of the present disclosure.

[0007] Aspects described herein generally relate to digital phase-locked loops (PLLs), including systems and methods for estimating and calibrating the integrated-nonlinearity of a digital-to-time converter (DTC).

[0008] A wireless communication device may be configured for multiple radio access technologies (RATs). In these examples, one or more transceivers of the communication device may be configured to perform carrier aggregation. Exemplary RATs include (but are not limited to) 2G, 3G, 4G, LTE, 5G, satellite navigation technologies (e.g., GNSS, etc.), BT, WiFi, CDMA, or one or more other wireless technologies as would be understood by one of ordinary skill in the art.

[0009] Aspects herein are applicable to transmitters, receivers, and other electronic devices requiring accurate clock generation, as would be understood by one of ordinary skill in the art. Although aspects are described with respect to wireless communications, the present disclosure is not limited to wireless communications implementations and may include other applications that employ clock generators and synchronization using one or more such generated clocks, including wired communications, data processing, or encryption, etc.

[0010] FIG. 1 illustrates a communication device 100 according to an example aspect of the present disclosure. The communication device 100 is configured to transmit and / or receive wireless communications via one or more wireless technologies. For example, the communication device 100 may be configured for wireless communications conforming to one or more fifth generation (5G) “New Radio” cellular communication protocols, such as, for example, one or more 5G protocols, as would be understood by one of ordinary skill in the art. The communication device 100 is not limited to these communication protocols, and may be configured for one or more additional or alternative wireless and / or wired communication protocols, such as, for example, one or more protocols of the Third Generation Partnership Project (e.g., Long-Term Evolution (LTE)), one or more wireless local area networking (WLAN) communication protocols, and / or one or more other communication protocols, as would be understood by one of ordinary skill in the relevant art.

[0011] Communications device 100 may be configured to communicate with one or more other communications devices, including, for example, one or more base stations, one or more access points, one or more other communications devices, and / or one or more other devices as one of ordinary skill in the art would understand. Although exemplary aspects of communications device 100 are described with respect to wireless communications, communications device 100 may also be configured for one or more wired communications technologies as one of ordinary skill in the art would understand.

[0012] In one exemplary aspect, the communications device 100 includes a controller 140 communicatively coupled to one or more transceivers 105. The transceivers 105 are configured to transmit and / or receive wireless communications via one or more wireless technologies. In one exemplary aspect, the transceivers 105 include processor circuitry configured to transmit and / or receive wireless communications conforming to one or more wireless protocols. In other aspects, additionally or alternatively, the transceivers 105 are configured to transmit and / or receive wired communications via one or more wired technologies. In one exemplary aspect, the processor circuitry of the transceivers 105 is configured to transmit and / or receive wired communications conforming to one or more wired protocols.

[0013] In one exemplary embodiment, the transceiver 105 includes a transmitter 110 and a receiver 120 configured to transmit and receive, respectively, multiple wireless communications via one or more antennas 130. In a wired communication embodiment, the transmitter 110 and the receiver 120 are configured to transmit and receive, respectively, wired communications.

[0014] In aspects having two or more transceivers 105, the two or more transceivers 105 may have their own antenna 130 or may share a common antenna via a duplexer. In one exemplary aspect, the transceiver 105 (including the transmitter 110 and / or the receiver 120) is configured to perform one or more baseband processing functions (e.g., media access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.).

[0015] In one exemplary aspect, the transceiver 105 additionally includes a clock generator 125 configured to generate one or more highly accurate synchronized clock signals that may be used by the transmitter 110, the receiver 120, one or more other components of the transceiver 105, the controller 140, and / or one or more other components of the communications device 100. In one exemplary aspect, the clock generator 125 includes processor circuitry configured to perform one or more operations and / or functions of the clock generator 125, including generating the one or more clock signals.

[0016] Antenna 130 may be a single antenna, may include multiple antennas, or may include one or more antenna elements forming an integer array of antenna elements. In one exemplary embodiment, antenna 130 is a phased array antenna, which includes multiple radiating elements (multiple antenna elements), each of which has a corresponding phase adjuster. Antenna 130 configured as a phased array antenna may be configured to perform one or more beamforming and / or beam scanning operations. The beamforming operations may include generating beams formed by shifting the phase of signals radiated from each radiating element to provide constructive / destructive interference, thereby steering the beam in a desired direction.

[0017] In one exemplary aspect, the controller 140 includes a processor circuit 150 configured to control the overall operation of the communications device 100, such as the operation of the one or more transceivers 105. The processor circuit 150 may be configured to control the transmission and / or reception of multiple wireless communications by the one or more transceivers 105 and / or to control phase shifts and / or amplifier gain values ​​associated with multiple antenna elements of the antenna 130.

[0018] In one exemplary aspect, processor circuitry 150 is configured to perform one or more baseband processing functions (e.g., media access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.) in cooperation with transceiver 105 or on behalf of such operations / functions performed by transceiver 105. Processor circuitry 150 is configured in one or more aspects to perform one or more applications and / or operating systems, power management (e.g., battery control and monitoring, etc.), display settings, volume control, and / or user interaction via one or more user interfaces (e.g., keyboard, touch screen display, microphone, speaker, etc.).

[0019] In one exemplary embodiment, the controller 140 further includes a memory 160 for storing data and / or instructions that, when executed by the processor circuitry 150, cause the processor circuitry 150 to perform the associated functions described herein.

[0020] The memory 160 may be any well-known volatile and / or non-volatile memory, including, for example, read only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read only memory (EPROM), and programmable read only memory (PROM). The memory 160 may be non-removable, removable, or a combination of both. The controller 140 may additionally or alternatively be configured to access an external memory and store data in or retrieve data from the external memory.

[0021] Examples of communication device 100 include (but are not limited to) mobile computing devices (mobile devices), such as laptop computers, tablet computers, mobile phones or smartphones, "phablets," personal digital assistants (PDAs), and mobile media players, wearable computing devices, such as computerized watches or "smart" watches and computerized glasses, and / or Internet of Things (IoT) devices. In some aspects of the present disclosure, communication device 100 may be a non-handheld communication device, including, for example, a personal computer (PC), a desktop computer, a television, a smart home device, a security device (e.g., electronic / smart locks), an automated teller machine, a computerized kiosk, an autonomous vehicle, a drone, and / or a fixed computing device, such as an in-vehicle / airborne / marine embedded computer terminal.

[0022] In one or more aspects, the communications device 100 or one or more components of the communications device 100 are additionally or alternatively configured to perform digital signal processing (e.g., using a digital signal processor (DSP)), modulation and / or demodulation (using a modulator / demodulator), digital-to-analog conversion (DAC) and / or analog-to-digital conversion (ADC) (using a digital-to-analog converter and an analog-to-digital converter, respectively), encoding / decoding (e.g., using an encoder / decoder having a convolutional encoder / decoder function, a tail-biting convolutional encoder / decoder function, a turbo encoder / decoder function, a Viterbi encoder / decoder function, and / or a low-density parity check (LDPC) encoder / decoder function), frequency conversion (e.g., using mixers, local oscillators, and filters), fast Fourier transform (FFT), precoding, and / or constellation mapping / desigmapping to receive and / or transmit multiple wireless communications conforming to one or more wireless protocols and / or to facilitate beamforming scanning operations and / or beamforming communication operations.

[0023] 2A illustrates a clock generator 200 according to an exemplary aspect of the present disclosure. FIG 2B illustrates a clock generator 201 according to an exemplary aspect of the present disclosure. Clock generators 200 and 201 may be implemented in communication device 100 as clock generator 125 in one or more aspects.

[0024] In one exemplary aspect, the clock generator 200 / 201 includes a phase-locked loop (PLL) 203 and a calibration circuit 205 configured to calibrate the clock generator 200 / 201. A reference clock oscillator 250, such as a crystal oscillator, may provide a reference clock signal to the PLL 203 (e.g., the PLL 203 may be driven by the reference clock signal). Although the illustrated examples show the oscillator 250 external to the clock generator 200 and the PLL 203, in one or more aspects the oscillator 250 may be included within the clock generator 200. In alternative aspects, the oscillator 250 is included within the controller 140 or other components of the communication device 100.

[0025] In one exemplary embodiment, the PLL 203 includes a time-to-digital converter (TDC) 210, a loop filter 215, a digital-to-time converter (DTC) 220, a voltage-controlled oscillator (VCO) 225, and an N-divider 230. In one exemplary embodiment, the loop filter 215 is configured to filter a digital output signal (e.g., a 1-bit signal) of the DTC 220 and generate a filtered signal that drives the VCO 225. In one exemplary embodiment, the VCO 225 is configured to generate one or more clock signals (F_vco) at one or more respective frequencies controlled by the filtered signal provided by the loop filter 215.

[0026] In operation, the output clock signal of the VCO 225 is fed back to the N divider 230. In one exemplary embodiment, the N divider 230 is configured to divide the output clock signal from the VCO 225 by N to obtain a feedback signal (F_vco / N). The feedback signal is then provided to the DTC 220 as shown in FIG. 2A or to the TDC 210 as shown in FIG. 2B. For example, the N divider 230 can be adjusted (e.g., the value of N can be adjusted) based on an external frequency programming signal. In one exemplary embodiment, the N divider 230 is a frequency or fractional divider.

[0027] In one exemplary embodiment shown in FIG. 2A, the clock generator 200 includes a DTC 220 in a feedback path of the PLL 203 and configured to modulate an output signal (F_vco / N) of the VCO 225 to generate a modulated signal (F_mod). In an alternative embodiment of the clock generator 200 shown in FIG. 2B, the DTC 220 modulates a reference clock signal (F_ref) of the reference clock oscillator 250 to generate a modulated reference clock signal (F_ref') and provides the modulated reference clock signal (F_ref') to the TDC 210. In one exemplary embodiment, one or more of the components of the PLL 203 include a processor circuit configured to perform one or more operations and / or functions of the respective components of the PLL 203.

[0028] In one exemplary embodiment, the TDC 210 is a bang-bang TDC, but is not limited thereto. In one exemplary embodiment illustrated in FIG. 2A, the TDC 210 is configured to receive a reference clock signal (F_ref) generated by a reference oscillator 250 and a modulated signal (F_mod) generated by a DTC 220. In this example, the DTC 220 generates the modulated signal (F_mod) based on a feedback signal from a VCO 225 that is divided by an N divider 230. The TDC 210 can compare the reference clock signal to a DTC output signal and generate a digital output signal (e.g., a 1-bit signal) based on the comparison of the reference clock signal and the DTC output signal.

[0029] In one exemplary embodiment, the TDC 210 is configured to measure a time interval of the reference clock signal and / or the feedback signal and convert the reference clock signal, the feedback signal, and / or a comparison of the reference clock and the feedback signal to a digital output (e.g., a binary output). The digital output signal generated by the TDC 210 is then provided from the TDC 210 to the loop filter 215. In one exemplary embodiment, the TDC 210 is configured to determine which signal edge is (the reference signal edge or the DTC output signal edge). In this example, the output of the TDC 210 is a positive one (+1) when the reference edge is leading and a negative one (-1) when the edge of the TDC output signal is leading.

[0030] In one example aspect, the calibration circuit 205 is configured to calibrate the clock generator 200 / 201 to correct for integral nonlinearity (INL) of the DTC 220 of the PLL 203. Before correction, the INL may be referred to as the inherent impairment of the DTC 220. After correction / pre-distortion, any remaining INL may be referred to as the residual INL.

[0031] In one exemplary embodiment, calibration circuitry 205 includes a code ramp 235, a pre-distortion (PD) look-up table (LUT) 240, and a statistics processor 245. In one exemplary embodiment, one or more of the components of calibration circuitry 205 include a processor circuit configured to perform one or more operations and / or functions of the respective components of calibration circuitry 205.

[0032] In one example aspect, code ramp 235 is configured to generate a desired DTC code (e.g., a code ramp) to control operation of PD-LUT 240. In this example, PD-LUT 240 is configured to generate a control signal that controls a modulation operation of DTC 220 (e.g., modulating a feedback signal (in FIG. 2A) or modulating a reference clock signal (in FIG. 2B)).

[0033] In one exemplary embodiment, statistics processor 245 is configured to receive (e.g., sample) the output of TDC 210 and the output of the desired DTC code generated by code ramp 235. Statistics processor 245 is configured to determine a distribution (e.g., the histogram distribution shown in FIG. 3) of the TDC output signal and generate a correction signal (e.g., an offset value) based on the determined distribution to correct the control signal generated by PD-LUT 240. In one exemplary embodiment, the collection of statistics by statistics processor 245 is performed after VCO 225 has locked onto a frequency.

[0034] In one exemplary embodiment, the statistical processor 245 is configured to determine the distribution based on the received TDC output signal and the DTC code generated by the code ramp 235. In this example, the statistical processor 245 counts the number of times the TDC output is −1 and the number of times the TDC output is +1 for the corresponding DTC code provided by the code ramp 235. From these statistics, the statistical processor 245 is configured to adapt the PD-LUT 240 using the determined adjustment / offset value. For example, if the DTC code has a value of k that results in the output of the TDC 210 having a 30:70 distribution (e.g., the TDC output is −1 30% of the time and +1 70% of the time), the statistical processor 245 corrects / adjusts the PD-LUT 240 to offset the output of the PD-LUT 240 such that the resulting TDC 210 approaches and / or achieves a 50:50 distribution.

[0035] For example, if the DTC code has an integral nonlinearity (e.g., 5 ps) and that integral nonlinearity significantly exceeds the system jitter (e.g., all of the noise in the system adds up to an RMS jitter of 0.5 ps), then the DTC code will produce a significant offset between edges (at the input of the TDC 210). As shown in Figure 3, this will cause the output of the TDC 210 to almost always return a value of +1. This will result in the histogram distribution 303 shown in Figure 3.

[0036] Alternatively, if the DTC code has an integral nonlinearity whose value (e.g., 1 ps) is closer to the jitter (e.g., 0.5 ps), the output of the TDC 210 will sometimes return +1 for the corresponding DTC code (due to the Gaussian distribution of the jitter) and other times return -1. This scenario is illustrated in the histogram distribution 301 of FIG. 3.

[0037] That is, in a scenario where the integral nonlinearity is significantly greater than the RMS of the jitter, the statistical processor 245 is configured to detect the sign of the integral nonlinearity, but its magnitude is not detectable until the difference between the magnitude of the integral nonlinearity and the RMS magnitude of the jitter becomes closer. When the difference between the magnitude of the integral nonlinearity and the RMS magnitude of the jitter becomes significantly smaller, the statistical processor 245 may determine statistics regarding the output of the TDC 210 (e.g., 30% -1s, 70% +1s, etc.). Based on these statistics, and as described in more detail below, the statistical processor 245 is advantageously able to accurately calculate the magnitude of the integral nonlinearity.

[0038] In one exemplary aspect, the statistical processor 245 is configured to perform a calibration process to adapt and adjust the PD-LUT 240. The calibration process may include (1) a coarse correction process, and / or (2) a fine correction process.

[0039] In one exemplary embodiment, when the integral nonlinearity is significantly greater than the RMS of the jitter, the statistical processor 245 may employ a coarse correction process until the histogram distribution for the particular DTC code produces both positive and negative integral nonlinearity values. The statistical processor 245 may then employ a fine correction process. The coarse and fine correction processes are described in detail below.

[0040] Coarse Correction Process In one exemplary aspect, when the inertial nonlinearity values ​​are larger than the jitter distribution (e.g., significantly larger when the jitter distribution returns only positive inertial nonlinearity values ​​or negative inertial nonlinearity values), the statistical processor 245 iteratively performs a coarse correction (). The coarse correction process is described with reference to FIG. 4.

[0041] 4 illustrates a flowchart 400 of a coarse correction method according to an exemplary embodiment of the present disclosure, which is described with reference to FIGS.

[0042] Flowchart 400 begins at operation 405 and proceeds to operation 410, where the sign of the integral nonlinearity (INL) is determined. In one exemplary embodiment, code ramp 235 and PD-LUT 240 perform a calibration sequence in which PD-LUT 240 generates an output corresponding to a desired DTC codeword. Statistics processor 245 then records the output of TDC 210. This recording of the output is repeated until statistics processor 245 has a sufficient number of records to determine the sign of the INL. In one exemplary embodiment, statistics processor 245 is configured to control code ramp 235 and PD-LUT 240 to perform the calibration sequence.

[0043] After operation 410, the flowchart 400 moves to operation 415 where the PD-LUT 240 is updated based on the determined sign of the INL. In this example, the statistical processor 245 adjusts the output of the PD-LUT 240 (i.e., the PD code) based on the determined sign of the INL. For example, if the DTC code produces more +1 results from the TDC 210, the PD code is decreased. Alternatively, if the DTC code produces more -1 results from the RDC 210, the PD code is increased. The INL remaining after the adjustment is now referred to as the residual INL.

[0044] After operation 415, the flowchart 400 transitions to operation 420 where additional statistics for the DTC code are obtained (e.g., by the statistical processor 245) and the distribution is analyzed (e.g., by the statistical processor 245). In one exemplary embodiment, the PD-LUT 240 generates an output corresponding to the desired DTC codeword, and the statistical processor 245 records the output of the TDC 210. This recording of the output is repeated by the statistical processor 245 until a sufficient number of records are obtained.

[0045] After operation 420, the flowchart 400 transitions to operation 425, where it is determined whether the INL value (e.g., the residual INL) is within the jitter range (e.g., whether (INL value)≈(jitter range)). In one example aspect, it is determined (e.g., by the statistical processor 245) whether the histogram distribution for the particular DTC code produces both a positive integral nonlinearity value and a negative integral nonlinearity value (e.g., the output of the PD-LUT 240 toggles around the optimal value, the output of the TDC 210 approaches and / or achieves a 50:50 distribution, etc.).

[0046] If operation 425 is affirmative (Yes), then the flowchart 400 proceeds to operation 430 where the flowchart 400 ends. Otherwise (No at operation 425), the flowchart 400 returns to operation 410 where the method is repeated by the iterative process.

[0047] Precision correction process The fine correction process is described with reference to FIG. 5, which illustrates a flowchart 500 of a fine correction method. In one exemplary embodiment, the fine correction process is performed when the INL value is within the jitter range (e.g., (INL value)≈(jitter range)) such that the histogram distribution for a particular DTC code produces both positive and negative integral nonlinearity values, and the output of the TDC 210 approaches and / or achieves a 50:50 distribution. The coarse and fine correction processes may be performed consecutively, or the fine correction process may be performed without previously performing the coarse correction process (e.g., when the DTC code produces both positive and negative integral nonlinearity values, when the INL value is within the jitter range, etc.).

[0048] In one example embodiment, the statistical processor 245 is configured to determine a fractional value of the PD-LUT, which may later be used for rounding or dithering. In this example, the two closest integer values ​​(lower and upper limits) for the PD-LUT 240 are known as the desired DTC code. The desired DTC code may be known, for example, based on the adjustment of the PD-LUT 240 in a coarse correction process.

[0049] In one example embodiment, the statistical processor 245 is configured to control the PD-LUT 240 and the code lamp 235 to drive the DTC 220 by the two closest integer values. The statistical processor 245 then collects statistics to determine the number of DTC 210 output values ​​of +1 and -1 when the smaller integer value (lower bound / floor value) is used to adjust the PD-LUT 240 (operation 510) and the number of DTC 210 output values ​​of +1 and -1 when the larger integer value (upper bound / ceiling value) is used to adjust the PD-LUT 240 (operation 515).

[0050] Based on the determined number, the statistical processor 245 determines a fractional value of the correction signal (operation 520). fractional (C)) is the formula

number

[0051] Advantageously, the determination of the fractional value can be determined according to a number of exemplary embodiments without requiring knowledge of jitter / sigma / RMS, however, as will be appreciated by those skilled in the art, the calculation of the fractional value is not limited to those number of exemplary embodiments.

[0052] In one example, when the jitter is very small compared to the DTC resolution, the clock generator 200 may be configured to increase the number of samples (i.e., the number of statistics obtained) and / or increase the jitter sigma. Increasing the jitter sigma may be accomplished by decreasing the bandwidth of the loop filter 215. In this example, decreasing the bandwidth would increase the VCO jitter.

[0053] In one exemplary embodiment, an initial calibration of the PLL 203 can be performed to correct for INL resulting from generation variations (i.e., generation-induced INL). This initial calibration can use both coarse and fine corrections. An online calibration can then be performed to compensate for environmental changes (e.g., temperature) or changes in the frequency of the VCO, etc. Given that adjustments during the online calibration are likely to be minimal, it is most likely that only fine corrections are required, and coarse corrections can be employed if necessary.

[0054] example The following examples relate to several further aspects.

[0055] Example 1 is a clock generator calibration system, comprising: a phased-locked loop (PLL) configured to generate an output clock signal; a correction circuit configured to adjust a frequency signal of the PLL based on the digital signal of the PLL, the digital signal being generated based on the frequency signal being adjusted.

[0056] Example 2 is the subject of example 1, wherein the frequency signal is a reference clock signal, and the output clock signal is generated based on the reference clock signal.

[0057] Example 3 is the subject of example 1, wherein the frequency signal corresponds to the output clock signal, and the frequency signal is a feedback signal into the PLL.

[0058] Example 4 is the subject matter of any of Examples 1 to 3, wherein the PLL a time-to-digital converter configured to generate the digital signal, the output clock signal being generated based on the digital signal; and a digital-to-time converter configured to generate the conditioned frequency signal based on the digital signal.

[0059] Example 5 is the subject matter of any of Examples 1 to 4, wherein the correction circuit is configured to determine statistics of values ​​of the digital signal, and the adjustment of the frequency signal is based on the determined statistics.

[0060] Example 6 is the subject matter of any of Examples 1 to 5, wherein the correction circuit a code ramp configured to generate a code; a statistics processor configured to generate a correction signal based on the generated code and the digital signal; and a pre-distortion lookup table (PD-LUT) configured to generate a control signal, the control signal controlling the adjustment of the frequency signal based on the correction signal and the generated code.

[0061] Example 7 is the subject matter of any of Examples 1 and 3 to 6, wherein the PLL a time-to-digital converter configured to generate the digital signal based on the regulated frequency signal and a reference signal; a controlled oscillator configured to generate the output clock signal based on the digital signal, the frequency signal being based on the output clock signal; and a digital-to-time converter in a feedback loop of the PLL, the digital-to-time converter configured to receive the frequency signal via the feedback loop and configured to generate the regulated frequency signal based on the digital signal.

[0062] Example 8 is the subject matter of any of Examples 1, 2, and 4 to 6, wherein the PLL comprises: a time-to-digital converter configured to generate the digital signal based on the adjusted frequency signal and a feedback signal related to the output clock signal; a controlled oscillator configured to generate the output clock signal based on the digital signal; a digital-to-time converter configured to receive the frequency signal and generate the regulated frequency signal based on the digital signal, the frequency signal being a reference clock signal; and

[0063] Example 9 is the subject matter of any of Examples 1 to 8, wherein the correction circuit a code ramp configured to generate a code; a statistics processor configured to generate a correction signal based on the generated code and the digital signal; a pre-distortion lookup table (PD-LUT) configured to generate a control signal and provide the control signal to the digital-to-time converter, the control signal controlling the adjustment of the frequency signal by the digital-to-time converter based on the correction signal and the generated code.

[0064] Example 10 is the subject matter of any of Examples 4 to 8, wherein the time-to-digital converter is a bang-bang time-to-digital converter.

[0065] Example 11 is the subject of example 9, wherein the time-to-digital converter is a bang-bang time-to-digital converter.

[0066] Example 12 is a non-transitory computer-readable storage medium having stored thereon an executable computer program, the program causing a processor to: generating an output clock signal based on a reference clock signal by a phased-locked loop (PLL); and and adjusting a frequency signal of the PLL based on the digital signal of the PLL, the digital signal being generated based on the frequency signal being adjusted.

[0067] Example 13 is the subject matter of example 12, wherein the frequency signal is a reference clock signal, and the output clock signal is generated based on the reference clock signal.

[0068] Example 14 is the subject matter of example 12, wherein the frequency signal corresponds to the output clock signal, and the frequency signal is a feedback signal into the PLL.

[0069] Example 15 is the subject matter of any of Examples 12 to 14, wherein the PLL a time-to-digital converter configured to generate the digital signal, the output clock signal being generated based on the digital signal; and a digital-to-time converter configured to generate the conditioned frequency signal based on the digital signal.

[0070] Example 16 is the subject matter of any of Examples 12-15, wherein the program further directs the processor to determine statistics of values ​​of the digital signal, and wherein the adjustment of the frequency signal is based on the determined statistics.

[0071] Example 17 is the subject matter of any of Examples 12-16, wherein the frequency signal is adjusted using a correction circuit, the correction circuit comprising: a code ramp configured to generate a code; a statistics processor configured to generate a correction signal based on the generated code and the digital signal; and a pre-distortion lookup table (PD-LUT) configured to generate a control signal, the control signal controlling the adjustment of the frequency signal based on the correction signal and the generated code.

[0072] Example 18 is the subject matter of any of Examples 12 and 14 to 17, wherein the PLL a time-to-digital converter configured to generate the digital signal based on the regulated frequency signal and a reference signal; a controlled oscillator configured to generate the output clock signal based on the digital signal, the frequency signal being based on the output clock signal; and a digital-to-time converter in a feedback loop of the PLL, the digital-to-time converter configured to receive the frequency signal via the feedback loop and configured to generate the regulated frequency signal based on the digital signal.

[0073] Example 19 is the subject matter of any of Examples 12, 13, and 15 to 17, wherein the PLL comprises: a time-to-digital converter configured to generate the digital signal based on the adjusted frequency signal and a feedback signal related to the output clock signal; a controlled oscillator configured to generate the output clock signal based on the digital signal; a digital-to-time converter configured to receive the frequency signal and generate the regulated frequency signal based on the digital signal, the frequency signal being a reference clock signal; and

[0074] Example 20 is the subject matter of any of Examples 18-19, wherein the frequency signal is adjusted using a correction circuit, the correction circuit comprising: a code ramp configured to generate a code; a statistics processor configured to generate a correction signal based on the generated code and the digital signal; a pre-distortion lookup table (PD-LUT) configured to generate a control signal and provide the control signal to the digital-to-time converter, the control signal controlling the adjustment of the frequency signal by the digital-to-time converter based on the correction signal and the generated code.

[0075] Example 21 is a communication device including a clock generator calibration system according to any of claims 1 to 11.

[0076] Example 22 is the subject matter of example 21, wherein the clock generator calibration system is included in a transceiver of the communication device.

[0077] Example 23 is a clock generator calibration method, comprising: generating an output clock signal based on a reference clock signal by a phased-locked loop (PLL); and adjusting a frequency signal of the PLL based on the digital signal of the PLL, the digital signal being generated based on the frequency signal being adjusted.

[0078] Example 24 is the subject matter of example 23, wherein the frequency signal is a reference clock signal, and the output clock signal is generated based on the reference clock signal.

[0079] Example 25 is the subject matter of example 23, wherein the frequency signal corresponds to the output clock signal, and the frequency signal is a feedback signal into the PLL.

[0080] Example 26 is the subject matter of any of Examples 23 to 25, wherein the PLL a time-to-digital converter configured to generate the digital signal, the output clock signal being generated based on the digital signal; and a digital-to-time converter configured to generate the conditioned frequency signal based on the digital signal.

[0081] Example 27 is the subject matter of any of Examples 23-26, further comprising determining statistics of values ​​of the digital signal, and wherein the adjustment of the frequency signal is based on the determined statistics.

[0082] Example 28 is the subject matter of any of Examples 23-27, wherein the frequency signal is adjusted using a correction circuit, the correction circuit comprising: a code ramp configured to generate a code; a statistics processor configured to generate a correction signal based on the generated code and the digital signal; and a pre-distortion lookup table (PD-LUT) configured to generate a control signal, the control signal controlling the adjustment of the frequency signal based on the correction signal and the generated code.

[0083] Example 29 is the subject matter of any of Examples 23 and 25 to 28, wherein the PLL a time-to-digital converter configured to generate the digital signal based on the regulated frequency signal and a reference signal; a controlled oscillator configured to generate the output clock signal based on the digital signal, the frequency signal being based on the output clock signal; and a digital-to-time converter in a feedback loop of the PLL, the digital-to-time converter configured to receive the frequency signal via the feedback loop and configured to generate the regulated frequency signal based on the digital signal.

[0084] Example 30 is the subject matter of any of Examples 23, 24, and 26 to 28, wherein the PLL comprises: a time-to-digital converter configured to generate the digital signal based on the adjusted frequency signal and a feedback signal related to the output clock signal; a controlled oscillator configured to generate the output clock signal based on the digital signal; a digital-to-time converter configured to receive the frequency signal and generate the regulated frequency signal based on the digital signal, the frequency signal being a reference clock signal; and

[0085] Example 31 is the subject matter of any of Examples 29-30, wherein the frequency signal is adjusted using a correction circuit, the correction circuit comprising: a code ramp configured to generate a code; a statistics processor configured to generate a correction signal based on the generated code and the digital signal; a pre-distortion lookup table (PD-LUT) configured to generate a control signal and provide the control signal to the digital-to-time converter, the control signal controlling the adjustment of the frequency signal by the digital-to-time converter based on the correction signal and the generated code.

[0086] Example 32 is a non-transitory computer-readable storage medium having stored thereon an executable computer program, the program directing a processor to perform any of the operations of Examples 23 to 31.

[0087] Example 33 is a computer program product having a computer program directly loadable into a memory of a controller, which, when executed by the controller, causes the controller to perform any of the operations of Examples 23 to 31.

[0088] Example 34 is the device shown and described.

[0089] Example 35 is a method shown and described.

[0090] Example 36 is a non-transitory computer-readable storage medium having stored thereon an executable computer program that instructs a processor to perform the method of example 35.

[0091] Conclusion The above description of the specific embodiments will sufficiently clarify the general nature of the disclosure that others may easily modify and / or adapt such specific embodiments for various applications by applying the knowledge of those skilled in the art without undue experimentation and without departing from the general concept of the disclosure. Such adaptations and modifications are therefore intended to be within the meaning and scope of equivalents of the disclosed embodiments, based on the teachings and guidance presented herein. It should be understood that the phrases or terms in the specification are intended to be descriptive and not limiting, and thus should be interpreted by those skilled in the art in light of the teachings and guidance.

[0092] References in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," etc., indicate that the embodiment being described may include a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, it is also noted that when a particular feature, structure, or characteristic is described in connection with one embodiment, it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0093] The exemplary embodiments described herein are provided for illustrative purposes and not for limiting purposes. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments. Thus, the specification is not intended to limit the disclosure. Rather, the scope of the disclosure is defined only according to the invention as set forth in the following claims and their equivalents.

[0094] Aspects may be implemented by hardware (e.g., circuitry), firmware, software, or any combination thereof. Aspects may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism that stores or transmits information in a form readable by a machine (e.g., a computing device). For example, machine-readable media may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Additionally, firmware, software, routines, instructions may be described herein as performing certain operations. However, it should be understood that such description is for convenience only and that in reality such operations originate from a computing device, processor, controller, or other device that executes the firmware, software, routines, instructions, etc. Additionally, any of several implementation variations may be performed by a general purpose computer.

[0095] For purposes of this description, the term "processor circuitry" should be understood to mean one or more circuits, one or more processors, logic, or a combination thereof. For example, a circuitry includes an analog circuit, a digital circuit, a state machine logic, a data processing circuit, a programmable processing circuit, other structural electronic hardware, or a combination thereof. A processor includes a microprocessor, a digital signal processor (DSP), a central processor (CPU), an application specific instruction set processor (ASIP), a graphics and / or image processor, a multi-core processor, or other hardware processor. A processor may be "hard-coded" with instructions that perform one or more corresponding functions in accordance with aspects described herein. Alternatively, a processor may access an internal memory and / or an external memory to retrieve instructions stored therein that, when executed by a processor, perform one or more corresponding functions associated with the processor and / or one or more functions and / or operations associated with the operation of a component having a processor embedded therein.

[0096] In one or more of the exemplary aspects described herein, the processor circuitry may include a memory for storing data and / or instructions. The memory may be any well-known volatile and / or non-volatile memory, including, for example, read-only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical disks, erasable programmable read-only memory (EPROM), and programmable read-only memory (PROM). The memory may be non-removable memory, removable memory, or a combination of both.

[0097] As would be apparent to one of ordinary skill in the art based on the teachings herein, the exemplary aspects are not limited to the communication protocols described herein, but may be applied to other wireless communication protocols / standards (e.g., LTE or other cellular protocols, other IEEE 802.11 protocols, etc.) as one of ordinary skill in the art would understand.

Claims

1. 1. A clock generator calibration system, comprising: A phase-locked loop (PLL) configured to generate an output clock signal, the phase-locked loop (PLL) comprising: a time-to-digital converter (TDC) configured to generate a digital output signal having a value; a digital-to-time converter (DTC) configured to perform a modulation operation on one of a feedback signal of the output clock signal or a reference clock signal from a reference clock oscillator to provide a modulated feedback signal or a modulated reference clock signal to the time-to-digital converter (TDC); A correction circuit, the correction circuit comprising: a code lamp configured to generate a digital-to-time converter (DTC) code; a predistortion look-up table (PD-LUT) configured to generate a control signal used to control the modulation operation of the digital-to-time converter (DTC); 1. A statistical processor, comprising: Sampling the values ​​of the digital output signal of the time-to-digital converter (TDC) in the phase-locked loop (PLL); counting the number of times a value is output by the time-to-digital converter (TDC) for a corresponding digital-to-time converter (DTC) code provided by the code ramp to determine a distribution of the sampled values ​​of the digital output signal of the time-to-digital converter (TDC) in the phase-locked loop (PLL) for the corresponding digital-to-time converter (DTC) codes generated by the code ramp; and generating a correction signal based on the distribution; and providing the correction signal to the predistortion look-up table (PD-LUT). a statistical processor; a correction circuit; the predistortion look-up table (PD-LUT) in the correction circuit is configured to receive a corresponding digital-to-time converter (DTC) code from the generated digital-to-time converter (DTC) codes generated by the code ramp and the correction signal from the statistical processor to generate the control signal, and the correction circuit is configured to calibrate the digital-to-time converter (DTC) in the phase-locked loop (PLL) based on the control signal to correct an integral nonlinearity (INL) of the digital-to-time converter (DTC) of the phase-locked loop (PLL). Clock generator calibration system.

2. 2. The clock generator calibration system of claim 1, wherein the digital output signal is generated based on the reference clock signal and the modulated feedback signal of the output clock signal, or is generated based on the modulated reference clock signal and the feedback signal of the output clock signal.

3. 2. The clock generator calibration system of claim 1, wherein the time-to-digital converter (TDC) is a bang-bang time-to-digital converter.

4. The phase-locked loop (PLL) a controlled oscillator configured to generate the output clock signal based on the digital output signal; 2. The clock generator calibration system of claim 1, wherein the digital-to-time converter (DTC) is included in a feedback loop of the phase-locked loop (PLL), and the digital-to-time converter (DTC) is configured to receive the feedback signal of the output clock signal from the controlled oscillator via the feedback loop of the phase-locked loop (PLL) and to generate the modulated feedback signal and provide the modulated feedback signal to the time-to-digital converter (TDC).

5. The digital-to-time converter (DTC) is not included in a feedback loop of the phase-locked loop (PLL), and the digital-to-time converter (DTC) is configured to receive the reference clock signal from the reference clock oscillator and to generate the modulated reference clock signal and provide the modulated reference clock signal to the time-to-digital converter (TDC).

2. The clock generator calibration system of claim 1.

6. A communications device including a clock generator calibration system according to any one of claims 1 to 5.

7. 1. An executable computer program, which when executed by a processor, causes the processor to: generating an output clock signal based on a reference clock signal by a phase-locked loop (PLL), the phase-locked loop (PLL) including a time-to-digital converter (TDC) and a digital-to-time converter (DTC); performing a modulation operation on one of a feedback signal of the output clock signal or a reference clock signal from a reference clock oscillator by the digital-to-time converter (DTC) to provide a modulated feedback signal or a modulated reference clock signal to the time-to-digital converter (TDC); generating, by said time-to-digital converter (TDC), a digital output signal having a value; The compensation circuit is a code lamp configured to generate a digital-to-time converter (DTC) code; a predistortion look-up table (PD-LUT) configured to generate a control signal used to control the modulation operation of the digital-to-time converter (DTC); a statistical processor, the statistical processor comprising: Sampling the values ​​of the digital output signal of the time-to-digital converter (TDC) in the phase-locked loop (PLL); counting the number of times a value is output by the time-to-digital converter (TDC) for a corresponding digital-to-time converter (DTC) code provided by the code ramp to determine a distribution of the sampled values ​​of the digital output signal of the time-to-digital converter (TDC) in the phase-locked loop (PLL) for the corresponding digital-to-time converter (DTC) codes from the code ramp; generating a correction signal based on the distribution and providing the correction signal to the predistortion look-up table (PD-LUT); the predistortion look-up table (PD-LUT) in the correction circuit is configured to receive a corresponding digital-to-time converter (DTC) code from the generated digital-to-time converter (DTC) codes generated by the code ramp and the correction signal from the statistical processor to generate the control signal, and the correction circuit is configured to calibrate the digital-to-time converter (DTC) in the phase-locked loop (PLL) based on the control signal to correct an integral nonlinearity (INL) of the digital-to-time converter (DTC) of the phase-locked loop (PLL). An executable computer program.

8. 8. The executable computer program product of claim 7, wherein the digital output signal is generated based on the reference clock signal and the modulated feedback signal of the output clock signal, or is generated based on the modulated reference clock signal and the feedback signal of the output clock signal.

9. The phase-locked loop (PLL) a controlled oscillator configured to generate the output clock signal based on the digital output signal; 8. The executable computer program product of claim 7, wherein the digital-to-time converter (DTC) is included in a feedback loop of the phase-locked loop (PLL), and the digital-to-time converter (DTC) is configured to receive the feedback signal of the output clock signal from the controlled oscillator via the feedback loop of the phase-locked loop (PLL) and to generate the modulated feedback signal and provide the modulated feedback signal to the time-to-digital converter (TDC).

10. The digital-to-time converter (DTC) is not included in a feedback loop of the phase-locked loop (PLL), and the digital-to-time converter (DTC) is configured to receive the reference clock signal from the reference clock oscillator and to generate the modulated reference clock signal and provide the modulated reference clock signal to the time-to-digital converter (TDC).

8. An executable computer program according to claim 7.

11. 1. A clock generator calibration system, comprising: A phase-locked loop (PLL) for generating an output clock signal, the phase-locked loop (PLL) comprising: a time-to-digital converter (TDC) configured to generate a digital output signal having a value; a digital-to-time converter (DTC) configured to perform a modulation operation on one of a feedback signal of the output clock signal or a reference clock signal from a reference clock oscillator to provide a modulated feedback signal or a modulated reference clock signal to the time-to-digital converter (TDC); A correction means, the correction means comprising: a code lamp which generates a digital-to-time converter (DTC) code; a predistortion look-up table (PD-LUT) that generates a control signal used to control the modulation operation of the digital-to-time converter (DTC); 1. A statistical processor, comprising: Sampling the values ​​of the digital output signal of the time-to-digital converter (TDC) in the phase-locked loop (PLL); counting the number of times a value is output by the time-to-digital converter (TDC) for a corresponding digital-to-time converter (DTC) code provided by the code ramp to determine a distribution of the sampled values ​​of the digital output signal of the time-to-digital converter (TDC) in the phase-locked loop (PLL) for the corresponding digital-to-time converter (DTC) codes among the digital-to-time converter (DTC) codes generated by the code ramp; and generating a correction signal based on the distribution, and providing the correction signal to the predistortion look-up table (PD-LUT); a statistical processor; A correction means, The predistortion look-up table (PD-LUT) in the correction means is configured to receive a corresponding digital-to-time converter (DTC) code from the generated digital-to-time converter (DTC) codes generated by the code ramp and the correction signal from the statistical processor to generate the control signal, and the correction means is configured to calibrate the digital-to-time converter (DTC) in the phase-locked loop (PLL) based on the control signal to correct an integral nonlinearity (INL) of the digital-to-time converter (DTC) of the phase-locked loop (PLL). Clock generator calibration system.

12. 12. The clock generator calibration system of claim 11, wherein the digital output signal is generated based on the reference clock signal and the modulated feedback signal of the output clock signal, or is generated based on the modulated reference clock signal and the feedback signal of the output clock signal.

13. A non-transitory computer readable storage medium storing an executable computer program according to any one of claims 7 to 10.

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