Receiving circuit

Abstract

To stabilize frequency characteristics of gain over a wide dynamic range of input optical signals.SOLUTION: A receiver circuit 10 comprises: a bypass circuit 13 that extracts bypass currents Iagc1 and Iagc2 from an optical current Ipd; a transimpedance amplifier 12 that converts a current signal Iin into a voltage signal Vout; and an inductor 11 that has a terminal 11a electrically connected with an input terminal Tin receiving the optical current Ipd, and a terminal 11b electrically connected with an input node 12a of the transimpedance amplifier 12. The bypass circuit 13 comprises: a bias power supply 34; a transistor 31 electrically connected between the terminal 11a and the bias power supply 34; a transistor 32 electrically connected between the terminal 11b and the bias power supply 34; and a parallel circuit 33 in which a resistive element 35 and a capacitor 36 are connected in parallel. The parallel circuit 33 is connected in series with the transistor 31.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a receiving circuit. [Background technology]

[0002] As optical communication systems become faster and have larger capacities, digital coherent optical transmission systems are being used for long-distance transmission. In digital coherent optical transmission systems, the analog electrical signal converted from the optical signal by the optical receiver is converted to a digital electrical signal by a high-speed A / D converter, and then various distortions that occur during the transmission of the optical signal through optical fiber are compensated for by performing digital signal processing. Optical receivers are required to have linearity in the conversion to analog electrical signals and amplification over a wide range of input power of the optical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-77956 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the optical receiving circuit described in Patent Document 1, a variable resistance element is provided at the input of the transimpedance amplifier in order to realize linear amplification operation in a wide dynamic range. In this technical field, it is desired to stabilize the frequency characteristic of gain in the wide dynamic range of the input optical signal.

[0005] This disclosure describes a receiver circuit capable of stabilizing the frequency characteristics of gain over a wide dynamic range of an input optical signal. [Means for solving the problem]

[0006] A receiving circuit according to one aspect of the present disclosure is a circuit that generates a voltage signal in response to an input current signal generated by a light receiving element in response to an optical signal. The receiving circuit includes an input terminal that receives the input current signal, a bypass circuit that extracts a bypass current from the input current signal, a transimpedance amplifier that has an input node and converts a current signal input to the input node into a voltage signal, and an inductor having a first end electrically connected to the input terminal and a second end electrically connected to the input node. The bypass circuit includes a bias power supply that supplies a bias voltage, a first variable resistance element electrically connected between the first end and the bias power supply, a second variable resistance element electrically connected between the second end and the bias power supply, and a parallel circuit in which a resistance element and a capacitor are connected in parallel. The parallel circuit is connected in series with the first variable resistance element or the second variable resistance element. Effect of the Invention

[0007] According to the present disclosure, it is possible to stabilize the frequency characteristic of gain over a wide dynamic range of an input optical signal. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of an optical receiving device including a receiving circuit according to an embodiment. [Diagram 2] FIG. 2 is a diagram illustrating a schematic configuration of an optical receiving device including a receiving circuit of a comparative example. [Diagram 3] FIG. 3 is a diagram showing frequency characteristics of gain in the optical receiving device shown in FIG. [Figure 4] FIG. 4 is a diagram showing frequency characteristics of gain in the optical receiving device shown in FIG. [Diagram 5] FIG. 5 is a diagram showing peaking in the frequency characteristics shown in FIGS. [Figure 6] FIG. 6 is a diagram for explaining the operation principle of the receiving circuit shown in FIG. [Figure 7] FIG. 7 is a diagram for explaining the operation principle of the receiving circuit shown in FIG. [Figure 8] FIG. 8 is a diagram for explaining a method for determining the resistance and capacitance values ​​of a parallel circuit. [Figure 9] FIG. 9 is a diagram illustrating a schematic configuration of an optical receiving device including a receiving circuit according to a modified example. [Figure 10] FIG. 10 is a diagram for explaining the frequency characteristic of gain in the optical receiving device shown in FIG. [Figure 11] FIG. 11 is a diagram illustrating a schematic configuration of an optical receiving device including a receiving circuit according to another modified example. [Figure 12] FIG. 12 is a diagram illustrating a schematic configuration of an optical receiving device including a receiving circuit according to yet another modified example. [Figure 13] FIG. 13 is a diagram illustrating a schematic configuration of an optical receiving device including a receiving circuit according to yet another modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0010] A receiving circuit according to one aspect of the present disclosure is a circuit that generates a voltage signal in response to an input current signal generated by a light receiving element in response to an optical signal. The receiving circuit includes an input terminal that receives the input current signal, a bypass circuit that extracts a bypass current from the input current signal, a transimpedance amplifier that has an input node and converts a current signal input to the input node into a voltage signal, and an inductor having a first end electrically connected to the input terminal and a second end electrically connected to the input node. The bypass circuit includes a bias power supply that supplies a bias voltage, a first variable resistance element electrically connected between the first end and the bias power supply, a second variable resistance element electrically connected between the second end and the bias power supply, and a parallel circuit in which a resistance element and a capacitor are connected in parallel. The parallel circuit is connected in series with the first variable resistance element or the second variable resistance element.

[0011] In this receiving circuit, a first variable resistance element is electrically connected between a first end of an inductor and a bias power supply, and a second variable resistance element is electrically connected between a second end of the inductor and a bias power supply. Furthermore, a parallel circuit in which a resistance element and a capacitor are connected in parallel is connected in series with the first variable resistance element or the second variable resistance element. When one of the first variable resistance element and the second variable resistance element that is connected in series with the parallel circuit is turned off and the other variable resistance element that is not connected in series with the parallel circuit is turned on, the frequency characteristic of the gain has a peak at a predetermined frequency. Since the impedance of the parallel circuit is determined by the resistance value of the resistance element at low frequencies and decreases by the capacitance value of the capacitor at high frequencies, the frequency characteristic of the gain when one variable resistance element is turned on and the other variable resistance element is turned off shows a characteristic in which the gain does not decrease at low frequencies and the amount of decrease in the gain increases at high frequencies. The frequency characteristic in the low gain state where the first variable resistance element and the second variable resistance element are in the ON state shows a characteristic obtained by adding the frequency characteristic of the gain when one variable resistance element is in the ON state and the other variable resistance element is in the OFF state and the frequency characteristic of the gain when one variable resistance element is in the OFF state and the other variable resistance element is in the ON state. Therefore, in the low gain state, the decrease in gain at low frequencies is suppressed and the decrease in gain at high frequencies is maintained. As a result, peaking in the low gain state can be suppressed, and the frequency characteristic of the gain can be stabilized in the wide dynamic range of the input optical signal.

[0012] The parallel circuit may be connected in series with the first variable resistance element. In a receiver circuit including a bypass circuit without a parallel circuit, the peaking of the frequency characteristics when the first variable resistance element is in the OFF state and the second variable resistance element is in the ON state may be greater than the peaking of the frequency characteristics when the first variable resistance element is in the ON state and the second variable resistance element is in the OFF state. If a parallel circuit is connected in series with the second variable resistance element to suppress the peaking of a receiver circuit having such frequency characteristics, the compensation of the frequency characteristics by the parallel circuit may become excessive, and the flatness of the frequency characteristics may decrease. On the other hand, by suppressing the peaking by connecting a parallel circuit in series with the first variable resistance element, the compensation of the frequency characteristics by the parallel circuit may be suppressed from becoming excessive, and therefore the flatness of the frequency characteristics may be improved.

[0013] The parallel circuit may be electrically connected between the first variable resistance element and the bias power supply. In this case, compared to a configuration in which the first variable resistance element is electrically connected between the parallel circuit and the bias power supply, it is possible to reduce the parasitic capacitance in the signal wiring connecting the input terminal and the first end. As a result, it is possible to suppress deterioration of the frequency characteristics.

[0014] The resistance value of the first variable resistance element may change in response to a control signal. The resistance value of the second variable resistance element may change in response to a control signal. In this case, the resistance value of the first variable resistance element and the resistance value of the second variable resistance element are controlled by one control signal. Therefore, it is possible to simplify the control of the resistance value of the first variable resistance element and the resistance value of the second variable resistance element.

[0015] The receiving circuit may further include a control circuit that generates a control signal in response to the voltage signal. In this case, the amount of bypass current can be changed in response to the voltage signal. For example, by generating a control signal such that the resistance value of the first variable resistive element and the resistance value of the second variable resistive element decrease as the amplitude of the voltage signal increases, the amount of bypass current can be increased and the gain can be reduced. As a result, it is possible to ensure the linearity of the voltage signal with respect to the input current signal in a wide dynamic range of the input optical signal.

[0016] The resistance value of the resistive element may be greater than the input impedance of the input node. In this case, since the impedance of the parallel circuit is greater at low frequencies, the amount of bypass current drawn from the input current signal by the variable resistive element connected in series with the parallel circuit, out of the first variable resistive element and the second variable resistive element, is reduced. Therefore, in a low-gain state in which the first variable resistive element and the second variable resistive element are in an on-state, the decrease in gain at low frequencies is further suppressed. As a result, peaking in the low-gain state can be suppressed.

[0017] The cutoff frequency of the parallel circuit may be smaller than half the peak frequency at which the conversion efficiency from the input current signal to the voltage signal is maximized when one of the first and second variable resistance elements connected in series to the parallel circuit is turned off and the other variable resistance element is turned on. In a frequency range lower than the cutoff frequency, the impedance of the parallel circuit is determined by the resistance element, so that the reduction in gain is suppressed. On the other hand, in a frequency range higher than the cutoff frequency, the impedance of the parallel circuit is reduced by the action of the capacitor, so that the gain is reduced. Therefore, by making the cutoff frequency smaller than half the above-mentioned peak frequency, it is possible to suppress the reduction in gain at low frequencies and reduce peaking in a low gain state.

[0018] The voltage value of the bias voltage may be equal to the average voltage value of the input voltage of the input node. In this case, almost no DC component of the input current signal flows into the first variable resistance element and the second variable resistance element, and a part of the AC component of the input current signal is extracted as a bypass current. Therefore, it is possible to realize gain control without reducing the DC component of the input current signal.

[0019] [Details of the embodiment of the present disclosure] Specific examples of receiving circuits according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0020] FIG. 1 is a diagram illustrating a schematic configuration of an optical receiving device including a receiving circuit according to an embodiment. The optical receiving device 1 illustrated in FIG. 1 receives an optical signal Pin transmitted from an optical transmitting device (not illustrated). The optical receiving device 1 includes a light receiving element PD and a receiving circuit 10. The optical receiving device 1 is used, for example, in a receiving section of a digital coherent optical transmission device. The light receiving element PD receives the optical signal Pin and generates a photocurrent Ipd (input current signal) corresponding to the optical signal Pin. The photocurrent Ipd may include an alternating current (AC) component corresponding to a modulated signal and a direct current (DC) component corresponding to an average power. When the signal strength (optical power) of the optical signal Pin increases, the AC component and the DC component of the photocurrent Ipd increase, and when the signal strength (optical power) of the optical signal Pin decreases, the AC component and the DC component of the photocurrent Ipd decrease. Examples of the light receiving element PD include a photodiode and an avalanche photodiode. One terminal (eg, cathode) of the light receiving element PD is electrically connected to a power supply that supplies a predetermined bias voltage VPD, and the other terminal (eg, anode) of the light receiving element PD outputs a photocurrent Ipd.

[0021] Note that "electrically connected" means that the two electrically connected parts are connected in a state in which signals can be transmitted and current and voltage can be supplied between them. Therefore, "electrically connected" can include cases where the two parts are directly connected by wiring and cases where the two parts are indirectly connected via other electric elements. "Electrically connected" is used in the same sense in the following explanation.

[0022] The receiving circuit 10 is a circuit that generates a voltage signal Vout in response to, for example, a photocurrent Ipd. The receiving circuit 10 is configured as, for example, an IC (Integrated Circuit). The receiving circuit 10 has, for example, an input terminal Tin, an output terminal Tout, and a control terminal Tc. The input terminal Tin is electrically connected to the anode of the light receiving element PD. The photocurrent Ipd is input to the input terminal Tin. The output terminal Tout outputs a voltage signal Vout to the outside of the receiving circuit 10. A control voltage Vagc (control signal) is input to the control terminal Tc. The control voltage Vagc is changed in response to the voltage signal Vout. For example, the control voltage Vagc increases as the amplitude of the voltage signal Vout increases. For example, when the receiving circuit 10 is manufactured as one semiconductor integrated device (for example, a semiconductor chip) by a semiconductor process, the input terminal Tin, the output terminal Tout, and the control terminal Tc may be bonding pads formed on the semiconductor chip. When a semiconductor chip on which the receiver circuit 10 is formed is mounted in a package, the input terminal Tin, the output terminal Tout, and the control terminal Tc may be electrical terminals provided on the outer surface of the package.

[0023] In addition, a differential amplifier circuit may be connected downstream of the receiver circuit 10 to convert the single-phase voltage signal Vout into a differential signal or to further amplify the voltage signal Vout. The receiver circuit 10 may be configured with a control circuit that generates a control voltage Vagc in response to the voltage signal Vout. When the receiver circuit 10 is configured on a semiconductor chip with these peripheral circuits, the output to the outside may be performed by a bonding pad formed at the output of the differential amplifier circuit, rather than the output terminal Tout.

[0024] The receiving circuit 10 includes an inductor 11, a transimpedance amplifier 12, and a bypass circuit 13.

[0025] The inductor 11 is an inductor element having an inductance L1. The inductor 11 is provided to increase the high frequency gain of the receiving circuit 10 and to reduce noise. The inductance L1 is, for example, 100 pH to 500 pH. The inductor 11 has a terminal 11a and a terminal 11b. The terminal 11a is electrically connected to the input terminal Tin. The terminal 11b is electrically connected to an input node 12a described later. The inductor 11 is, for example, disposed on the same substrate as the transimpedance amplifier 12, and is formed by wiring on the substrate. That is, the inductor 11 corresponds to an inductance component of the wiring electrically connecting the input terminal Tin and the input node 12a. When a relatively large inductance L1 is required, the inductor 11 may be formed, for example, as a spiral inductor on a semiconductor chip.

[0026] The transimpedance amplifier 12 is a circuit that converts the current signal Iin into a voltage signal Vout. Specifically, the transimpedance amplifier 12 includes a voltage amplifier 21 and a feedback resistor element 22. The input terminal and the output terminal of the voltage amplifier 21 are electrically connected via the feedback resistor element 22. That is, the feedback resistor element 22 is electrically connected between the input and output of the voltage amplifier 21. The current signal Iin is generated by extracting bypass currents Iagc1 and Iagc2 from the photocurrent Ipd. The bypass currents Iagc1 and Iagc2 are controlled by the bypass circuit 13, the details of which will be described later. The increase and decrease of the voltage signal Vout are inverted with respect to the increase and decrease of the current signal Iin. For example, when the amount of current of the current signal Iin increases, the voltage value of the voltage signal Vout decreases (drops).

[0027] The voltage amplifier 21 is, for example, an inverting amplifier circuit. The transimpedance amplifier 12 outputs a voltage signal Vout to the outside of the receiving circuit 10 via an output terminal Tout. The gain of the transimpedance amplifier 12 (the ratio of the amount of change in the voltage signal Vout to the amount of change in the current signal Iin) is determined by the resistance value (transimpedance) of the feedback resistance element 22. The gain of the transimpedance amplifier 12 is calculated by ΔVout / ΔIin, where ΔVout is the amount of change in the voltage signal Vout and ΔIin is the amount of change in the current signal Iin that causes the amount of change ΔVout. The input impedance of the transimpedance amplifier 12 is, for example, about 10 to 100 Ω.

[0028] The transimpedance amplifier 12 has an input node 12a and an output node 12b. The input node 12a is a connection point between an input terminal of the voltage amplifier 21 and one end of the feedback resistance element 22. That is, a current signal Iin is input to the input node 12a. The output node 12b is a connection point between an output terminal of the voltage amplifier 21 and the other end of the feedback resistance element 22. That is, a voltage signal Vout is output from the output node 12b.

[0029] The bypass circuit 13 is a circuit for performing gain control that controls a gain, which is the conversion efficiency from the photocurrent Ipd to the voltage signal Vout. The bypass circuit 13 generates a current signal Iin by extracting bypass currents Iagc1 and Iagc2 from the photocurrent Ipd. The bypass circuit 13 includes a transistor 31 (first variable resistance element), a transistor 32 (second variable resistance element), a parallel circuit 33, and a bias power supply 34. The bypass circuit 13 changes the bypass currents Iagc1 and Iagc2 in response to a control voltage Vagc. The control voltage Vagc is input from a gain control circuit that generates the control voltage Vagc in response to the voltage signal Vout, for example. Automatic gain control (AGC) can be performed by changing the bypass currents Iagc1 and Iagc2 in response to the voltage signal Vout. The gain control circuit can be configured using prior art, and a detailed description thereof will be omitted.

[0030] The transistors 31 and 32 are, for example, field effect transistors (MOSFETs) having a MOS (Metal-Oxide-Semiconductor) structure. In this embodiment, N-channel MOS transistors are used as the transistors 31 and 32. The transistor 31 is electrically connected between the terminal 11a of the inductor 11 and a bias power supply 34. Specifically, the drain of the transistor 31 is electrically connected to the terminal 11a of the inductor 11. The source of the transistor 31 is electrically connected to the bias power supply 34 via the parallel circuit 33. The gate of the transistor 31 is electrically connected to a control terminal Tc. A control voltage Vagc is supplied to the gate of the transistor 31.

[0031] The transistor 32 is electrically connected between the terminal 11b of the inductor 11 and the bias power supply 34. Specifically, the drain of the transistor 32 is electrically connected to the terminal 11b of the inductor 11. The source of the transistor 32 is electrically connected to the bias power supply 34. The gate of the transistor 32 is electrically connected to a control terminal Tc. A control voltage Vagc is supplied to the gate of the transistor 32. The size (gate width) of the transistor 31 and the size (gate width) of the transistor 32 may be the same as or different from each other.

[0032] The parallel circuit 33 includes a resistive element 35 and a capacitor 36, and is a circuit in which the resistive element 35 and the capacitor 36 are connected in parallel. The parallel circuit 33 is connected in series with the transistor 31. In this embodiment, the parallel circuit 33 is electrically connected between the transistor 31 and the bias power supply 34. The parallel circuit 33 has a node 33a and a node 33b. The node 33a is a connection point between one end of the resistive element 35 and one end of the capacitor 36. The node 33b is a connection point between the other end of the resistive element 35 and the other end of the capacitor 36. The node 33a is electrically connected to the source of the transistor 31. The node 33b is electrically connected to the bias power supply 34. The resistance value R1 of the resistive element 35 is sufficiently larger than the input impedance of the transimpedance amplifier 12 (input node 12a), and is set to, for example, several hundred Ω to several kΩ. The capacitance value C1 of the capacitor 36 is set to, for example, several tens of fF to several hundreds of fF. The method of determining the resistance value R1 and the capacitance value C1 will be described later.

[0033] The bias power supply 34 is a circuit that supplies a bias voltage Vbias. The bias voltage Vbias is, for example, a DC voltage. The bias power supply 34 has, for example, the same circuit configuration as the transimpedance amplifier 12. The voltage value of the bias voltage Vbias is substantially equal to the average voltage value of the input voltage Vin of the input node 12a.

[0034] In the bypass circuit 13 configured in this manner, the control voltage Vagc input to the control terminal Tc is supplied to the gate of the transistor 31 and the gate of the transistor 32. The bias voltage Vbias is supplied to the source of the transistor 31 via the parallel circuit 33, and the bias voltage Vbias is supplied to the source of the transistor 32. The input voltage Vin of the input node 12a is applied to the drain of the transistor 31 and the drain of the transistor 32. Since the voltage value of the bias voltage Vbias is substantially equal to the voltage value of the input voltage Vin of the input node 12a, the transistors 31 and 32 operate in a deep triode region (linear region) when the bypass circuit 13 is in an on state. The deep triode region is a state in which the result of subtracting the threshold voltage of the transistor from the gate-source voltage of the transistor is much larger than the drain-source voltage.

[0035] In the linear region, when the drain voltage of the transistors 31 and 32 increases, the drain current also increases in response to the increase in the drain voltage. In particular, when the drain voltage is relatively small, the drain current can be considered to change in proportion to the drain voltage (linear). The resistance value R of the transistor 31 AGC1 The on-resistance (ON resistance) can be expressed as the ratio of the drain voltage to the drain current. This resistance R AGC1 As the gate-source voltage increases, the resistance R AGC1 Similarly, the resistance value R of the transistor 32 varies according to the control voltage Vagc. AGC2 (on-resistance) decreases as the gate-source voltage increases, so the resistance R AGC2 changes according to the control voltage Vagc. That is, the transistors 31 and 32 act as a variable resistor controlled by the control voltage Vagc. AGC1 The resistance R is set to, for example, several tens of Ω to several kΩ. AGC2 is set to, for example, several tens of Ω to several kΩ. In this embodiment, the resistance value R AGC2 is the resistance value R AGC1is set to a value substantially equal to

[0036] That is, the transistor 31 is AC grounded by the bias power supply 34, and the transistor 31 is biased in the deep triode region. Since the average potential (DC potential) of the terminal 11a and the average potential (DC potential) of the node 33b are substantially the same, almost no DC component of the photocurrent Ipd flows into the transistor 31, and part of the AC component of the photocurrent Ipd flows into the transistor 31 as the bypass current Iagc1. In other words, the transistor 31 passes the bypass current Iagc1 between the drain and source of the transistor 31 in response to the control voltage Vagc.

[0037] Similarly, the transistor 32 is AC grounded by the bias power supply 34, and the transistor 32 is biased in the deep triode region. Since the average potential (DC potential) of the terminal 11b and the source potential of the transistor 32 are substantially the same, almost no DC component of the photocurrent Ipd flows into the transistor 32, and a part of the AC component of the photocurrent Ipd flows into the transistor 32 as the bypass current Iagc2. In other words, the transistor 32 passes the bypass current Iagc2 between the drain and source of the transistor 32 in response to the control voltage Vagc.

[0038] That is, when the amplitude of the photocurrent Ipd increases, the amplitude of the voltage signal Vout increases. As the amplitude of the voltage signal Vout increases, the control voltage Vagc increases. As the control voltage Vagc increases, the resistance value R AGC1 and resistance value R AGC2 becomes smaller, some of the signal components (AC components) excluding the DC component of the photocurrent Ipd are extracted as the bypass currents Iagc1 and Iagc2. As a result, the amplitude of the current signal Iin is suppressed, and the possibility that the transimpedance amplifier 12 will be saturated by a large signal input is reduced.

[0039] Next, the frequency characteristics of the receiver circuit 10 will be described in comparison with a receiver circuit 100 of a comparative example with reference to Figs. 2 to 7. First, the configuration of the receiver circuit 100 will be described with reference to Fig. 2. Fig. 2 is a diagram showing a schematic configuration of an optical receiver including a receiver circuit of a comparative example. As shown in Fig. 2, the receiver circuit 100 of the comparative example differs from the receiver circuit 10 mainly in that it includes a bypass circuit 113 instead of the bypass circuit 13. The bypass circuit 113 differs from the bypass circuit 13 mainly in that it does not include a parallel circuit 33.

[0040] The frequency characteristics of the receiving circuit 10 and the receiving circuit 100 are compared with each other with reference to FIG. 3 to FIG. 5. FIG. 3 is a diagram showing the frequency characteristics of the gain in the optical receiving device shown in FIG. 2. FIG. 4 is a diagram showing the frequency characteristics of the gain in the optical receiving device shown in FIG. 1. FIG. 5 is a diagram showing peaking in the frequency characteristics shown in FIG. 3 and FIG. 4. The horizontal axis of FIG. 3 and FIG. 4 indicates the frequency (unit: GHz) of the photocurrent Ipd. The vertical axis of FIG. 3 and FIG. 4 indicates the gain (unit: dB). The gain shown in these figures is the normalized conversion efficiency from the photocurrent Ipd to the voltage signal Vout. For example, the curve shown by "high gain" indicates the relative change to the value with respect to the gain at a frequency of 1 GHz as a reference, in dB. The high gain is, for example, the maximum gain in each of the receiving circuit 10 and the receiving circuit 100. The curves shown by "medium gain" or "low gain" also indicate the relative change with respect to the gain at a frequency of 1 GHz of the curve shown by "high gain", in dB. As shown by the values ​​of each gain at a frequency of 1 GHz, "medium gain" corresponds to a -3 dB decrease from "high gain," and "low gain" corresponds to a -6 dB decrease from "high gain." The vertical axis in Figure 5 indicates peaking (unit: dB). Peaking represents the height of the peak, and is the difference between the gain at a frequency of 1 GHz and the maximum gain in the frequency range being calculated. Specifically, peaking is obtained by subtracting the gain at a frequency of 1 GHz from the maximum gain in the frequency range being calculated.

[0041] The frequency characteristics shown in Figures 3 and 4 were calculated using an equivalent circuit of the optical receiver 1. In the equivalent circuit, the transistors 31 and 32 are represented as resistive elements. The resistance value R AGC1 ,R AGC2 was set to a value according to each gain, and the inductance L1 was set to 300 pH. The voltage value of the bias voltage Vbias was set to the same value as the average voltage value of the input voltage Vin of the input node 12a of the transimpedance amplifier 12. The receiving circuit 10 and the receiving circuit 100 differ in the set values ​​of the resistance value R1 and the capacitance value C1. The receiving circuit 100 was represented by setting the resistance value R1 to 0 Ω and the capacitance value C1 to 0 F. The receiving circuit 10 was represented by setting the resistance value R1 to 3.3 kΩ and the capacitance value C1 to 80 fF. Note that the resistance value R AGC1 ,R AGC2 has been adjusted.

[0042] When the transistors 31 and 32 are both in the off state, the bypass currents Iagc1 and Iagc2 are not drawn from the photocurrent Ipd, and the gain of the receiver circuit 10 is high. Therefore, the frequency characteristics in the high gain state were calculated by turning off both the transistors 31 and 32. When the transistors 31 and 32 are both in the on state, the bypass currents Iagc1 and Iagc2 are drawn from the photocurrent Ipd, and the gain of the receiver circuit 10 is medium or low. Therefore, the frequency characteristics in the medium gain state and the low gain state were calculated by turning on both the transistors 31 and 32. More specifically, the frequency characteristics in the medium gain state were calculated by turning on both the transistors 31 and 32. AGC1 and resistance value R AGC2 The frequency response in the low gain state was calculated by setting the resistance R AGC1 and resistance value R AGC2The calculation was done by setting the value of the low gain state (80 Ω). In the equivalent circuit, the high gain state is the resistance value R AGC1 and resistance value R AGC2 were calculated by setting both to 1 TΩ.

[0043] As shown in Figures 3 and 4, the frequency characteristics of the receiving circuit 10 in the high gain state and the frequency characteristics of the receiving circuit 100 in the high gain state are substantially the same. The frequency characteristics of the receiving circuit 100 in the medium gain state and the low gain state (see Figure 3) have peaks at frequencies around 30 GHz, which adversely affect the transmission characteristics. On the other hand, the frequency characteristics of the receiving circuit 10 in the medium gain state (see Figure 4) have no peaks, and the frequency characteristics in the low gain state have a slight peak at a frequency around 25 GHz.

[0044] As shown in Fig. 5, in the receiving circuit 100, the peaking increases as the gain decreases. The peaking in the low gain state is about 2.3 dB. On the other hand, in the receiving circuit 10, no peak occurs in the high gain state or the medium gain state. The peaking in the low gain state of the receiving circuit 10 is about 0.7 dB, which is lower than the peaking in the low gain state of the receiving circuit 100.

[0045] The operation principle of the receiving circuits 10 and 100 will be described with reference to FIG. 6 and FIG. 7. FIG. 6 is a diagram for explaining the operation principle of the receiving circuit shown in FIG. 2. FIG. 7 is a diagram for explaining the operation principle of the receiving circuit shown in FIG. 1. The horizontal axis of FIG. 6 and FIG. 7 indicates the frequency (unit: GHz) of the photocurrent Ipd. The vertical axis of FIG. 6 and FIG. 7 indicates the gain (unit: dB). The gain shown in these figures is the normalized conversion efficiency from the photocurrent Ipd to the voltage signal Vout. For example, the curve indicated by "Tr31-OFF, Tr32-OFF" corresponding to the case of high gain is based on the gain at a frequency of 1 GHz, and the relative change to that value is shown in dB. This reference gain is, for example, the maximum gain in each of the receiving circuits 10 and 100. The other curves also indicate the relative change in dB based on the gain at a frequency of 1 GHz corresponding to the high gain of the curve indicated by "Tr31-OFF, Tr32-OFF". As shown by the gain values ​​at a frequency of 1 GHz, the curves indicated by "Tr31-ON, Tr32-OFF" and "Tr31-OFF, Tr32-ON" correspond to the medium gain case, which is -3 dB lower than the high gain case of the curve indicated by "Tr31-OFF, Tr32-OFF". The curve indicated by "Tr31-ON, Tr32-ON" corresponds to the low gain case, which is -6 dB lower than the high gain case of the curve indicated by "Tr31-OFF, Tr32-OFF".

[0046] The frequency characteristics shown in Fig. 6 and Fig. 7 were calculated using the equivalent circuit of the optical receiving device 1. To simulate the receiving circuit 100, the setting values ​​of each circuit element of the equivalent circuit were set to the same values ​​as those used in the calculation of the frequency characteristics of Fig. 3. To simulate the receiving circuit 10, the setting values ​​of each circuit element of the equivalent circuit were set to the same values ​​as those used in the calculation of the frequency characteristics of Fig. 4.

[0047] 6, when both the transistors 31 and 32 are in the off state (high gain state), the frequency characteristic of the receiving circuit 100 has no peak. When the transistor 31 is in the on state and the transistor 32 is in the off state, the frequency characteristic of the receiving circuit 100 has a peak at a frequency near 35 GHz. This peak occurs due to resonance caused by the capacitance of the light receiving element PD, the pad capacitance of the light receiving element PD and the receiving circuit 10, the capacitance of an ESD (Electro-Static Discharge) element (not shown) and the like, the inductance of the bonding wire connecting the light receiving element PD and the receiving circuit 100, and the inductance of the noise suppression inductor of the transimpedance amplifier 12. For the same reason, when the transistor 31 is in the off state and the transistor 32 is in the on state, the frequency characteristic of the receiving circuit 100 has a peak at a frequency near 28 GHz. When transistors 31 and 32 are both on (low gain state), the frequency characteristics of the receiving circuit 100 are a sum of the frequency characteristics when transistor 31 is on and transistor 32 is off, and the frequency characteristics when transistor 31 is off and transistor 32 is on, and have a peak at a frequency around 30 GHz.

[0048] 7, when both the transistors 31 and 32 are in the off state (high gain state), the frequency characteristic of the receiving circuit 10 is substantially the same as that of the receiving circuit 100 and has no peak. The parallel circuit 33 has a time constant τ (=R1×C1) determined by a resistance value R1 and a capacitance value C1. The impedance of the parallel circuit 33 is determined by the resistance value R1 at low frequencies and decreases by the capacitance value C1 at high frequencies, with the cutoff frequency fc determined by the time constant τ as a boundary. Since the resistance value R1 is set to a value sufficiently larger than the input impedance of the transimpedance amplifier 12, the impedance of the parallel circuit 33 increases at low frequencies, and the bypass current Iagc1 is hardly drawn from the photocurrent Ipd. On the other hand, the impedance of the parallel circuit 33 decreases at high frequencies, and the amount of the bypass current Iagc1 drawn from the photocurrent Ipd increases. Therefore, when the transistor 31 is on and the transistor 32 is off, the frequency characteristics of the receiver circuit 10 exhibit a characteristic in which the gain does not decrease at low frequencies but the amount of decrease in gain increases at high frequencies.

[0049] When the transistor 31 is in an off state and the transistor 32 is in an on state, a certain amount of the bypass current Iagc2 is extracted from the photocurrent Ipd at low and high frequencies, as in the receiving circuit 100, but the amount of the bypass current Iagc2 decreases in the intermediate frequency range. That is, when the transistor 31 is in an off state and the transistor 32 is in an on state, the frequency characteristic of the receiving circuit 10 has a peak at a frequency near 28 GHz. When both the transistors 31 and 32 are in an on state, the frequency characteristic of the receiving circuit 10 becomes a characteristic that is a sum of the frequency characteristic when the transistor 31 is in an on state and the transistor 32 is in an off state and the frequency characteristic when the transistor 31 is in an off state and the transistor 32 is in an on state, and the peaking in the intermediate frequency range is canceled. As a result, a characteristic with reduced peaking is obtained.

[0050] Next, a method for determining the resistance value R1 of the resistive element 35 and the capacitance value C1 of the capacitor 36 will be described with reference to FIG. 8. FIG. 8 is a diagram for explaining a method for determining the resistance value and capacitance value of a parallel circuit. The horizontal axis of FIG. 8 indicates the frequency (unit: GHz) of the photocurrent Ipd. The vertical axis of FIG. 8 indicates the gain (unit: dB). The gain shown in FIG. 8 is the normalized conversion efficiency from the photocurrent Ipd to the voltage signal Vout. In calculating the frequency characteristics shown in FIG. 8, the same values ​​as those used in calculating the frequency characteristics of FIG. 7 were used as the setting values ​​of each circuit element except for the capacitance value C1 of the equivalent circuit.

[0051] First, the resistance value R1 is determined. In a low gain state where the transistor 31 is on, as described above, the bypass current Iagc1 is hardly drawn from the photocurrent Ipd at low frequencies. For this reason, the impedance of the transistor 31 as viewed from the drain side must be sufficiently large compared with the input impedance of the transimpedance amplifier 12. Since the input impedance of the transimpedance amplifier 12 is generally about several tens of Ω to a hundred and several tens of Ω, the resistance value R1 is determined to be, for example, several kΩ. Here, it is assumed that the input impedance of the transimpedance amplifier 12 is 80 Ω, and the resistance value R1 is determined to be 3.3 kΩ.

[0052] Next, the capacitance value C1 is determined. It is necessary to draw off the bypass current Iagc1 to some extent at a frequency that is about half the peak frequency when the transistor 31 is in the off state (in other words, the parallel circuit 33 is in a provisionally open state) and the transistor 32 is in the on state. The peak frequency is the frequency at which the gain is maximized in the frequency characteristics. In other words, the peak frequency is the frequency at which a peak occurs in the frequency characteristics. Therefore, at a frequency that is half the peak frequency, the impedance of the parallel circuit 33 becomes equal to the resistance value R of the transistor 31. AGC1 The capacitance value C1 is determined so that the peak frequency is several tens of GHz and the resistance value R AGC1Assuming that the impedance is several tens of Ω, the capacitance C1 is determined so that the cutoff frequency fc of the parallel circuit 33 is several hundreds of MHz. The cutoff frequency fc is expressed by equation (1), and the capacitance C1 is determined from equation (1). The capacitance C1 is determined to be, for example, several tens of fF to several hundreds of fF. A capacitor 36 having this capacitance C1 can be formed on an IC (semiconductor chip). The impedance of the parallel circuit 33 decreases as the frequency increases due to the action of the capacitor 36, as will be described later. Therefore, at high frequencies, the amount of bypass current Iagc1 drawn out is determined mainly by the on-resistance of the transistor 31 (resistance value R AGC1 ) can be determined by

number

[0053] 7, the peak frequency when the transistor 31 is in the off state and the transistor 32 is in the on state is about 28 GHz. Therefore, the impedance of the parallel circuit 33 is set to the resistance value R of the transistor 31 so as to draw out the bypass current Iagc1 at 14 GHz, which is half the frequency of the peak frequency. AGC1 In order for the transistor 31 to extract the bypass current Iagc1 from the photocurrent Ipd, the resistance value R AGC1 must be smaller than the input impedance of the transimpedance amplifier 12. Furthermore, the resistance value R AGC1 In order to adjust the bypass current Iagc1 according to AGC1 It is preferable that it is smaller than .

[0054] The cutoff frequency fc is set to about 140 MHz so that the impedance of the parallel circuit 33 is about 1 / 100 of the resistance value R1 (=3.3 kΩ) at half the frequency (14 GHz) of the peak frequency. AGC1 (=80Ω). More specifically, the impedance of the parallel circuit 33 at high frequencies is reduced to 1 / 10 when the frequency is increased tenfold due to the action of the capacitor 36. Therefore, if the impedance of the parallel circuit 33 at 14 GHz is to be reduced to 1 / 100 of that at low frequencies, the cutoff frequency fc may be set to 1 / 100 of half the peak frequency. For example, at low frequencies (e.g., 1 / 100 of half the peak frequency), the impedance of the parallel circuit 33 is mainly determined by the resistance value R1, and at high frequencies (e.g., half the peak frequency), the impedance of the parallel circuit 33 can be reduced to 1 / 100 of the resistance value R1 or less. For example, the impedance of the parallel circuit 33 is 3.3 kΩ at frequencies lower than 140 MHz, and 33 Ω at a frequency of 14 GHz. From the formula (1), the capacitance value C1 for fc=140 MHz is calculated to be 340 fF.

[0055] Furthermore, the capacitance value C1 determined by calculation is changed stepwise to calculate the frequency characteristic of the receiving circuit 10. A preferable characteristic is selected from the plurality of frequency characteristics calculated by changing the capacitance value C1 stepwise, and the capacitance value C1 corresponding to the characteristic is adopted. For example, as shown in FIG. 8, when the capacitance value C1 is 340 fF, the flatness of the frequency characteristic is reduced although no peak occurs. On the other hand, when the capacitance value C1 is 30 fF, the cutoff frequency fc becomes large and the peak cannot be sufficiently suppressed. When the capacitance value C1 is 80 fF, the flatness of the frequency characteristic can be improved while suppressing the peak. Therefore, in this calculation, 80 fF is adopted as the capacitance value C1. As described above, in the gain adjustment by the transistors 31 and 32, a peak may occur in the frequency characteristic depending on the gain, but the frequency characteristic can be compensated to suppress the peak by providing the parallel circuit 33.

[0056] As described above, in the receiving circuit 10, the transistor 31 is electrically connected between the terminal 11a of the inductor 11 and the bias power supply 34, and the transistor 32 is electrically connected between the terminal 11b of the inductor 11 and the bias power supply 34. Furthermore, the parallel circuit 33, in which the resistive element 35 and the capacitor 36 are connected in parallel, is connected in series with the transistor 31. When the transistor 31 is turned off and the transistor 32 is turned on, the frequency characteristic of the gain has a peak at a predetermined frequency. Since the impedance of the parallel circuit 33 is determined by the resistance value R1 of the resistive element 35 at low frequencies and is reduced by the capacitance value C1 of the capacitor 36 at high frequencies, the frequency characteristic of the gain when the transistor 31 is turned on and the transistor 32 is turned off shows a characteristic in which the gain does not decrease at low frequencies and the amount of decrease in the gain increases at high frequencies. The frequency characteristic in the low gain state where both the transistors 31 and 32 are on exhibits a characteristic obtained by adding together the frequency characteristic of the gain when the transistor 31 is on and the transistor 32 is off, and the frequency characteristic of the gain when the transistor 31 is off and the transistor 32 is on. Therefore, in the low gain state, the decrease in gain at low frequencies is suppressed, and the decrease in gain at high frequencies is maintained. As a result, peaking in the low gain state can be suppressed, and the frequency characteristic of the gain can be stabilized in the wide dynamic range of the input optical signal Pin.

[0057] In the receiver circuit 100, the peaking of the frequency characteristics is greater when the transistor 31 is in the OFF state and the transistor 32 is in the ON state than when the transistor 31 is in the ON state and the transistor 32 is in the OFF state. If an attempt is made to suppress the peaking of the receiver circuit 100 having such frequency characteristics by connecting the parallel circuit 33 in series with the transistor 32, the compensation of the frequency characteristics by the parallel circuit 33 may become excessive, and the flatness of the frequency characteristics may decrease. On the other hand, by suppressing the peaking by connecting the parallel circuit 33 in series with the transistor 31, the compensation of the frequency characteristics by the parallel circuit 33 may be suppressed from becoming excessive, and therefore the flatness of the frequency characteristics may be improved.

[0058] A high-speed photocurrent Ipd is transmitted through the signal wiring connecting the input terminal Tin to the terminal 11a of the inductor 11. In a configuration in which the transistor 31 is connected between the parallel circuit 33 and the bias power supply 34, a resistance element 35 and a capacitor 36 are connected to the signal wiring, so that there is a risk that the capacitance parasitic to the signal wiring will increase compared to a configuration in which the transistor 31 is connected to the signal wiring. In contrast, the parallel circuit 33 is electrically connected between the transistor 31 and the bias power supply 34. Therefore, the capacitance parasitic to the signal wiring can be suppressed, and deterioration of the frequency characteristics can be suppressed.

[0059] Resistance value R of transistor 31 AGC1 and the resistance value R of the transistor 32 AGC2 changes according to the control voltage Vagc. In other words, the resistance value R AGC1 and resistance value R AGC2 Therefore, the resistance value R AGC1 and resistance value R AGC2 It is possible to simplify the control of the resistance R AGC1 and resistance value R AGC2 are controlled in conjunction with each other, so the resistance value R AGC1 and resistance value R AGC2 can be fixed by the ratio between the size of transistor 31 and the size of transistor 32.

[0060] The resistance value R1 of the resistive element 35 is set to a value larger than the input impedance value of the input node 12a. Therefore, since the impedance of the parallel circuit 33 becomes large at low frequencies, the amount of the bypass current Iagc1 drawn from the photocurrent Ipd decreases. Therefore, in a low-gain state in which the transistors 31 and 32 are turned on, the decrease in gain at low frequencies is further suppressed. As a result, peaking in a low-gain state can be further suppressed.

[0061] In a frequency region lower than the cutoff frequency fc of the parallel circuit 33, the impedance of the parallel circuit 33 is determined by the resistance value R1 of the resistive element 35, so that a reduction in gain is suppressed. On the other hand, in a frequency region higher than the cutoff frequency fc, the impedance of the parallel circuit 33 is reduced by the capacitance value C1 of the capacitor 36, so that the gain is reduced. Therefore, by making the cutoff frequency fc lower than half the peak frequency when the transistor 31 is in the off state and the transistor 32 is in the on state, it is possible to suppress a reduction in gain at low frequencies in a low gain state and reduce peaking.

[0062] The voltage value of the bias voltage Vbias is substantially equal to the average voltage value of the input voltage Vin of the input node 12a. In this case, the DC component of the photocurrent Ipd hardly flows into the transistor 31 and the transistor 32, and a part of the AC component of the photocurrent Ipd is extracted as the bypass currents Iagc1 and Iagc2. Therefore, it is possible to realize gain control without reducing the DC component of the photocurrent Ipd. Furthermore, when the photocurrent Ipd is relatively small, the extraction of the AC component of the photocurrent Ipd is suppressed, so that the attenuation of the AC component can be avoided. When the photocurrent Ipd is relatively large, the AC component of the photocurrent Ipd is extracted from the photocurrent Ipd as the bypass currents Iagc1 and Iagc2, so that the AC component of the photocurrent Ipd can be attenuated. As a result, it is possible to ensure the linearity of the voltage signal with respect to the photocurrent in a wide dynamic range of the optical signal Pin.

[0063] The receiving circuit according to the present disclosure is not limited to the above embodiment.

[0064] An optical receiving device including a receiving circuit according to a modified example will be described with reference to Figs. 9 to 13. Fig. 9 is a diagram showing a schematic configuration of an optical receiving device including a receiving circuit according to a modified example. Fig. 10 is a diagram for explaining the frequency characteristics of gain in the optical receiving device shown in Fig. 9. The horizontal axis of Fig. 10 indicates the frequency (unit: GHz) of the photocurrent Ipd. The vertical axis of Fig. 10 indicates the gain (unit: dB). The gain shown in Fig. 10 is the normalized conversion efficiency from the photocurrent Ipd to the voltage signal Vout.

[0065] For example, the curve indicated by "Tr31-OFF, Tr32-OFF" corresponding to the high gain case shows the relative change in dB with respect to the gain at a frequency of 1 GHz as a reference. This reference gain is, for example, the maximum gain of the receiving circuit 10A. The other curves also show the relative change in dB with respect to the gain at a frequency of 1 GHz corresponding to the high gain of the curve indicated by "Tr31-OFF, Tr32-OFF". As the values ​​of each gain at a frequency of 1 GHz indicate, the curve indicated by "Tr31-OFF, Tr32-ON" corresponds to a high gain, just like the curve indicated by "Tr31-OFF, Tr32-OFF". The curve indicated by "Tr31-ON, Tr32-OFF" corresponds to a low gain, just like the curve indicated by "Tr31-ON, Tr32-ON".

[0066] As shown in FIG. 9, the optical receiving device 1A mainly differs from the optical receiving device 1 in that the optical receiving device 1A includes a receiving circuit 10A instead of the receiving circuit 10. The receiving circuit 10A mainly differs from the receiving circuit 10 in that the receiving circuit 10A includes a bypass circuit 13A instead of the bypass circuit 13. The bypass circuit 13A mainly differs from the bypass circuit 13 in that the parallel circuit 37 is included instead of the parallel circuit 33. The parallel circuit 37 has a circuit configuration similar to that of the parallel circuit 33. Specifically, the parallel circuit 37 includes a resistive element 38 and a capacitor 39, and is a circuit in which the resistive element 38 and the capacitor 39 are connected in parallel. The parallel circuit 37 is connected in series with the transistor 32. In this modification, the parallel circuit 37 is electrically connected between the transistor 32 and the bias power supply 34.

[0067] The parallel circuit 37 has a node 37a and a node 37b. The node 37a is a connection point between one end of the resistive element 38 and one end of the capacitor 39. The node 37b is a connection point between the other end of the resistive element 38 and the other end of the capacitor 39. The node 37a is electrically connected to the source of the transistor 32. The node 37b is electrically connected to the bias power supply 34. The resistance value R2 of the resistive element 38 is sufficiently larger than the input impedance of the transimpedance amplifier 12 (input node 12a), and is set to, for example, several hundred Ω to several kΩ. The capacitance value C2 of the capacitor 39 is set to, for example, several tens of fF to several hundreds of fF. The method of determining the resistance value R2 and the capacitance value C2 is the same as the method of determining the resistance value R1 and the capacitance value C1.

[0068] The receiving circuit 10A also has the same effect as the receiving circuit 10. As shown in Fig. 10, the frequency characteristics of the receiving circuit 10A in a low gain state are less flat than the frequency characteristics of the receiving circuit 10 in a low gain state. As shown in Fig. 10, the frequency characteristics when the transistor 31 is on and the transistor 32 is off have small peaking and a gradual amount of gain fluctuation. Therefore, it is considered that the decrease in flatness is caused by excessive gain compensation by the parallel circuit 37.

[0069] FIG. 11 is a diagram that shows a schematic configuration of an optical receiving device including a receiving circuit according to another modification. As shown in FIG. 11, the optical receiving device 1B mainly differs from the optical receiving device 1 in that it includes a receiving circuit 10B instead of the receiving circuit 10. The receiving circuit 10B mainly differs from the receiving circuit 10 in that it includes a bypass circuit 13B instead of the bypass circuit 13. The bypass circuit 13B mainly differs from the bypass circuit 13 in that it further includes a parallel circuit 37 in addition to the parallel circuit 33. That is, the parallel circuit 33 is connected in series to the transistor 31, and the parallel circuit 37 is connected in series to the transistor 32. In this modification, the parallel circuit 33 is electrically connected between the transistor 31 and the bias power supply 34. The parallel circuit 37 is electrically connected between the transistor 32 and the bias power supply 34.

[0070] The receiving circuit 10B also provides the same effects as the receiving circuit 10.

[0071] Fig. 12 is a diagram showing a schematic configuration of an optical receiving device including a receiving circuit according to yet another modified example. As shown in Fig. 12, the optical receiving device 1C differs from the optical receiving device 1 mainly in that it includes a receiving circuit 10C instead of the receiving circuit 10. The receiving circuit 10C differs from the receiving circuit 10 mainly in that it includes a bypass circuit 13C instead of the bypass circuit 13. The bypass circuit 13C differs from the bypass circuit 13 mainly in that it further includes a control circuit 40.

[0072] The control circuit 40 is a circuit that generates a control voltage Vagc in response to the voltage signal Vout. Specifically, the control circuit 40 detects the amplitude of the voltage signal Vout and generates the control voltage Vagc in response to the amplitude. For example, the control circuit 40 increases the voltage value of the control voltage Vagc as the amplitude of the voltage signal Vout increases. The control circuit 40 outputs the control voltage Vagc to the gate of the transistor 31 and the gate of the transistor 32.

[0073] The receiving circuit 10C has the same effect as the receiving circuit 10. The receiving circuit 10C includes a control circuit 40 that generates a control voltage Vagc in response to the voltage signal Vout. Therefore, the current amounts of the bypass currents Iagc1 and Iagc2 can be changed in response to the amplitude of the voltage signal Vout. For example, as the amplitude of the voltage signal Vout increases, the resistance value R of the transistor 31 decreases. AGC1 and the resistance value R of the transistor 32 AGC2 By generating the control voltage Vagc so that Ipd is small, the amounts of the bypass currents Iagc1 and Iagc2 can be increased and the gain can be reduced. As a result, it is possible to ensure the linearity of the voltage signal Vout with respect to the photocurrent Ipd in a wide dynamic range of the optical signal Pin.

[0074] In the bypass circuit 13C, the bias power supply 34 has the same configuration as the transimpedance amplifier 12. Specifically, the bias power supply 34 is a dummy TIA including a voltage amplifier 34a and a feedback resistor 34b. The input terminal and the output terminal of the voltage amplifier 34a are electrically connected via the feedback resistor 34b. That is, the feedback resistor 34b is electrically connected between the input and output of the voltage amplifier 34a. Since the bias power supply 34 has a circuit configuration similar to that of the transimpedance amplifier 12, a bias voltage Vbias can be generated to compensate (cancel) a change in the input voltage Vin caused by a change in the power supply voltage and temperature of the voltage amplifier 21. Therefore, the voltage value of the bias voltage Vbias is substantially equal to the average voltage value (input potential) of the input voltage Vin. According to this configuration, the DC component of the photocurrent Ipd hardly flows into the transistor 31 and the transistor 32, and a part of the AC component of the photocurrent Ipd is extracted as the bypass currents Iagc1 and Iagc2. As a result, it is possible to realize gain control without reducing the DC component of the photocurrent Ipd in response to changes in the power supply voltage and temperature of the receiver circuit 10C.

[0075] FIG. 13 is a diagram that shows a schematic configuration of an optical receiving device including a receiving circuit according to yet another modified example. As shown in FIG. 13, the optical receiving device 1D receives a differential optical signal (optical signal Pin and optical signal Pinb). The optical receiving device 1D is mainly different from the optical receiving device 1C in that it includes a receiving circuit 10D instead of the receiving circuit 10C, and further includes a light receiving element PDb. The light receiving element PDb receives the optical signal Pinb and generates a photocurrent Ipdb according to the optical signal Pinb. Examples of the light receiving element PDb include a photodiode and an avalanche photodiode. One terminal (e.g., a cathode) of the light receiving element PDb is electrically connected to a power supply that supplies a predetermined bias voltage VPD, and the other terminal (e.g., an anode) of the light receiving element PDb outputs a photocurrent Ipdb.

[0076] The receiving circuit 10D is a circuit that generates differential voltage signals (voltage signals Vout and Voutb) according to the photocurrents Ipd and Ipdb. The receiving circuit 10D differs from the receiving circuit 10C mainly in that it further includes an input terminal Tinb and an output terminal Toutb, that it further includes an inductor 11D and a transimpedance amplifier 12D, and that it includes a bypass circuit 13D instead of the bypass circuit 13C. The input terminal Tinb is electrically connected to the anode of the light receiving element PDb. The photocurrent Ipdb is input to the input terminal Tinb. The output terminal Toutb outputs the voltage signal Voutb to the outside of the receiving circuit 10D.

[0077] The inductor 11D is an inductance element similar to the inductor 11. The inductor 11D has an inductance L1. The inductor 11D has a terminal 11c and a terminal 11d. The terminal 11c is electrically connected to the input terminal Tinb. The terminal 11d is electrically connected to an input node 12c described later. The inductor 11D is disposed, for example, on the same substrate as the transimpedance amplifier 12D, and is formed by wiring on the substrate. That is, the inductor 11D corresponds to an inductance component of the wiring electrically connecting the input terminal Tinb and the input node 12c. Note that, when a relatively large inductance L1 is required, the inductor 11D may be formed, for example, as a spiral inductor on a semiconductor chip.

[0078] The transimpedance amplifier 12D is a circuit that converts the current signal Iinb into a voltage signal Voutb. The transimpedance amplifier 12D has the same configuration as the transimpedance amplifier 12. Specifically, the transimpedance amplifier 12D includes a voltage amplifier 21D and a feedback resistor element 22D. The input terminal and the output terminal of the voltage amplifier 21D are electrically connected via the feedback resistor element 22D. That is, the feedback resistor element 22D is electrically connected between the input and output of the voltage amplifier 21D. The current signal Iinb is generated by extracting the bypass currents Iagc1b and Iagc2b from the photocurrent Ipdb. The bypass currents Iagc1b and Iagc2b are controlled by the bypass circuit 13D. The increase and decrease of the voltage signal Voutb are inverted with respect to the increase and decrease of the current signal Iinb. For example, when the current amount of the current signal Iinb increases, the voltage value of the voltage signal Voutb decreases (drops).

[0079] The voltage amplifier 21D is, for example, an inverting amplifier circuit. The gain of the transimpedance amplifier 12D (the ratio of the amount of change in the voltage signal Voutb to the amount of change in the current signal Iinb) is determined by the resistance value (transimpedance) of the feedback resistor element 22D. The gain of the transimpedance amplifier 12D is calculated by ΔVoutb / ΔIinb, where ΔVoutb is the amount of change in the voltage signal Voutb and ΔIinb is the amount of change in the current signal Iinb that produces the amount of change ΔVoutb. The input impedance of the transimpedance amplifier 12D is, for example, about 10 to 100 Ω.

[0080] The transimpedance amplifier 12D has an input node 12c and an output node 12d. The input node 12c is a connection point between an input terminal of the voltage amplifier 21D and one end of the feedback resistor element 22D. That is, a current signal Iinb is input to the input node 12c. The output node 12d is a connection point between an output terminal of the voltage amplifier 21D and the other end of the feedback resistor element 22D. That is, a voltage signal Voutb is output from the output node 12d.

[0081] The bypass circuit 13D generates a current signal Iin by extracting bypass currents Iagc1 and Iagc2 from the photocurrent Ipd, and generates a current signal Iinb by extracting bypass currents Iagc1b and Iagc2b from the photocurrent Ipdb. The bypass circuit 13D is mainly different from the bypass circuit 13C in that it further includes a transistor 31D, a transistor 32D, and a parallel circuit 33D. In addition, in FIG. 13, the control circuit 40 generates a control voltage Vagc according to the differential voltage signals Vout and Voutb. Specifically, the control circuit 40 detects the amplitude of the differential voltage signals Vout and Voutb, and generates a control voltage Vagc according to the amplitude. For example, the control circuit 40 increases the voltage value of the control voltage Vagc as the amplitude of the differential voltage signals Vout and Voutb increases. The control circuit 40 outputs the control voltage Vagc to the gate of the transistor 31, the gate of the transistor 32, the gate of the transistor 31D, and the gate of the transistor 32D. The amplitude of the differential voltage signals Vout, Voutb corresponds to the peak value of the difference voltage between the voltage signals Vout and Voutb.

[0082] The transistors 31D and 32D are, for example, field effect transistors having a MOS structure. In this modification, N-channel MOS transistors are used as the transistors 31D and 32D. The transistor 31D is electrically connected between the terminal 11c of the inductor 11D and the bias power supply 34. Specifically, the drain of the transistor 31D is electrically connected to the terminal 11c of the inductor 11D. The source of the transistor 31D is electrically connected to the bias power supply 34 via the parallel circuit 33D. The gate of the transistor 31D is electrically connected to the control circuit 40. A control voltage Vagc is supplied to the gate of the transistor 31D.

[0083] The transistor 32D is electrically connected between the terminal 11d of the inductor 11D and the bias power supply 34. Specifically, the drain of the transistor 32D is electrically connected to the terminal 11d of the inductor 11D. The source of the transistor 32D is electrically connected to the bias power supply 34. The gate of the transistor 32D is electrically connected to the control circuit 40. A control voltage Vagc is supplied to the gate of the transistor 32D. The size (gate width) of the transistor 31, the size (gate width) of the transistor 32, the size (gate width) of the transistor 31D, and the size (gate width) of the transistor 32D may be the same as or different from each other.

[0084] The parallel circuit 33D has a similar configuration to the parallel circuit 33. Specifically, the parallel circuit 33D includes a resistive element 35D and a capacitor 36D, and is a circuit in which the resistive element 35D and the capacitor 36D are connected in parallel. The parallel circuit 33D is connected in series with the transistor 31D. In this modification, the parallel circuit 33D is electrically connected between the transistor 31D and the bias power supply 34. The parallel circuit 33D has a node 33c and a node 33d. The node 33c is a connection point between one end of the resistive element 35D and one end of the capacitor 36D. The node 33d is a connection point between the other end of the resistive element 35D and the other end of the capacitor 36D. The node 33c is electrically connected to the source of the transistor 31D. The node 33d is electrically connected to the bias power supply 34. The resistance value R3 of the resistive element 35D is set to be sufficiently larger than the input impedance of the transimpedance amplifier 12D (input node 12c), for example, several hundred Ω to several kΩ. The capacitance value C3 of the capacitor 36D is set to be, for example, several tens of fF to several hundreds of fF. The method of determining the resistance value R3 and the capacitance value C3 is the same as the method of determining the resistance value R1 and the capacitance value C1.

[0085] The receiving circuit 10D also has the same effect as the receiving circuit 10C. The optical receiving device 1D can also be configured using two receiving circuits 10C shown in Fig. 12. Compared to a configuration using two receiving circuits 10C, the receiving circuit 10D has one bias power supply 34 and one control circuit 40. This makes it possible to reduce the power consumption of the optical receiving device 1D and the receiving circuit 10D.

[0086] A differential transimpedance amplifier may be used instead of the transimpedance amplifier 12 and the transimpedance amplifier 12D. For example, the differential transimpedance amplifier has a non-inverting input node and an inverting input node, an input terminal Tin is electrically connected to the non-inverting input node via an inductor 11, and an input terminal Tinb is electrically connected to the inverting input node via an inductor 11D. The differential transimpedance amplifier further has a non-inverting output node and an inverting output node, the non-inverting output node is electrically connected to an output terminal Tout, and the inverting output node is electrically connected to an output terminal Toutb. The differential transimpedance amplifier generates differential voltage signals Vout, Voutb according to the difference between a current signal Iin input to the non-inverting input node and a current signal Iinb input to the inverting input node. The bias power supply 34 is shared by the positive phase circuit (transistors 31, 32 and parallel circuit 33) and the negative phase circuit (transistors 31D, 32D and parallel circuit 33D) included in the bypass circuit 13D, but the bias power supply 34 may be provided separately for each of the positive phase circuit and the negative phase circuit.

[0087] In the receiver circuits 10, 10A, 10B, and 10C, the same control voltage Vagc is supplied to the transistors 31 and 32, but different control voltages Vagc may be supplied to the transistors. In the receiver circuit 10D, the same control voltage Vagc is supplied to the transistors 31, 31D, 32, and 32D, but different control voltages Vagc may be supplied to the transistors.

[0088] In the receiving circuits 10, 10B, 10C, and 10D, the parallel circuit 33 may be electrically connected between the terminal 11a and the transistor 31. Similarly, in the receiving circuits 10A and 10B, the parallel circuit 37 may be electrically connected between the terminal 11b and the transistor 32. In the receiving circuit 10D, the parallel circuit 33D may be electrically connected between the terminal 11c and the transistor 31D.

[0089] In the receiving circuits 10, 10A, 10B, 10C, and 10D, the transistor 31 may be replaced by another configuration functioning as a variable resistance element, and the transistor 32 may be replaced by another configuration functioning as a variable resistance element. Similarly, in the receiving circuit 10D, the transistors 31D and 32D may be replaced by another configuration functioning as a variable resistance element. For example, the transistors 31, 31D, 32, and 32D may be bipolar transistors. In this case, the gate, source, and drain are replaced by the base, emitter, and collector, respectively. [Explanation of symbols]

[0090] 1, 1A, 1B, 1C, 1D...Optical receiving device 10, 10A, 10B, 10C, 10D...Receiving circuit 11…Inductor 11D…Inductor 11a…Terminal 11b…Terminal 11c…Terminal 11d…Terminal 12...Transimpedance amplifier 12D...Transimpedance Amplifier 12a…Input node 12b…Output node 12c…Input node 12d…Output node 13, 13A, 13B, 13C, 13D...Bypass circuit 21…Voltage amplifier 21D…Voltage amplifier 22...Feedback resistor element 22D…Feedback resistor element 31...Transistor (first variable resistance element) 31D...Transistor 32...Transistor (second variable resistance element) 32D...Transistor 33...Parallel circuit 33D…Parallel circuit 33a…node 33b…node 33c…Node 33d…node 34…Bias power supply 34a…Voltage amplifier 34b...Feedback resistor element 35...Resistance element 35D…Resistance element 36…Capacitor 36D…Capacitor 37...Parallel circuit 37a…node 37b…node 38...Resistance element 39…Capacitor 40...Control circuit Iagc1: Bypass current Iagc1b…Bypass current Iagc2: Bypass current Iagc2b: Bypass current Iin…Current signal Iinb…Current signal Ipd…Photocurrent (input current signal) Ipdb…Photocurrent PD: Light receiving element PDb: Light receiving element Pin…Optical signal Pinb…Optical signal Tc…Control terminal Tin: Input terminal Tinb: Input terminal Tout: Output terminal Toutb…Output terminal VPD: Bias voltage Vagc…Control voltage (control signal) Vbias: Bias voltage Vin: Input voltage Vout: Voltage signal Voutb: Voltage signal

Claims

1. A receiving circuit that generates a voltage signal in response to an input current signal generated by a light receiving element in response to an optical signal, an input terminal for receiving the input current signal; a bypass circuit for extracting a bypass current from the input current signal; a transimpedance amplifier having an input node and converting a current signal input to the input node into the voltage signal; an inductor having a first end electrically connected to the input terminal and a second end electrically connected to the input node; Equipped with The bypass circuit includes: A bias power supply for supplying a bias voltage; a first variable resistance element electrically connected between the first end and the bias power supply; a second variable resistance element electrically connected between the second end and the bias power supply; a parallel circuit in which a resistor element and a capacitor are connected in parallel; Equipped with The parallel circuit is connected in series with the first variable resistance element or the second variable resistance element.

2. The receiver circuit according to claim 1 , wherein the parallel circuit is connected in series with the first variable resistance element.

3. The receiver circuit according to claim 2 , wherein the parallel circuit is electrically connected between the first variable resistance element and the bias power supply.

4. The resistance value of the first variable resistance element varies in response to a control signal; 4. The receiving circuit according to claim 1, wherein a resistance value of the second variable resistive element varies in response to the control signal.

5. The receiver circuit of claim 4 , further comprising a control circuit that generates the control signal in response to the voltage signal.

6. 6. The receiving circuit according to claim 1, wherein a resistance value of the resistive element is greater than a value of an input impedance of the input node.

7. 7. The receiving circuit according to claim 1, wherein a cutoff frequency of the parallel circuit is lower than half a peak frequency at which a conversion efficiency from the input current signal to the voltage signal is maximized when one of the first variable resistance element and the second variable resistance element connected in series to the parallel circuit is set to an off state and the other variable resistance element is set to an on state.

8. 8. The receiving circuit according to claim 1, wherein a voltage value of the bias voltage is equal to an average voltage value of an input voltage of the input node.

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