Semiconductor Chips and Components

Abstract

A semiconductor chip (LD) having a structured chip rear side (RS) is specified, the chip rear side being configured for electrical and thermal coupling of the semiconductor chip (LD), the semiconductor chip (LD) having emitter regions (E) configured for generating electromagnetic radiation (L), the structured chip rear side (RS) having connection pads (AP) configured for electrically coupling the emitter regions (E). The connection pads (AP) are p-contacts or n-contacts, and in a top view, all connection pads (AP) configured as either p-contacts or n-contacts overlap at least two of the emitter regions (E), respectively, and each of these connection pads is configured for electrically coupling only one of the emitter regions (E). Furthermore, a component (100) specifically comprising at least one such semiconductor chip (LD) is specified.

Description

[Technical field]

[0001] The specifications for the semiconductor chip are defined, and furthermore, the specifications for the components are defined. [Background technology]

[0002] A semiconductor chip or chips are often mounted on an external support, e.g. a standardized chip submount, to which they are electrically and thermally connected. In many cases, it is desirable for the thermal and electrical connections of the semiconductor chips to be uniform. In many cases, it is desirable for the pitch distance, e.g. the emitter distance, between the semiconductor chips or between the radiation-emitting regions of a semiconductor chip to be short. Summary of the Invention

[0003] One objective is to specify semiconductor chips and components that have improved properties with respect to electrical and thermal interconnects and / or have short pitch or emitter distances.

[0004] This object is solved by a semiconductor chip and a component according to the independent claims. Further embodiments and further developments of the semiconductor chip and the component are the subject of the dependent claims.

[0005] In at least one embodiment of the semiconductor chip, the semiconductor chip has a textured chip bottom side configured to provide electrical and thermal connections to the semiconductor chip.

[0006] In at least one further embodiment of the semiconductor chip, the semiconductor chip has an organized chip bottom side configured to electrically and thermally connect the semiconductor chip. The semiconductor chip has emitter regions configured to generate electromagnetic radiation. The organized chip bottom side has connection pads configured to electrically connect the emitter regions. The connection pads are p-contacts or n-contacts, and in a top view, all connection pads formed as either p-contacts or n-contacts overlap at least two of the emitter regions, and each connection pad is configured to electrically connect only one of the emitter regions.

[0007] According to at least one embodiment of the semiconductor chip, the semiconductor chip has emitter regions configured to generate electromagnetic radiation. The bottom side of the structured chip has connection pads configured to electrically connect the emitter regions. For example, the semiconductor chip is a dual emitter or a multi-emitter, such as a triple emitter or quadruple emitter. The emitter regions can be an integral part of a common semiconductor body of the semiconductor chip.

[0008] In particular, the emitter region is defined by a so-called ridge region or ridge. A semiconductor chip having such a ridge region is also called a ridge laser or stripe laser. Such a semiconductor chip may have one or more stripe waveguides formed in the semiconductor region of the semiconductor chip. Such stripe waveguides may be configured for one-dimensional guiding along a guiding direction of the laser radiation generated in the active region of the semiconductor chip. If the semiconductor chip has two or more emitter regions, the semiconductor chip may have two or more such stripe waveguides.

[0009] For example, the emitter region or stripe waveguide extends along the lateral direction of the semiconductor body of the semiconductor chip. In particular, the stripe waveguide is in the form of a ridge protruding along the vertical direction. If the semiconductor chip has several emitter regions, the semiconductor chip may have several stripe waveguides, which are arranged next to each other in a top view, in particular in the form of convex ridges arranged next to each other.

[0010] A lateral direction is understood to mean in particular a direction parallel to a main plane of extension of a semiconductor chip, for example to a main plane of extension of a semiconductor body of the semiconductor chip. A vertical direction is understood to mean in particular a direction oriented perpendicular to a main plane of extension of the semiconductor chip or of the semiconductor body. The vertical direction and the lateral direction are perpendicular to each other.

[0011] For example, the semiconductor chip is an edge-emitting semiconductor chip. In an edge-emitting semiconductor chip, such as a ridge laser or stripe laser, the laser radiation is emitted at a side of the semiconductor chip. The generated laser radiation propagates essentially along a lateral direction parallel to the stripe waveguide.

[0012] According to at least one embodiment of the semiconductor chip, the bottom side of the structured chip has a number of connection pads, via which the emitter regions can be electrically connected to the outside, for example by contact structures of the carrier. The emitter regions can be individually electrically contacted via the connection pads. For example, the number of connection pads assigned to the same electrical polarity of the semiconductor chip is equal to or greater than the number of emitter regions. Each of the emitter regions can be electrically connected to only one connection pad or to multiple connection pads.

[0013] According to at least one embodiment of the semiconductor chip, the bottom side of the chip is formed in a honeycomb or matrix shape. In particular, the connection pads present on the bottom side of the chip can be arranged in a honeycomb or matrix shape.

[0014] Specifically, the bottom side of the structured chip has at least one n-contact or several n-contacts and at least one p-contact or several p-contacts. Specifically, the semiconductor chip is free of wire bonds. Avoiding wire bonds improves signal propagation time, high frequency performance, and high frequency impedance.

[0015] For example, the bottom side of the organized chip may have, in addition to the connection pads, further additional connection pads, where the connection pads form p-contacts and the further additional connection pads form n-contacts, or vice versa. For example, the connection pads and the further additional connection pads are disposed on a common plane, e.g., on a common redistribution plane.

[0016] Such semiconductor chips can utilize pitch distances that are difficult to achieve with conventional interconnection techniques. The use of redistribution planes, and in particular a single redistribution plane, allows for small pitch or ridge distances.

[0017] According to one embodiment of the semiconductor chip, the pitch distance, ridge distance, or waveguide distance is less than 50 μm, less than 30 μm, or less than 20 μm, for example between 5 μm and 50 μm.

[0018] In particular, the waveguide structure faces the mounting surface of the support (submount), in particular for reasons of improving heat dissipation. By mounting one or several semiconductor chips, for example in the same mounting plane, the pitch or ridge distance is narrowed or the tolerances are improved with respect to the observance of the desired pitch or ridge distance. In particular, the tolerance chain is improved. It is possible to arrange all the light emitting points on one plane.

[0019] Connection of multiple p-contacts and n-contacts with a dense arrangement (e.g., pitch can be less than 50 μm or 30 μm) can be realized. For example, the n-side of the semiconductor chip is connected from below, specifically from the same side as the p-side or from a common contact plane with the p-side. The embodiments of the semiconductor chip or component described herein differ from the case where the p-contacts and n-contacts are arranged on two different sides.

[0020] The substrate of the semiconductor chip, for example the GaN substrate, can be undoped. In other words, it is no longer necessary to dope the substrate to make it conductive. This improves the crystal quality. The EPI quality also improves. This leads to an improvement in the performance of the semiconductor chip. The electrical series resistance can be reduced since the current is no longer conducted through the entire substrate. This means that Uf is lowered. This means that the power losses of the semiconductor chip are also reduced. Finally, this increases the so-called WPE (Popt / Pel = Wall Plug Efficiency), i.e. the outlet efficiency or overall efficiency.

[0021] In particular, several semiconductor chips can be mounted on the same mounting plane. This also improves the tolerance chain (the influence of the chip thickness is eliminated). All light emitting points of the semiconductor chips can be on one plane. In particular, one, for example only one, rewiring plane is required to provide contact or connection pads of one or more semiconductor chips, for example for mounting on a support (submount). For example, no bonding wire connections are required to connect the semiconductor chips on the support. However, the support may have bonding wire connections.

[0022] The embodiments of the semiconductor chip or component described herein provide improved image quality, such as color uniformity and resolution. Multi-ridge semiconductor chips are brighter and less adversely affected in terms of blinking, i.e. flickering. The assembly requires less mounting space and less optical complexity due to the close waveguide spacing. Sub-pixel modulation can be achieved, for example, with short time intervals. For each pixel, a red, green or blue laser (r, g or b laser) can be turned on for a few nanoseconds. For example, 10 nanoseconds is divided into several short pulses. The semiconductor chip or laser is overcurrented, for example with a 50% duty cycle. In this way, the spectrum can be broadened. This provides improved image quality.

[0023] By pulse width modulation, brightness dimming can be achieved. A wider spectrum can be achieved by suppressing optical artifacts in the optical system (e.g. glasses such as data glasses, AR glasses, or VR glasses). Furthermore, the rgb emission spot becomes narrower. The larger overlap area from the r, g, and b pixels allows the rgb pixel to be "written" with multiple colors at the same time, resulting in a better image description or field of view. In particular, from the viewpoint of glasses architecture, a narrow emitter spacing is desirable because it allows multiple pixels to be written in parallel. However, this is difficult to achieve at the edge of the glasses.

[0024] Multi-ridges can be combined with small lenses, which leads to improved squint angles and corrections. This also reduces the form factor of the engine. If there are more ridges or if wavelength tuning is possible, high current performance may be less important. Lower operating currents are required to drive the chip just below threshold. To achieve fast switching times, semiconductor chips, especially lasers, operate just below threshold. Higher power is often associated with higher threshold. Connecting multiple emitting regions, such as multiple semiconductor chips or lasers in parallel, reduces power consumption for the same optical power while improving dynamic brightness control.

[0025] By distributing the current over several radiation-emitting regions, such as several ridges, the current consumption per region / ridge is reduced, which makes it possible to achieve shorter switching times.

[0026] In at least one embodiment of the support, the support has a textured contact surface configured to receive and make electrical contact with a semiconductor chip or chips.

[0027] In at least one embodiment of the component, the component has at least one semiconductor chip, particularly a semiconductor chip as described herein, and a support, where the at least one semiconductor chip is disposed on the support and is conductively connected to the support via an organized contact structure of the support.

[0028] In at least one embodiment of the component, the component comprises at least one semiconductor chip and a support, the semiconductor chip being arranged on the support, in particular the semiconductor chip being conductively connected to the support via an organized contact structure.

[0029] For example, the structured contact structure is a honeycomb structure or a contact pad structure. Deviations from this may also be made in the form of a matrix. For example, the contact structure may be on the bottom side of the chip, on the contact surface of the carrier, or a combination of the bottom side of the chip and the contact surface of the carrier.

[0030] In this disclosure, for clarity, components are often described in terms of a semiconductor chip having a support, but features described in relation to components can also be used separately in the semiconductor chip or separately in the support, or at least as well, and vice versa.

[0031] The semiconductor chips can be arranged on a support (submount) and electrically and / or thermally connected to the support (submount). In particular for generating electromagnetic radiation, the semiconductor chip can have a single semiconductor body, an organized semiconductor body or several semiconductor bodies. The semiconductor body can take the form of a ridge or multiple ridges. In particular, the semiconductor body has multiple ridges, i.e. multiple radiation-emitting regions. The ridges or radiation-emitting regions can be electrically contacted in particular separately, i.e. individually.

[0032] For example, the semiconductor chip is a radiation emitting semiconductor chip such as a laser, a thin film LED, a VCSEL, an HCSEL, an edge emitting laser, a ridge laser, a flip chip, or a pixelated LED. The semiconductor chip may also take the form of a laser array, such as a VCSEL array.

[0033] Components with at least one such semiconductor chip can be used in displays, in projectors (for example as pico-, power-, single- or multimode lasers), in data glasses, AV glasses or AR glasses (augmented reality glasses, virtual reality glasses) or in the field of so-called "augmented and virtual reality" or in the automotive industry. The component or semiconductor chip can take the form of a laser bar.

[0034] According to at least one embodiment of the component, the chip top side, for example the n-side top side of the component or semiconductor chip, has a structure, for example an organized electrical contact surface. The chip top side can be organized in any way. The component can comprise a plurality of semiconductor chips. It is also possible for the component to comprise a single semiconductor chip with a plurality of radiation-emitting areas. The organized chip top side, in particular the organized electrical contact surface, can be formed for electrical contact, in particular for individual electrical contact of the semiconductor chip or radiation-emitting areas of the semiconductor chip.

[0035] According to at least one embodiment of the component, the chip bottom side, e.g. the p-side bottom side of a semiconductor chip or the p-side bottom sides of multiple semiconductor chips, can be fitted or attached to the chip top side via an organized contact structure, e.g. via a honeycomb structure / contact pad structure.

[0036] It is also possible for the chip top side to be formed as a p-side and the chip bottom side to be formed as an n-side. Furthermore, the p-contact(s) and n-contact(s) of a semiconductor chip or component can be on a common plane. The p-contact(s) and / or n-contact(s) of one or more semiconductor chips can be on a common plane. For example, the common plane is an interface between one or more semiconductor chips and a support. The common plane can be a chip submount interface.

[0037] According to at least one embodiment of the component, the support has a structured contact surface. The structured contact surface of the support can be adapted to electrical contact points of one or more semiconductor chips. The contact points of the one or more semiconductor chips can be formed by connection pads present on a bottom side of the semiconductor chip or on a plurality of bottom sides of a plurality of semiconductor chips. For example, the structured contact surface of the support has a plurality of contact pads arranged side by side. In particular, the structured contact surface of the support has a honeycomb structure.

[0038] According to at least one embodiment of the component, the semiconductor chip comprises a semiconductor body, which may be electrically conductively connected to contact pads on the support via electrical distribution layers and / or connection pads, which contact pads on the support may be components of a structured contact surface of the support.

[0039] According to at least one embodiment of the component or semiconductor chip, an electrical distribution layer is arranged between the semiconductor body and the support. In particular, a single insulating layer or a single insulating plane is arranged between the electrical distribution layer and the support. For example, the single insulating layer or the single insulating plane is arranged vertically between the electrical distribution layer and the connection pads present on the bottom side of the chip.

[0040] An insulating layer or plane may have through contacts disposed therein. Specifically, a component or semiconductor chip may have a single redistribution or contact plane.

[0041] The insulating layer may have at least one opening or several openings. In each opening, a conductive through contact may be formed. Via the through contact or via a number of through contacts, the electrical distribution layer may be conductively connected to one or more connection pads. For example, the connection pads are arranged on the bottom side of the chip. In particular, the connection pads are electrical contact points of one or more semiconductor chips. The connection pads may be electrically and in particular thermally connected, for example, via one or more connection layers, to contact pads of the structured contact area of ​​the support.

[0042] In particular, supports or submounts corresponding to multiple chip designs can be formed. This means less variation and less logistics for different chip designs. The chip-submount interface can be standardized with respect to the process, in particular with respect to the connection of one or more semiconductor chips to the support. For different chip designs, the interface can always be the same. Also, for different chip designs, similar or identical materials can be used in the contact area of ​​the support. For different chip designs, the contact area of ​​the support can have the same structure. Also, the same interconnection technology can be used for different chip designs or multiple chip types.

[0043] If the contact surface of the support has several contact pads or several honeycombs arranged next to each other, the best possible heat dissipation is obtained by interconnecting several, in particular the maximum possible number of contact pads or honeycombs.

[0044] According to at least one embodiment, the semiconductor body or ridge is electrically connected via several partial regions of the contact surface of the carrier, in particular via several honeycombs or contact pads, in this way a uniform current injection can be achieved.

[0045] The distribution layer, in particular in the form of a metallization, can be adapted in terms of its layer thickness, so that the conductor current carrying capacity and the heat spreading in the immediate vicinity of the ridge or radiation emitting region of the semiconductor body can be adjusted and improved as desired.

[0046] The thermal and electrical connection of the semiconductor chip in general, and in particular of the optoelectronic chip, can be improved by a number of contacts (connections, ridges) on the mounting side. Optimal thermal connection and current injection can be achieved in particular by the possible connection of the semiconductor chip in a number of positions. The contact pads of the contact area of ​​the carrier can also be standardized, and a standardized assembly and connection technology can be achieved.

[0047] Further embodiments and further developments of the semiconductor chip or component will become apparent from the exemplary embodiments described below in conjunction with FIGS. 1 to 10D. [Brief description of the drawings]

[0048] [Figure 1] A cross-sectional view of the component is shown. [Figure 2A] 1A-1D illustrate schematic diagrams of several example embodiments of components having different contact options for one or more semiconductor chips. [Figure 2B] 1A-1D illustrate schematic diagrams of several example embodiments of components having different contact options for one or more semiconductor chips. [Figure 2C] 1A-1D illustrate schematic diagrams of several example embodiments of components having different contact options for one or more semiconductor chips. [Figure 2D] 1A-1D illustrate schematic diagrams of several example embodiments of components having different contact options for one or more semiconductor chips. [Figure 2E] 1A-1D illustrate schematic diagrams of several example embodiments of components having different contact options for one or more semiconductor chips. [Figure 3A]1A-1D show schematic diagrams of several exemplary embodiments of a component having different embodiments of a contact surface of a support; [Figure 3B] 1A-1D show schematic diagrams of several exemplary embodiments of a component having different embodiments of a contact surface of a support; [Figure 3C] 1A-1D show schematic diagrams of several exemplary embodiments of a component having different embodiments of a contact surface of a support; [Figure 3D] 1A-1D show schematic diagrams of several exemplary embodiments of a component having different embodiments of a contact surface of a support; [Figure 4] FIG. 1 shows a schematic diagram of a component having a honeycomb structure. [Diagram 5] 1 shows a schematic diagram of a further embodiment of a component; [Figure 6] 1 shows a schematic diagram of a further embodiment of a component; [Figure 7A] 1 shows a schematic diagram of further contact options. [Figure 7B] 1 shows a schematic diagram of further contact options. [Figure 8A] 1 shows a schematic diagram of a semiconductor chip on a support. [Figure 8B] 1 shows a schematic diagram of a semiconductor chip on a support. [Figure 9A] 1A-1D show schematic diagrams of various arrangements of connection or contact pads. [Figure 9B] 1A-1D show schematic diagrams of various arrangements of connection or contact pads. [Figure 9C] 1A-1D show schematic diagrams of various arrangements of connection or contact pads. [Figure 9D] 1A-1D show schematic diagrams of various configurations of connection or contact pads; [Figure 10A] 1 shows a schematic diagram of a further exemplary embodiment of a semiconductor chip or component; [Figure 10B] 1 shows a schematic diagram of a further exemplary embodiment of a semiconductor chip or component; [Figure 10C]1 shows a schematic diagram of a further exemplary embodiment of a semiconductor chip or component; [Figure 10D] 1 shows a schematic diagram of a further exemplary embodiment of a semiconductor chip or component; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] Identical, equivalent or equivalently acting elements are designated by the same reference numerals in the figures. The figures are schematic and therefore not necessarily drawn to scale. Relatively small elements, in particular layer thicknesses, may be shown rather exaggeratedly large for the sake of clarity.

[0050] 1 shows a component 100 with at least one semiconductor chip LD on a support S. The semiconductor chip LD has a semiconductor body HL, which is in particular configured to generate electromagnetic radiation L. The semiconductor body HL has a first semiconductor layer, a second semiconductor layer and an active zone, e.g. a pn junction zone, arranged between the first and second semiconductor layers. For example, the semiconductor body HL has a first semiconductor layer, a second semiconductor layer and an active region, e.g. a pn junction region, arranged between the first and second semiconductor layers, which active region is configured to generate electromagnetic radiation, in particular coherent electromagnetic radiation, during operation of the semiconductor chip HL.

[0051] The semiconductor chip LD may be a laser. For example, the semiconductor chip LD is a ridge laser. The semiconductor chip LD has an active region R. In particular, the active region R is a subregion of an active region of the semiconductor body HL. For example, the active region R is a ridge region. The semiconductor chip LD, or the semiconductor body HL of the semiconductor chip LD, may have a number of subregions, such as subregions E1, E2, E3, E4, each forming, for example, an emitter or emitter region. The partial regions may be spatially separated from one another or may form a continuous structure. It is also possible to arrange a number of semiconductor chips LD, each forming an emitter or emitter region E1, E2, E3, or E4, on the support S. The emitter or emitter region may each have an active region R, such as a ridge region.

[0052] The component 100 comprises an insulating layer IP or insulating plane IP, which is arranged in the vertical direction between the semiconductor body HL of the semiconductor chip LD and the support S. The insulating layer IP may or may not be an integral part of the semiconductor chip LD. The insulating layer IP may comprise or be formed from at least one of these materials: Al-nitride, Si-nitride, Al-oxide and / or Be-oxide. Such materials exhibit high thermal conductivity.

[0053] The insulating layer IP has at least one opening or several openings. In each opening, a through contact V is arranged. In particular, the through contact V penetrates the insulating layer IP.

[0054] The component 100 or semiconductor chip LD has an electrical distribution layer US, in particular arranged between the semiconductor body HL and an insulating layer IP. In particular, the electrical distribution layer US is configured to make electrical contact with a semiconductor layer, in particular a p-side semiconductor layer or an n-side semiconductor layer of the semiconductor body HL. For example, the insulating layer IP forms a single insulating plane of the semiconductor chip LD between the electrical distribution layer US and the chip bottom side RS.

[0055] The component 100 or the semiconductor chip LD may have several distributed layers US arranged side by side, for example, each of which is uniquely associated with one of the emitter regions E1, E2, E3, and E4, and vice versa.

[0056] The component 100 or semiconductor chip LD has a number of connection pads AP. An insulating layer IP is arranged between the electrical distribution layer US and the connection pads AP in the vertical direction. In particular, the electrical distribution layer US is conductively connected to the connection pad AP or to the connection pads AP via a through contact V or via multiple through contacts V. The side with the connection pads AP can be referred to as the chip bottom side or the structured chip bottom side RS.

[0057] The semiconductor chip LD has a structured chip bottom side RS configured for electrically and thermally connecting the semiconductor chip LD. The semiconductor chip LD has emitter regions E, e.g. a number of emitter regions E1, E2, E3, and E4 (see Figures 2A-2E), which are configured for generating electromagnetic radiation L. The structured chip bottom side RS has a number of connection pads AP configured for electrically connecting the emitter regions E.

[0058] In Fig. 1, the semiconductor chip LD is shown to have a chip top side VS and a side surface LS, and the side surface LS connects the chip top side VS and the chip bottom side RS. The chip top side VS is specifically a semiconductor top side. The semiconductor chip LD is specifically implemented as an edge-emitting semiconductor chip LD, and during operation of the semiconductor chip LD, electromagnetic radiation L is emitted from the semiconductor chip LD at the side surface LS.

[0059] The semiconductor chip LD comprises a semiconductor body HL having an emitter region E, an electrical distribution layer US and an insulating layer IP, the insulating layer IP being arranged between the semiconductor body HL and the connection pads AP in the vertical direction. The insulating layer IP has at least one opening or openings, in which a conductive through contact V or through contacts V are formed. The through contacts V are, for example, shown diagrammatically in Figs. 2A-4. In particular, the through contact is configured to conductively connect one of the connection pads AP to the electrical distribution layer US. One of the connection pads AP or a plurality of connection pads AP can be conductively connected to the electrical distribution layer US via one or more through contacts V.

[0060] 2A-3D show that each of the emitter regions E1-E4 can be electrically connected via one connection pad AP and one through contact V. FIGS. 4 and 7B also show that the emitter regions E1, E2, E3, or E4 can be electrically contacted via multiple connection pads AP and multiple through contacts V. Multiple through contacts V can be arranged on the insulating layer IP, and the electrical distribution layer US is conductively connected to multiple connection pads AP via multiple through contacts V. Furthermore, each of the emitter regions E1-E4 can be uniquely assigned to one of the distribution layers US, and vice versa.

[0061] The support S has a number of contact pads KP. The contact pads KP form a contact structure of the support S. For example, the component 100 has one or more conductive connection layers C. Via the conductive connection layer(s) C, the contact pads KP can be electrically connected to the connection pads AP. In particular, the arrangement of the contact pads KP of the support S is adapted to the arrangement of the connection pads AP of the semiconductor chip LD.

[0062] Figures 2A-2E in particular show the bottom side RS of the structured chip according to different embodiments. In these figures, possible positions of contact pads KP1, KP2, KP3 and KP4 associated with connection pads AP1, AP2, AP3 and AP4 on the support S are shown in schematic form. In Figures 2C, 2D and 2E, possible positions of further connection pads WA and further contact pads WK on the support S associated with the further connection pads WA are also shown in schematic form.

[0063] On the left side of each Figure 2A to 2E the positions of the connection pads AP1, AP2, AP3 and AP4 are shown in schematic relation to the positions of the emitter regions E1, E2, E3 and E4. On the right side of each Figure 2A to 2E the electrical contact of the emitter regions E1, E2, E3 and E4 via a through contact V as well as for example via a further through contact DV are also shown in schematic relation. The further through contact DV connects the semiconductor body HL to a further connection pad WA present on the chip bottom side RS.

[0064] Specifically, in top view, at least one of the connection pads AP overlaps at least two of the emitter regions E1-E4, and at least one connection pad AP is configured to electrically connect only one of the at least two emitter regions. Furthermore, in top view, the connection pads AP1-AP4, specifically all connection pads AP, can overlap at least two of the emitter regions E1-E4, or exactly two emitter regions, respectively. However, each connection pad AP is still configured to electrically connect only one of the emitter regions E1-E4.

[0065] FIG. 2A shows an embodiment of a component 100 or a semiconductor chip LD, in which the connection pads AP1-AP4 and / or contact pads KP1-KP4, respectively, overlap several emitters or emitter regions E1-E4, in particular two emitters or emitter regions E1-E4, respectively. The connection pads AP1-AP4 and / or contact pads KP1-KP4, respectively, may be configured to electrically contact a single emitter or one single emitter region, in particular. On the left side, no through contacts V are shown. On the right side, it is diagrammatically shown that the connection pads AP1-AP4, respectively, are conductively connected to one of the emitter regions or emitter regions E1-E4 via at least one through contact V. In particular, the connection pads AP1-AP4 are formed as p-contacts.

[0066] The exemplary embodiment shown in Fig. 2B is substantially the same as the exemplary embodiment of the component 100 or the semiconductor chip LD shown in Fig. 2A, except that the connection pads AP1-AP4 and / or the contact pads KP1-KP4, respectively, overlap all of the emitters or emitter regions E1-E4 arranged on the support S. In particular, the contact pads KP1-KP4 may extend laterally on the support S.

[0067] The exemplary embodiment shown in Fig. 2C basically corresponds to the exemplary embodiment of the component 100 or the semiconductor chip LD shown in Fig. 2A. However, the further connection pad WA or the further contact pad WK is arranged in particular in the same plane as the contact pad KP or the connection pad AP. In particular, the further connection pad WA and the connection pad AP are assigned to different electrical polarities of the semiconductor chip LD. For example, the connection pad AP forms a p-contact and the further connection pad WA forms an n-contact of the semiconductor chip LD or vice versa.

[0068] In particular, the further contact pads WK and the contact pads KP are assigned to different electrical polarities of the component 100 or the semiconductor chip LD. For example, the further contact pads WK form n-contacts and the contact pads KP form p-contacts of the component 100 or vice versa. Thus, in particular, no wire bonds are required on the chip top side, in particular on the n-side. For example, the semiconductor body has internal through contacts DV that pass through the active area and are conductively connected to the further connection pads WA or to the further contact pads WK.

[0069] The exemplary embodiment shown in FIG. 2D is basically the same as the exemplary embodiment of the component 100 or the semiconductor chip LD shown in FIG. 2B, but is very similar to FIG. 2C with an additional connection pad WA or an additional contact pad WK.

[0070] The exemplary embodiment shown in Fig. 2E basically corresponds to the exemplary embodiment of the component 100 or the semiconductor chip LD shown in Fig. 2D, whereas the component 100 or the semiconductor chip LD has additional further connection pads WA and additional further contact pads WK. In Fig. 2D, two additional further connection pads WA or two additional further contact pads WK are shown. In Fig. 2E, four additional further connection pads WA or four additional further contact pads WK are shown.

[0071] According to Fig. 2A-2E, the semiconductor chip LD has a number of connection pads AP1-AP4 and a number of through contacts V, each of the connection pads AP1-AP4 being configured to make electrical contact with one single emitter region E1, E2, E3 or E4. In top view, each of the connection pads AP1-AP4 overlaps several emitter regions, in particular exactly two or four emitter regions. In addition to the connection pads AP1-AP4, the semiconductor chip LD has further connection pads WA, where the connection pads AP1-AP4 form p-contacts of the semiconductor chip LD and the further connection pads WA form n-contacts of the semiconductor chip LD or vice versa. In particular, the p-contacts and the n-contacts of the semiconductor chip LD, i.e. the connection pads AP1-AP4 and the further connection pads WA of the semiconductor chip LD, are arranged in a common contact plane.

[0072] FIG. 3A shows a component 100 with another exemplary support design for the semiconductor chip LD shown in FIG. 2A. The support S has a contact structure with a number of contact pads KP1-KP4 arranged side by side. The support S has lateral metallizations SM, each of which is conductively connected to one of the contact pads AP1-AP4. The lateral metallizations SM may be denoted as submount connection pads. Via such submount connection pads, the submount may be conductively connected to the surrounding electrical structure. In particular, the contact pads AP1-AP4 are arranged between the lateral metallizations SM.

[0073] Figure 3B shows a component 100 with an exemplary support design for the semiconductor chip LD shown in Figure 2B. According to Figure 3B, all metallizations SM are arranged on the same side of the contact pads AP1 to AP4.

[0074] FIG. 3C shows a component 100 with another exemplary support design for the semiconductor chip LD shown in FIG. 2C. The support S may have further through contacts VH. The further through contacts VH may pass through the body of the support S. The further through contacts VH are in particular through vias in the submount S or in the support S. By means of the further through contacts VH, the component 100 may be electrically contactable from the outside via the rear surface of the support S, in particular only via the rear surface of the support S. Deviating from this, a redistribution layer RL in the support S is shown in FIG. 3C in a schematic manner. Through the redistribution layer RL, the outer metallization SM may be conductively connected to the inner metallization, in particular in the form of the contact pads KP1 or KP3. The redistribution layer RL may be completely embedded in the support S.

[0075] FIG. 3D shows a component 100 having an exemplary support design for the semiconductor chip LD shown in FIG. 2E.

[0076] FIG. 4 shows a component 100 or semiconductor chip LD with a honeycomb structure. The honeycomb structure can be a bottom side metallization BMLD of the semiconductor chip LD. The active region R or emitter region E, specifically the ridge R, can be electrically connected via several honeycombs, specifically via through contacts V. Thus, uniform current injection can be achieved. Furthermore, a large area metal bonding surface of the semiconductor chip LD is realized via the honeycomb structure. The inclined honeycomb layout can serve as a standardized chip submount interface and can be used for different semiconductor chips LD or different ridge configurations.

[0077] 5 and 6 respectively show a component 100 having a chip top side VS, a chip bottom side RS, and a support top side SV. The support top side SV matches the chip bottom side RS. In particular, the support top side SV is formed in a honeycomb shape.

[0078] The chip top side VS, specifically the n-side, can be organized as needed. The chip bottom side RS, specifically the p-side, can be adapted to the chip top surface VS via a honeycomb / contact pad structure. The ridges R or emitter regions E can be electrically connected via several honeycombs / contact pads, thus achieving uniform current injection. Specifically, only one redistribution / contact plane is needed. The design of the contact pads with only one insulation level is largely independent of the position and location of the ridges R or emitter regions E.

[0079] By increasing the thickness of the metallization on the ridge R or on the emitter region E, in particular an improvement in the conductor current carrying capacity and heat spreading can be achieved. The redistribution is performed in only one insulating plane. The insulating plane can have an electrical through contact V at the vertical overlap of the connection metallization, i.e. the connection pad, and the ridge R, i.e. the emitter region E, respectively. The insulating plane can have a high thermal conductivity and a high dielectric strength. The insulating layer, i.e. the insulating layer IP, can be made of Al-nitride, Si-nitride, Al-oxide, Be-oxide or similar material. The connection pads AP or contact pads KP can be made to have as large a surface area as possible. They can cover as large a portion of the chip connection plane as possible. Furthermore, they can cover several emitter regions E, in particular several ridges R, improving heat dissipation.

[0080] Figures 7A and 7B show some further contact possibilities, namely very similar to the exemplary embodiments shown in Figures 3B and 3C, respectively. On the other hand, each connection pad AP according to Figure 7A may overlap three emitter regions E1-E3. According to Figure 7B, the semiconductor chip LD may have five or more emitter regions E. The connection pads AP may be arranged in a matrix on the chip bottom side RS.

[0081] 8A shows a semiconductor chip LD arranged on a support S. The support S is arranged on a further submount T, for example a so-called base plate T. The submount T is the base plate of the semiconductor chip.

[0082] FIG. 8B is an enlarged view of FIG. 8A. The semiconductor chip LD may have a plurality of radiation-emitting regions, in particular a plurality of emitters or emitter regions E. FIG. 8B shows a semiconductor chip LD having two emitter regions E1 and E2 in a schematic manner. The distance between adjacent emitters or between emitter regions E1 and E2 may be 5 μm to 50 μm. The number of emitters or emitter regions may be more than 2, 3, 4 or even more than 6. The semiconductor chip LD is in particular a so-called multi-emitter. In particular, no bonding wire connection is required for the connection of the semiconductor chip LD. However, FIG. 8B shows in a schematic manner that a bonding wire connection can be used for the electrical connection between the support S and the contact regions of the base plate T.

[0083] 9A, 9B, 9C and 9D show different distributions of p-connection pads AP and n-connection pads WA, here for 12 channels as an example. In particular, the connection pads AP are arranged in a matrix. 9A, 9B and 9C show respectively two, four and six additional connection pads WA. The connection pads AP and the further additional connection pads WA are assigned to different electrical polarities of the semiconductor chip LD or component 100. Each scheme for the distribution of p-connection pads and n-connection pads can be scalable and variable in terms of the number of channels / ridges, pad size, pad spacing and in terms of pad segmentation. 9A, 9B and 9C show in particular an organized chip bottom side RS with connection pads AP and further connection pads WA. 9D shows in particular the chip bottom side RS and the modulator side. The modulator side can be defined by the surface of the support S.

[0084] Fig. 10A shows that the semiconductor chip LD may have separate sub-regions, in particular separate emitter regions E1-E4. On the left side, the semiconductor chip LD is formed continuously. The left side semiconductor chip LD may have a single semiconductor body HL with emitter regions E1-E4. On the right side, Fig. 10A shows two separate semiconductor bodies HL or two separate semiconductor chips LD, which respectively have two emitter regions E1 and E2 or two emitter regions E3 and E4.

[0085] On the left side of Fig. 10A, a semiconductor chip with four emitters or emitter regions E1-E4 is shown diagrammatically. Such a semiconductor chip may have high yield losses, since all four emitters or emitter regions E1-E4 must be in specification and have a total wavelength spread of, for example, 10 nm. Achieving four different wavelengths in one chip requires a lot of effort.

[0086] The semiconductor chip LD can be divided into two chip regions, each of which has two emitters or emitter regions at half the chip width (see the right side of FIG. 10A). Only two emitters or two emitter regions should be specified. This results in a much higher yield, since at most only one emitter or one emitter region or one chip region is wavelength shifted. Thus, the effort required to fabricate the individual chip regions is much less. It is also possible to form each chip region as one semiconductor chip.

[0087] Specifically, Fig. 10A shows two separate semiconductor chips LD on the right side, which may be disposed on a common support S. Figs. 10B-10D also show two separate semiconductor chips LD, which may be disposed on a common support S. In Figs. 10A-10D, for reasons of clarity, the support S is not explicitly shown in some cases.

[0088] The two semiconductor chips 10C are spatially separated from each other by a lateral intermediate region D or a lateral distance D. The lateral intermediate region D may be between 5 μm and 50 μm in width.

[0089] The lateral distance A between two adjacent emitter regions E1-E4 may be 20 μm-60 μm, for example, 25 μm±5 μm, 30 μm±5 μm, 35 μm±5 μm, or 50 μm±5 μm. For example, the lateral distance A is 50 μm. For example, the lateral distance A is indicated by the distance between two light-emitting points of two adjacent emitter regions E on the side surface LS of the semiconductor chip LD or the side surface of the component 100.

[0090] A lateral distance D between two adjacent semiconductor chips LD may be longer or shorter than a lateral distance A between two adjacent emitter regions E. Specifically, the intermediate region D between two adjacent semiconductor chips LD is configured to set a lateral distance AZ between two adjacent outer emitter regions E of the adjacent semiconductor chips LD.

[0091] The component 100 may have an equal lateral separation distance for all emitter regions E1-E4. In this case, the lateral distance AZ between two adjacent outer emitter regions E of adjacent semiconductor chips LD is the same as the lateral distance A between adjacent emitter regions E of the same semiconductor chip LD. For example, the equal lateral pitch distance is about 50 μm. Also, the equal pitch distance may be 30 μm±5 μm, 35 μm±5 μm, 40 μm±5 μm, 45 μm±5 μm, or 50 μm±5 μm.

[0092] Each of the semiconductor chips LD shown in Figures 10B to 10D may have a lateral width NB of, for example, 150 μm. The semiconductor chip LD having the four emitter regions E1 to E4 shown on the left side of Figure 10A may have a width AG of approximately 300 μm.

[0093] The widths shown in relation to Figures 10A-10D are merely examples, and the present disclosure is not limited to these quantities.

[0094] The chip regions or semiconductor chips LD shown on the right side of FIG. 10A can be fixed, specifically soldered, to a support S so that a predetermined distance between the emitter regions or between the chip regions can be maintained with a maximum manufacturing tolerance of, for example, ±2 μm. The distance between the emitter regions E or between the chip regions can be 50 μm or less, for example, 30 μm, or 20 μm, 10 μm or less, for example, 2 μm to 5 μm. By combining chip regions or different semiconductor chips LD, a wavelength expansion of about 10 nm (FWHM) can be achieved. Specifically, the semiconductor chip LD has two or more resonators. For example, the number of resonators of the semiconductor chip is 2, 3, 4, or 6, for example, 2 to 6, 2 to 4, or 4 to 6.

[0095] Such a semiconductor chip LD is particularly suitable for some applications where the coherence (narrow spectral width) of the laser emission usually creates problems. Such problems include, for example, optical artifacts in image displays, which are caused, for example, by the interaction of small spectral bandwidths of the emission and / or by periodic structures in the beam path, for example diffractive optical structures. To avoid this problem, the semiconductor chip LD described herein can be used. With such a semiconductor chip LD, the spectral emission width can be broadened. One way to achieve an increase in the spectral emission width is to overlap the spectra of the individual ridges with a small wavelength offset. In many cases, a spectral width (wavelength broadening) of about 10 nm (FWHM) is desired. To achieve this value, the wavelength offset between emitters or emitter regions on the semiconductor chip LD can be about 2 μm to 5 μm between the individual resonators on the semiconductor chip LD.

[0096] The component 100 has multiple resonators, and the semiconductor chip LD and the emitter regions E, E1, E2, E3, and E4 are arranged adjacent to each other such that during operation of the component 100, the spectra of the individual emitter regions E, E1, E2, E3, and E4 overlap with a wavelength offset. In particular, the wavelength offset is 2 μm to 5 μm between the individual resonators. As a result, a spectral width of 10 nm ± 5 nm can be achieved.

[0097] The embodiment shown in FIG. 10B basically corresponds to the embodiment shown on the right side of FIG. 10A. Meanwhile, the through contacts V are shown diagrammatically. Due to the specific design of the through contacts V, each of the connection pads AP or each of the contact pads KP is configured to electrically contact one single emitter or one single emitter region E1-E4 (see also FIGS. 2A-3D). In top view, each of the connection pads AP or each of the contact pads KP may cover several emitters or emitter regions E1-E4. In all figures, the through contacts V are rather close to local through contacts V. The through contacts V do not extend, in particular along the lateral direction, over the entire width or length of the emitter or emitter region E1-E4 with which the through contacts V are associated.

[0098] According to Fig. 10B, the lateral distance A between adjacent emitter regions E1 and E2 or between emitter regions E3 and E4 of the same semiconductor chip LD may be about 30 μm or 50 μm. The lateral distance AZ between two adjacent outer emitter regions E2 and E3 of adjacent semiconductor chips LD may be longer or shorter than the lateral distance A. For example, the lateral distance AZ is, for example, 70 μm or 30 μm.

[0099] The embodiment shown in FIG. 10C is substantially the same as the embodiment shown in FIG. 10B, in particular after the semiconductor chip LD or a number of semiconductor chips LD have been attached to the support S.

[0100] The exemplary embodiment shown in Fig. 10D is basically the same as the exemplary embodiment shown in Fig. 10A or 10B, except for the distance between the emitters or between the emitter regions E1 to E4, or between the emitter regions, or between the semiconductor chips LD. Specifically, the lateral distance A is, for example, 30 μm. The lateral distance AZ may be about 70 μm.

[0101] 10B-10D thus show a component 100 with a number of emitter regions E, E1, E2, E3 and E4, a number of connection pads AP and a number of through contacts V. Each connection pad AP is configured to make electrical contact with one single emitter region E1, E2, E3 or E4. In top view, each connection pad AP may overlap at least two or exactly two emitter regions E1 and E2 or emitter regions E3 and E4.

[0102] The component 100 has at least two semiconductor chips LD, which are arranged next to each other on the support S and are conductively connected to the support S via organized contact structures of the support S. In particular, the semiconductor chips LD are different from single emitters and each have at least two emitter regions E. For example, each semiconductor chip LD is formed as a double emitter. Each semiconductor chip LD may have a chip bottom side RS with at least two connection pads AP, each of which is configured to be in electrical contact with only one single emitter region E and overlap at least two emitter regions E in a top view.

[0103] The semiconductor chip LD and the emitter region E can be arranged next to each other to obtain a wavelength expansion of 10 nm±5 nm. A component 100 having such a semiconductor chip LD can be applied to AR glasses, VR glasses, or data glasses to enhance image quality by wavelength expansion.

[0104] In Figures 10B-10D, the semiconductor chips LD are each formed as double emitters with exactly two emitter regions E. The component 100 may have exactly two semiconductor chips LD or may have more than two semiconductor chips LD, for example three or four semiconductor chips LD. Deviating from Figures 10B-10D, it is possible to form the semiconductor chips LD each as triple emitters with exactly three emitter regions E. In particular, the emitter regions E are each formed to generate coherent radiation. The semiconductor chips LD can be constructed similarly.

[0105] This patent application claims the priority of German patent application No. 10 2021 115 231.3 and of German patent application No. 10 2021 123 015.2, the disclosure content of which is hereby incorporated by reference.

[0106] Although the invention has been described with reference to exemplary embodiments, it is not intended that the invention be limited to the exemplary embodiments, but rather that the invention includes any novel feature and any combination of features, and in particular any combination of features in the claims, even if that feature or combination is not itself explicitly set forth in the claims or in the exemplary embodiments.

[0107] List of reference numbers 100 Components LD Semiconductor Chip LS Semiconductor chip side A is the distance between two adjacent emitter regions on the same semiconductor chip AG Semiconductor chip / multi-emitter width D Distance / mid-area between two adjacent semiconductor chips AZ is the distance between two adjacent emitter regions of adjacent semiconductor chips AP Connection Pad AP1 First connection pad AP2 Second connection pad AP3 3rd connection pad AP4 4th connection pad BMLD Bottom Side Metallization C Connection Layer E Emitter area / emitter E1 First emitter area / emitter E2 Second emitter area / emitter E3 Third emitter area / emitter E4 4th emitter area / emitter IP insulation layer, insulation level KP Contact Pad KP1 1st Contact Pad KP2 2nd Contact Pad KP3 3rd Contact Pad KP4 4th Contact Pad L radiation, light NB Semiconductor chip / double emitter width R Ridge, Ridge region, Emitter region RL Redistribution Layer RS chip bottom side S Support, submount SM Lateral Metallization / Submount Connection Pads SV support upper side T Submount, Base Plate US Distribution Tier V through contact VH Further through contacts / Through via contacts in submount / Through via contacts in base plate VS Chip top side / Semiconductor top side WA More Connection Pads WK More Contact Pads

Claims

1. A semiconductor chip (LD) having a structured chip bottom side (RS), the bottom side (RS) of the assembly chip is adapted for electrical and thermal connection to the semiconductor chip (LD); The semiconductor chip (LD) comprises an emitter region (E) configured to generate electromagnetic radiation (L); the bottom side (RS) of the assembly chip comprises connection pads (AP) arranged for said electrical connection of the emitter regions (E); the connection pads (AP) are p-contacts, and in top view, all of the connection pads (AP) formed as p-contacts are configured to overlap at least two of the emitter regions (E) of the semiconductor chip (LD) and to electrically connect only one of the emitter regions (E); in addition to the connection pad (AP) formed as a p-contact, the semiconductor chip (LD) has a further connection pad (WA), which further connection pad (WA) forms an n-contact of the semiconductor chip (LD), the p-contact and the n-contact of the semiconductor chip (LD) being arranged on a common contact plane, Semiconductor chip (LD).

2. The semiconductor chip (LD) has a chip top side (VS) and a side surface (LS), The side surface (LS) connects the chip top side (VS) to the chip bottom side (RS); The semiconductor chip (LD) is formed as an edge-emitting semiconductor chip (LD), During operation of the semiconductor chip (LD), electromagnetic radiation (L) is emitted from the semiconductor chip (LD) at the side surface (LS). A semiconductor chip (LD) according to claim 1.

3. 2. The semiconductor chip (LD) according to claim 1, wherein in top view all connection pads (AP) formed as p-contacts overlap three or four emitter regions (E) of the semiconductor chip (LD), respectively.

4. A semiconductor chip (LD) as described in claim 1, wherein the connection pads (AP), which are p-contacts, each overlap with all of the emitter regions (E) of the semiconductor chip (LD).

5. The semiconductor chip (LD) comprises a semiconductor body (HL) having the emitter region (E), an electrical distribution layer (US) and an insulating layer (IP), said insulating layer (IP) being arranged vertically between said semiconductor body (HL) and said connection pad (AP); The insulating layer (IP) has at least one opening, and a conductive through contact (V) is formed in the opening; one of said connection pads (AP) is conductively connected to said electrical distribution layer (US) via said through contact (V); A semiconductor chip (LD) according to claim 1.

6. The semiconductor chip (LD) of claim 5, wherein a plurality of through contacts (V) are disposed in the insulating layer (IP), and the electrical distribution layer (US) is conductively connected to a plurality of connection pads (AP) via the plurality of through contacts (V).

7. 6. The semiconductor chip (LD) of claim 5, wherein the insulating layer (IP) forms an insulating plane between the electrical distribution layer (US) and the chip bottom side (RS), which is the only insulating plane of the semiconductor chip (LD).

8. The semiconductor chip (LD) includes a plurality of connection pads (AP) and through contacts (V), each of said connection pads (AP) is configured to make electrical contact with one single emitter region (E); A semiconductor chip (LD) according to claim 5.

9. The semiconductor chip (LD) according to any one of claims 1 to 8, wherein the emitter regions (E) of the semiconductor chip (LD) extend parallel to each other and are each formed as a ridge region, and the emitter regions (E) are configured to generate coherent electromagnetic radiation.

10. A semiconductor chip (LD) according to any one of claims 1 to 8, wherein the connection pads (AP) on the bottom side (RS) of the chip are arranged in a honeycomb or matrix shape so that the organized chip bottom side (RS) having the connection pads (AP) is formed in a honeycomb or matrix shape.

11. A component (100) comprising at least one semiconductor chip (LD) according to any one of claims 1 to 8 and a support (S), The at least one semiconductor chip (LD) is arranged on the support (S) and is conductively connected to the support (S) via an organized contact structure of the support (S). The component (100).

12. the semiconductor chip (LD) has a semiconductor body (HL) which is conductively connected to contact pads (KP) on the support (S) via an electrical distribution layer (US) and via connection pads (AP) on the chip bottom side (RS), said electrical distribution layer (US) being arranged between said semiconductor body (HL) and said support (S); Between the electrical distribution layer (US) and the support (S) a single insulating layer (IP) is arranged; The component (100) of claim 11.

13. The component (100) comprises a number of emitter regions (E, E1, E2, E3, E4), a number of connection pads (AP) and a number of through contacts (V); each of said connection pads (AP) is configured to make electrical contact with one single emitter region (E, E1, E2, E3, E4); The component (100) of claim 11.

14. The component (100) comprises a number of emitter regions (E, E1, E2, E3, E4), a number of connection pads (AP) and a number of through contacts (V); the emitter regions (E, E1, E2, E3, E4) are each conductively connected to a contact pad (KP) of the organized contact structure of the support (S) via the connection pads (AP) and the through contacts (V); each of said connection pads (AP) is assigned to at most one single emitter region of said emitter regions (E, E1, E2, E3, E4); The component (100) of claim 11.

15. Component (100) according to claim 11, wherein the connection pads (AP) on the chip bottom side (RS) of the semiconductor chip (LD) are arranged in a honeycomb or matrix manner, such that the organized contact structure of the chip bottom side (RS) and / or the support (S) of the semiconductor chip (LD) is formed in a honeycomb or matrix manner.

16. The component (100) comprises a further semiconductor chip (LD), the further semiconductor chip (LD) being arranged next to the semiconductor chip (LD) on the support (S) and being conductively connected to the support (S) via the organized contact structures of the support (S), The semiconductor chips (LD) are different from single emitters and each has at least two emitter regions (E, E1, E2, E3, E4), Each of the semiconductor chips (LD) has a chip bottom side (RS) having at least two connection pads (AP); said at least two connection pads (AP) are configured to be in electrical contact with one single emitter region (E, E1, E2, E3, E4), and in top view, each of said at least two connection pads (AP) overlaps at least two emitter regions (E, E1, E2, E3, E4); The component (100) of claim 11.

17. Component (100) according to claim 16, wherein the component (100) comprises a plurality of resonators, the semiconductor chip (LD) and the emitter regions (E, E1, E2, E3, E4) being arranged side by side, and during operation of the component (100) the spectra of the individual emitter regions (E, E1, E2, E3, E4) overlap with a wavelength offset of 2 μm to 5 μm between the individual resonators, thereby achieving a spectral width of 10 nm ± 5 nm.

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