Semiconductor Device

Abstract

To suppress destruction of an internal element of a semiconductor device when ESD is applied.SOLUTION: When static electricity is applied to an I / O signal pad 25, a discharge path 50 is formed by a static protection mechanism. A gate switch circuit 110 is arranged corresponding to a protection transistor 101x having a drain electrically connected to the I / O signal pad 25. The gate switch circuit 110 electrically connects the gate of the protection transistor 101x to a first node NP1 whose potential is higher than the I / O GND line GL when the discharge path 50 is formed in a case in which static electricity is applied to the I / O signal pad 25.SELECTED DRAWING: Figure 18

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a protection function against ESD (Electro Static Discharge). [Background technology]

[0002] Conventionally, semiconductor devices are equipped with electrostatic protection circuits for protecting internal circuits from electrostatic discharge to input / output terminals from the outside. For example, Japanese Patent Application Laid-Open No. 2009-99641 (Patent Document 1) shows a circuit configuration in which an electrostatic protection circuit made of MOS (Metal Oxide Semiconductor) transistors is connected between an input / output line connected to an input / output terminal and a power supply line and a ground line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-99641 A Summary of the Invention [Problem to be solved by the invention]

[0004] As part of the operation check test of the semiconductor device, an electrostatic breakdown test (hereinafter referred to as "ESD test") is performed to check whether the ESD protection function described above operates normally. In the ESD test, the breakdown resistance of the semiconductor device is evaluated when an electric stress simulating ESD is applied to external terminals such as a power supply terminal, a GND terminal, and a signal input / output (I / O) terminal.

[0005] On the other hand, in recent years, the miniaturization of the manufacturing process of semiconductor devices has progressed, leading to a decrease in the breakdown voltage of transistors and an increase in the parasitic resistance of wiring. During ESD testing or exposure to electrostatic discharge (hereinafter referred to as "ESD application") in the semiconductor assembly process or the mounting process in electronic devices, a current (hereinafter referred to as "ESD current") flowing from an external terminal into the semiconductor is guided to another external terminal having a reference potential at the time of ESD application by the operation of an electrostatic protection circuit. At this time, if the parasitic wiring resistance of the ESD current path increases, the amount of voltage drop that occurs when the ESD current flows increases. As a result, there is a concern that a potential difference exceeding the breakdown voltage will be applied to an internal element (transistor) connected to the ESD current path at the time of ESD application.

[0006] The present disclosure is intended to solve the above-mentioned problems, and provides a semiconductor device capable of suppressing damage to internal elements when ESD is applied.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] According to one embodiment, a semiconductor device includes a signal pad, a GND pad, a plurality of drive transistors, and an electrostatic protection mechanism. The plurality of drive transistors are electrically connected between a power supply line and a GND line via a signal node electrically connected to the signal pad. The plurality of drive transistors include a transistor to be protected having a drain electrically connected to the signal pad. When an electric signal (e.g., static electricity) is applied to the signal pad with the GND pad having a reference potential, the electrostatic protection mechanism forms a discharge path from the signal pad to the GND pad. The electrostatic protection mechanism includes a gate switch circuit. The gate switch circuit controls an electrical connection destination of the gate of the transistor to be protected when the electric signal is applied. The gate switch circuit electrically connects the gate to a first node having a higher potential than the GND line when the discharge path is formed when the electric signal (static electricity) is applied. Effect of the Invention

[0009] According to one embodiment, damage to internal elements when ESD is applied can be suppressed. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating an overall configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 11 is a circuit diagram for explaining a problem that occurs when ESD is applied in an electrostatic protection mechanism according to a comparative example. [Diagram 3] 1 is a circuit diagram illustrating a multi-stage stack configuration of output circuits of a semiconductor device; [Figure 4] 4 is a circuit diagram for explaining a problem that occurs when ESD is applied in the case where an electrostatic protection mechanism according to a comparative example is applied to the output circuit shown in FIG. 3. [Diagram 5] 4 is a circuit diagram illustrating an electrostatic protection mechanism of the semiconductor device according to the first embodiment. FIG. [Figure 6] 6 is a table comparing potentials at various portions of the semiconductor device shown in FIG. 5 when ESD is applied; [Figure 7] 4 is an operational characteristic diagram of the electrostatic protection mechanism of the semiconductor device according to the first embodiment. FIG. [Figure 8] FIG. 11 is a circuit diagram illustrating an electrostatic protection mechanism of the semiconductor device according to the second embodiment. [Figure 9] FIG. 11 is a conceptual diagram illustrating an example of a layout of an I / O circuit of a semiconductor device according to a third embodiment. [Figure 10] FIG. 11 is a circuit diagram illustrating an example of a layout of an electrostatic protection mechanism in a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a circuit diagram illustrating an electrostatic protection mechanism of the semiconductor device according to the fourth embodiment. [Figure 12] FIG. 13 is a circuit diagram illustrating an electrostatic protection mechanism of the semiconductor device according to the fifth embodiment. [Figure 13] 13 is a table comparing potentials at various portions of the semiconductor device shown in FIG. 12 when ESD is applied. [Figure 14]13 is a diagram showing the operating characteristics of the electrostatic protection mechanism of the semiconductor device according to the fifth embodiment. FIG. [Figure 15] FIG. 13 is a circuit diagram illustrating an electrostatic protection mechanism of the semiconductor device according to the sixth embodiment. [Figure 16] 16 is a chart comparing potentials at various portions of the semiconductor device shown in FIG. 15 when ESD is applied. [Figure 17] FIG. 13 is a diagram showing the operating characteristics of the electrostatic protection mechanism of the semiconductor device according to the sixth embodiment. [Figure 18] 1 is a circuit diagram for explaining a comprehensive concept of an electrostatic protection mechanism of a semiconductor device according to an embodiment of the present invention; [Figure 19] FIG. 11 is a circuit diagram for explaining a comprehensive concept of an electrostatic protection mechanism of a semiconductor device according to a modified example of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and redundant explanations will not be repeated. In addition, in the drawings, configurations may be omitted or simplified for the sake of convenience.

[0012] [Embodiment 1] As shown in Fig. 1, the semiconductor device 10 according to the present embodiment includes a core region 20 and an I / O region 30 provided in the outer periphery region. In the core region 20, for example, a core logic configured as an ASIC (application specific integrated circuit) having a predetermined function, an analog circuit, etc. are arranged. Note that in Fig. 1, the I / O region 30 is provided over the entire outer periphery, and the core region 20 is arranged on the inner periphery side of the I / O region 30, but it is also possible to include a part of the outer periphery region in the core region 20.

[0013] The I / O region 30 includes an I / O cell 100 serving as a signal input / output interface, a power cell 200 for I / O power, a power cell 200G for I / OGND, a power cell 206 for core power, and a power cell 206G for core GND. The I / O cell 100 is electrically connected to a pad SP for signal input / output. The power cell 200 is electrically connected to a pad VP for I / O power, and the power cell 200G is electrically connected to a pad VG for I / OGND. Furthermore, the power cell 206 is electrically connected to a pad VPC for core power, and the power cell 206G is electrically connected to a pad VGC for core GND.

[0014] The I / O power supply voltage input to the pad VP is transmitted to the power supply line PL via the power supply cell 200. The I / O ground voltage (GND) input to the pad VP is transmitted to the GND line GL via the power supply cell 200G. The core power supply voltage input to the pad VPC is transmitted to the power supply line PLC via the power supply cell 206. The core ground voltage (GND) input to the pad VGC is transmitted to the GND line GLC via the power supply cell 206G.

[0015] The power supply lines PLC, PL and the GND lines GLC, GL are arranged in the peripheral region and supply the power supply voltage and ground voltage (GND) to each circuit inside the semiconductor device 10. The power supply voltage and GND for the core are supplied to the core region 20. On the other hand, the power supply voltage and ground voltage (GND) for the I / O are not supplied to the core region 20.

[0016] Incidentally, a plurality of power supply voltages of different voltage levels may be input to the semiconductor device 10. In this case, a plurality of power supply lines PL, PLC are provided, each electrically connected to a different pad VP, VPC. For example, a pad and a power supply line for a power supply dedicated to the I / O cell are provided separately from a pad and a power supply cell for a power supply supplied to the core region. Furthermore, a part of an electrostatic protection circuit, which will be described later, is disposed in the power supply cell 200. In addition, from the viewpoint of preventing noise propagation, a GND pad VG and a GND line GL for supplying a ground voltage (GND) to the I / O cell 200 may be electrically separated from a GND pad VGC and a GND line GLC for supplying a ground voltage (GND) to the core region 20.

[0017] During an ESD test of the semiconductor device 10, some of the pads among the I / OGND pad VG, the I / O power supply pad VP, the core power supply pad VPC, and the core GND pad VGC are grounded as reference terminals having a reference potential during the test. Furthermore, in this state, an electric signal simulating ESD is applied from a test device external to the semiconductor device 10 to the pad SP or the remaining pads not set as reference terminals among the I / OGND pad VG, the I / O power supply pad VP, the core power supply pad VPC, and the core GND pad VGC, to evaluate the breakdown resistance of the semiconductor device 10.

[0018] As described above, the time of ESD application in this disclosure includes a case where an electric signal simulating ESD is intentionally applied to a pad in an ESD test, as well as a case where unintentional ESD is applied to a pad as an electric signal in a semiconductor assembly process, a mounting process in an electronic device, etc. By appropriately operating an electrostatic protection mechanism described in detail below against such application of an electric signal due to static electricity, i.e., ESD application, damage to internal elements (typically, transistors) can be suppressed.

[0019] <Comparative example of electrostatic protection mechanism> Next, problems that may occur when ESD is applied to the semiconductor device 10 to which a microfabrication process is applied will be described through a description of a comparative example of an electrostatic protection mechanism.

[0020] 2, a P-type transistor 101 and an N-type transistor 102 that configure an output circuit are arranged in an I / O cell 100 of the semiconductor device 10. The transistor 101 is electrically connected between a power supply line PL and a signal node Nio that is electrically connected to an I / O signal pad 205. The transistor 102 is electrically connected between the signal node Nio and a GND line GL for I / O (hereinafter also referred to as an I / O GND line GL).

[0021] In this disclosure, the term "electrically connected" is not limited to a direct connection by wiring, but also includes an electrical connection that allows a current path to be formed via other elements not shown, such as a resistive element. For example, in Fig. 2, the electrical connection between the drain and source of the transistor 102 and the signal node Nio and the I / O GND line GL is shown to be realized by directly connecting the source and drain to the signal node Nio and the I / O GND line GL by wiring. However, the drain and source of the transistor 102 may be connected to the signal node Nio and the I / O GND line GL via a resistive element not shown.

[0022] The power supply line PL is electrically connected to a power supply pad 202, and the I / O GND line GL is electrically connected to a GND pad 201. The GND pad 201 and the power supply pad 202 are equivalent to the I / O GND pad VG and the I / O power supply pad VP, respectively, shown in Fig. 1. The I / O signal pad 205 is equivalent to the pad SP shown in Fig. 1.

[0023] An output signal of the output buffer 21 is input to the gates of the transistors 101 and 102. When the semiconductor device 10 is in operation, the transistor 101 or 102 is turned on by the output signal of the output buffer 21. As a result, one of an H (high) level voltage (VDD) and an L (low) level voltage (GND) is selectively output to the I / O signal pad 205.

[0024] The electrostatic protection mechanism according to the comparative example is realized by protection diodes 105 and 106 arranged in the I / O cell 100 and an ESD circuit 210 arranged in the power cell 200. The protection diode 105 is electrically connected between the signal node Nio and the power line PL with the forward direction being the direction from the signal node Nio to the power line PL. The protection diode 106 is electrically connected between the signal node Nio and the I / OGND line GL with the forward direction being the direction from the I / OGND line GL to the signal node Nio.

[0025] The ESD circuit 210 is disposed between a power supply line PL electrically connected to the power supply pad 201 and an I / O GND line GL. The ESD circuit 210 is a general term for any known configuration, but is typically configured to include an N-type transistor that autonomously turns on in response to the occurrence of an ESD current.

[0026] When ESD is applied to the I / O signal pad 205 while the I / O GND pad 201 has a reference potential, the protection diode 105 and the ESD circuit 210 operate in response, and a discharge path 50 for the applied ESD is formed inside the semiconductor device 10. In the discharge path 50, an ESD current Iesd flows through the path of the I / O signal pad 205-protection diode 105-power line PL-ESD circuit 210-I / O GND line GL-GND pad 201.

[0027] When ESD is applied, an ESD current Iesd flows through the discharge path 50, causing a potential difference Vdio between the signal node Nio and the power supply line PL, and a potential difference Vesd between the power supply line PL and the I / OGND line GL.

[0028] The potential difference Vdio is represented by the sum of the forward voltage of the protection diode 105 and the voltage drop caused by the wiring parasitic resistance for electrically connecting the protection diode 105 between the signal node Nio and the power supply line PL.

[0029] Similarly, the potential difference Vesd is represented by the sum of the voltage drop that occurs when the ESD circuit 210 is activated and the voltage drop that occurs due to the parasitic resistance of the wiring for electrically connecting the ESD circuit 210 between the power supply line PL and the I / OGND line GL.

[0030] As a result, the voltage Vio of the signal node Nio when ESD is applied is represented by the sum of the above-mentioned potential differences Vesd and Vdio (Vio=Vdio+Vesd). On the other hand, the source of the transistor 102 is electrically connected to the I / O GND line GL, which is electrically connected to the GND pad 201 having the reference potential when ESD is applied, and therefore the potential is 0 [V].

[0031] As a result, when ESD is applied, the potential difference Vstd2 applied between the drain and source of the transistor 102 is equivalent to the voltage Vio of the signal node Nio. Also, when the potential of the gate of the transistor 102 becomes 0 [V] when ESD is applied, the potential difference Vsdt1 applied between the gate and drain of the transistor 102 is equivalent to the voltage Vio of the signal node Nio. On the other hand, in advanced processes where miniaturization is progressing, as described above, the above-mentioned voltage Vio increases due to an increase in the wiring parasitic resistance in the discharge path 50 formed when ESD is applied, and the withstand voltage of each transistor also decreases. For these reasons, there is a concern that a potential difference exceeding the withstand voltage will be applied between the gate and drain and between the drain and source of the transistor 102 when ESD is applied.

[0032] In order to ensure a sufficient withstand voltage between the drain and source of the transistor 102, it is possible to adopt a multi-stage vertical stack configuration in which a plurality of transistors are electrically connected in series.

[0033] FIG. 3 shows a circuit diagram illustrating a multi-stage stacked configuration of output circuits of a semiconductor device. 3, in the multi-stage stacked output circuit, a plurality of P-type transistors 101x and 101y are electrically connected in series between the power supply line PL and the signal node Nio. Similarly, a plurality of N-type transistors 102x and 102y are electrically connected in series between the signal node Nio and the I / O GND line GL.

[0034] For example, when the operating voltage of each transistor is 1.8 [V], while the power supply voltage VDD1 supplied to the power supply line PL is 3.3 [V], a multi-stage vertical stack configuration using two transistors can be applied to the output circuit as shown in the example of Figure 3. This makes it possible to reduce the potential difference applied to one transistor stage to about the operating voltage.

[0035] In the multi-stage stacked output circuit, some of the transistors electrically connected in series are fixed to the on state, while the on / off state of the remaining transistors is controlled according to the output signal from the output buffer 21 (FIG. 2). This allows the I / O signal pad 205 to selectively output either the H level (VDD1) or the L level (GND).

[0036] 3, the transistors 101x and 102x, whose drains are electrically connected to the signal node Nio, are fixed on. For this reason, the gate of the transistor 101x needs to be fixedly set to the ground voltage GND, and the gate of the transistor 102x needs to be fixedly set to the power supply voltage VDD2 (1.8 [V]).

[0037] Therefore, in order to stably fix the transistor 102x to the on state when the semiconductor device 10 is started (powered on), it is necessary to quickly supply the power supply voltage VDD2 to the gate. At this time, in order to accommodate a usage mode in which the power supply voltage VDD1 is input to the semiconductor device 10 before the power supply voltage VDD2, it is conceivable to generate the power supply voltage VDD2 from the power supply voltage VDD1.

[0038] 3, for example, a reference voltage VREF equivalent to a power supply voltage VDD2 (1.8 [V]) is generated by dividing a power supply voltage VDD1 (3.3 [V]) by resistor elements R1 and R2. Furthermore, a gate switch circuit 110 is disposed for the gate of the transistor 102x. The gate switch circuit 110 selectively supplies one of the power supply voltage VDD2 supplied from outside the semiconductor device 10 and the reference voltage VREF generated by voltage division to the gate of the transistor 102x in response to a control signal SL.

[0039] This makes it possible to stabilize the operation of the output circuit at the start of the semiconductor device 10 even in a power start-up sequence in which the power supply voltage VDD2 is supplied later than the power supply voltage VDD1. That is, the degree of freedom of the power start-up sequence for the semiconductor device 10 is improved.

[0040] FIG. 4 shows a circuit diagram for explaining problems that arise when ESD is applied when an electrostatic protection mechanism similar to that shown in FIG. 2 is applied to the multi-stage stacked output circuit shown in FIG.

[0041] 4, power supply voltage VDD1 is supplied by a power supply line PL1, while power supply voltage VDD2 is supplied by a power supply line PL2. Power supply lines PL1 and PL2 are electrically connected to I / O power supply pad 202 and power supply pad 203, respectively. Power supply pad 202 to which VDD1 is input and power supply pad 203 to which VDD2 is input are included in I / O power supply pad SP in Fig. 1. Furthermore, a reference voltage VREF obtained by dividing power supply voltage VDD1 by resistor elements R1 and R2 is supplied by a reference voltage line PLr.

[0042] As shown in Fig. 4, the protection diodes 105 and 106 and the ESD circuit 210 similar to those in Fig. 2 are electrically connected to the power supply line PL1, the signal node Nio, and the I / OGND line GL. In the configuration in Fig. 4 as well, the GND pad 201 serves as a terminal having a reference potential, and when ESD is applied to the signal pad 205 and an ESD current is generated, a voltage Vio (Vio = Vesd + Vdio) similar to that in Fig. 2 is generated at the signal node Nio. However, since the ESD circuit 210 is also configured with transistors vertically stacked in multiple stages like the output circuit, it has a low ability to suppress the potential difference when the ESD current flows, and the potential difference Vesd generated in the ESD circuit 210 is larger than that in the configuration in Fig. 2.

[0043] At this time, in the transistor 102x, the potential difference applied between the drain and source is the voltage Vio shared by the transistors 102x and 102y, and is therefore mitigated to half that of the transistor 102 in Fig. 2. In other words, by configuring the output circuit in a multi-stage vertical stack configuration, the potential difference applied between the drain and source of each transistor when ESD is applied is mitigated.

[0044] When ESD is applied to the signal pad 205 while the I / O GND pad 201G has a reference potential, the power line PL2 is not involved in the ESD discharge path 50 accompanying the application of ESD. Therefore, the power line PL2 is transmitted to the power line PL2 via the ESD circuit 211 electrically connected between the power line PL2 and the I / O GND line GL, which is the potential of 0 [V]. For this reason, when the gate switch circuit 110 electrically connects the gate of the transistor 102x to the power line PL2 during the application of ESD, there is a concern that a potential difference equivalent to the voltage Vio of the signal node Nio is applied between the drain and gate of the transistor 102x. In this way, even if the output circuit is configured in a multi-stage vertical stacked configuration, the potential difference applied between the drain and gate during the application of ESD is not alleviated in the transistor having a drain electrically connected to the I / O signal pad 205. That is, it is understood that the application of a microfabrication process increases the risk of destruction of the gate oxide film of the transistor 102x in the semiconductor device 10.

[0045] <Explanation of electrostatic protection mechanism according to embodiment 1> 5, the output circuit of the semiconductor device 10 according to the first embodiment is configured similarly to that of FIG 4, and includes P-type transistors 101x and 101y and N-type transistors 102x and 102y. That is, the transistors 101x, 101y, 102x, and 102y are electrically connected in series between the power supply line PL1 and the I / O GND line GL via the signal node Nio, and correspond to one example of "plurality of drive transistors."

[0046] In particular, the P-type transistors 101x and 101y correspond to "plurality of first transistors," and the N-type transistors 102x and 102y correspond to "plurality of second transistors." Also, among the transistors 101x, 101y, 102x, and 102y, the transistors 101x and 102x having drains connected to the signal node Nio correspond to one embodiment of the "transistor to be protected." In particular, the transistor 101x corresponds to the "first transistor to be protected," and the transistor 102x corresponds to the "second transistor to be protected."

[0047] The semiconductor device 10 according to the first embodiment includes an I / O GND pad 201, a core GND pad 201G (hereinafter simply referred to as a "core GND pad 201G"), a power supply pad 202 to which a power supply voltage VDD1 is supplied, and a power supply pad 203 to which a power supply voltage VDD2 is supplied. The power supply voltage VDD2 is equivalent to the operating voltage VDD of each transistor. For example, the power supply voltage VDD1 is twice the power supply voltage VDD2. The core GND pad 201G is equivalent to the pad VGC for the core GND shown in FIG. 1, and is electrically connected to the core GND line GLC for the core region 20. The I / O GND line GL and the core GND line GLC are electrically connected via diodes 107 and 108 to prevent noise propagation between the GNDs. The diodes also function as an electrostatic protection mechanism, as described later.

[0048] The power supply line PL1 is electrically connected to the power supply pad 202 and transmits the power supply voltage VDD1. The power supply line PL2 is electrically connected to the power supply pad 203 and transmits the power supply voltage VDD2. As in Fig. 4, the resistance elements R1 and R2 divide the power supply voltage VDD1 to generate a reference voltage VREF equivalent to the power supply voltage VDD2. In this way, one embodiment of a "voltage dividing circuit" can be configured by the resistance elements R1 and R2.

[0049] The voltage division ratio r (r<1) of the resistor elements R1 and R2 is expressed as r=VDD2 / VDD1 (when VDD1=2·VDD2, r=0.5). The reference voltage line PLr transmits the reference voltage VREF.

[0050] The gate of the P-type transistor 101x is fixed to the ground voltage GND by, for example, being electrically connected to an I / OGND line GL. Meanwhile, a gate switch circuit 110n is provided corresponding to the N-type transistor 102x. The gate switch circuit 110n controls an electrical connection destination (hereinafter also simply referred to as a "gate connection destination") of a gate node Ngn corresponding to the gate of the transistor 102x. Specifically, the gate switch circuit 110n selectively electrically connects one of a power supply line PL2 (power supply voltage VDD1) and a reference voltage line PLr (reference voltage VREF) to the gate node Ngn according to the voltage level (H / L) of a control signal SL.

[0051] The switch control circuit 130 generates a control signal SL for controlling the gate switch circuit 110n during operation of the semiconductor device 10. For example, under a power startup sequence in which the power supply voltage VDD1 is supplied before the power supply voltage VDD2, the switch control circuit 130 sets the control signal SL (for example, H level) during startup of the semiconductor device 10 so as to electrically connect the reference voltage line PLr to the gate node Ngn. After that, after the timing at which the power supply voltage VDD2 is supplied, the switch control circuit 130 inverts the control signal SL (for example, L level) so as to electrically connect the power supply line PL2 to the gate node Ngn. Hereinafter, in this embodiment, the operation of the semiconductor device 10 refers to a state in which a predetermined power supply voltage is supplied to the power supply lines (PL1, PL2), including the execution period of the power supply startup sequence.

[0052] In the semiconductor device 10 according to the first embodiment, the electrostatic protection mechanism 300 includes protection diodes 105 and 106, ESD circuits 210 and 211, diodes 107 and 108, and an N-type transistor 115n. Furthermore, the gate switch circuit 110 used during operation of the semiconductor device 10 functions as a part of the electrostatic protection mechanism 300 by operating as described above when ESD is applied.

[0053] 5 shows a case where ESD is applied to the I / O signal pad 205 while the core GND pad 201G has a reference potential. That is, the I / O signal pad 205 corresponds to an embodiment of a "signal pad." Furthermore, the core GND pad 201G corresponds to an embodiment of a "GND pad." Moreover, the power supply line PL1 and the I / O GND line GL correspond to an embodiment of a "power supply line" and a "GND line."

[0054] The protection diodes 105 and 106 are electrically connected between the signal node Nio, which is electrically connected to the I / O signal pad 205, and the power supply line PL1 and the I / OGND line GL, respectively, as in Fig. 4. The ESD circuit 210 is electrically connected between the power supply line PL1 and the I / OGND line GL, as in Fig. 4. The ESD circuit 211 is disposed between the I / O power supply line PL2 and the I / OGND line GL, as in Fig. 4.

[0055] When ESD is applied, the protection diode 105 and the ESD circuit 210 operate, forming a discharge path 50 for the applied ESD inside the semiconductor device 10. In the discharge path 50, an ESD current Iesd flows through a path of the I / O signal pad 205-protection diode 105-power line PL1-ESD circuit 210-I / O GND line GL-core GND line GLC-core GND pad 201G. The ESD current Iesd generates a potential difference Vdio1 between the signal node Nio and the power line PL, and generates a potential difference Vesd between the power line PL and the I / O GND line GL.

[0056] The diode 108 is electrically connected between the I / O GND line GL and the core GND line GLC. The diode 107 is connected in anti-parallel to the diode 108. The cathode side of the diode 108 is electrically connected to the core GND pad 201G so as to pass an ESD current when ESD is applied. As a result, when an ESD current is generated in the discharge path 50, a potential difference Vdio2 is generated between the anode and cathode of the diodes 107 and 108.

[0057] As a result, when ESD is applied to the semiconductor device 10 according to the first embodiment, potentials shown in FIG. 6 are generated at various locations.

[0058] First, the potential of the I / OGND line GL rises by a potential difference Vdio2 caused by the conduction of the diode 108 with respect to the reference potential (0 [V]) of the core GND pad 201G that serves as the reference terminal when ESD is applied. Furthermore, the potential of the power supply line PL1 becomes higher than the potential of the I / OGND line GL by a potential difference Vesd that occurs in response to the operation of the ESD circuit 210.

[0059] Furthermore, the potential of the signal node Nio electrically connected to the I / O signal pad 205 becomes higher than the potential of the power supply line PL1 by a potential difference Vdio1 caused by the conduction of the protection diode 105.

[0060] In contrast, the potential of the power supply line PL2 in a floating state becomes approximately equal (Vdio2) to that of the I / OGND line GL. This is because the potential Vdio2 of the I / OGND line GL is transmitted to the power supply line PL2 via the ESD circuit 211. On the other hand, the potential of the reference voltage line PLr is represented by the sum of the potential difference Vdio2 generated by the conduction of the diode 108 and the product (r·Vesd) of the potential difference Vesd between the power supply line PL1 and the I / OGND line GL and the voltage division ratio r (r<1).

[0061] The potential difference Vstd1 applied between the gate and drain of the transistor 102x varies depending on the gate connection destination. Specifically, when the gate node Ngn is electrically connected to the power supply line PL2 during ESD application, Vstd1 becomes equivalent to the potential difference between the signal node Nio and the I / O GND pad 201 (Vstd1=Vdio1+Vesd). In contrast, when the gate node Ngn is electrically connected to the reference voltage line PLr, Vstd1 becomes Vstd1=Vdio1+(1-r)·Vesd, which is lower by r·Vesd compared to when it is connected to the power supply line PL2.

[0062] 5 again, the transistor 115n has a drain electrically connected to the transmission node of the control signal SL and a source electrically connected to the cathode of the diode 108. The gate of the transistor 115n is electrically connected to the anode of the diode 108. The transistor 115n and the diodes 107 and 108 are designed so that a potential difference Vio2 generated at the diode 108 is larger than a threshold voltage Vth of the transistor 115n.

[0063] As a result, when an ESD current occurs in the discharge path 50, the transistor 115n turns on in conjunction with the conduction of the diode 108, and the control signal SL can be forcibly set to the L level. That is, the diode 108 corresponds to an embodiment of a "current detection diode," and the transistor 115n corresponds to an embodiment of a "control transistor." The gate switch circuit 110n is configured to electrically connect the gate of the transistor 102x to the reference voltage line PLr when the control signal SL is at the L level.

[0064] Fig. 7 shows an operating characteristic diagram of the electrostatic protection mechanism 300 of the semiconductor device according to embodiment 1. The vertical axis of Fig. 7 shows the magnitude of the ESD current Iesd, and the horizontal axis shows the potential difference Vstd1 applied between the gate and drain of the transistor 102x.

[0065] When ESD is applied, the relationship between Vstd1 and Iesd when the gate node Ngn is electrically connected to the power supply line PL2 is shown by the dotted characteristic line CL1, while the relationship between Vstd1 and Iesd when the gate node Ngn is electrically connected to the reference voltage line PLr is shown by the solid characteristic line CL2.

[0066] 6, in the region where ESD current Iesd occurs, on characteristic line CL1, Vstd1=Vesd+Vdio1, while on characteristic line CL2, Vstd1=r·Vesd+Vdio1 (r<0). Therefore, it can be seen that between characteristic lines CL1 and CL2, for the same ESD current Iesd, the potential difference Vstd1 is reduced by r times (r·Vesd) the potential difference Vesd, which is the amount of voltage drop due to the ESD current.

[0067] In this way, in the semiconductor device 10 according to the first embodiment, the gate connection destination of the N-type transistor 102x (transistor to be protected) in the multi-stage stacked output circuit when ESD is applied can be appropriately controlled by the gate switch circuit 110n. This makes it possible to stably reduce the potential difference Vstd1 applied between the gate and drain of the N-type transistor 102x, thereby suppressing damage to the transistor 102x when ESD is applied.

[0068] Furthermore, the control signal SL (L level) of the gate switch circuit 110n when ESD is applied can be generated by the conduction of the diode 108 and the transistor 115n in response to the generation of the ESD current. This makes it possible to reduce the potential difference Vstd1 in the transistor 102x when ESD is applied without providing a new configuration for inputting the control signal SL from outside the semiconductor device 10.

[0069] [Embodiment 2] In the second embodiment, an electrostatic protection configuration for reducing the potential difference applied between the gate and drain of a P-type transistor constituting an output circuit of the semiconductor device 10 when ESD is applied will be described, similarly to the first embodiment.

[0070] 8, the electrostatic protection mechanism 301 of the semiconductor device 10 according to the second embodiment further includes a gate switch circuit 110p, as compared with the electrostatic protection mechanism 300 (FIG. 5) according to the first embodiment. The gate switch circuit 110p is provided in a P-type transistor 101x having a drain electrically connected to the signal node Nio.

[0071] The gate switch circuit 110p is electrically connected between a gate node Ngp electrically connected to the gate of the transistor 101x and the I / OGND line GL and the reference voltage line PLrp. The gate switch circuit 110p switches the gate connection destination according to the voltage level (H / L) of a control signal SL shared with the gate switch circuit 110n.

[0072] The gate switch circuit 110p is configured to electrically connect the gate node Ngp to the I / OGND line GL (ground voltage GND) when the control signal SL is at H level. This allows the transistor 101x to be fixed to ON during operation of the semiconductor device 10. The gate switch circuit 110p is different from the gate switch circuit 110n provided for the N-type transistor 102x and is additionally provided for applying ESD.

[0073] In contrast, when the control signal SL is forcibly set to the L level in response to the occurrence of an ESD current as described in the first embodiment, the gate node Ngp is configured to be electrically connected to the reference voltage line PLrp. A reference voltage VREFp obtained by dividing the power supply voltage VDD1 of the power supply line PL1 by the resistance elements R3 and R4 is transmitted to the reference voltage line PLrp. That is, an example of a "voltage dividing circuit" can be configured by the resistance elements R3 and R4. The other configuration in FIG. 8 is the same as that in FIG. 5, and therefore detailed description will not be repeated.

[0074] Among the multiple P-type transistors constituting the output circuit of the semiconductor device 10, the drain of the transistor 101x is connected to a signal node Nio that is electrically connected to the I / O signal pad 205. Therefore, when ESD is applied with the gate node Ngp electrically connected to the I / O GND line GL, a potential difference (Vdio1+Vesd) equivalent to that of the transistor 102x is applied between the gate and drain of the transistor 101x.

[0075] In contrast, when ESD is applied, by electrically connecting the gate node Ngp to the reference voltage line PLrp, the potential difference between the gate and drain of the P-type transistor 101x can be reduced similarly to the transistor 102x in embodiment 1. Furthermore, by controlling the operation of the gate switch circuit 110p as described above, the control signal SL, which is forcibly set to the L level (GND) in response to the occurrence of an ESD current, can be shared by the gate switch circuits 110n and 110p.

[0076] In this manner, in the semiconductor device according to the second embodiment, a gate switch circuit 110p for applying ESD is additionally disposed for the P-type transistor 101x in the multi-stage stacked output circuit. The gate switch circuit 110p appropriately controls the gate connection destination of the transistor 101x when ESD is applied, and the potential difference applied between the gate and drain of the transistor 101x can be stably reduced. This makes it possible to suppress destruction of the transistor 101x when ESD is applied.

[0077] Also, the reference voltage VREFp may be equal to the reference voltage VREF. In this case, the gate switch circuit 110p is configured to electrically connect the reference voltage line PLr in the first embodiment to the gate node Ngp when the control signal SL is at the L level. Then, the arrangement of the resistive elements R3 and R4 and the reference voltage line PLrp shown in FIG. 8 can be omitted.

[0078] [Embodiment 3] In the third embodiment, an example of the layout of the electrostatic protection mechanism according to the first or second embodiment with respect to a plurality of output circuits will be described.

[0079] FIG. 9 is a conceptual diagram illustrating an example of a layout of an I / O circuit of the semiconductor device 10 according to the third embodiment.

[0080] As shown in Fig. 9, a plurality of I / O blocks 15 are provided using at least a part of the peripheral region of the semiconductor device 10. In the example of Fig. 9, a configuration example in which four I / O blocks 15a to 15d are provided is shown, but the number of I / O blocks 15 is arbitrary. Furthermore, analog circuit blocks can be arranged in regions 17x to 17z between the I / O blocks 15.

[0081] Each I / O block 15 is provided with a plurality of I / O signal pads 205. Furthermore, an I / O circuit for inputting and outputting digital signals (H level / L level) to and from each I / O signal pad 205 is disposed corresponding to the I / O signal pad 205. The I / O circuit includes an output circuit configured by the transistors 101x, 101y, 102x, and 102y described in the first and second embodiments.

[0082] The switch control circuit 130 is shared among the multiple I / O blocks 15a to 15d. That is, in each I / O block 15, the gate switch circuits 110n and 110p are controlled by a common control signal SL. The control signal SL may be amplified by a repeater formed of an even number of inverters 16 and transmitted to an I / O block 15 that is distant from the switch control circuit 130.

[0083] FIG. 10 shows an example of the layout of electrostatic protection mechanisms in each I / O block 15. In FIG.

[0084] As shown in FIG. 10, in one I / O block 15, N circuit blocks 150 (N is an integer equal to or greater than 2) and M circuit blocks 160 (M is a natural number) are arranged.

[0085] A configuration equivalent to the above-mentioned I / O circuit is further arranged in the circuit block 150. Therefore, in the circuit block 150, of the configurations described in the first and second embodiments, an I / O signal pad 205, transistors 101x, 101y, 102x, and 102y constituting an output circuit, and protection diodes 105 and 106 are arranged.

[0086] The circuit blocks 160 are arranged for each different power supply voltage level. In the example of Fig. 10, two types of power supply voltages VDD1 and VDD2 are supplied to the semiconductor device 10, so M=2 and two circuit blocks 160 are arranged. In each of the two circuit blocks 160, an ESD circuit 210 electrically connected between the power supply line PL1 (power supply voltage VDD1) and the I / O GND line GL, and an ESD circuit 211 electrically connected between the power supply line PL2 (power supply voltage VDD2) and the I / O GND line GL are arranged. The circuit block 160 corresponds to the I / O power supply cell 200 shown in Fig. 1.

[0087] Furthermore, in each circuit block 160, a diode 108 that passes an ESD current from the I / O GND line GL to the core GND line GLC, and a diode 107 that is connected in anti-parallel to the diode 108 are arranged.

[0088] One circuit block 170 is disposed in one I / O block 15. Gate switch circuits 110p, 110n and a transistor 115n are disposed in the circuit block 170. That is, the gate switch circuits 110p, 110n and the transistor 115n are shared among N circuit blocks 150 in the same I / O block 15. That is, each circuit block 150 corresponds to an embodiment of an "input / output circuit," and the N circuit blocks 150 sharing a circuit block 170 correspond to an embodiment of a "plurality of circuit blocks."

[0089] As described above, the control signal SL of the gate switch circuits 110p, 110n is common to the multiple I / O blocks 15a to 15d. Therefore, in each I / O block 15, the gate node Ngn electrically connected to the gate of the transistor 102x in the M circuit blocks 150 is also common to the multiple I / O blocks 15a to 15d. Similarly, the gate node Ngp electrically connected to the gate of the transistor 101x in the M circuit blocks 150 is also common to the multiple I / O blocks 15a to 15d.

[0090] In this way, it is sufficient to dispose only one circuit block 170, which is configured by elements for reducing the gate-drain potential difference of the transistors 101x and 102x when ESD is applied, in each I / O block 15. That is, the gate switch circuits 110p and 110n and the transistor 115n can be shared among N circuit blocks 150, which need to be disposed for each of the multiple (N) I / O signal pads 205. Also, the transistor 115n, which electrically connects the generation node of the control signal SL to the core GND pad 201G in response to the occurrence of an ESD current, can be configured with a relatively small transistor size. For example, the transistor 115n can be configured with a gate width of about several (μm) to a dozen (μm).

[0091] In this way, according to the layout of the semiconductor device of embodiment 3, it is possible to reduce the area occupied by the circuit elements that are additionally arranged to suppress damage to the transistors 101x and 102x when ESD is applied, as described in embodiments 1 and 2.

[0092] [Embodiment 4] In the fourth embodiment, a modified example of forcibly setting the control signal of the gate switch circuit in response to the occurrence of an ESD current will be described.

[0093] As shown in FIG. 11, the electrostatic protection mechanism 302 of the semiconductor device of embodiment 4 differs from the electrostatic protection mechanism 300 (FIG. 5) of embodiment 1 in that it includes a P-type transistor 115p instead of the N-type transistor 115n.

[0094] The transistor 115p has a drain electrically connected to a transmission node of the control signal SL and a source electrically connected to a reference voltage line PLr (reference voltage VREF). The gate of the transistor 115p is electrically connected to a power supply line PL2. The other configurations in FIG. 8 are the same as those in FIG. 5, and therefore detailed description will not be repeated.

[0095] As described in FIG. 5 and FIG. 6, when the core GND pad 201G is set as the reference terminal and ESD is applied to the signal pad 205, the power supply line PL2 is in a floating state, and the potential of the I / O GND line GL is transmitted via the ESD circuit 211 (FIG. 4), and the potential becomes Vdio2. Meanwhile, in response to the occurrence of the ESD current Iesd, the diode 108 becomes conductive, and the potential of the reference voltage line PLr rises to Vdio2+r·Vesd. In response to this, the transistor 115p is turned on by the gate being at a low potential relative to the source, and the control signal SL is forcibly set to the H level (Vdio2+r·Vesd). That is, in the fourth embodiment, the transistor 115p corresponds to one example of the "control transistor". That is, a voltage (H level) equal to or higher than the power supply voltage VDD, which is the operating voltage of the transistors 101x, 101, 102x, and 102y, is transmitted from the transistor 115p to the gate switch circuit 110n.

[0096] Therefore, in the fourth embodiment, the gate switch circuit 110n is configured to electrically connect the gate of the transistor 102x to the reference voltage line PLr when the control signal SL is at H level, in contrast to the first embodiment. Also, the gate switch circuit 110n is configured to electrically connect the gate of the transistor 102x to the power supply line PL2 when the control signal SL is at L level, in contrast to the first embodiment.

[0097] During operation of the semiconductor device 10, the power supply voltage VDD2 is supplied to the power supply line PL2, and the reference voltage VREF equivalent to the power supply voltage VDD2 is also supplied to the reference voltage line PLr. Therefore, the gate and source of the transistor 115p are at substantially the same potential, and the transistor 115p is turned off. As a result, the gate switch circuit 110n switches the gate connection destination of the transistor 102x according to the control signal SL from the switch control circuit 130. In the fourth embodiment, the switch control circuit 130 is also configured to set the control signal SL to the L level during the period when the gate node Ngn should be electrically connected to the power supply line PL2. Conversely, the switch control circuit 130 sets the control signal SL to the H level during the period when the gate node Ngn should be electrically connected to the reference voltage line PLr.

[0098] In this way, in the semiconductor device according to the fourth embodiment, the voltage level of the control signal SL of the gate switch circuit 110n is forcibly set in response to the occurrence of an ESD current using a P-type transistor, thereby achieving the same effect as that of the first embodiment. That is, by appropriately controlling the gate connection destination of the transistor 102x when ESD is applied, it is possible to prevent the transistor 102x from being destroyed when ESD is applied.

[0099] 8 may be further disposed in the configuration of Fig. 11 to combine the fourth embodiment with the second embodiment. In this case, the gate switch circuit 110p is also configured to electrically connect the gate node Ngp to the reference voltage line PLrp or PLr when the control signal SL is at H level, contrary to the second embodiment. That is, when the second and fourth embodiments are combined, the gate switch circuit 110p is configured to electrically connect the gate node Ngp to the I / OGNDGL when the control signal SL is at L level.

[0100] It is also possible to apply the layout of the third embodiment to the fourth embodiment or a combination of the second and fourth embodiments. In this case, a P-type transistor 115p can be arranged in place of the N-type transistor 115n in the circuit block 170 of FIG.

[0101] [Embodiment 5] In the fifth embodiment, an electrostatic protection mechanism for output circuits in a multi-stage stack configuration in a semiconductor device with one type of power supply voltage will be described.

[0102] As shown in FIG. 12, in the semiconductor device 10 according to the fifth embodiment, the output circuit includes P-type transistors 101x and 101y and N-type transistors 102x and 102y, similar to those in the first embodiment (FIG. 5).

[0103] The electrostatic protection mechanism 303 of the semiconductor device according to the fourth embodiment includes protection diodes 105 and 106, an ESD circuit 210, an N-type transistor 115n, and diodes 107 and 108, which are arranged in the same manner as in the first embodiment (FIG. 5).

[0104] On the other hand, in the semiconductor device according to the fourth embodiment, a power supply voltage VDD1 equivalent to the operating voltage VDD (e.g., 1.8 [V]) of the transistors 101x, 101y, 102x, and 102y is supplied to the power supply line PL1 via the power supply pad 202. Therefore, the N-type transistor 102x having a drain electrically connected to the signal node Nio has its gate (gate node Ngn) electrically connected to the power supply line PL1, and is fixed to an on state.

[0105] Furthermore, the electrostatic protection mechanism 303 has a gate switch circuit 110p configured with an inverter 117. The gate switch circuit 110p (inverter 117) switches the gate connection destination of a P-type transistor 101x having a drain electrically connected to a signal node Nio between a power supply line PL1 and an I / O GND line GL.

[0106] An input node Ncnt of the inverter 117 is electrically connected to the drain of a transistor 115n and is also electrically connected to a power supply line PL1 via a pull-up resistor Rpl. As in the first embodiment (FIG. 5), the transistor 115n is turned on in response to conduction of the diode 108 due to the occurrence of an ESD current.

[0107] When the semiconductor device is not in operation or when ESD is not applied, the transistor 115n is turned off, and an H-level voltage (power supply voltage VDD1) is input to the inverter 117. Therefore, the inverter 117 electrically connects the gate node Ngp to the I / OGND line GL. This fixes the P-type transistor 101x to an ON state.

[0108] In contrast, when ESD is applied while the core GND pad 201G has the reference potential, an ESD current flows through the discharge path 50, and as a result, the transistor 115n is turned on, inputting a voltage of the L level (ground voltage GND) to the inverter 117. As a result, the inverter 117 electrically connects the gate node Ngp to the power supply line PL1. In this way, in the electrostatic protection mechanism 303 of the fourth embodiment, when ESD is applied, the gate connection destination of the P-type transistor 101x is switched from the I / O GND line GL to the power supply line PL1.

[0109] Furthermore, when ESD is applied while the core GND pad 201G has a reference potential, potential differences Vdio2, Vesd, and Vdio similar to those in the first embodiment (FIG. 5) are generated in the discharge path 50 of the ESD current. As a result, when ESD is applied to the semiconductor device 10 according to the fifth embodiment, potentials shown in FIG.

[0110] 13, the potential of the I / OGND line GL rises with respect to the reference potential (0 [V]) of the core GND pad 201G by a potential difference Vdio2 caused by the conduction of the diode 108. Furthermore, the potential of the power supply line PL1 becomes higher than the potential of the I / OGND line GL by a potential difference Vesd caused in response to the operation of the ESD circuit 210.

[0111] Furthermore, the potential of the signal node Nio (I / O signal pad 205) electrically connected to the drain of the transistor 101x becomes higher than the potential of the power line PL1 by a potential difference Vdio1 caused by the conduction of the protection diode 105.

[0112] Therefore, if the gate node Ngp remains electrically connected to the I / OGND line GL when ESD is applied, the potential difference Vstd1 applied between the gate and drain of the transistor 102x when an ESD current occurs will be (Vesd+Vdio1).

[0113] In contrast, the gate node Ngp is electrically connected to the power supply line PL1 by the inverter 117, so that the potential difference Vstd1 applied between the gate and drain of the transistor 102x is reduced to Vdio1 when an ESD current occurs.

[0114] Fig. 14 shows an operating characteristic diagram of the electrostatic protection mechanism 303 of the semiconductor device according to embodiment 5. The vertical and horizontal axes of Fig. 14 respectively show the magnitude of the ESD current Iesd and the potential difference Vstd1 applied between the gate and drain of the transistor 102x, similarly to Fig. 7.

[0115] When ESD is applied, the relationship between Vstd1 and Iesd when the gate node Ngp is electrically connected to the I / OGND line GL is shown by the dotted characteristic line CL3, while the relationship between Vstd1 and Iesd when the gate node Ngn is electrically connected to the power supply line PL1 is shown by the solid characteristic line CL4.

[0116] 13, in the region where the ESD current Iesd occurs, Vstd1=Vesd+Vdio1 on the characteristic line CL3, while Vstd1=Vesd on the characteristic line CL4. Therefore, it can be seen that, between the characteristic lines CL3 and CL4, for the same ESD current Iesd, the potential difference Vstd1 is reduced by the potential difference Vesd, which is the amount of voltage drop due to the ESD current.

[0117] In this way, in the semiconductor device 10 according to the fourth embodiment, by disposing the gate switch circuit 110p for applying ESD, it is possible to control the gate connection destination of the P-type transistor 101x in the multi-stage stacked output circuit when ESD is applied. This makes it possible to stably reduce the potential difference Vstd1 applied between the gate and drain of the P-type transistor 101x, thereby suppressing damage to the transistor 101x when ESD is applied.

[0118] It is also possible to apply the layout of the third embodiment to the fifth embodiment. In this case, in the circuit block 170 of Fig. 10, the inverter 117 shown in Fig. 12 is arranged as the gate switch circuit 110p, and the arrangement of the gate switch circuit 110n is omitted.

[0119] [Embodiment 6] In the sixth embodiment, a modified example of the gate connection destination by the gate switch circuit 110n in the first to fourth embodiments will be described.

[0120] As shown in FIG. 15, the electrostatic protection mechanism 304 of the semiconductor device according to the sixth embodiment differs from the electrostatic protection mechanism 300 (FIG. 5) of the first embodiment in that it includes a gate switch circuit 111n instead of the gate switch circuit 110n.

[0121] The gate switch circuit 111n has the function of the gate switch circuit 110n in response to the control signal SL, and further has the function of electrically connecting the gate node Ngn to the signal node Nio (the I / O signal pad 205) in response to the ESD control signal SLesd.

[0122] The ESD control signal SLesd is input to the gate switch circuit 111n in response to the transistor 115n being turned on due to the occurrence of an ESD current in the discharge path 50. That is, when the ESD control signal SLesd is set to the L level (ground voltage GND), the gate switch circuit 111n electrically connects the gate node Ngn to the signal node Nio. On the other hand, when the transistor 115n is off, the ESD control signal SLesd is fixed to the H level (power supply voltage VDD2) by the pull-up resistor Rpl.

[0123] When the ESD control signal SLesd is set to the H level, the gate switch circuit 111n, like the gate switch circuit 110n, selectively electrically connects one of the power supply line PL1 and the reference voltage line PLr to the gate node Ngn in response to the control signal SL from the switch control circuit 130. This makes it possible to fix the transistor 102x in the on state during operation of the semiconductor device 10.

[0124] Other configurations in Fig. 15 are similar to those in Fig. 5, and therefore detailed description will not be repeated. That is, in the electrostatic protection mechanism 304 according to the sixth embodiment, the protection diodes 105 and 106, the ESD circuit 210, the N-type transistor 115n, and the diodes 107 and 108 are arranged in the same manner as in the first embodiment (Fig. 5).

[0125] Therefore, when ESD is applied, potential differences Vdio2, Vesd, and Vdio similar to those in the first embodiment (FIG. 5) are generated in the discharge path 50 of the ESD current. As a result, when ESD is applied to the semiconductor device 10 according to the sixth embodiment, potentials shown in FIG.

[0126] First, the potential of the I / OGND line GL rises by a potential difference Vdio2 caused by the conduction of the diode 108 with respect to the reference potential (0 [V]) of the core GND pad 201G that was the reference when ESD was applied. Furthermore, the potential of the power supply line PL1 becomes higher than the potential of the I / OGND line GL by a potential difference Vesd that occurs in response to the operation of the ESD circuit 210.

[0127] Furthermore, the potential of the signal node Nio (I / O signal pad 205) electrically connected to the drain of the transistor 101x becomes higher than the potential of the power line PL1 by a potential difference Vdio1 caused by the conduction of the protection diode 105 (Vesd+Vdio1+Vdio2).

[0128] On the other hand, the gate node Ngn is electrically connected to the signal node Nio by the gate switch circuit 111n, and therefore has the same potential as the signal node Nio. As a result, the potential difference Vstd1 applied between the gate and drain of the transistor 102x can be set to 0.

[0129] Fig. 17 shows an operating characteristic diagram of the electrostatic protection mechanism 304 of the semiconductor device according to embodiment 6. The vertical and horizontal axes of Fig. 17 respectively show the magnitude of the ESD current Iesd and the potential difference Vstd1 applied between the gate and drain of the transistor 102x, similarly to Fig. 7.

[0130] When ESD is applied, the relationship between Vstd1 and Iesd when the gate node Ngp is electrically connected to the power supply line PL2 outside the path of the ESD current is shown by the characteristic line CL1 (dotted line) similar to Fig. 7. On the other hand, the relationship between Vstd1 and Iesd when the gate node Ngn is electrically connected to the signal node Nio (I / O signal pad 205) is shown by the characteristic line CL5, which is represented by a solid line.

[0131] In the region where the ESD current Iesd occurs, as described in the first embodiment, on the characteristic line CL1, Vstd1=Vesd+Vdio1, whereas on the characteristic line CL5, Vstd1=0.

[0132] In this manner, in the semiconductor device 10 according to the sixth embodiment, the gate connection destination when ESD is applied can be controlled to the signal node Nio by the arrangement of the gate switch circuit 111n. This makes it possible to stably reduce the potential difference Vstd1 applied between the gate and drain of the transistor 102x in the output circuit having a multi-stage vertical stack configuration, thereby suppressing damage to the transistor 102x when ESD is applied.

[0133] In the sixth embodiment, a resistor or diode may be inserted into the connection path between the signal node Nio and the gate node Ngn by the gate switch circuit 111n. In this case, the diode is disposed such that the anode is electrically connected to the signal node Nio. That is, the signal node Nio or a node coupled to the signal node Nio via a resistor or a diode in a conductive state is set as the gate connection destination when ESD is applied.

[0134] Moreover, it is possible to combine the embodiment 2 with the embodiment 6. That is, it is also possible to additionally arrange a gate switch circuit 111p (not shown) for electrically connecting the gate node Ngp to the signal node Nio when ESD is applied to the configuration of FIG.

[0135] Alternatively, as in the fourth embodiment, a P-type transistor 115p similar to that in FIG. 11 may be disposed instead of the N-type transistor 115n to generate the ESD control signal SLesd. In this case, the gate switch circuits 111n and 111p are configured to electrically connect the gate nodes Ngn and Ngp to the signal node Nio when the ESD control signal SLesd is at H level (power supply voltage VDD2). Furthermore, instead of the pull-up resistor Rpl in FIG. 15, a pull-down resistor (not shown) is disposed to fix the ESD control signal SLesd to L level when the transistor 115p is off.

[0136] It is also possible to apply the layout of the third embodiment to the semiconductor device of the sixth embodiment. In this case, the gate switch circuits 111n and 111p and the pull-up resistor Rpl (or the pull-down resistor) can be arranged in the circuit block 170 of FIG.

[0137] The overall concept of the electrostatic protection mechanism of the semiconductor device according to the present embodiment described above is shown in the circuit diagram of FIG.

[0138] As shown in FIG. 18 , it can be seen that the electrostatic protection mechanism of the semiconductor device according to this embodiment includes protection diodes 105 and 106, an ESD circuit 210, a gate switch circuit 110 that controls the gate connection destination of the transistor to be protected when ESD is applied, and a switch control mechanism 120 that controls the gate switch circuit 110.

[0139] The gate switch circuit 110 includes the gate switch circuits 110n, 110p, 111n, and 111p described in the embodiments 1 to 6. The gate switch circuit 110 is provided corresponding to at least one of the transistors 101x and 102x having a drain electrically connected to the I / O signal pad 205 (signal node Nio) among a plurality of transistors constituting an output circuit of the semiconductor device.

[0140] 18 shows an example of a configuration in which the gate switch circuit 110 is provided only for the transistor 102x. Alternatively, unlike in FIG 18, it is also possible to provide a configuration in which the gate switch circuit 110 is provided only for the transistor 101x, or for each of the transistors 101x and 102x. As described above, since the gate switch circuit 110 is used for the N-type transistor 101x during operation of the semiconductor device 10, there is no need to additionally provide the gate switch circuit 110 for when ESD is applied.

[0141] The gate switch circuit 110 electrically connects the gate node Ngn or Ngp to a first node NP1, thereby reducing the potential difference applied between the gate and drain of the transistor 101x or 102x when ESD is applied. The first node NP1 includes the reference voltage lines PLr, PLrp in the first to fourth embodiments, the power supply line PL1 in the fifth embodiment, and the signal node Nio or a node coupled to the signal node Nio via a resistor element or a diode in a conductive state in the sixth embodiment. That is, the first node NP1 comprehensively indicates a node that becomes at a higher potential than the I / OGND line GL in response to the occurrence of an ESD current in the discharge path 50.

[0142] In the first to sixth embodiments, an electrostatic protection mechanism for a plurality of transistors constituting an output circuit having a multi-stage stack configuration suitable for miniaturized transistors has been described. For this reason, the gate switch circuit 110 electrically connects the gate node Ngn (Ngp) to the second node NP2 that supplies a gate voltage for turning on the transistors 101x and 102x during operation of the semiconductor device. The second node NP2 includes a power supply line PL2 (embodiments 1 to 4) for the transistor 102x and an I / OGND line GL (embodiments 2 and 5) for the transistor 101x. As described above, the power supply line PL2 supplies the operating voltage VDD of the transistors 101x, 101y, 102x, and 102y. From the above description, it can be understood that the second node NP2 is not necessarily included in the path (discharge path 50) of the ESD current.

[0143] The switch control mechanism 120 can be configured with an N-type transistor 115n (FIG. 5, etc.) or a P-type transistor 115p (FIG. 11) and a diode 108. Note that the switch control mechanism 120 is not limited to the exemplified configuration and can adopt any configuration as long as it can control the gate switch circuit 110 (110n, 110p, 111n, 111p) in the same manner as described in the first to sixth embodiments. With this configuration, it is possible to control the gate switch circuit 110 without inputting a signal from outside the semiconductor device 10 when ESD is applied.

[0144] In the above, in this embodiment, the application of the electrostatic protection mechanism to an output circuit configured by connecting two P-type and two N-type transistors (drive transistors) in series has been described. However, the electrostatic protection mechanism according to this embodiment can also be applied to an output circuit configured by connecting three or more P-type and three or more N-type transistors (drive transistors) in series. Even in such a configuration, the potential difference between the drain and gate becomes maximum when ESD is applied in a transistor (protected transistor) having a drain connected to the signal node Nio. Therefore, by arranging the gate switch circuit 110 for at least a part or all of the protection transistor, it is possible to suppress the destruction of the transistor when ESD is applied.

[0145] Furthermore, the electrostatic protection mechanism of the semiconductor device according to this embodiment can also be applied to a semiconductor device having a single-stage output circuit composed of one P-type and one N-type transistor.

[0146] As shown in Fig. 19, the single-stage output circuit includes a P-type transistor 101 and an N-type transistor 102, similar to those in Fig. 2. That is, in the modified example of Fig. 19, the transistors 101 and 102 correspond to one embodiment of "plurality of driving transistors". In particular, the P-type transistor 101 corresponds to the "first transistor" and the "transistor to be protected". Similarly, the N-type transistor 102 corresponds to the "second transistor" and the "transistor to be protected".

[0147] 19, the electrostatic protection mechanism of the semiconductor device according to this embodiment also includes protection diodes 105 and 106, an ESD circuit 210, a gate switch circuit 110 that controls the gate connection destination of the transistor to be protected when ESD is applied, and a switch control mechanism 120 similar to that in FIG.

[0148] 19, each of the transistors 101 and 102 has a drain electrically connected to the I / O signal pad 205 (signal node Nio). Therefore, the gate switch circuit 110 is provided corresponding to at least one of the transistors 101 and 102. FIG. 19 also shows, as an example, a configuration in which the gate switch circuit 110 is provided only for the transistor 102. Alternatively, the gate switch circuit 110 may be provided only for the transistor 101, or for each of the transistors 101 and 102.

[0149] The gate switch circuit 110 electrically connects the gate node Ngn or Ngp to the first node NP1, thereby reducing the potential difference applied between the gate and drain of the transistor 101 or 102 when ESD is applied. In the modification of Fig. 19, the first node NP1 includes the power supply line PL1 (embodiment 4) and the signal node Nio in embodiment 6, or a node coupled to the signal node Nio via a resistor element or a diode in a conductive state.

[0150] 19 is controlled to electrically connect the gate node Ngn (Ngp) to the output node of the output buffer 21 (FIG. 1) except when ESD is applied, including when the semiconductor device is in operation. This makes it possible to selectively output one of an H-level voltage and an L-level voltage to the I / O signal pad 205 in accordance with the output signal of the output buffer 21 when the semiconductor device 10 is in operation.

[0151] The output node of the output buffer 21 is not usually included in the path of the ESD current (discharge path 50). Therefore, by controlling the output destination of the gate node Ngn (Ngp) when ESD is applied by the gate switch circuit 110, it is possible to reduce the potential difference applied between the gate and drain of the transistor 101 or 102 when ESD is applied. As a result, even for the transistors 101 and 102 constituting a single-stage output circuit, it is possible to suppress damage when ESD is applied by applying the electrostatic protection mechanism according to this embodiment.

[0152] With regard to the multiple embodiments described above, we would like to confirm that it is intended from the beginning of the application that the configurations described in each embodiment may be appropriately combined, including combinations not mentioned in the specification, to the extent that no inconsistencies or contradictions arise.

[0153] While the present disclosure has been specifically described above based on the embodiment, it goes without saying that the present disclosure is not limited to the embodiment and can be modified in various ways without departing from the gist of the present disclosure. [Explanation of symbols]

[0154] 10 semiconductor device, 15, 15a to 15d I / O block, 16 repeater, 17x to 17z area, 20 core area, 21 output buffer, 30 I / O area, 50 discharge path, 100 I / O cell, 101, 101x, 101y, 102, 102x, 102y transistor (drive transistor), 115n, 115p transistor (control transistor), 105, 106 protection diode, 107, 108 diode, 110, 110n, 110p, 111n, 111p gate switch circuit, 117 inverter, 120 switch control mechanism, 130 switch control circuit, 150, 160, 170 circuit block, 200, 200G power cell (for I / O), 201 GND pad (for I / O), 201G GND pad (for core), 202, 203 power pad, 205 signal pad, 206, 206G power cell (for core), 210, 211 ESD circuit, 300 to 304 electrostatic protection mechanism, GL I / O GND line, GLC core GND line, Ngn, Ngp gate node, Nio signal node, PL, PL1, PL2 power line (for I / O), PLC power line (for core), PLr, PLrp reference voltage line, R1 to R4 resistive element, Rpl pull-up resistor, SL, SLesd control signal (gate switch circuit), VDD1, VDD2 power supply voltage, VP, VPC pad (power supply voltage), VG, VGC pad (GND), VREF, VREFp reference voltage.

Claims

1. A signal pad; A GND pad; a plurality of drive transistors electrically connected between a power supply line and a GND line via a signal node electrically connected to the signal pad; an electrostatic protection mechanism for forming a discharge path from the signal pad to the GND pad when an electric signal is applied to the signal pad; The plurality of driving transistors include a protected transistor having a drain electrically connected to the signal pad; The electrostatic protection mechanism includes: a gate switch circuit for controlling an electrical connection destination of a gate of the protection target transistor when the electrical signal is applied; The gate switch circuit electrically connects the gate to a first node that has a higher potential than the GND line when the discharge path is formed during application of the electrical signal.

2. a first power supply voltage higher than an operating voltage of each of the drive transistors is supplied to the power supply line; The semiconductor device includes: a voltage divider circuit for resistively dividing the first power supply voltage and outputting a second power supply voltage equivalent to the operating voltage to a reference voltage line; 2. The semiconductor device according to claim 1, wherein said first node includes said reference voltage line.

3. a power supply voltage equivalent to an operating voltage of each of the drive transistors is supplied to the power supply line; 2. The semiconductor device according to claim 1, wherein said first node includes said power supply line.

4. 2. The semiconductor device according to claim 1, wherein said first node includes said signal node or a node electrically connected to said signal node via a resistive element or a diode in a conductive state.

5. The electrostatic protection mechanism includes: a switch control mechanism for outputting a predetermined voltage to the gate switch circuit in response to the formation of the discharge path; 2. The semiconductor device according to claim 1, wherein said gate switch circuit operates to electrically connect said gate of said transistor to be protected to said first node when said predetermined voltage is input.

6. The switch control mechanism includes: a current sensing diode arranged to conduct when a current is generated in the discharge path; 6. The semiconductor device according to claim 5, further comprising a control transistor arranged to transmit said predetermined voltage to said gate switch circuit by turning on in response to conduction of said current sensing diode.

7. 7. The semiconductor device according to claim 6, wherein said predetermined voltage is a ground voltage.

8. 7. The semiconductor device according to claim 6, wherein said predetermined voltage is a power supply voltage equal to or higher than an operating voltage of each of said drive transistors.

9. The plurality of driving transistors include a plurality of first transistors electrically connected in series between the power supply line and the signal node; a plurality of second transistors electrically connected in series between the signal node and the GND line; 2. The semiconductor device according to claim 1, wherein said gate switch circuit electrically connects said gate to a second node which supplies a gate voltage for turning on said transistor to be protected when said semiconductor device is in operation.

10. 10. The semiconductor device according to claim 9, wherein the gate switch circuit is arranged corresponding to each of a first transistor to be protected among the plurality of first transistors, the first transistor having a drain electrically connected to the signal pad, and a second transistor to be protected among the plurality of second transistors, the second transistor having a drain electrically connected to the signal pad.

11. The semiconductor device includes: A plurality of input / output circuits are provided, each of the plurality of input / output circuits includes a set of the plurality of drive transistors and the signal pad; the gate switch circuit is shared among N input / output circuits (N: an integer of 2 or more) among the plurality of input / output circuits, 10. The semiconductor device according to claim 9, wherein in said N input / output circuits, said gates of said N transistors to be protected which share said gate switch circuit are electrically connected to each other.

12. a switch control mechanism for outputting a predetermined voltage to the gate switch circuit in response to the formation of the discharge path; the gate switch circuit operates to electrically connect the gate of the protection target transistor to the first node when the predetermined voltage is input; 12. The semiconductor device according to claim 11, wherein said gate switch circuit and said switch control mechanism are shared among said N input / output circuits.

13. The plurality of driving transistors include a first transistor electrically connected between the power supply line and the signal node; a second transistor electrically connected between the signal node and the GND line; The semiconductor device includes: an output buffer for generating an output signal from the signal pad during operation of the semiconductor device; 2. The semiconductor device according to claim 1, wherein said gate switch circuit electrically connects an output node of said output buffer to said gate when said semiconductor device is in operation.

14. 14. The semiconductor device according to claim 13, wherein said gate switch circuits are arranged corresponding to said first and second transistors, respectively.

15. 2. The semiconductor device according to claim 1, wherein said electrical signal is electrical disturbance noise.

16. the electrical disturbance noise is electrostatic discharge, 16. The semiconductor device according to claim 15, wherein the electrostatic discharge includes a test electric signal simulating the electrostatic discharge.

17. 2. The semiconductor device according to claim 1, wherein said discharge path includes said power supply line and said GND line.

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