Semiconductor Device

Abstract

To improve ohmic contact properties for a GaN-based semiconductor of an electrode.SOLUTION: A semiconductor device S having gallium nitride comprises a semiconductor layer having a first surface 31 including a first region, and a second region that is a belt-like convex part projecting from the first region or a belt-like concave part recessed from the first region. On the first surface, at least one of a surface of the first region or the second region has a crystal face that includes the (000-1) plane direction and a plane direction different from the (1-100) plane direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device made of a GaN-based semiconductor and a method for manufacturing the semiconductor device. [Background technology]

[0002] A conventional semiconductor element and a method for manufacturing the semiconductor element are described in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-66398 A Summary of the Invention

[0004] The semiconductor element disclosed herein is a semiconductor element having gallium nitride, and comprises a semiconductor layer having a first surface including a first region and a second region which is a strip-shaped convex portion protruding from the first region or a strip-shaped concave portion recessed from the first region, and at least one of the surfaces of the first region or the second region of the first surface has a crystal plane including a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

[0005] The present disclosure also provides a method for manufacturing a semiconductor device, comprising the steps of preparing a substrate, forming a semiconductor layer having gallium nitride on a first surface of the substrate, and peeling the semiconductor layer from the substrate, wherein the semiconductor layer is peeled from the substrate such that the peeled surface is a crystal plane that includes a plane orientation different from the (000-1) plane orientation and the (1-100) plane orientation.

[0006] The semiconductor element of the present disclosure is a semiconductor element having gallium nitride, comprising a semiconductor layer epitaxially grown starting from a substrate, the semiconductor layer having a first surface including a first region and a second region adjacent to the first region, the second region being a peeled surface formed when the semiconductor layer is separated from the substrate, the peeled surface having a crystal plane including a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation. [Brief description of the drawings]

[0007] The objects, features and advantages of the present disclosure will become more apparent from the following detailed description and drawings. [Figure 1] 1 is a cross-sectional view illustrating a schematic diagram of a semiconductor element according to an embodiment of the present disclosure. [Diagram 2] 1A to 1C are diagrams for explaining a manufacturing method of a semiconductor element according to the present disclosure. [Diagram 3] 2 is an enlarged photograph showing a cross-sectional shape near an opening of base substrate 1. [Figure 4] 2 is an enlarged photograph showing a cross-sectional shape near an opening of base substrate 1. [Figure 5A] 2 is a cross-sectional view that illustrates a state in which a deposition inhibiting mask is laminated on a first base surface of a base substrate 1. FIG. [Figure 5B] 1 is a cross-sectional view showing a schematic state in which a semiconductor layer is formed on a deposition inhibiting mask. [Figure 5C] FIG. 2 is a cross-sectional view showing a schematic state in which a ridge is formed in a semiconductor layer. [Figure 5D] FIG. 2 is a cross-sectional view showing a schematic state in which an n-type insulating layer is formed on a flat portion of a semiconductor layer having a ridge. [Figure 5E] 4 is a cross-sectional view showing a schematic state in which a p-type electrode is laminated on the ridge and the insulating layer. FIG. [Figure 5F] 1 is a cross-sectional view showing a schematic state in which an electrode pad is laminated on a p-type electrode. [Figure 5G] FIG. 11 is a cross-sectional view showing a state in which the deposition suppression mask has been removed. [Figure 5H]1 is a cross-sectional view showing a schematic state in which a semiconductor laser element separated from a base substrate is turned upside down. [Figure 5I] 4 is a cross-sectional view showing a schematic state in which an n-type electrode is laminated on a second base surface of the semiconductor laser element. FIG. [Figure 5J] FIG. 2 is a cross-sectional view showing a schematic state in which a pair of cavity facets are end-face coated. [Figure 5K] 1 is a cross-sectional view showing a schematic state in which a semiconductor laser element is bonded to a mounting substrate via an n-type electrode. [Figure 6] 5C is an enlarged photograph of the semiconductor layer as viewed from above in FIG. 5H. [Figure 7] 1 is a cross-sectional view illustrating a schematic diagram of a semiconductor element according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] First, a configuration on which the semiconductor element and the manufacturing method of the semiconductor element according to the present disclosure are based will be described.

[0009] Conventionally, as described in Patent Document 1, for example, semiconductor elements and methods for manufacturing semiconductor elements involve forming a mask layer having a plurality of stripe-shaped openings on a base substrate made of a material different from GaN-based semiconductors, such as a C-plane sapphire substrate and a silicon substrate with a (111) plane orientation, and selectively growing a GaN-based semiconductor layer with a (0001) plane orientation on the surface of the base substrate exposed through the openings, thereby manufacturing a GaN-based semiconductor element.

[0010] Although electrodes are formed on the GaN-based semiconductor layer manufactured by such a method for manufacturing a semiconductor device, there is room for improvement in terms of, for example, the ohmic contact of the electrodes with the GaN-based semiconductor.

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are diagrammatically illustrated for ease of illustration.

[0012] (First embodiment) 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. The semiconductor device S according to this embodiment is made of a GaN-based semiconductor and has a crystal structure in which crystals have grown in the (0001) plane orientation of the GaN-based semiconductor (perpendicular to the (0001) plane 32). As shown in FIG. 2, which will be described later, the semiconductor device S has a first surface 31 of the GaN-based semiconductor in the (000-1) plane orientation, which faces a planar first base surface 1a, which is one main surface of a base substrate 1. The first surface 31 has a planar first region W1 and a second region W2 protruding from the first region W1. Therefore, the first surface 31 has three crystal surfaces 10a, 10b, and 10c (second region W2) having a plane orientation different from the (000-1) plane, and two nitrogen polarity surfaces (hereinafter also referred to as "N surfaces") 10d and 10e (first region W1) located in the <11-20> direction (left-right direction in Figure 1) of these crystal surfaces 10a, 10b, and 10c.

[0013] As described later, such a plurality of crystal planes are constituted by a fracture surface 10a, one side surface 10b, and the other side surface 10c of a strip-shaped protrusion 9 formed by peeling off the semiconductor layer 3 from the base substrate 1, and have three or more crystal planes with different plane orientations. Since such a plurality of crystal planes 10a, 10b, and 10c are formed by the protrusion 9, they protrude from the (000-1) plane in the (000-1) plane orientation (direction perpendicular to the (000-1) plane).

[0014] The protrusions 9 are realized as a structure in which the GaN semiconductor protrudes from the N-face of the semiconductor layer 3, which is a GaN semiconductor epitaxially grown (ELO; Epitaxial Lateral Overgrowth) from the base substrate 1, and therefore it is possible to expose a crystal face other than the N-face (000-1). The protrusions 9 contain GaN that was already present when the deposition suppression mask was formed, and the ohmic contact can be improved by adjusting the amount of impurities, such as Si, on the base substrate 1 side.

[0015] As described above, in the protrusion 9, the three crystal faces 10a, 10b, and 10c with different orientations are exposed, so that ohmic contact can be more easily achieved. The three crystal faces 10a, 10b, and 10c expose crystal faces other than the nitrogen polar faces 10d and 10e, for example, the M face (1-100), the A face (11-20), and the R face (1-102). The n-type electrode 12 is formed continuously on the multiple crystal faces 10a, 10b, and 10c and the nitrogen polar faces 10d and 10e. This significantly improves the ohmic contact with the n-type electrode 12, and improves the adhesion and stability of the n-type electrode 12. A p-type electrode 14, which will be described later, is disposed as a second electrode on the second face 32 facing the first face 31 of the semiconductor layer 3.

[0016] The ohmic resistance for determining the ohmic contact can be measured by, for example, the Transmission Line Model (TLM) method or the Circular Transmission Line Model (CTLM) method.

[0017] The semiconductor element in this embodiment may have a protrusion 9 in the center of the first surface 31. In other words, the first surface 31 has a plurality of first regions W1 sandwiching second regions W2 therebetween.

[0018] The surface of the first region W1 may have a crystal plane including the same plane orientation as the surface of the second region W2. In this case, for example, by polishing a part of the surface of the second region W2 (e.g., 10a), the first region W1 and the second region W2 may have a crystal plane with a (000-1) plane orientation.

[0019] In the semiconductor element of this embodiment, the contact area between the first electrode 12 and the first region W1 may be larger than the contact area between the first electrode 12 and the second region W2.

[0020] In the contact area between the first electrode 12 and the second region W2, the area of ​​the crystal planes including the (000-1) or (1-100) plane orientation may be smaller than the area of ​​the crystal planes including plane orientations other than the (000-1) and (1-100) plane orientations.

[0021] 2 is a diagram for explaining one embodiment of the method for manufacturing a semiconductor device according to the present disclosure, showing steps (a), (b), (c), and (d) of the manufacturing process of the semiconductor device.

[0022] The method for manufacturing a semiconductor device according to the embodiment includes performing a substrate reuse step of repeating the above-mentioned steps (a) to (d) one or more times.

[0023] 2, step (a) is a mask formation step, step (b) is an element formation step, step (c) is a mask removal step, and step (d) is an element isolation step.

[0024] The base substrate 1 commonly used in each of the steps (a) to (d) has a first base surface 1a, which is one flat main surface that serves as a starting point for semiconductor crystal growth, and a second base surface 1b, which is the other flat main surface on the back side of the first base surface 1a. At least the front surface of the first base surface 1a is covered with a nitride semiconductor. The base substrate 1 used in the embodiment is, for example, a gallium nitride (GaN) substrate cut from a single crystal ingot of GaN.

[0025] The GaN substrate may be either an n-type substrate or a p-type substrate, in which impurities such as Si are doped into the semiconductor. For example, the impurity density of the substrate is 1×10 19 cm -3 In addition to a GaN substrate, base substrate 1 may be a substrate obtained by forming a GaN semiconductor layer on the surface of a substrate other than GaN, such as a sapphire substrate, a silicon substrate, or a SiC substrate.

[0026] The surface of the base substrate 1 is not limited to a GaN layer, and any substrate made of a GaN-based semiconductor can be used. The term "GaN-based semiconductor" used here refers to, for example, Al x Ga y In z N(0≦x≦1-1≦y≦1-1≦z≦1; x+y+z=1).

[0027] A protective layer 4 may be formed on the second base surface 1b and substrate end surface 1c of the base substrate 1 located on the opposite side (lower side) of the first base surface 1a, excluding the first base surface 1a which is the starting point of semiconductor crystal growth. The protective layer 4 is formed to suppress deterioration of the base substrate 1 and decomposition of the nitride semiconductor in the process described below. The protective layer 4 may be formed of a layer containing, for example, aluminum oxide or alumina. However, the protective layer 4 may not be present on the substrate end surface 1c.

[0028] Without the protective layer 4, the rear surface of the base substrate 1 is likely to gradually decompose thermally and change in quality. This causes changes in the thermal emissivity and an in-plane distribution of the thermal emissivity due to the change in quality of the second base surface 1b, which is the rear surface of the base substrate 1. This causes the growth conditions of the semiconductor crystal to deviate from the optimum conditions, which is a factor in reducing mass productivity. By covering the second base surface 1b of the base substrate 1 with the protective layer 4 as in this embodiment, it is possible to suppress the change in quality of the second base surface 1b of the base substrate 1, stabilize the growth conditions of the semiconductor crystal, and improve mass productivity.

[0029] The first method of manufacturing a semiconductor device using the above-mentioned base substrate 1 includes steps (a) to (d) shown in Fig. 2. In step (a), a deposition suppression mask 2 is formed on the first base surface 1a of the base substrate 1. In step (b), a semiconductor layer 3 is formed on the masked first base surface 1a of the base substrate 1. In step (c), the deposition suppression mask 2 is removed by etching. In step (d), the semiconductor layer 3 is separated from the first base surface 1a of the base substrate 1.

[0030] (1) Process (a) (first time) In step (a), which is a mask formation step, a deposition suppression mask 2 for suppressing the growth of semiconductor crystals (semiconductor layer 3) is formed in a predetermined pattern on first base surface 1a of base substrate 1 (GaN substrate).

[0031] As a specific example, a SiO2 layer having a thickness of about 100 to 1000 nm is formed as the deposition suppression mask 2. The SiO2 layer is formed by first stacking silicon oxide (SiO2), which is to be the material of the deposition suppression mask 2, on the first base surface 1a to a thickness of about 100 to 1000 nm by a PCVD (Plasma Chemical Vapor Deposition) method or the like.

[0032] Next, unnecessary SiO2 layer portions are removed by photolithography and HF (hydrofluoric acid)-based wet etching or dry etching using fluorine-based gas such as CF4, etc. As a result, a SiO2 layer having a predetermined pattern can be formed on the first base surface 1a as a deposition suppression mask 2.

[0033] The exposed surface E visible through the band-shaped groove (upward opening) between the masks 2 is the first crystal growth region where the aforementioned first base surface 1a is exposed, and is the region that serves as the starting point for the growth of the semiconductor crystal in the subsequent step (b).

[0034] The opening width or groove width, which is the width in the (11-20) plane orientation of exposed surface E, i.e., the parallel direction (left-right direction in the figure), is, for example, 2 to 20 μm. In the embodiment, the parallel direction width of the deposition suppression mask 2 is set to, for example, 50 to 200 μm.

[0035] The relationship between the width of the deposition inhibiting mask 2 in the parallel direction and the width of the exposed surface E in the parallel direction may be set in consideration of the crystal growth rate ratio shown below and the thickness of the semiconductor layer 3 to be grown. In other words, the crystal growth rate ratio is the ratio of the crystal growth rate of the semiconductor layer 3 formed in step (b) in a direction perpendicular to the first base surface 1a of the base substrate 1 to the crystal growth rate in a direction parallel to the first base surface 1a of the base substrate 1.

[0036] The mask pattern of the deposition suppression mask 2 may be a band or stripe pattern, or may be a lattice pattern in which a plurality of bands are arranged so as to intersect vertically and horizontally at right angles. Any pattern may be used as long as it is a so-called repeat pattern in which openings separated by a certain interval (repeat pitch) are repeated multiple times.

[0037] The deposition suppression mask 2 may have an uneven surface by etching or the like. This makes it possible to provide unevenness on the back surface of the semiconductor element S separated in step (d), which has the effect of improving the ohmic contact and adhesion between the first surface 31 of the semiconductor element S (the surface peeled off after the semiconductor element S is separated) and the n-type electrode 12.

[0038] Furthermore, in consideration of ease of peeling and separation of the semiconductor layer 3 described below, the edge region of the first base surface 1a of the base substrate 1 near the substrate end surface 1c of the base substrate 1 is also covered with the above-mentioned deposition inhibiting mask 2. This allows the semiconductor layer 3 located at the end of the base substrate 1 near the edge to be peeled off cleanly and reliably.

[0039] The deposition suppression mask 2 is made of a mask material containing silicon oxide, such as SiO2. The deposition suppression mask 2 may be made of any material that does not allow the semiconductor layer 3 to grow from the surface of the mask material by vapor phase growth. Other than those containing silicon oxide, zirconium oxide (ZrO X ), titanium dioxide (TiO X ), aluminum oxide (AlO X ) or other oxides can be used. Alternatively, a transition metal selected from chromium (Cr), tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), or other transition metals can be used. In addition, the deposition method of the mask material can be appropriately selected from a method suitable for the mask material, such as vapor deposition, sputtering, and coating and curing.

[0040] (2) Process (b) (first time) In step (b), which is an element formation step, a semiconductor crystal is grown from exposed surface E, which is the first crystal growth region, so as to spread onto the adjacent deposition suppression mask 2, to form a semiconductor layer 3 that becomes an element. The semiconductor layer 3 in this embodiment is a nitride semiconductor, and the nitride semiconductor is grown by epitaxial growth from the first base surface 1a, beyond the upper edge opening of the groove in the deposition suppression mask 2, and onto the deposition suppression mask 2.

[0041] As a specific example, the element formation process can use vapor phase epitaxy methods such as hydride vapor phase epitaxy (HVPE) using chlorides as Group III (Group 13 element) raw materials, metal organic chemical vapor deposition (MOCVD) using organic metals as Group III raw materials, or molecular beam epitaxy (MBE).

[0042] For example, when growing a GaN layer as the semiconductor layer 3 by the MOCVD method, first, the base substrate 1 on which the deposition suppression mask 2 is patterned is inserted into a reaction chamber of an epitaxial apparatus, and the base substrate 1 is heated while supplying hydrogen gas, nitrogen gas, or a mixed gas of hydrogen and nitrogen, and a Group V source gas (containing a Group 15 element) such as ammonia, to a predetermined growth temperature, for example, 1050 to 1100°C.

[0043] Next, after the temperature of base substrate 1 has stabilized, in addition to the above gases, a Group III (containing Group 13 element) source such as trimethylgallium (TMG) is supplied to vapor-grow semiconductor layer 3 from exposed surface E, which is the crystal growth region.

[0044] At this time, the doping amount can be adjusted by supplying a source gas containing an n-type impurity such as Si or a p-type impurity such as Mg, and a GaN layer of the desired conductivity type can be obtained. Also, before the growing crystal exceeds the upper edge opening of the groove between the deposition suppression masks 2 or fills up the groove, the supply of the source gas is temporarily stopped to stop the growth of the semiconductor crystal, and before the supply of the source gas is resumed, a "weak portion" that facilitates peeling off of the semiconductor layer 3 described below may be formed as a partial layer or film.

[0045] As an example of a fragile portion, for example, when growing a GaN layer, a layer made of a mixed crystal of GaN and BN, AlN, InN, or the like may be formed as the fragile portion between the upper semiconductor layer 3 on the opening side of the groove and the lower semiconductor layer 3 on the exposed surface E side.

[0046] In addition, there are weak areas such as Al, which has a different lattice constant from the crystal growth layer. x Ga y In z N (0≦x≦1-1≦y<1-1≦z≦1; x+y+z=1) may be formed. Alternatively, a weak portion of a superlattice structure may be formed by alternately stacking AlGaN layers and GaN layers. The weak portion may be formed by periodically changing the crystal growth conditions to alternately stack layers with large GaN crystal grains and layers with small GaN crystal grains, or by forming a layer with a different impurity concentration, for example, by changing the concentration of silicon (Si), which is used as an n-type impurity for GaN.

[0047] Due to these fragile parts, when the semiconductor element S is separated and peeled off from the base substrate 1, stress is likely to concentrate at the fragile parts and cause cracks, making it possible to easily separate the semiconductor element S from the base substrate 1. Furthermore, by forming the n-type electrode 12 so as to cover the three crystal faces 10a, 10b, and 10c of the protrusion 9, which is a part of the first surface 31 of the semiconductor element S, due to these fragile parts, it is possible to improve ohmic contact.

[0048] When the aforementioned weak portion is created, GaN is grown laterally (ELO: Epitaxial Lateral Over-Growth) starting from the upper surface (surface) of the weak portion. When the weak portion is not created, GaN is grown laterally starting from the exposed surface E (first base surface 1a of base substrate 1) between the masks described above. For example, an n+ type GaN layer doped with, for example, Si as an n-type impurity is grown in an island shape in the (0001) plane orientation by MOCVD. The thickness of the n+ type GaN layer is, for example, 10 μm, and the impurity concentration is, for example, 1×10 18 cm -3 The distance between the n+ type GaN layers in the <11-20> direction is, for example, about 10 μm.

[0049] The n+ type GaN layer is grown, for example, at a temperature of 1100°C and a pressure of 30 kPa. When growing the n+ type GaN layer, for example, TMG and NH3 are used as source gases, H2 and N2 are used as carrier gases, and SiH4 diluted with nitrogen is used as the n-type dopant. One island-shaped n+ type GaN layer is grown from one stripe window.

[0050] Next, the crystal growth conditions are adjusted so as to promote vertical growth, and an n-type GaN layer is grown on the n+-type GaN layer by MOCVD. The thickness of this n-type GaN layer is, for example, 5 μm, and the impurity concentration is, for example, 1×10 16 cm -3 In this way, after the n-type GaN layer is grown, the overall spacing between the n+ type GaN layer and the n-type GaN layer in the <11-20> direction is, for example, about 5 μm.

[0051] After the crystal growth surface of the semiconductor layer 3 exceeds the upper edge of the deposition suppression mask 2, the semiconductor layer 3 grows laterally (left and right in the figure) along the upper surface of the deposition suppression mask 2. Therefore, the semiconductor layer 3 can be a semiconductor layer with few threading dislocations, which is suitable for use in light emitting diodes (abbreviated as LEDs) and laser diodes (abbreviated as LDs) and the like.

[0052] Then, step (b) (first time) may be terminated after each semiconductor layer 3, which has begun to grow from the exposed surface E between the masks, comes into contact with the adjacent semiconductor layer 3 or before they overlap each other, or it may be terminated after they come into contact with each other.

[0053] (3) Process (c) (first time) After the above-mentioned step (b) (first time) is completed, a mask removal step (c) is performed. In the step (c), the base substrate 1 is removed from the vapor phase growth apparatus (epitaxial apparatus), and the deposition suppression mask 2 is removed using an etchant that does not substantially attack the grown semiconductor layer 3.

[0054] For example, in the case of a mask made of a SiO2 film, HF-based wet etching is performed. By etching, each deposition suppression mask 2 is removed, and the semiconductor layer 3 becomes substantially T-shaped, as shown in Fig. 2(c), with only a connection part made of a thin semiconductor wall or pillar remaining on the exposed surface E between the adjacent deposition suppression masks 2. This shape allows the semiconductor layer 3 to be separated smoothly.

[0055] (4) Process (d) (first time) In step (d), which is an element isolation process, the semiconductor layer 3 is separated from the base substrate 1 using a member or tool such as a support substrate 6 having an adhesive layer 5 made of solder using a material such as AuSn on one surface (in this embodiment, the second surface 32) of the semiconductor layer 3, to form individual semiconductor elements S.

[0056] In step (d), first, for example, a support substrate 6 having an adhesive layer 5 on its lower surface is placed opposite the surface of the base substrate 1 on which the semiconductor layer 3 is formed (i.e., the first base surface 1a), and the adhesive layer 5 is bonded to the semiconductor layer 3 by applying pressure and heat.

[0057] Thereafter, an external force is applied so as to peel the semiconductor layer 3, which is bonded and integrated with the adhesive layer 5, upward, and the semiconductor layer 3 is lifted up from the first base surface 1a of the base substrate 1. This makes it possible to separate the main body of the semiconductor element S.

[0058] In step (d), instead of the step of separating using adhesive layer 5 made of solder using a material such as AuSn, separation may be performed using an adhesive tape such as a dicing tape or a double-sided tape.

[0059] After the semiconductor elements are separated, the base substrate 1 is polished to remove damage caused by the peeling of the semiconductor elements S during the epitaxial growth process, and the mask formation process (a), element formation process (b), mask removal process (c), and element separation process (d) are performed in the same manner as in the first manufacturing process. This allows high-quality semiconductor elements S with excellent ohmic contact equivalent to that obtained in the first manufacturing process to be repeatedly manufactured using the same base substrate 1. Types of damage include pits caused by the reaction between the SiO2 mask and Ga, surface roughness of GaN caused by the formation, heating, and removal processes of the SiO2 mask, and dislocations caused by peeling.

[0060] In addition to polishing, wet etching or dry etching may be used for this damage removal step. Alternatively, each of steps (a) to (d) may be repeated by shifting the mask opening without removing the damage.

[0061] 3 and 4 are enlarged photographs showing the cross-sectional shape near the opening of the base substrate 1. The cross-sectional shape of the opening of the base substrate 1 after the semiconductor element S was peeled off was concave, and the damage depth Δd was 1 μm or less.

[0062] Therefore, by polishing or wet etching the first base surface 1a of the base substrate 1 after use to a depth of 1 μm or less, the above-mentioned crystal lattice defects such as pits, surface roughness, and dislocations can be removed.

[0063] Second embodiment 5A to 5K are cross-sectional views that typically show a manufacturing procedure of a semiconductor laser element according to a second embodiment of the present disclosure. FIG. 5A shows a state in which a deposition suppression mask 2 is laminated on a first base surface 1a of a base substrate 1, and FIG. 5B shows a state in which a semiconductor layer 3 is formed on the deposition suppression mask 2. FIG. 5C shows a state in which a ridge 3c is formed on the semiconductor layer 3, and FIG. 5D shows a state in which an insulating film 15 is formed on a flat portion 3b of the semiconductor layer 3 having the ridge 3c. FIG. 5E shows a state in which a p-type electrode 14 is laminated on the ridge 3c and the insulating film 15, and FIG. 5F shows a state in which an electrode pad 16 is laminated on the p-type electrode 14. FIG. 5G shows a state in which the deposition suppression mask 2 has been removed, and FIG. 5H shows a state in which the semiconductor laser element separated from the base substrate 1 has been turned over. Fig. 5I shows a state in which an n-type electrode 12 is formed on the first surface 31 of the semiconductor layer 3, Fig. 5J shows a state in which a pair of cavity faces are end-face coated, and Fig. 5K shows a state in which the semiconductor laser element is bonded to a mounting substrate 17 via the n-type electrode 12. Fig. 6 is an enlarged photograph of the semiconductor layer 3 seen from above in Fig. 5H. Note that parts corresponding to those in the above-mentioned embodiment are given the same reference numerals, and duplicated explanations will be omitted.

[0064] The semiconductor laser element, which is the semiconductor element of this embodiment, is a roughly rectangular parallelepiped with a length of 50 to 1300 μm, a width of 30 to 250 μm, and a height of 5 to 150 μm, and is formed so that two resonator faces face each other in the longitudinal direction perpendicular to the paper surface of FIG. 5K, and is configured to emit laser light from one of the resonator faces.

[0065] Base substrate 1 is made of n-type gallium nitride (GaN) and is, for example, a transparent substrate in which the normals of first base surface 1a and second base surface 1b are in the c-axis direction or have an off angle with respect to the c-axis, and has a thickness of about 40 to 600 μm. Base substrate 1 can be formed from a GaN wafer with a diameter of about 2 inches. Base substrate 11 is doped with an n-type dopant such as Si and may be conductive.

[0066] As shown in FIG. 5A, a deposition suppression mask 2 having a plurality of grooves 2a in a stripe shape is laminated on the first base surface 1a of the base substrate 1, and a nitride semiconductor is epitaxially grown on the deposition suppression mask 2 to laminate a semiconductor layer 3 as shown in FIG. 5B. As the deposition suppression mask 2, for example, a SiO2 layer having a thickness of about 100 to 1000 nm is formed. The SiO2 layer is formed by first laminating silicon oxide (SiO2), which is the material of the deposition suppression mask 2, on the first base surface 1a to a thickness of about 100 to 1000 nm by a PCVD (Plasma Chemical Vapor Deposition) method or the like. Next, unnecessary SiO2 layer portions are removed by photolithography and HF (hydrofluoric acid)-based wet etching or dry etching using a fluorine-based gas such as CF4. As a result, a SiO2 layer having a predetermined pattern can be formed as the deposition suppression mask 2. From the strip-shaped grooves 2a of the deposition inhibiting mask 2, the first base surface 1a is partially exposed, which is a region E that becomes the starting point of the growth of the semiconductor crystal.

[0067] As shown in FIG. 5C, the semiconductor layer 3 has a ridge 3c on the opposite side to the base substrate 1. As shown in FIG. 5D, an insulating film 15 is provided on the flat portion 3b of the semiconductor layer 3 except for the upper surface of the ridge 3c. In addition, a p-type electrode 14, which is a second electrode, is provided on the semiconductor layer 3. In this example, the insulating film 15 is provided on the semiconductor layer 3 other than the ridge 3c, and the p-type electrode 14 is provided on the semiconductor layer 3 through the insulating film 15 in this location. In this way, the semiconductor layer 3 and the p-type electrode 14 do not need to be electrically connected over the entire surface, and as in this embodiment, the portion under the p-type electrode 14 other than the ridge 3c may be covered with the insulating film 15.

[0068] Furthermore, the semiconductor layer 3 has a strip-shaped protrusion 9 in a region facing the base substrate 1, as shown in Fig. 5C. An n-type electrode 12, which is a first electrode, is provided on the first surface 31 of the semiconductor layer 3, as shown in Fig. 5J. In this example, the n-type electrode 12 is provided on the first surface 31 of the semiconductor layer 3 including the protrusion 9.

[0069] The semiconductor layer 3 has a thickness of about 2 to 5 μm, and is configured by laminating thin films of nitride semiconductors. For example, the semiconductor layer 3 is configured by laminating a first n-type nitride semiconductor layer, a second n-type nitride semiconductor layer, an active layer, a first p-type nitride semiconductor layer, a second p-type nitride semiconductor layer, a third p-type nitride semiconductor layer, and a fourth p-type nitride semiconductor layer in this order on the first base surface 1a of the base substrate 1. These semiconductor layers 3 have a composition formula of In x Al y Ga 1-x-y The semiconductor layer 3 mainly contains a mixed crystal of indium nitride (InN), aluminum nitride (AlN), and gallium nitride (GaN), which can be expressed as N (0≦x≦1-1≦y≦1-1≦x+y≦1). As n-type impurities contained in the semiconductor layer 3, silicon (Si), germanium (Ge), tin (Sn), sulfur (S), oxygen (O), titanium (Ti), zinc (Zr), cadmium (Cd), etc. can be used. As p-type impurities, magnesium (Mg), zinc (Zn), beryllium (Be), manganese (Mn), calcium (Ca), strontium (Sr), etc. can be used. The active layer can have a multiple quantum well structure in which barrier layers and well layers are repeatedly stacked by changing the ratio of the In and Ga components of InGaN. The active layer may or may not contain impurities.

[0070] The third p-type nitride semiconductor layer and the fourth p-type nitride semiconductor layer are etched to form a ridge 3c that protrudes in a strip shape. The width of the ridge 3c is about 2 to 20 μm, and the height is about −1.3 to 0.6 μm. The ridge 3c exists over the entire lengthwise direction from one cavity facet to the other cavity facet of the semiconductor layer 3. Both end facets in the longitudinal direction of the ridge 3c are each included in the cavity facet of the semiconductor laser element. Aluminum oxynitride (AlO x N y The mirror layer may be formed of a thin film of, for example, SiO2 (0≦x≦1-1≦y≦1.5), silicon dioxide (SiO2), or tantalum pentoxide (Ta2O5).

[0071] Thus, the semiconductor layer 3 of the semiconductor laser element is a laminate in which a plurality of semiconductor layers are stacked, and includes the semiconductor layer 3, which is a laminate having a convex portion 9 (second region W2) protruding from the first region W1, and the n-type electrode 12 located on the first region W1 and the second region W2. The first region W1 has a rough surface region a, which has a surface roughness larger than that of the other region b, in a contact region with the n-type electrode 12. The surface roughness can be measured, for example, by an atomic force microscope (AFM). In this example, the other region b is located between the rough surface region a and the convex portion 9.

[0072] The other regions b extend in a strip shape along the protrusions 9 in the vicinity of the protrusions 9, and the rough surface regions a are located in a strip shape along the other regions b. Such rough surface regions a can adjust the surface roughness of a part (rough surface region a) of the first region W1 of the semiconductor layer 3 located on the surface of the deposition inhibiting mask 2 by roughening at least a part of the surface of the deposition inhibiting mask 2 arranged on the base substrate 1. The large surface roughness of the part of the first region W1 can improve the connection with the electrode 12.

[0073] In addition, since the surface roughness of a portion of the first region W1 is large, a crystal plane having a plane orientation different from the (000-1) plane orientation and the (1-100) plane orientation can be located on the first region W1. That is, the surface of the first region W1 can have a crystal plane including a plane orientation different from the (000-1) plane orientation and the (1-100) plane orientation. In this case, the rough surface region a may have a crystal plane such as, for example, the A plane (11-20) or the R plane (1-102).

[0074] Furthermore, in the contact region between the first electrode 12 and the first region W1, the area of ​​the crystal planes including the (000-1) or (1-100) plane orientation may be smaller than the area of ​​the crystal planes including plane orientations other than the (000-1) and (1-100) plane orientations.

[0075] In a direction perpendicular to the longitudinal direction of the convex portion 9 (parallel direction), when the total width of the first region W1 is B0, the width of the other region b is B1, and the width of the rough surface region a is B2, the width B1 of the other region b is 10% or more and 80% or less of the total width B0, and the width B2 of the rough surface region a is 20% or more and 90% or less of the total width B0.

[0076] In this example, the semiconductor layer 3, which is a laminate, is made of a GaN-based semiconductor, and the other region a and the rough surface region b of the first region W1 are two nitrogen polarity planes (hereinafter also referred to as "N faces") located in the <11-20> direction (left and right direction in Figure 5C) of the aforementioned three crystal planes 10a, 10b, 10c of the first surface 31.

[0077] The surface roughness of the other region b is 0.05 nm or more and less than 1 nm, and the surface roughness of the rough region a is 1 nm or more and less than 1000 nm.

[0078] As shown in FIG. 7, the convex portion 9 has a first convex region 9a located on the semiconductor layer 3 side, and a second convex region 9b located closer to the base substrate 1 side (the tip side of the convex portion 9) than the first convex region 9a. The impurity concentration of the second convex region 9b is lower than the impurity concentration of the first convex region 9a. The first convex region 9a may be located closer to the tip side of the convex portion 9 than the second convex region 9b. The first convex region 9a and the second convex region 9b form a connection portion in a connected state. Such a convex portion 9 can be formed by separating the semiconductor layer 3 together with a part of the base substrate 1 from the base substrate 1.

[0079] The dislocation density of the second convex region 9b may be smaller than the dislocation density of the first convex region 9a. The convex portion 9 is formed by crystal growth of a nitride semiconductor on the exposed surface E of the first base surface 1a of the base substrate 1, and refers to a state in which the first convex region 9a and the second convex region 9b are connected. In this case, the dislocation density of the first convex region 9a is, for example, 1×10 4 More than 1×10 7 The dislocation density of the second convex region 9b is, for example, 1×10 3 5×10 or more 6or less. Also, the number of dislocation defects in the connection portion may be more than the number of dislocation defects in the second convex region 9b. Also, the number of dislocation defects in the connection portion may be more than the number of dislocation defects in the first convex region 9a. The dislocation density can be adjusted by varying the growth conditions during the growth of the semiconductor layer 3. That is, the dislocation density may be greater than the regions located above and below the connection portion.

[0080] The density of dislocations, which are crystal defects in the semiconductor crystal, can be adjusted by appropriately controlling the growth conditions of the semiconductor layer 3.

[0081] The length of the first convex region 9a in the protruding direction of the convex portion 9 may be greater than the length of the second convex region 9b in the protruding direction of the convex portion 9. In addition, the surface area of ​​the first convex region 9a may be greater than the surface area of ​​the second convex region 9b.

[0082] The first region W1 may be a rough surface over the entire surface or only in a portion thereof. When only a portion thereof is rough, the rough surface region a may be located near the protrusion 9. That is, in the parallel direction, the area of ​​the region between the outer edge of the rough surface region a and the protrusion 9 may be smaller than the area of ​​the region between the other outer edge of the rough surface region a and the outer edge of the semiconductor layer 3.

[0083] A plurality of rough surface regions a may be located on both sides of the protrusion 9. In this example, the protrusion 9 is located between two rough surface regions a. In this case, the n-type electrode 12 may be configured to cover only one of the rough surface regions a on both sides of the protrusion 9.

[0084] In the above embodiment, the semiconductor layer 3 has a strip-shaped protrusion 9. However, in another embodiment, instead of the protrusion 9, a strip-shaped recess 9' (second region W2) may be provided in which the first surface 31 is recessed from the flat first region W1. Even in such a configuration, at least one of the first region W1 and the second region W2 has a crystal plane with a plane orientation different from the (000-1) plane orientation and the (1-100) plane orientation, thereby enabling a crystal plane having high ohmic contact with a conductor layer such as an electrode to be developed, thereby improving the bonding reliability between layers. Note that by adjusting the direction in which stress occurs when the semiconductor layer 3 is peeled off, a recess 9' can be formed to enable a crystal plane 10a to be developed as shown by the imaginary line in FIG. 7.

[0085] The semiconductor element S of this embodiment has a first surface 31 of a GaN-based semiconductor with a (000-1) surface orientation facing the planar first base surface 1a, which is one main surface of the base substrate 1. The first surface 31 has a planar first region W1 and a second region W2 recessed from the first region W1. Therefore, the first surface 31 has a plurality of crystal planes (second region W2) including a surface orientation different from the (000-1) plane, and two nitrogen polarity planes (hereinafter also referred to as "N faces") 10d, 10e (first region W1) located in the <11-20> direction (left and right direction in FIG. 1) of these crystal planes. As such, the plurality of crystal planes expose crystal planes other than the nitrogen polarity planes 10d, 10e, for example, the M plane (1-100), the A plane (11-20), and the R plane (1-102).

[0086] The present disclosure can be embodied in the following aspects (1) to (32).

[0087] (1) A semiconductor device having gallium nitride, a semiconductor layer having a first surface including a first region and a second region which is a strip-shaped protrusion protruding from the first region or a strip-shaped recess; A semiconductor element, wherein at least one of the surfaces of the first region and the second region of the first surface has a crystal plane including a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

[0088] (2) the semiconductor layer further has a second surface opposite to the first surface, A semiconductor element, wherein at least one of the surfaces of the first region or the second region of the first surface has a crystal plane including a plane orientation different from a plane orientation opposite to the plane orientation of the second surface.

[0089] (3) A semiconductor element, wherein the convex portion has three or more crystal faces with mutually different plane orientations.

[0090] (4) A semiconductor element, wherein one of the three or more crystal faces of the protrusion is a crystal face having a (000-1) plane orientation and a (1-100) plane orientation.

[0091] (5) A semiconductor element, wherein a surface of the first region has a crystal plane including a different plane orientation from a surface of the second region.

[0092] (6) A semiconductor element, wherein a surface of the first region has a crystal plane including the same plane orientation as a surface of the second region.

[0093] (7) A semiconductor element further comprising a first electrode disposed in the first region and the second region of the first surface.

[0094] (8) A semiconductor element, wherein the first electrode is an n-type electrode.

[0095] (9) The semiconductor layer further has a second surface opposite to the first surface, The semiconductor device further includes a second electrode disposed on the second surface.

[0096] (10) A semiconductor element, wherein the surface of the first region has a (000-1) surface orientation.

[0097] (11) A semiconductor element, wherein the surface of the second region has a (000-1) plane orientation.

[0098] (12) A semiconductor element, wherein the first surface has the second region and a plurality of second regions sandwiching the two regions.

[0099] (13) A semiconductor element, wherein surfaces of the second regions have crystal planes including a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

[0100] (14) A semiconductor element, wherein the surface of the first region has a crystal plane including a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

[0101] (15) A semiconductor element, wherein a contact area between the first electrode and the first region is larger than a contact area between the first electrode and the second region.

[0102] (16) In a contact region between the first electrode and the first region, an area of ​​a crystal plane having a (000-1) or (1-100) surface orientation is smaller than an area of ​​a crystal plane having a surface orientation other than the (000-1) or (1-100) surface orientation.

[0103] (17) In a contact region between the first electrode and the second region, an area of ​​a crystal plane having a (000-1) or (1-100) surface orientation is smaller than an area of ​​a crystal plane having a surface orientation other than the (000-1) or (1-100) surface orientation.

[0104] (18) A semiconductor element, wherein the recess has a plurality of crystal faces having different plane orientations.

[0105] (19) A semiconductor element, wherein one of the plurality of crystal faces of the recess is a crystal face including a (000-1) plane orientation and a (1-100) plane orientation.

[0106] (20) A method for manufacturing a semiconductor element, comprising the steps of: peeling the semiconductor layer from the substrate together with a portion of the substrate connected to the semiconductor layer.

[0107] (21) A method for manufacturing a semiconductor element, comprising the steps of: peeling the semiconductor layer from the substrate such that a portion of the semiconductor layer remains on the substrate.

[0108] (22) The method further includes a step of forming a mask on the first surface of the substrate before forming the semiconductor layer, the mask exposing a region that will become a starting point of growth of the semiconductor layer; The semiconductor layer is grown from the region along a surface of the mask.

[0109] (23) A method for manufacturing a semiconductor device, wherein the surface of the mask on which the semiconductor layer is grown has projections and recesses.

[0110] (24) A semiconductor device having gallium nitride, a semiconductor layer epitaxially grown starting from a substrate, the semiconductor layer having a first surface including a first region and a second region adjacent to the first region; the second region is a release surface formed when separated from the substrate; A semiconductor element, wherein the exfoliated surface has a crystal plane including a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

[0111] (25) A semiconductor element, wherein the convex portion has a first convex region and a second convex region having an impurity concentration lower than that of the first convex region.

[0112] (26) A semiconductor element, wherein the first convex region is located further forward than the second convex region.

[0113] (27) A semiconductor element, wherein the convex portion has a first convex region and a second convex region having a lower dislocation density than the first convex region.

[0114] (28) The convex portion has a connection portion where the first convex region and the second convex region are connected, A semiconductor element, wherein the connection portion has a dislocation density greater than that of the first convex region.

[0115] (29) The convex portion has a connection portion where the first convex region and the second convex region are connected, The convex portion has a first convex region and a second convex region having a lower dislocation density than the first convex region.

[0116] (30) The convex portion has a connection portion where the first convex region and the second convex region are connected, A semiconductor element, wherein the connection portion has a dislocation density greater than that of the first convex region.

[0117] (31) The convex portion 7 has a connection portion where the first convex region and the second convex region are connected, A semiconductor element, wherein the connection portion has a higher dislocation density than the second convex region.

[0118] (32) A semiconductor element, wherein the first convex region is larger than the second convex region.

[0119] According to the semiconductor element of the present disclosure, since the semiconductor element has planar portions 10a-10e with high ohmic contact, high bonding reliability is obtained without the need for a process for improving the ohmic contact between the semiconductor layer 3 and the insulating film 15 and between the semiconductor layer 3 and the n-type electrode 12, and the semiconductor element can be realized as, for example, a semiconductor laser element. This improves the productivity of the semiconductor element, making it possible to provide a semiconductor element with excellent mass productivity.

[0120] According to the method for manufacturing a semiconductor device of the present disclosure, it is possible to realize a semiconductor device having a surface with high ohmic contact without increasing the number of steps, which facilitates mass production of semiconductor devices with high bonding reliability.

[0121] Although the present disclosure has been described in detail above, the present disclosure can be implemented in various other forms without departing from its spirit or main features. Therefore, the above-described embodiments are merely examples in all respects, and the scope of the present disclosure is indicated in the claims and is not limited in any way by the text of the specification. Furthermore, all modifications and changes falling within the scope of the claims are within the scope of the present disclosure. [Explanation of symbols]

[0122] 1 Base Board 1a First base surface 1b Second base surface 1d Edge 2. Deposition suppression mask 3 Semiconductor layer 3a Remaining portion of semiconductor layer 3b Plane part 3c Ridge 4 protective layer 5 Adhesive layer 6 Support substrate 9 Connection 9a 1st convex area 9b 2nd convex area 10a, 10b, 10c Multiple crystal faces 12 n-type electrode 14 p-type electrode 15 Insulating layer 16 Mounting board 31 Page 1 32 2nd page E Exposed surface S Semiconductor element

Claims

1. A semiconductor device having gallium nitride, a semiconductor layer having a first surface including a first region and a second region that is a strip-shaped recess recessed from the first region; The semiconductor layer further has a second surface opposite to the first surface, the second surface having a ridge; the second region has a fracture surface and a plurality of crystal planes including a plane orientation different from the (000-1) plane; the surface of the first region has a (000-1) plane orientation; the semiconductor element further includes a first electrode disposed in the first region and the second region of the first surface; A semiconductor element, wherein a contact area between the first electrode and the first region is larger than a contact area between the first electrode and the second region.

2. 2. The semiconductor device of claim 1 , A semiconductor element, wherein at least one of the surfaces of the first region or the second region of the first surface has a crystal plane including a plane orientation different from a plane orientation opposite to the plane orientation of the second surface.

3. 3. The semiconductor device according to claim 1, A semiconductor element, wherein a surface of the first region has a crystal plane including a different plane orientation from a surface of the second region.

4. 3. The semiconductor device according to claim 1, A semiconductor element, wherein a surface of the first region has a crystal plane including the same plane orientation as a surface of the second region.

5. The semiconductor device according to any one of claims 1 to 4, The semiconductor element, wherein the first electrode is an n-type electrode.

6. The semiconductor device according to any one of claims 1 to 5, The semiconductor device further includes a second electrode disposed on the second surface.

7. The semiconductor device according to any one of claims 1 to 6, The first surface has the second region and a plurality of first regions sandwiching the second region.

8. 8. The semiconductor device according to claim 7, A semiconductor device, wherein surfaces of the plurality of first regions have crystal planes including a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

9. The semiconductor device according to any one of claims 1 to 7, A semiconductor device, wherein a surface of the first region has a crystal plane including a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

10. The semiconductor device according to any one of claims 1 to 5, a semiconductor element, in which in a contact region between the first electrode and the first region, an area of ​​a crystal plane including a (000-1) or (1-100) surface orientation is smaller than an area of ​​a crystal plane including a surface orientation different from the (000-1) and (1-100) surface orientations.

11. The semiconductor device according to any one of claims 1 to 5, a semiconductor element, wherein in a contact region between the first electrode and the second region, an area of ​​a crystal plane including a (000-1) or (1-100) surface orientation is smaller than an area of ​​a crystal plane including a surface orientation different from the (000-1) and (1-100) surface orientations.

12. A semiconductor device according to any one of claims 1 to 11, The first region further comprises a roughened region.

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