Integrated Circuits

Abstract

To inspect the capacity size of a capacitive element provided on a semiconductor substrate without enlarging the area of the semiconductor substrate.SOLUTION: An integrated circuit includes a capacitive element to be inspected Ct_1 and an inspection circuit 10 on the same semiconductor substrate. The inspection circuit 10 includes a capacitive element for inspection Cs_1 and a comparison circuit Cmp that compares the voltage of a node B and the voltage of a signal Vref_B with each other, in a first period, connects the other end of the capacitive element to be inspected Cmp to the node B and applies the voltage of s signal Vref_A to the node B, and in a second period after the first period, based on the capacity ratio between the capacitive element to be inspected Ct_1 and the capacitive element for inspection Cs_1, changes the voltage of the node B, and based on a result of comparison made by the comparison circuit Cmp, inspects the capacity size of the capacitive element to be inspected Ct_1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates, for example, to integrated circuits. [Background technology]

[0002] An example of a technique for testing the capacitance size of a capacitive element formed on a semiconductor substrate is the technique described in Patent Document 1. Specifically, the technique described in Patent Document 1 provides a test capacitive element on a semiconductor substrate in addition to a capacitive element to be tested, and compares the potential generated in the test capacitive element with the potential generated in the test capacitive element to determine whether the accuracy of the capacitance size of the test capacitive element is within a desired range. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-128203 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the technology described in Patent Document 1, as described in paragraph 0041 of the document, it is necessary to provide a test capacitive element having the same capacitance size as the capacitive element to be tested on the same semiconductor substrate. Therefore, the above technology has a problem in that the area of ​​the semiconductor substrate increases. [Means for solving the problem]

[0005] An integrated circuit according to one embodiment of the present disclosure is an integrated circuit including a test capacitive element and a test circuit on the same semiconductor substrate, one end of the test capacitive element being maintained at a predetermined voltage, the test circuit including a test capacitive element and a comparison circuit that compares the voltage of an input node with a predetermined reference voltage, during a first period, the other end of the test capacitive element is connected to an input node of the comparison circuit and a first voltage is applied to the input node, and during a second period after the first period, the voltage of the input node of the comparison circuit is changed based on the capacitance ratio of the test capacitive element and the test capacitive element, and the capacitance size of the test capacitive element is tested based on the comparison result of the comparison circuit. [Brief description of the drawings]

[0006] [Figure 1] 2 is a circuit diagram of the integrated circuit according to the first embodiment, including a test circuit and its surrounding circuitry. FIG. [Diagram 2] FIG. 4 is a diagram illustrating the operation of a test circuit. [Diagram 3] FIG. 4 is a diagram illustrating the operation of a test circuit. [Figure 4] FIG. 11 is a circuit diagram of the periphery of an integrated circuit according to a second embodiment, including a test circuit. [Diagram 5] FIG. 4 is a diagram illustrating the operation of a test circuit. [Figure 6] FIG. 4 is a diagram illustrating the operation of a test circuit. [Figure 7] FIG. 11 is a circuit diagram of the peripheral circuit including a test circuit in an integrated circuit according to a third embodiment. [Figure 8] FIG. 4 is a diagram illustrating the operation of a test circuit. [Figure 9] FIG. 4 is a diagram illustrating the operation of a test circuit. [Figure 10] FIG. 13 is a circuit diagram of the peripheral circuit including a test circuit in an integrated circuit according to a fourth embodiment. [Figure 11] FIG. 13 is a circuit diagram of the peripheral circuit including a test circuit in an integrated circuit according to a fifth embodiment. [Figure 12] FIG. 13 is a circuit diagram of the peripheral circuit including a test circuit in an integrated circuit according to a sixth embodiment. [Figure 13]FIG. 13 is a circuit diagram of the peripheral circuit including a test circuit in an integrated circuit according to a seventh embodiment. [Figure 14] FIG. 13 is a circuit diagram of the peripheral circuit including a test circuit in an integrated circuit according to an eighth embodiment. [Figure 15] FIG. 2 is a diagram showing an electrical configuration of the display device. [Figure 16] FIG. 1 is a perspective view showing a display device to which an integrated circuit is applied. [Figure 17] FIG. 2 is a diagram showing a configuration of a pixel circuit in a display device. [Figure 18] FIG. 1 is a diagram showing a configuration of an integrated circuit in a display device. [Figure 19] FIG. 2 is a diagram showing a configuration of a driver circuit in an integrated circuit. [Figure 20] FIG. 13 is a diagram showing an electrical configuration of another display device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0008] [First embodiment] 1 is a circuit diagram of an integrated circuit according to the first embodiment, including a test circuit 10 and its surroundings. In the diagram, around the test circuit 10, n test target capacitive elements Ct_1 to Ct_n are provided on the same semiconductor substrate together with the elements constituting the test circuit 10. Each of the test subject capacitive elements Ct_1 to Ct_n is a capacitive element (capacitor) to be tested. In this embodiment, one of the test subject capacitive elements Ct_1 to Ct_n is selected in order to be the test subject. The test circuit 10 includes a determination circuit 110, a control circuit 120, n switches Swt_1 to Swt_n and Swr, m test capacitance elements Cs_1 to Cs_m, and a comparison circuit Cmp. A switch Swt_1 is provided corresponding to the test subject capacitive element Ct_1, a switch Swt_2 is provided corresponding to the test subject capacitive element Ct_2, and similarly, a switch Swt_n is provided corresponding to the test subject capacitive element Ct_n.

[0009] One end of the test capacitive element Ct_1 is connected to a node N_1, and the other end is connected to one end of the switch Swt_1. A signal Vtemp_1 is supplied to the node N_1. The voltage of the signal Vtemp_1 is arbitrary and is approximately constant over time. One end of the test capacitive element Ct_2 is connected to a node N_2, and the other end is connected to one end of the switch Swt_2. A signal Vtemp_2 is supplied to the node N_2. The voltage of the signal Vtemp_2 is arbitrary and is approximately constant over time. Similarly, a signal Vtemp_n is supplied to a node N_n. The voltage of the signal Vtemp_n is arbitrary and is approximately constant over time. The other end of each of the switches Swt_1 to Swt_n is commonly connected to a node B.

[0010] The test capacitance elements Cs_1 to Cs_m are used to test the capacitance of a capacitance element selected as a test target among the test capacitance elements Ct_1 to Ct_n. Note that in this description, testing refers to measuring the capacitance or determining whether the capacitance is within a predetermined range. If the capacitance size of the test capacitance element Cs_1 is "1", the capacitance sizes of the test capacitance elements Cs_2, Cs_3, ..., Cs_m are, for example, "1 / 2", "1 / 4", ..., "1 / 2", in that order. (m-1) Specifically, when the capacitance size of the test capacitance element Cs_1 is 10 fF, the capacitance sizes of the test capacitance elements Cs_2, Cs_3, ..., Cs_m are 5 fF, 2.5 fF, ..., {10 / 2 (m-1)}fF. One end of each of the test capacitive elements Cs_1 to Cs_m is commonly connected to a node B. The other end of each of the test capacitive elements Cs_1 to Cs_m is supplied with signals Bf_1, Bf_2, Bf_3, . . . , Bf_m in this order.

[0011] One end of the switch Swr is connected to the node B, and the other end of the switch Swr is supplied with a signal Vref_A via a node Refin. The node Refin is an example of the first node. In this description, the node includes not only a separately provided terminal or electrode, but also a wiring provided on a semiconductor substrate. For the switches Swt_1 to Swt_n and Swr, "on" means that one end and the other end are closed and conductive, or that the switch is in a low impedance state, and "off" means that one end and the other end are open and non-conductive, or that the switch is in a high impedance state. The switches Swt_1 to Swt_n and Swr are each composed of a transistor that turns on or off between the source and drain nodes according to the voltage of the gate node, for example.

[0012] The comparator circuit Cmp compares the voltage applied to the positive input terminal (+) with the voltage of the signal Vref_B applied to the negative input terminal (-) and outputs a signal Cout indicating the comparison result. In detail, if the voltage of the positive input terminal (+) is equal to or higher than the voltage of the signal Vref_B, the comparator circuit Cmp outputs the signal Cout at an H level, and if the voltage of the positive input terminal (+) is lower than the voltage of the signal Vref_B, the comparator circuit Cmp outputs the signal Cout at an L level. Although the power supply voltage of the comparison circuit Cmp is not particularly illustrated, it is, for example, 1.8 V (volts). When the power supply voltage of the comparison circuit Cmp is 1.8 V, the H level of the logic level of the signal Out indicating the comparison result is 1.8 V, and the L level is 0 V. In this embodiment, the positive input terminal (+) of the comparison circuit Cmp, i.e., node B, is an example of an input node.

[0013] The determination circuit 110 tests the capacitance size of the test-subject capacitive element selected as the test target based on the logic level of the signal Out, and outputs a signal Out indicating the result of the test. The control circuit 120 controls the switches Swt_1 to Swt_n and Swr to be on or off individually, and controls the voltages of the signals Bf_1 to Bf_m, Vref_A and Vref_B.

[0014] Next, the operation of the test circuit 10 according to the first embodiment will be described. For convenience, a case will be described where the test capacitance element Ct_1 is selected as the test target. It is assumed that the capacitance size of the test capacitance element Ct_1 is approximately 1.00 pF (=1000 fF), m=8, and test capacitance elements Cs_1 to Cs_8 are provided. If the capacitance size of the test capacitance element Cs_1 is 10 fF, the capacitance size of the test capacitance element Cs_8 is 0.078 fF.

[0015] In this embodiment, the basic operation of the test circuit 10 for testing the capacitance size of one test target capacitive element is divided into two periods: a first period and a second period. First, in the first period, the control circuit 120 turns on the switch Swt_1 corresponding to the test target capacitive element Ct_1 as shown in Fig. 1, and turns off the switches Swt_2 to Swt_n corresponding to the other test target capacitive elements Ct_2 to Ct_n. The control circuit 120 also turns on the switch Swr, sets the voltage of the signal Vtemp_1 to, for example, 5.0V, sets the voltages of the signals Bf_1 to Bf_m and Vref_A to 0V, and sets the voltage of the signal Vref_B to 30.0mV. Therefore, in the first period, the node B, that is, the positive input terminal (+) of the comparison circuit Cmp is 0V, while the negative input terminal (-) is 30.0mV, and the signal Cout becomes L level. It should be noted that the 0V of the signal Vref_A in the first period is an example of a first voltage. In the first period, one end and the other end of each of the test capacitance elements Cs_1 to Cs_8 are at the same potential, so that the charge stored in each of the test capacitance elements Cs_1 to Cs_8 is reset to zero.

[0016] Next, in a second period after the first period, the control circuit 120 turns off the switch Swr while keeping the switch Swt_1 on, as shown in Fig. 2. By turning off the switch Swr, the node Refin is disconnected from the node B. Furthermore, the control circuit 120 changes the voltage of the signal Bf_1 from 0 V to 5 V while maintaining the voltages of the signals Bf_2 to Bf_m at 0 V. Since the capacitance size of the test capacitive element Cs_1 is 10 fF, the charge that moves due to the voltage change of the signal Bf_1 is 50 fC (=5 V×10 fF).

[0017] As described above, when the test capacitive elements Cs_1 to Cs_8 are provided with m=8, the capacitance size seen from the node B is approximately 1020 fF. This capacitance size is a combined capacitance of 1000 fF of the test capacitive element Ct_1 and 20 fF of the test capacitive elements Cs_1 to Cs_8. Therefore, if the actual capacitance size of the test capacitance element CT_1 is correctly 1.00 pF, the voltage of node B will rise by 49.0 mV (50 fC / 1020 fF). Therefore, in the comparator circuit Cmp, the positive input terminal (+) is 49.0 mV, while the negative input terminal (-) is 30.0 mV, so the signal Cout is inverted to the H level.

[0018] On the other hand, if the actual capacitance size of the test capacitance element Ct_1 is 1.65 pF or more, the voltage of the node B in the second period is less than 30.0 mV, so that the signal Cout maintains the L level and is not inverted. Therefore, if the logic level of the signal Cout is maintained at the L level from the first period to the second period, the determination circuit 110 can determine that the actual capacitance size of the test capacitive element Ct_1 is 1.65 pF or more.

[0019] The signal Cout may be inverted to the H level if the actual capacitance of the test capacitance element Ct_1 is smaller than 1.00 pF and outside the expected range. Therefore, when the signal Cout is inverted to the H level in the second period, the control circuit 120 repeats the same operation again using a capacitance element smaller than the test capacitance element Cs_1, for example, the test capacitance element Cs_2. 1, the control circuit 120 turns on the switches Swt_1 and Swr and turns off the other switches Swt_2 to Swt_n, sets the voltage of the signal Vtemp_1 to 5.0 V, the voltages of the signals Bf_1 to Bf_m and Vref_A to 0 V, and sets the voltage of the signal Vref_B to 30.0 mV. As a result, the signal Cout becomes the L level again.

[0020] 3, in the second period, the control circuit 120 turns off the switch Swr while turning on the switch Swt_1, and changes the voltage of the signal Bf_2 from 0 V to 5 V while maintaining the voltages of the signals Bf_1, Bf_3 to Bf_m at 0 V. Since the capacitance size of the test capacitive element Cs_2 is 5 fF, the charge that moves due to the voltage change of the signal Bf_2 is 25 fC. For this reason, if the capacitance size of the test capacitance element CT_1 is 1.00 pF, the voltage of node B rises by 25 fC / 1020 fF, or 24.5 mV. Therefore, in the comparison circuit Cmp, the positive input terminal (+) is 24.5 mV, while the negative input terminal (-) is 30.0 mV, so the signal Cout maintains the L level. On the other hand, if the actual capacitance size of the test subject capacitive element Ct_1 is less than 0.814 pF, the voltage of the node B again becomes 30.0 mV or more in the second period, and the signal Cout is inverted to the H level.

[0021] Therefore, if the logical level of the signal Cout is maintained at the L level from the second period to the first period, the judgment circuit 110 can determine that the actual capacitance size of the test capacitance element Ct_1 is within an expected range including 1.00 pF, specifically, in the range of 0.814 pF or more and less than 1.65 pF. Furthermore, if the logic level of the signal Cout is inverted to the H level from the second period to the first period, the determination circuit 110 can determine that the actual capacitance size of the test subject capacitive element Ct_1 is less than 0.814 pF.

[0022] The test capacitive element Cs_1 is an example of a first test capacitive element, and the test capacitive element Cs_2 is an example of a second test capacitive element. If the signal Cout is inverted in the second determination, the control circuit 120 repeats the same operation again using a capacitance element smaller than the testing capacitance element Cs_2, for example, the testing capacitance element Cs_3. Although not shown in particular, in the third second period, the charge moved by the voltage change of the signal Bf_3 is 12.5 fC. Therefore, in the third determination, if the actual capacitance size of the test capacitance element Ct_1 is 0.398 pF or more, the signal Cout maintains the L level, and if it is less than 0.398 pF, the signal Cout is inverted to the H level. Therefore, if the logic level of the signal Cout is maintained at the L level in the third determination, it can be determined that the actual capacitance size of the test capacitance element Ct_1 is in the range of 0.398 pF or more and less than 0.814 pF. Also, if the logic level of the signal Cout is inverted to the H level in the third determination, it can be determined that the actual capacitance size of the test capacitance element Ct_1 is less than 0.398 pF.

[0023] Thereafter, when the logical level of signal Cout is inverted to H level, the test capacitance elements used for the test are switched in sequence to Ct_4, Ct_5, ..., Ct_8, and signal Cout is maintained at L level, thereby enabling the range in which the actual capacitance size of test capacitance element Ct_1 falls to be tested.

[0024] Note that, here, we have taken the example of selecting the test capacitive element Ct_1 as the target for testing among the test capacitive elements Ct_1 to Ct_n, but by selecting the test capacitive elements Ct_2, Ct_3, ..., Ct_n one by one in turn and performing the same operation, the test capacitive elements Ct_2 to Ct_n can also be tested in the same manner.

[0025] In the first embodiment, the amount of voltage change at node B when transitioning from the first period to the second period is the product of the quotient (capacitance ratio) obtained by dividing the capacitance size of the test capacitive element used by the sum of the capacitance size of the test capacitive element to be tested and the test capacitive elements Ct_1 to Ct_n, multiplied by the amount of voltage change in the test capacitive element. As described above, when one of the test capacitive elements Ct_1 to Ct_n is selected as the test target, if the voltage change amount of node B in the first test is less than that of signal Vref_B, the logic level of signal Cout is not inverted. If the capacitance size of the test capacitive element is maximum in a given test, it can only be tested whether the actual capacitance size of the test capacitive element selected as the test target is equal to or greater than a given value. Therefore, it is preferable to set the voltage of signal Vref_B to be less than the voltage change amount of node B.

[0026] In the first embodiment, the voltage of the signal Vref_B is constant at 30.0 mV in the first and second periods, but it may be varied. Specifically, in the first period, the control circuit 120 sets, for example, the signal Vref_B to a voltage equal to or higher than the voltage of the signal Vref_A, for example, 1.0 mV, which causes the signal Cout to go to the H level. Next, in the second period, the control circuit 120 changes the voltage of the signal Vref_B by gradually increasing it. When the voltage of the signal Vref_B gradually changes in the second period, the determination circuit 110 determines the actual capacitance size of the test capacitance element Ct_1 from the voltage a of the signal Vref_B when the signal Cout is inverted from the H level to the L level.

[0027] Specifically, if the voltage of the signal Vref_B when the signal Cout is inverted is a(V), the determination circuit 110 calculates the capacitance size X(fF) of the test capacitance element Ct_1 by the following equation (1). X = (50 - 20 a) / a … (1)

[0028] For example, if the voltage a of the signal Vref_B is 0.030 V (=30.0 mV) when the signal Cout is inverted, the determination circuit 110 determines that the capacitance size of the test capacitive element Ct_1 is 1650 fF (=1.65 pF) based on equation (1). Furthermore, if the voltage a of the signal Vref_B is 0.060V (=60.0mV) when the signal Cout is inverted, the determination circuit 110 determines the capacitance size of the test capacitive element Ct_1 to be 813fF (=0.813pF) based on the formula (1). For example, if the voltage a of the signal Vref_B is 0.061V (=60.1mV) when the signal Cout is inverted, the determination circuit 110 determines the capacitance size of the test capacitive element Ct_1 to be 800fF (=0.800pF) based on the formula (1). In other words, if the voltage a of the signal Vref_B when the signal Cout is inverted is in the range of 30.0 mV or more and less than 60.1 mV, the judgment circuit 110 can determine that the capacitance size of the test capacitance element Ct_1 is in the range of 0.814 pF or more and less than 1.65 pF.

[0029] If the voltage a of the signal Vref_B when the signal Cout is inverted is 0.049 V (=49.0 mV), the capacitance size of the test capacitance element Ct_1 is 1000 fF (=1.0 pF).

[0030] In this manner, in the configuration in which the voltage of the signal Vref_B is gradually changed in the second period and the capacitance size of the test capacitive element is tested based on the voltage a of the signal Vref_B when the logic level of the signal Cout is inverted, it is not necessary to repeat the first and second periods multiple times. Therefore, in this configuration, the capacitance size of the test capacitive element can be tested in a shorter time than in the configuration in which the first and second periods are repeated multiple times.

[0031] Alternatively, instead of gradually changing the voltage of the signal Vref_B in the second period, in the above example, the voltage may be switched between 30.0 mV and 60.1 mV and judged based on the logical level of the signal Cout. In detail, if the signal Cout inverts to the L level when the voltage of the signal Vref_B is 30.0 mV, and then inverts again to the H level when the voltage of the signal Vref_B is 60.1 mV, the capacitance size of the test capacitive element Ct_1 can be tested to be in the range of 0.814 pF or more and less than 1.65 pF. If the signal Cout is maintained at the H level when the voltage of the signal Vref_B is 30.0 mV in the second period, it can be determined that the capacitance size of the test capacitive element Ct_1 is 1.65 pF or more. If the signal Cout is at the L level when the voltage of the signal Vref_B is 60.1 mV, it can be determined that the capacitance size of the test capacitive element Ct_1 is less than 0.814 pF.

[0032] The voltages of 30.0 mV and 60.1 mV of the signal Vref_B in the second period are merely examples, and are determined by the lower and upper limits of the range of capacitance size that the test capacitive element must satisfy. In a fourth embodiment described below, 30.0 mV is an example of a first reference voltage, and 60.1 mV is an example of a second reference voltage.

[0033] In the first embodiment, only one of the test capacitance elements Cs_1 to Cs_m is used, but they may be used in combination as appropriate. For example, if two test capacitance elements Cs_1 and Cs_2 are used, the signals Bf_1 and Bf_2 may be changed from 0V to 5V in the second period. When the signals Bf_1 and Bf_2 are changed from 0V to 5V, the charge that moves is 75fC.

[0034] Furthermore, when, for example, the test capacitive element Ct_1 is selected as the test target among the test capacitive elements Ct_1 to Ct_n, a parasitic capacitance is added to the node B in addition to the test capacitive element Ct_1. In this case, in the first embodiment, since the switch Swt_1 is on in the first period and the second period, the parasitic capacitance can be treated as being connected in parallel to the test capacitive element Ct_1. Therefore, in the first embodiment, the test circuit 10 actually tests a combined capacitance including the parasitic capacitance and the test capacitive element selected as the test target.

[0035] [Second embodiment] In the first embodiment, signals Bf_1 to Bf_m are sequentially supplied to the other ends of the test capacitive elements Cs_1 to Cs_m, respectively. In this configuration, for example, when the test capacitive element Cs_1 is used to change the voltage of the signal Bf_1, the charge transfer caused by the voltage change also extends to the other test capacitive elements Cs_2 to Cs_m. Next, a second embodiment will be described in which the charge transfer caused by the voltage change is limited to only a limited number of test capacitance elements.

[0036] FIG. 4 is a circuit diagram showing a test circuit 10 and the like in the integrated circuit according to the second embodiment. 1, in the second embodiment, switches Sws_1 to Sws_m are provided in one-to-one correspondence with the testing capacitive elements Cs_1 to Cs_m in this order. Also, in the second embodiment, a signal Vref_B is supplied from the control circuit 120 to the determination circuit 110.

[0037] In the second embodiment, the switch Sws_1 is provided between the node B and the test capacitive element Cs_1. In detail, one end of the switch Sws_1 is connected to the node B, and the other end of the switch Sws_1 is connected to one end of the test capacitive element Cs_1. The switch Sws_2 is provided between the node B and the test capacitive element Cs_2, the switch Sws_3 is provided between the node B and the test capacitive element Cs_3, and similarly, the switch Sws_m is provided between the node B and the test capacitive element Cs_m. In the second embodiment, the other ends of the test capacitive elements Cs_1 to Cs_m are grounded to a potential Gnd that is a reference for a voltage of zero. Note that the other ends of the test capacitive elements Cs_1 to Cs_m are not limited to the potential Gnd, and may be kept at a substantially constant potential over time.

[0038] Next, the operation of the test circuit 10 according to the second embodiment will be described. For convenience, similarly to the first embodiment, a case will be described in which a test subject capacitive element Ct_1 is selected as a test target, and the capacitance size of the test subject capacitive element Ct_1 is approximately 1.00 pF.

[0039] In the second embodiment, the basic operation of the test circuit 10 for testing the capacitance size of one test target capacitive element is divided into three periods: a first period, a second period, and a third period. First, in the initial first period, the control circuit 120 turns on the switches Swt_1 and Swr, turns off the switches Swt_2 to Swt_n, and turns off the switches Sws_1 to Sws_m, as shown in FIG. Furthermore, the control circuit 120 sets the voltage of the signal Vtemp_1 to, for example, 5.0 V, the voltage of the signal Vref_A to 0 V, and the voltage of the signal Vref_B to a voltage less than 0 V. Note that the 0 V of the signal Vref_A in the second period is an example of a first voltage. In the first period, since the negative input terminal (-) is less than 0V with respect to 0V at node B, the signal Cout becomes H level.

[0040] In a second period after the first period, the control circuit 120 turns off the switch Swt_1 and turns on the switch Sws_1, as shown in Fig. 5. The control circuit 120 also changes the voltage of the signal Vref_A from 0 V to 1 V. By turning on the switch Sws_1, a charge of 10 fC is accumulated in the test capacitive element Cs_1. The 1 V of the signal Vref_A in the second period is an example of the second voltage. In the second period, the signal Cout is maintained at the H level.

[0041] In a third period after the second period, the control circuit 120 turns off the switch Swr and then turns on the switch Swt1, as shown in Fig. 6. If the capacitance size of the test capacitive element Ct_1 is X (fF), in the third period, the capacitance size of the combined capacitance of the test capacitive element Ct_1 and the test capacitive element Cs_1 is (X+10)fF as seen from the node B. The charge of 10fC accumulated in the test capacitive element Cs_1 in the second period is reallocated to the combined capacitance in the third period. Due to this reallocation, the voltage of the node B drops by {10 / (X+10)}V from 1V in the second period. Conversely, the voltage b of the node B in the third period can be expressed by the following equation (2). 1-b={10 / (X+10)} …(2)

[0042] By solving this equation (2) for X, we can express it as the following equation (3). X=10·b / (1-b) …(3) In the third period, the determination circuit 110 determines the actual capacitance size of the test subject capacitive element Ct_1 by substituting the voltage b of the signal Vref_B when the signal Cout is inverted from H to L level into the above equation (3). For example, if the voltage b of the signal Vref_B is 0.994V (=994mV) when the signal Cout is inverted, the determination circuit 110 determines that the capacitance size of the test capacitance element Ct_1 is 1657fF (=1.66pF) based on the equation (3). Furthermore, for example, if the voltage b of the signal Vref_B is 0.988V (=988mV) when the signal Cout is inverted, the determination circuit 110 determines that the capacitance size of the test capacitance element Ct_1 is 823fF (=0.823pF) based on the equation (3). In other words, if the voltage b of the signal Vref_B when the signal Cout is inverted is in the range of 988 mV or more and less than 994 mV, the judgment circuit 110 can certify that the capacitance size of the test capacitance element Ct_1 is in the range of 0.823 pF or more and less than 1.66 pF.

[0043] If the voltage b of the signal Vref_B when the signal Cout is inverted is 0.990 V (=990 mV), the capacitance size of the test capacitance element Ct_1 is 1000 fF (=1.0 pF).

[0044] Alternatively, instead of gradually changing the voltage of the signal Vref_B, the voltage of the signal Vref_B may be switched between two levels, 988 mV and 994 mV in the above example, during the third period, and the determination may be made based on the logical level of the signal Cout. In detail, if the signal Cout is at the H level when the voltage b of the signal Vref_B is 988 mV, and if the signal Cout is at the L level when the voltage b of the signal Vref_B is 994 mV, the capacitance size of the test capacitive element Ct_1 can be determined to be in the range of 0.823 pF or more and less than 1.66 pF. If the signal Cout is inverted to the L level when the voltage of the signal Vref_B is 994 mV, it can be determined that the capacitance of the test capacitive element Ct_1 is 1.66 pF or more. If the signal Cout is maintained at the H level when the voltage of the signal Vref_B is 988 mV, it can be determined that the capacitance of the test capacitive element Ct_1 is less than 0.823 pF.

[0045] The second embodiment is similar to the first embodiment in that the test subject capacitive elements to be tested are selected one by one, and that the test capacitive element is selected in accordance with the capacitance size of the test subject capacitive element to be tested. Also, the capacitance size of the test-subject capacitive element selected as the test target is tested together with the parasitic capacitance of node B, similarly to the first embodiment.

[0046] According to the second embodiment, the capacitance size of the test capacitive elements Cs_1 to Cs_m can be smaller than the capacitance size of the test capacitive element selected as the test subject capacitive element, so that the area of ​​the semiconductor substrate can be prevented from increasing.

[0047] [Third embodiment] Next, a third embodiment will be described.

[0048] FIG. 7 is a circuit diagram showing a test circuit 10 and the like in an integrated circuit according to the third embodiment. In the third embodiment, compared to the second embodiment shown in Fig. 4, switches Trd_1 to Trd_m are provided in one-to-one correspondence with the test capacitive elements Cs_1 to Cs_m. In detail, the switch Trd_1 is provided in correspondence with the test capacitive element Cs_1, the switch Trd_2 is provided in correspondence with the test capacitive element Cs_2, and similarly, the transistor Trd_m is provided in correspondence with the test capacitive element Cs_m. Here, if an integer i between 1 and m is used to generally describe the test capacitance elements Cs_1 to Cs_m and the switches Trd_1 to Trd_m, one end of the switch Trd_i is connected to one end of the test capacitance element Cs_i, and the other end of the switch Trd_i is connected to the other end of the test capacitance element Cs_i.

[0049] The switches Trd_1 to Trd_m are turned on or off individually by the control circuit 120. The switches Trd_1 to Trd_m are actually composed of transistors. Specifically, when the switch Trd_i is composed of a transistor, the drain node of the transistor is connected to one end of the test capacitive element Cs_i, the source node of the transistor is connected to the other end of the test capacitive element Cs_i, and a control signal specifying on or off is supplied from the control circuit 120 to the gate node of the transistor.

[0050] Next, the operation of the test circuit 10 according to the third embodiment will be described. For convenience, the description will be given assuming that the test subject capacitive element Ct_1 is selected as the test subject and the capacitance size of the test subject capacitive element Ct_1 is approximately 1.00 pF.

[0051] In the third embodiment, the basic operation of the test circuit 10 for testing the capacitance size of one test target capacitive element is divided into three periods: a first period, a second period, and a third period. First, in the initial first period, as shown in FIG. 7, the control circuit 120 turns on the switches Swt_1 and Swr, turns off the switches Swt_2 to Swt_n, turns off the switches Sws_1 to Sws_m, turns on the switch Trd_1, and turns off the switches Trd_2 to Trd_m. Moreover, the control circuit 120 sets the voltage of the signal Vtemp_1 to, for example, 5.0 V, the voltage of the signal Vref_A to 0 V, and the voltage of the signal Vref_B to less than 0 V. In the first period, the negative input terminal (-) is less than 0 V with respect to the 0 V of the node B, so that the signal Cout becomes the H level. Moreover, by turning on the switch Trd_1, the charge stored in the test capacitance element Cs_1 is reset to zero.

[0052] In a second period after the first period, the control circuit 120 turns off the switch Swt_1, turns on the switch Sws_1, and turns off the switch Trd_1, as shown in Fig. 8. The control circuit 120 also changes the voltage of the signal Vref_A from 0 V to 1 V. By turning on the switch Sws_1, a charge of 10 fC is accumulated in the test capacitance element Cs_1. In the second period, the signal Cout is maintained at the H level.

[0053] In a third period after the second period, the control circuit 120 turns off the switch Swr and then turns on the switch Swt1, as shown in Fig. 9. In addition, the control circuit 120 gradually increases the signal Vref_B from a voltage equal to or higher than 0 V. Other operations are similar to those of the second embodiment, and the judgment circuit 110 determines the actual capacitance size of the test capacitance element Ct_1 by substituting the voltage b of the signal Vref_B when the signal Cout is inverted from H to L level in the third period into the above equation (3).

[0054] In the third embodiment, similarly to the first and second embodiments, the test capacitive elements to be tested are selected one by one, and the test capacitive element is selected according to the capacitance size of the test capacitive element to be tested. Also, the capacitance size of the test-subject capacitive element selected as the test target is tested together with the parasitic capacitance of node B, similarly to the first and second embodiments.

[0055] According to the third embodiment, the capacitance size of the test capacitive elements Cs_1 to Cs_m can be smaller than the capacitance size of the test capacitive element selected as the test subject capacitive element, so that the area of ​​the semiconductor substrate can be prevented from increasing.

[0056] [Fourth embodiment] In the first to third embodiments, when testing the capacitance size of one test subject capacitive element, it was necessary to repeat the first and second periods two or more times, or to change the voltage of the signal Vref_B. Next, a fourth embodiment will be described in which it is not necessary to change the voltage of the signal Vref_B in the first and second periods when testing the capacitance size of a test subject capacitive element.

[0057] Fig. 10 is a circuit diagram of the integrated circuit according to the fourth embodiment, including the test circuit 10. The fourth embodiment differs from the first embodiment shown in Fig. 1 in that an AND circuit L1, a NOR circuit L2, and an EX-OR circuit L3 are added, and the comparison circuit Cmp includes comparators Cmp1 and Cmp2. The positive input terminal (+) of comparator Cmp1 and the positive input terminal (+) of comparator Cmp2 are connected to node B. A signal Vref_B1 is supplied to the negative input terminal (-) of comparator Cmp1, and a signal Vref_B2 is supplied to the negative input terminal (-) of comparator Cmp2. Comparators Cmp1 and Cmp2 output an H-level signal if the voltage applied to their positive input terminals (+) is equal to or greater than the voltage applied to their negative input terminals (-), and output an L-level signal if the voltage applied to their positive input terminals (+) is less than the voltage applied to their negative input terminals (-). The comparator Cmp1 is an example of a first comparator, and the comparator Cmp2 is an example of a second comparator. The voltages of the signals Vref_B1 and Vref_B2 are approximately constant over time, and the voltage of the signal Vref_B1 is higher than the voltage of the signal Vref_B2 by α.

[0058] The voltage of the signal Vref_B1 and the voltage of the signal Vref_B2 are voltages whose nature is determined by the upper and lower limits of the range of capacitance size that the test capacitive element should satisfy. The voltage of the signal Vref_B1 is an example of a first reference voltage, and the voltage of the signal Vref_B2 is an example of a second reference voltage. Moreover, the output signal of the comparator Cmp1 is an example of a first comparison result signal, and the output signal of the comparator Cmp2 is an example of a second comparison result signal.

[0059] The AND circuit L1 obtains a logical AND of the output signal of the comparator Cmp1 and the output signal of the comparator Cmp2 and outputs it as a signal Out1. The NOR circuit L2 obtains a NOR of the output signal of the comparator Cmp1 and the output signal of the comparator Cmp2 and outputs it as a signal Out2. The EX-OR circuit L3 obtains an exclusive OR of the output signal of the comparator Cmp1 and the output signal of the comparator Cmp2 and outputs it as a signal Out3.

[0060] Although not shown, the power supply voltage of the comparators Cmp1, Cmp2, the AND circuit L1, the NOR circuit L2, and the EX-OR circuit L3 is preferably a low voltage (for example, 1.8 V).

[0061] In this configuration, if the voltage of node B in the second period is lower than the voltage of signal Vref_B2, signal Out2 goes to H level and signals Out1 and Out3 go to L level. In other words, the fact that signal Out2 is at H level in the second period indicates that the actual capacitance size of the test target capacitive element selected as the test target is larger than the upper limit of the range of capacitance size to be satisfied (the upper limit corresponding to the voltage of signal Vref_B1). Furthermore, if the voltage of node B in the second period is equal to or higher than the voltage of signal Vref_B2 and lower than the voltage of signal Vref_B1, signal Out3 goes to H level and signals Out1 and Out2 go to L level. In other words, the fact that signal Out3 is H level in the second period indicates that the actual capacitance size of the test target capacitive element selected as the test target falls within the range of capacitance sizes that should be satisfied. If the voltage of node B in the second period is equal to or higher than the voltage of signal Vref_B1, signal Out1 goes to H level, and signals Out2 and Out3 go to L level. In other words, in the second period, signal Out1 being at H level indicates that the actual capacitance size of the test subject capacitive element selected as the test target is smaller than the lower limit of the range of capacitance size to be satisfied (the lower limit corresponding to the voltage of signal Vref_B2).

[0062] The parasitic capacitance of node B in the fourth embodiment is similar to that in the first to third embodiments.

[0063] [Fifth embodiment] The voltages of the signals Vref_B1 and Vref_B2 in the second embodiment are generated, for example, according to the following fifth embodiment.

[0064] 11 is a circuit diagram of the peripheral circuit including the test circuit 10 in the integrated circuit according to the fifth embodiment. The fifth embodiment has memory circuits M1 and M2, an adder Ad, and DA converters Da1 and Da2, in comparison with the fourth embodiment shown in FIG. The memory circuit M1 stores data RefD indicating the voltage data of the signal Vref_B2. The memory circuit M2 stores data αD indicating the offset value of the voltage of the signal Vref_B2, specifically, a voltage equivalent to α. The adder Ad adds the data RefD and the data αD. The DA converter Da1 converts the data output from the adder Ad into an analog signal Vref_B1 and supplies the signal Vref_B1 to the negative input terminal (-) of the comparator Cmp1. The DA converter Da2 converts the data RefD into an analog signal Vref_B2 and supplies the signal Vref_B2 to the negative input terminal (-) of the comparator Cmp2.

[0065] In the fifth embodiment, the voltage of the signal Vref_B1 is calculated by adding data RefD indicating the voltage of the signal Vref_B2 with data αD indicating a voltage equivalent to α, and the output data indicating the sum is converted to analog, but this is not the only possible configuration. For example, the voltage of the signal Vref_B2 may be calculated by adding data equivalent to -α to data RefD indicating the voltage of the signal Vref_B1, and the sum may be converted to analog. That is, in this description, the adder is used to mean not only addition but also subtraction. In the fifth embodiment, the data RefD and the data αD can be changed as appropriate. Therefore, according to the fifth embodiment, the expected (allowable) capacity range can be easily changed compared to a configuration that does not use the DA converters Da1 and Da2. Furthermore, in the fifth embodiment, even if there is variation in the output characteristics of the DA converters Da1 and Da2, the influence of the variation can be suppressed by appropriately correcting the data RefD and the data αD.

[0066] In the fourth or fifth embodiment, two comparators and three logic circuits, specifically, comparators Cmp1, Cmp2, AND circuit L1, NOR circuit L2, and EX-OR circuit L3, are used to check whether the voltage of node B is in a range equal to or greater than the voltage of signal Vref_B2 and less than the voltage of signal Vref_B1, or if it is outside the range, whether it is lower or higher than the range. The present invention is not limited to this configuration, and the number of comparators and logic circuits may be increased to check whether the voltage is included in any of a plurality of voltage ranges, or if it is outside the plurality of voltage ranges, whether it is lower or higher than the range. The parasitic capacitance of node B in the fifth embodiment is the same as that in the fourth embodiment.

[0067] [Sixth embodiment] In the test circuit 10, the voltage change of the node B is determined by the comparison circuit Cmp, etc., but in such a configuration, there are cases where the voltage of the node B needs to be outputted to the outside of the integrated circuit. Next, a sixth embodiment will be described in which the voltage of the node B is outputted to the outside.

[0068] FIG. 12 is a peripheral circuit diagram including a test circuit 10 in an integrated circuit according to a sixth embodiment. In the sixth embodiment, compared to the first embodiment shown in FIG. 1, an impedance converter Imc is included and a terminal Ext_N is provided. The impedance converter Imc is, for example, a non-inverting amplifier circuit. Specifically, the impedance converter Imc has a positive input terminal (+) connected to node B and an output terminal connected to the terminal Ext_N and the negative input terminal (-). The terminal Ext_N is a terminal for outputting to the outside of the integrated circuit.

[0069] According to the sixth embodiment, even if node B has a relatively high impedance, it is converted to a relatively low impedance by the impedance converter Imc and output to the terminal Ext_N. Therefore, if the terminal Ext_N is connected to a measuring instrument or the like other than the integrated circuit, it becomes possible to inspect the circuit connected to node B before the comparator circuit Cmp based on the voltage of node B output from the terminal Ext_N.

[0070] [Seventh embodiment] Fig. 13 is a circuit diagram of the integrated circuit according to the seventh embodiment, including the test circuit 10. In the seventh embodiment, a switch Swo is provided in comparison with the sixth embodiment shown in Fig. 12. In detail, the switch Swo is provided between the node B and the terminal Ext_N, and is controlled to be turned on or off by the control circuit 120.

[0071] When the switch Swo is off, the voltage of node B is output to the terminal Ext_N, as in the sixth embodiment. For this reason, if the terminal Ext_N is connected to a measuring instrument or the like other than the integrated circuit, it becomes possible to inspect the circuit connected to node B before the comparator circuit Cmp, based on the voltage of node B output from the terminal Ext_N. On the other hand, if the switch Swo is on, a predetermined voltage can be applied to the node B via the terminal Ext_N by a measuring instrument or the like separate from the integrated circuit. This makes it possible to inspect the circuits connected after the comparison circuit Cmp by the measuring instrument or the like.

[0072] [Eighth embodiment] FIG. 14 is a circuit diagram showing a test circuit 10 and the like in the integrated circuit according to the eighth embodiment. In the eighth embodiment, a switch Swo and a terminal Ext_N are provided, as compared to the first embodiment shown in Fig. 1. The switch Swo is provided between the negative input terminal (-) of the comparison circuit Cmp and the output terminal of the comparison circuit Cmp, and is controlled to be on or off by the control circuit 120. The terminal Ext_N is a terminal for outputting to the outside of the integrated circuit or a terminal for inputting a signal from the outside, and is connected to the output terminal of the comparison circuit Cmp.

[0073] In this configuration, if the switch Swo is on, the comparison circuit Cmp functions as a non-inverting amplifier circuit as in the sixth embodiment. Therefore, it is possible to connect a measuring instrument or the like other than the integrated circuit to the terminal Ext_N and to inspect a circuit connected to node B upstream of the comparison circuit Cmp based on the voltage of node B output from the terminal Ext_N.

[0074] [Example of application to display devices] Next, a display device to which an integrated circuit including the test circuit 10 is applied will be described. FIG. 15 is a block diagram showing the electrical configuration of the display device DM, FIG. 16 is a perspective view showing the configuration of the display device DM excluding the printed circuit board 40, and FIG. 17 is a diagram showing the configuration of a pixel circuit 210 in the liquid crystal panel 20.

[0075] 15, the display device DM includes a liquid crystal panel 20, an FPC board 30, and a printed circuit board 40. Note that FPC is an abbreviation for Flexible Printed Circuits. The liquid crystal panel 20 is a transmissive type used, for example, as a light valve of a liquid crystal projector. In the liquid crystal panel 20, a Y driver 230 is provided on the periphery of a display area 200. In the display area 200, pixel circuits 210 corresponding to pixels of an image to be displayed are arranged in a matrix. In detail, in the display area 200, a plurality of scanning lines 212 are provided extending in the X direction in the figure, and a plurality of data lines 214 are provided extending in the Y direction and electrically insulated from the scanning lines 212. Then, pixel circuits 210 are provided corresponding to intersections of the plurality of scanning lines 212 and the plurality of data lines 214.

[0076] If the number of scanning lines 212 is m and the number of data lines 214 is n, the pixel circuits 210 are arranged in a matrix of m rows and n columns. Both m and n are integers of 2 or more. In order to distinguish the rows of the matrix in the scanning lines 212 and the pixel circuits 210, they may be referred to as 1, 2, 3, ..., (m-1), m rows from the top in the figure. Similarly, in order to distinguish the columns of the matrix in the data lines 24 and the pixel circuits 210, they may be referred to as 1, 2, 3, ..., (n-1), n ​​columns from the left in the figure. The Y driver 230 selects the scanning lines 212 one by one in the order of, for example, the 1st, 2nd, 3rd, ..., mth rows in accordance with a control signal supplied via the FPC board 30, and sets the scanning signal to the selected scanning line 212 to H level. Note that the Y driver 230 sets the scanning signals to the scanning lines 212 other than the selected scanning line 212 to L level.

[0077] For convenience of explanation, the configuration of the pixel circuit 210 will be described. 17, the pixel circuit 210 includes a transistor 216 and a liquid crystal element 220. The transistor 216 is, for example, an n-channel thin film transistor. In the pixel circuit 210, a gate node of the transistor 216 is connected to a scanning line 212. A source node of the transistor 216 is connected to a data line 214. A drain node of the transistor 216 is connected to a pixel electrode 218 patterned into a substantially square shape in a plan view.

[0078] A common electrode 208 is provided in common to all pixels so as to face the pixel electrode 218. A voltage LCcom is applied to the common electrode 208. A liquid crystal 205 is sandwiched between the pixel electrode 218 and the common electrode 208. Therefore, for each pixel circuit 210, a liquid crystal element 220 is formed by the pixel electrode 218, the common electrode 208, and the liquid crystal 205.

[0079] As described later, during a horizontal scanning period when the scanning signal to a certain scanning line 212 is at H level, the data line driving circuit 240 supplies a data signal of a voltage corresponding to the gradation of the pixel to be expressed by the pixel circuit 210 to the data line 214 corresponding to the pixel circuit 210 located on that scanning line 212.

[0080] In the scanning line 212 where the scanning signal is at H level, the transistor 216 of the pixel circuit 210 provided corresponding to the scanning line 212 is turned on. When the transistor 216 is turned on, the data line 214 and the pixel electrode 218 are electrically connected, so that the data signal supplied to the data line 24 reaches the pixel electrode 218 via the turned-on transistor 216. When the scanning line 212 becomes L level, the transistor 116 is turned off, but the voltage of the data signal that has reached the pixel electrode 118 is held by the capacitance of the liquid crystal element 220.

[0081] As is well known, in the liquid crystal element 220, the orientation state of the liquid crystal 205 changes in response to the electric field generated by the pixel electrode 218 and the common electrode 208. Therefore, the liquid crystal element 220 has a transmittance (optical state) that corresponds to the effective value of the applied voltage. Therefore, in the liquid crystal panel 20, the transmittance changes for each liquid crystal element 220 of the pixel circuit 210. Such a voltage holding operation on the liquid crystal elements 220 is performed in the order of the 1st, 2nd, 3rd, ..., mth rows, so that a voltage corresponding to a data signal is held in each of the liquid crystal elements 220 of the pixel circuits 210 arranged in m rows and n columns. By holding the voltage in this manner, each of the liquid crystal elements 220 has a target transmittance, and an image made up of pixels arranged in m rows and n columns is generated.

[0082] 16, the integrated circuit 1 is a semiconductor chip having a substantially rectangular parallelepiped shape, and is mounted by face-down bonding on an FPC board 30. The liquid crystal panel 20 is housed in a frame-shaped case 22 that is open in the display area. One end of the FPC board 30 is connected to the liquid crystal panel 20. The other end of the FPC board 30 is connected to a printed circuit board 40.

[0083] Returning to Fig. 15, the printed circuit board 40 includes a control circuit 400. The control circuit 400 receives grayscale data and a synchronization signal from a higher-level circuit (not shown). The grayscale data specifies the grayscale level of a pixel in an image to be displayed digitally, for example, in 8 bits. The control circuit 400 supplies a control signal generated based on the synchronization signal to the Y driver 230 via the FPC board 30. Moreover, the control circuit 400 supplies the integrated circuit 1 with a control signal generated in accordance with the grayscale data and a synchronization signal.

[0084] The integrated circuit 1 includes a driver circuit that generates analog data signals from grayscale data for one row and supplies the analog data signals to each of the data lines 214, in addition to the test circuit 10 according to any one of the first to eighth embodiments described above. The driver circuit includes a test target capacitive element that is to be tested.

[0085] 18 is a block diagram showing a configuration of the integrated circuit 1. The integrated circuit 1 includes a test circuit 10 according to any one of the first to eighth embodiments described above, a plurality of driver circuits Drv, a data input circuit 12, and a data controller 14. The driver circuits Drv are provided in one-to-one correspondence with the data lines 214. When the number of data lines 214 is a plurality of n, the number of driver circuits Drv also becomes a plurality of n. The data input circuit 12 is an interface for inputting grayscale data and a synchronization signal supplied from the control circuit 400 via the FPC board 30. The data controller 14 distributes the grayscale data supplied via the data input circuit 12 to the n driver circuits Drv in accordance with the synchronization signal supplied via the data input circuit 12.

[0086] The n driver circuits Drv are arranged along the long side of the integrated circuit 1. As shown in Fig. 15 and Fig. 16, the integrated circuit 1 is mounted on the FPC board 30 so that the long side of the integrated circuit 1 is aligned with the X direction, which is the extension direction of the scanning lines 212, and therefore the n driver circuits Drv are also provided along the extension direction of the scanning lines 212. Note that the X direction, which is the extension direction of the scanning lines 212, is an example of a predetermined direction.

[0087] The test circuit 10 is provided in the integrated circuit 1 next to an area in which n driver circuits Drv are arranged along the extension direction of the scanning line 212. The test circuit 10 tests the capacitance size of a test target capacitive element included in each of the n driver circuits Drv, and adjusts parameters in each of the n driver circuits Drv based on the tested capacitance size. Examples of the parameters will be described later.

[0088] Each driver circuit Drv latches the grayscale data supplied corresponding to the column of the driver circuit Drv and converts the grayscale data into an analog data signal. Each of the n driver circuits Drv simultaneously outputs the converted data signal in accordance with the selection of the scanning line 212 by the Y driver 230.

[0089] 19 is a diagram showing a schematic configuration of a driver circuit Drv provided corresponding to the j-th column data line 214. The driver circuit Drv includes an arithmetic circuit Air_j, a latch circuit Lat_j, a DA conversion circuit Dac_j, and an amplifier circuit Amp_j. The arithmetic circuit Air_j performs arithmetic operations on the grayscale data supplied corresponding to the j-th column. Examples of such arithmetic operations include conversion to data suitable for the liquid crystal panel 100 and arithmetic operations to suppress variations. The latch circuit Lat_j latches the grayscale data that has been subjected to calculations and the like until the scanning line 212 is selected by the Y driver 230. The DA conversion circuit Dac_j converts the latched gray scale data into an analog signal. The amplifier circuit Amp_j appropriately amplifies the analog signal and outputs it as a data signal to the data line 214 in the j-th column.

[0090] In FIG. 19, the elements of the arithmetic circuit Air_j, the latch circuit Lat_j, the DA conversion circuit Dac_j, and the amplifier circuit Amp_j are not connected to each other in order to indicate that other elements may be present between these elements.

[0091] The test capacitance element Ct in the driver circuit Drv can be a capacitance element included in the DA conversion circuit Dac_j. Specifically, the DA conversion circuit Dac_j can be configured with a driver described in JP 2016-80805 A or a driver described in JP 2016-90882 A, and various capacitors constituting these drivers can be used as the test capacitance element. Therefore, the number of test-subject capacitive elements in one driver circuit Drv is one or more.

[0092] The test circuit 10 selects the n driver circuits Drv one by one in order, and further selects the capacitive elements included in the selected driver circuits Drv one by one in a predetermined order as test objects, and tests the capacitance sizes of the selected capacitive elements. Then, the control circuit 120 in the test circuit 10 adjusts the parameters of the selected driver circuit Drv according to the tested capacitance size.

[0093] Specifically, when the control circuit 120 selects the jth column driver circuit Drv and selects the capacitive element included in the driver circuit Drv as the test target, it adjusts the parameters specifying the calculation content of the arithmetic circuit Air_j included in the jth column driver circuit Drv, the gain of the amplifier circuit Amp_j, and the reference current, reference voltage, etc. in these elements, according to the capacitance size of the capacitive element.

[0094] The periods inspected by the control circuit 120 include periods that do not affect the display, specifically, horizontal and vertical scanning blanking periods, if they are display periods. The horizontal scanning blanking period is the period from the end of selection of one scanning line 212 to the start of selection of the next scanning line 212. The vertical scanning blanking period is the period from the end of selection of the last scanning line 212 in one frame to the start of selection of the first scanning line 212 in the next frame. In general, since the vertical scanning blanking period is longer than the horizontal scanning blanking period, it is possible to continuously test the capacitance sizes of more capacitive elements in the vertical scanning blanking period than in the horizontal scanning blanking period.

[0095] 15, the driver circuits Drv in one-to-one correspondence with the data lines 214 supply data signals to the data lines 214, but the present invention is not limited to this configuration. For example, one driver circuit Drv may be associated with k data lines 214, and data signals may be supplied to the k data lines 214 in one horizontal scanning period in a time-division manner. Here, k is any integer equal to or greater than 2.

[0096] 15, the display device DM has a configuration in which the integrated circuit 1 is mounted on the FPC board 30 and the liquid crystal panel 20 and the integrated circuit 1 are separate, but the present invention is not limited to this configuration. For example, as shown in Fig. 20, the function of the integrated circuit 1 may be transferred to the liquid crystal panel 20. Specifically, the element substrate in the liquid crystal panel 20 may be a semiconductor substrate, and the semiconductor substrate may have the function of the integrated circuit 1. The display device DM is not limited to the liquid crystal panel 100, and can also be applied to an organic EL panel using an OLED. In the organic EL panel, it is preferable that the semiconductor substrate constituting the organic EL panel has the function of the integrated circuit 1. [Explanation of symbols]

[0097] 1...integrated circuit, 10...test circuit, 20...liquid crystal panel, 30...FPC board, 40...printed board, 110...judgment circuit, 120...control circuit, Ct_1 to Ct_n, Ct...capacitive element to be tested, Cs_1 to Cs_m...capacitive elements for testing, Cmp...comparison circuit, Cmp1, Cmp2...comparator, Ext_N...terminal.

Claims

1. The test subject capacitance element and the test circuit are included in the same semiconductor substrate; an integrated circuit in which one end of the test subject capacitance element is maintained at a predetermined voltage, The test circuit includes: A test capacitance element; a comparison circuit for comparing a voltage at an input node with a predetermined reference voltage; Including, one end of the test capacitance element is connected to an input node of the comparison circuit, The test circuit includes: In the first period, The other end of the test subject capacitance element is connected to an input node of the comparison circuit; applying a first voltage to the input node; resetting the charge stored in the test capacitance element to zero; a first node to which the first voltage is applied is connected to an input node of the comparison circuit; During a second period of time subsequent to the first period of time, disconnecting the first node from an input node of the comparison circuit; a voltage applied to the other end of the test capacitive element is changed to change a voltage at an input node of the comparison circuit based on a capacitance ratio between the test capacitive element and the test capacitive element; The capacitance size of the test capacitive element is verified based on the comparison result of the comparator. Integrated circuits.

2. The test subject capacitance element and the test circuit are included in the same semiconductor substrate; an integrated circuit in which one end of the test subject capacitance element is maintained at a predetermined voltage, The test circuit includes: A test capacitance element; a comparison circuit for comparing a voltage at an input node with a predetermined reference voltage; Including, In the first period, The other end of the test subject capacitance element is connected to an input node of the comparison circuit; applying a first voltage to the input node; a first node to which the first voltage is applied is connected to an input node of the comparison circuit; one end of the test capacitance element is disconnected from the input node of the comparison circuit; During a second period of time subsequent to the first period of time, The other end of the test subject capacitance element is disconnected from the input node of the comparison circuit; one end of the test capacitance element is connected to an input node of the comparison circuit; changing a voltage applied to the first node from the first voltage to a second voltage; During a third period following the second period, disconnecting the first node from an input node of the comparison circuit; a capacitance ratio of the test capacitance element to the test capacitance element, and a voltage of the input node of the comparison circuit is changed based on the capacitance ratio of the test capacitance element and the test capacitance element; The capacitance size of the test capacitive element is verified based on the comparison result of the comparator. Integrated circuits.

3. The test circuit includes: During the second period, resetting the charge stored in the test capacitive element to zero; 3. The integrated circuit of claim 2.

4. Including a determination circuit, the comparison circuit includes a first comparator and a second comparator; the reference voltage includes a first reference voltage and a second reference voltage that is different from the first reference voltage; the first comparator compares a voltage of the input node with the first reference voltage and outputs a first comparison result signal indicating a comparison result; the second comparator compares the voltage of the input node with the second reference voltage and outputs a second comparison result signal indicative of the comparison result; The determination circuit determines, based on the first comparison result signal and the second comparison result signal, whether a voltage change based on a capacitance ratio at the input node is smaller than a predetermined range, is within the predetermined range, or is larger than the predetermined range.

4. An integrated circuit according to claim 1.

5. an adder that adds an offset value to voltage data that specifies the first reference voltage; a first DA converter that converts the voltage data into the first reference voltage; a second DA converter for converting the output data of the adder into the second reference voltage; 5. The integrated circuit of claim 4, comprising:

6. An impedance converter that converts the impedance of the input node and outputs the converted impedance to a terminal.

6. An integrated circuit according to any one of claims 1 to 5.

7. A plurality of driver circuits each including the test subject capacitance element are arranged along a predetermined direction; The test circuit includes: The driver circuits are arranged in an area adjacent to the area in the predetermined direction.

7. An integrated circuit according to any preceding claim.

8. the driver circuit generates a data signal having a voltage corresponding to grayscale data by using the test capacitance element; The data signal is output to a pixel circuit that is in an optical state corresponding to the voltage of the data signal.

8. The integrated circuit of claim 7.

9. a plurality of data lines, the driver circuit, and the pixel circuit; the driver circuits are provided corresponding to the plurality of data lines; The pixel circuits are provided corresponding to the plurality of data lines.

9. The integrated circuit of claim 8.

10. The test subject capacitance element and the test circuit are included in the same semiconductor substrate; an integrated circuit in which one end of the test subject capacitance element is maintained at a predetermined voltage, The test circuit includes: A test capacitance element; a comparison circuit for comparing a voltage at an input node with a predetermined reference voltage; Including, In the first period, The other end of the test subject capacitance element is connected to an input node of the comparison circuit; applying a first voltage to the input node; During a second period of time subsequent to the first period of time, changing a voltage of an input node of the comparison circuit based on a capacitance ratio between the test capacitance element and the test capacitance element; testing the capacitance size of the test subject capacitive element based on the comparison result of the comparison circuit; The capacitance size of the test capacitive element is larger than the capacitance size of the test capacitive element. Integrated circuits.

11. the test subject capacitive element is a plurality of elements, the test capacitance element is a plurality of elements, The number of the test capacitive elements is greater than the number of the test capacitive elements.

11. The integrated circuit of claim 10.

12. The test subject capacitance element and the test circuit are included in the same semiconductor substrate; an integrated circuit in which one end of the test subject capacitance element is maintained at a predetermined voltage, The test circuit includes: A test capacitance element; a comparison circuit for comparing a voltage at an input node with a predetermined reference voltage; Including, In the first period, The other end of the test subject capacitance element is connected to an input node of the comparison circuit; applying a first voltage to the input node; During a second period of time subsequent to the first period of time, changing a voltage of an input node of the comparison circuit based on a capacitance ratio between the test capacitance element and the test capacitance element; testing the capacitance size of the test subject capacitive element based on the comparison result of the comparison circuit; the test capacitive element includes a first test capacitive element and a second test capacitive element; a capacitance size of the first test capacitive element is different from a capacitance size of the second test capacitive element, A capacitance size of the test capacitance element is tested based on a comparison result of the comparator circuit when a voltage change based on the capacitance ratio is generated using the first test capacitance element and a comparison result of the comparator circuit when a voltage change based on the capacitance ratio is generated using the second test capacitance element. Integrated circuits.

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