Light emitting body, method and apparatus for manufacturing light emitting body, light emitting element and method for manufacturing the same, and electronic device

Abstract

The light-emitting body comprises: a base semiconductor part that contains a nitride semiconductor; a compound semiconductor part that contains a nitride semiconductor and that is located above the base semiconductor part; and a first electrode and a second electrode. The base semiconductor part has a first part and a second part for which the density of threading dislocations that extend in the thickness direction is smaller than that of the first part. At least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor part, and at least a portion of the first electrode is located above the second part.

Description

[Technical field]

[0001] The present disclosure relates to light emitters. [Background technology]

[0002] In the nitride semiconductor laser described in Patent Document 1, an anode and a cathode are formed on one side of a chip including a semiconductor layer. If the current path from the anode to the cathode includes a portion parallel to the c-plane of the semiconductor layer, the light emission efficiency decreases. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2000-49415 Summary of the Invention

[0004] The light emitting body according to the present disclosure comprises a base semiconductor portion including a nitride semiconductor, a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion, and a first electrode and a second electrode, wherein the base semiconductor portion has a first portion and a second portion in which the density of threading dislocations extending in the thickness direction is lower than that of the first portion, and at least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor portion, and at least a portion of the first electrode is located above the second portion. [Brief description of the drawings]

[0005] [Figure 1] FIG. 2 is a perspective view showing a configuration of a light emitter according to the embodiment. [Diagram 2] 1 is a schematic diagram illustrating a configuration of a light-emitting device according to an embodiment of the present invention. [Diagram 3] 4 is a flowchart showing an example of a method for manufacturing a light-emitting body according to the present embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of a manufacturing apparatus for a light-emitting body according to the present embodiment. [Diagram 5] 1 is a perspective view showing a configuration of a light emitter according to Example 1. FIG. [Figure 6] FIG. 2 is a plan view showing a configuration of a compound semiconductor portion. [Figure 7] 1 is a cross-sectional view showing a configuration of a light emitter according to Example 1. FIG. [Figure 8] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 9] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 10] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 11] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 12] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 13] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 14] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 15] 4 is a cross-sectional view showing another configuration of the light emitter of Example 1. FIG. [Figure 16] FIG. 4 is a perspective view showing another configuration of the light emitter of Example 1. [Figure 17] 17A and 17B are top and cross-sectional views of FIG. 16. [Figure 18] FIG. 4 is a perspective view showing another configuration of the light emitter of Example 1. [Figure 19] 19A and 19B are top and cross-sectional views of FIG. 18. [Figure 20] 1 is a cross-sectional view showing a configuration of a light-emitting element according to Example 1. FIG. [Figure 21] 1 is a perspective view showing a configuration of a light emitting element according to Example 1. FIG. [Figure 22] 4 is a cross-sectional view showing another configuration of the light-emitting device according to the first embodiment. FIG. [Figure 23] 4 is a cross-sectional view showing another configuration of the light-emitting device according to the first embodiment. FIG. [Figure 24] 4 is a cross-sectional view showing another configuration of the light-emitting device according to the first embodiment. FIG. [Diagram 25]1 is a perspective view showing a configuration of a light emitting substrate (semiconductor laser array) according to Example 1. FIG. [Figure 26] 4 is a perspective view showing another configuration of the light emitting substrate according to the first embodiment. FIG. [Figure 27] 4 is a flowchart showing an example of a method for manufacturing the light emitting device according to the first embodiment. [Figure 28] 28A to 28C are schematic cross-sectional views showing a method for manufacturing the light-emitting device of FIG. 27. [Figure 29] 28 is a plan view illustrating a method for manufacturing the light-emitting device of FIG. 27. [Diagram 30] 5A to 5C are schematic cross-sectional views showing another example of the method for manufacturing the light-emitting device according to the first embodiment. [Diagram 31] 5A to 5C are schematic cross-sectional views showing another example of the method for manufacturing the light-emitting device according to the first embodiment. [Diagram 32] 3 is a cross-sectional view showing an example of lateral growth of a base semiconductor portion (ELO semiconductor layer) in Example 1. FIG. [Diagram 33] 1 is a cross-sectional view showing the configuration of a light-emitting body according to Example 2. FIG. [Diagram 34] FIG. 11 is a perspective view showing a configuration of a light-emitting module according to a fourth embodiment. [Diagram 35] FIG. 11 is a perspective view showing another configuration of the light-emitting module according to the fourth embodiment. [Diagram 36] FIG. 13 is a schematic diagram illustrating a configuration of an electronic device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Light emitter] FIG. 1 is a perspective view showing the configuration of a light emitter according to this embodiment. As shown in FIG. 1, the light emitter 21 according to this embodiment includes a base semiconductor section 8 including a nitride semiconductor, a compound semiconductor section 9 including a nitride semiconductor and located above the base semiconductor section 8, and a first electrode E1 and a second electrode E2. The base semiconductor section 8 has a first section B1 and a second section B2 in which the density of threading dislocations extending in the thickness direction (Z direction) is lower than that of the first section B1. At least a part of the first electrode E1 and at least a part of the second electrode E2 are located on the compound semiconductor section 9. At least a part of the first electrode E1 may be located above the second section B2. Hereinafter, the direction from the base semiconductor section 8 to the compound semiconductor section 9 is defined as the upward direction. In the light emitter 21, the base semiconductor section 8 may be the base semiconductor layer 8, and the compound semiconductor section 9 may be the compound semiconductor layer 9. The light emitter 21 may be a light emitting diode (LED) chip or a semiconductor laser chip.

[0007] Since the base semiconductor portion 8 of the light emitter 21 includes the second portion B2 (low-defect portion) having a low density of threading dislocations, the light emission efficiency and reliability can be improved in a configuration in which the first and second electrodes E1 and E2 are provided on one side of the chip. This is because threading dislocations cause heat generation.

[0008] In this embodiment, the second portion B2 of the base semiconductor portion 8 and the first electrode E1 may overlap in a plan view. "Two members overlap" means that at least a portion of one member overlaps the other member in a plan view (including a perspective plan view) seen in the thickness direction of each member, and these members may or may not be in contact with each other.

[0009] The nitride semiconductor included in the base semiconductor portion 8 and the compound semiconductor portion 9 can be expressed as, for example, AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductor, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor portion 8 may be a doped type (e.g., n-type containing donors) or a non-doped type.

[0010] The base semiconductor portion 8 including a nitride semiconductor can be formed by an ELO (Epitaxial Lateral Overgrowth) method. In the ELO method, for example, the base semiconductor portion 8 is grown laterally on a template substrate having a mask pattern (selective growth mask) including an opening and a mask portion (described later). In this way, a low-defect portion (second portion B2) having a low threading dislocation density can be formed on the mask portion. The number of threading dislocations (dislocations extending in the thickness direction) inherited by the compound semiconductor portion 9 (for example, a GaN-based semiconductor layer) on the second portion B2 is reduced, and thus the light emission efficiency can be improved.

[0011] [Light Emitting Devices] 2 is a schematic diagram showing the configuration of a light emitting device according to this embodiment. The light emitting substrate 22 according to this embodiment includes a plurality of light emitting bodies 21 (chips) and a support substrate SK on which the plurality of light emitting bodies 21 are mounted. The light emitting element 23 according to this embodiment includes one or more light emitting bodies 21 and a support body ST on which the one or more light emitting bodies 21 are mounted. Hereinafter, the light emitting body 21, the light emitting substrate 22, the light emitting element 23, and a light emitting module described later may be collectively referred to as a light emitting device.

[0012] [Manufacture of luminous body] Fig. 3 is a flow chart showing an example of a method for manufacturing a light emitter according to this embodiment. In the manufacturing method shown in Fig. 3, after a step of preparing a template substrate (substrate for ELO growth), a step of forming a base semiconductor portion 8 by the ELO method, a step of forming a compound semiconductor portion 9, and a step of forming first and second electrodes E1 and E2 are performed.

[0013] Fig. 4 is a block diagram showing an example of an apparatus for manufacturing a light-emitting body according to this embodiment. The apparatus 70 for manufacturing a light-emitting body in Fig. 4 includes a semiconductor formation unit 72 that forms a base semiconductor portion 8 and a compound semiconductor portion 9 on a template substrate, an electrode formation unit 73 that forms first and second electrodes E1 and E2, and a control unit 74 that controls the semiconductor formation unit 72 and the electrode formation unit 73.

[0014] The semiconductor forming unit 72 may include an MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the semiconductor forming unit 72 and the electrode forming unit 73 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network. The above-mentioned program and a recording medium on which the above-mentioned program is stored are also included in this embodiment.

[0015] Example 1 (composition) FIG. 5 is a perspective view showing the configuration of the light emitter according to Example 1. FIG. 6 is a plan view showing the configuration of the compound semiconductor section. FIG. 7 is a cross-sectional view showing the configuration of the light emitter according to Example 1. As shown in FIGS. 5 to 7, the light emitter 21 according to Example 1 includes a base semiconductor section 8, a compound semiconductor section 9 located on the base semiconductor section 8, a first electrode E1 which is an anode, and a second electrode E2 which is a cathode. The light emitter 21 can also be called a semiconductor laser chip.

[0016] The base semiconductor portion 8 and the compound semiconductor portion 9 are nitride semiconductor layers (for example, GaN-based semiconductor layers), and the base semiconductor portion 8 is an n-type semiconductor layer having a donor. In FIG. 5 and other drawings, the <11-20> direction of the base semiconductor portion 8 is the X direction, the <1-100> direction is the Y direction, <0001> The direction is the Z direction (thickness direction).

[0017] The base semiconductor portion 8 is a free-standing layer having no supporting material, the upper surface of the base semiconductor portion 8 being in contact with the compound semiconductor portion 9, and the lower surface 8U of the base semiconductor portion 8 being exposed (the lower surface 8U is exposed on a chip basis, but may not be exposed after mounting).

[0018] The base semiconductor portion 8 includes a first portion B1 including threading dislocations KD extending in the Z direction, and a second portion B2 and a third portion B3 having a threading dislocation density lower than that of the first portion B1. The second portion B2, the first portion B1, and the third portion B3 are arranged in this order in the X direction, and the first portion B1 is located between the second portion B2 and the third portion B3. The first portion B1 is a portion that was located above an opening in the mask layer 6 when the base semiconductor portion 8 was formed by the ELO method (described later). The threading dislocation densities of the second portion B2 and the third portion B3 are ⅕ or less (for example, 5×10) of the threading dislocation density of the first portion B1. 6 / cm 2 (see below).

[0019] The compound semiconductor section 9 is formed by forming a first type (n-type) semiconductor layer 9N having a donor, an active layer 9K, and a second type (p-type) semiconductor layer 9P having an acceptor, in this order. The first type semiconductor layer 9N is formed by forming a first contact layer 9A, a first cladding layer 9B, and a first optical guide layer 9C, in this order. The second type semiconductor layer 9P is formed by forming an electron blocking layer 9D, a second optical guide layer 9E, a second cladding layer 9F, and a second contact layer 9G, in this order, and a first electrode E1 (anode) is formed on the second contact layer 9G.

[0020] The second electrode E2 is provided on the same side as the first electrode E1 with respect to the base semiconductor portion 8. The second electrode E2 is in contact with the first contact layer 9A, and the first and second electrodes E1 and E2 may not overlap in a plan view. Specifically, a part of the compound semiconductor portion 9 may be dug down to the first contact layer 9A, and the second electrode E2 may be formed so as to be in contact with the first contact layer 9A exposed in the dug-down portion 9Q of the compound semiconductor portion 9. The first electrode E1 is located, for example, on the (0001) plane of the second-type semiconductor layer 9P (second contact layer 9G), and the second electrode E2 is located on the (0001) plane of the first-type semiconductor layer 9N (first contact layer 9A). In the first embodiment, the region of the first contact layer 9A in contact with the second electrode E2 has the same thickness as the other regions, but the region of the first contact layer 9A in contact with the second electrode E2 may have a smaller thickness than the other regions. For example, a thin film portion having a smaller thickness than the surrounding area may be formed in the first contact layer 9A by digging out a part of the first contact layer 9A, and the second electrode E2 (cathode) may be provided so as to be in contact with this thin film portion. The upper surface of the thin film portion (contact surface with the second electrode E2) may be the (0001) plane of the first contact layer 9A, which is, for example, a nitride semiconductor layer.

[0021] When the compound semiconductor portion 9 is recessed by etching or the like, the c-face ((0001) face) of the first contact layer 9A (for example, an n-GaN layer) is exposed and the second electrode E2 (cathode) is brought into contact with the c-face of the first contact layer 9A, thereby making it possible to reduce the contact resistance (compared to the case of contacting the -c-face). Note that the c-face is a gallium polar face, and the -c-face is a nitrogen polar face.

[0022] In a plan view, the first electrode E1 and the second electrode E2 are aligned in the X direction (first direction). The first and second electrodes E1 and E2 are shaped so that their longitudinal direction is in the Y direction (second direction). The size WC in the X direction of the second electrode E2 may be smaller than the size W3 in the X direction of the third portion B3. The size WC in the X direction of the second electrode E2 may be larger than the size in the X direction of the first electrode E1.

[0023] 7, the first electrode E1 has a first region L1 in contact with the ridge portion RJ, and in a plan view, the entire first region L1 may overlap with the second portion B2 (low defect portion) of the base semiconductor portion 8. The size WR of the first region L1 in the X direction may be smaller than the size W2 of the second portion B2 in the X direction.

[0024] The compound semiconductor section 9 has an optical resonator LK including a pair of resonator end faces F1 and F2, and a resonator length K1, which is a distance between the pair of resonator end faces F1 and F2, is 200 μm or less. The resonator length K1 may be 20 μm or more and 200 μm or less. Each of the resonator end faces F1 and F2 is an m-plane of the compound semiconductor section 9 and is included in a cleavage plane of the compound semiconductor section 9. That is, each of the resonator end faces F1 and F2 can be formed by cleaving the compound semiconductor section 9, which is a nitride semiconductor layer (e.g., a GaN-based semiconductor layer), along the m-plane. At least one of the base semiconductor section 8 and the compound semiconductor section 9 may have a scribe mark for cleavage (a mark of a cleavage starting point). The resonator end faces F1 and F2 can also be formed by etching.

[0025] Each of the cavity end faces F1 and F2 is covered with a reflector film UF (e.g., a dielectric film), and the optical reflectance of the cavity end face F1 on the light emitting surface side is, for example, 50% or more. The optical reflectance of the cavity end face F2 on the light reflecting surface side is higher than that of the cavity end face F1. Although not shown in Figures 5 and 7, the reflector film UF can be formed on the entire cleavage surface (m-plane) of the base semiconductor portion 8 and the compound semiconductor portion 9.

[0026] The first electrode E1 overlaps with the optical resonator LK in a plan view, and also overlaps with the second portion B2 of the base semiconductor portion 8. The length in the Y direction of the first and second electrodes E1 and E2 may be shorter than the resonance length K1. In this way, the first and second electrodes E1 and E2 do not interfere with the cleavage of the compound semiconductor portion 9.

[0027] The optical resonator LK includes a portion (portion overlapping with the first electrode E1 in plan view) of each of the first-type semiconductor layer 9N, the active layer 9K, and the second-type semiconductor layer 9P. For example, the optical resonator LK includes a portion (portion overlapping with the first electrode E1 in plan view) of each of the first cladding layer 9B, the first optical guide layer 9C, the active layer 9K, the second optical guide layer 9E, and the second cladding layer 9F.

[0028] In the optical resonator LK, the refractive index (optical refractive index) decreases in the order of the active layer 9K, the first optical guide layer 9C, and the first cladding layer 9B, and the refractive index decreases in the order of the active layer 9K, the second optical guide layer 9E, and the second cladding layer 9F. Therefore, light generated by the combination of holes supplied from the first electrode E1 and electrons supplied from the second electrode E2 in the active layer 9K is confined in the optical resonator LK (particularly, the active layer 9K), and laser oscillation occurs due to stimulated emission and feedback action in the active layer 9K. The laser light generated by the laser oscillation is emitted from a light emission region EA of the resonator end face F1 on the emission surface side.

[0029] The cavity end faces F1 and F2 are formed by m-plane cleavage, and therefore have excellent planarity and perpendicularity to the c-plane (parallelism of the cavity end faces F1 and F2), resulting in high optical reflectivity. This reduces mirror loss, enabling stable laser oscillation even with a short cavity length of 200 μm or less, where it is difficult to reduce mirror loss. The cavity end faces F1 and F2 are formed on the second part B2, which is a low-dislocation portion, and therefore have excellent planarity of the cleavage facets, resulting in high optical reflectivity.

[0030] The compound semiconductor section 9 includes a ridge section (current confinement section) RJ that overlaps with the first electrode E1 in a planar view, and the ridge section RJ includes the second cladding layer 9F and a part of the second optical guide layer 9E (the part that overlaps with the first electrode E1 in a planar view). Insulating films DF are provided on both sides of the ridge section RJ. The refractive index of the insulating film DF may be smaller than the refractive index of the second optical guide layer 9E and the second cladding layer 9F. By providing the ridge section RJ and the insulating film DF, the current path between the first electrode E1 and the first-type semiconductor layer 9N is constricted on the anode side, and light can be efficiently emitted within the resonator LK.

[0031] In plan view, the entire ridge portion RJ overlaps with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 (the ridge portion RJ does not overlap with the first portion B1). In this way, a current path from the first electrode E1 through the active layer 9K to the first-type semiconductor layer 9N is formed in the portion (low dislocation portion) that overlaps with the second portion B2 in plan view, and the light emission efficiency of the active layer 9K is improved. This is because threading dislocations impede the movement of charges, resulting in a decrease in light emission efficiency.

[0032] In the first embodiment, the sum T1 of the thickness of the base semiconductor portion 8 and the thickness of the compound semiconductor portion 9 can be set to 50 μm or less. If this sum T1 of the thicknesses is too large, it becomes difficult to cleave the semiconductor layer so that the resonance length is 200 μm or less.

[0033] The base semiconductor portion 8 may include a base end face (a cleavage plane of the base semiconductor portion 8) that is flush with the resonator end face F1, and the density of dislocations in the base end face (dislocations measured by CL on the cleavage plane, mainly basal plane dislocations) may be equal to or higher than the threading dislocation density in the second portion B2. In addition, the surface roughness of at least one of the pair of resonator end faces F1 and F2 (for example, the resonator end face F2 on the reflecting surface side) may be smaller than the surface roughness of the side face 9S (see FIG. 6), which is the a-plane of the compound semiconductor portion 9. The a-plane is the (11-20) plane of the compound semiconductor portion 9, which is a nitride semiconductor layer.

[0034] In the first embodiment, for example, a power of 200 mW or less is supplied between the first and second electrodes E1 and E2, and a light emitter with low power consumption and low output can be realized due to the short resonance length of 200 μm or less. A configuration in which the first and second electrodes E1 and E2 are provided on one side of the chip generally has the disadvantage that the current path becomes longer and the electrical resistance becomes larger, but in the case of a short resonance length (low output) as in the first embodiment, this is hardly a problem. In addition, there is an advantage that mounting (flip chip mounting) on ​​a submount or the like can be easily performed.

[0035] The lower surface (rear surface) of the base semiconductor portion 8 may include a region 8C where the surface roughness is locally increased (a rough surface region where the surface is rougher than the surroundings). At least one of convex portions and concave portions may be generated in the region 8C. For example, a plurality of randomly shaped protrusions or a plurality of randomly shaped concave portions may be formed. The region 8C may be a region corresponding to the first portion B1 (for example, a central region). The region 8C may be formed so as not to overlap with the ridge portion RJ in a planar view. The region 8C may improve heat dissipation. A dielectric film made of the same material as the reflector film UF may be formed on at least a part of the region 8C.

[0036] Fig. 8 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 8, the first electrode E1 may have a region other than the first region L1 overlapping with the first part B1 in a plan view. Also, the region other than the first region L1 may be located on the insulating film DF.

[0037] 9 and 10 are cross-sectional views showing another configuration of the light emitter of Example 1. As shown in Fig. 9 and 10, the second electrode E2 located in the recessed portion 9Q of the compound semiconductor portion may overlap with the first portion B1 of the base semiconductor portion 8 in a plan view.

[0038] Fig. 11 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 11, the thickness of the second electrode E2 is greater than the thickness of the first electrode E1, and the first electrode E1 and the second electrode E2 may be at the same upper surface level. The first electrode E1 and the second electrode E2 may be made of different conductive materials.

[0039] Fig. 12 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 12, the compound semiconductor portion 9 has a bank portion BK, and the ridge portion RJ and the bank portion BK are at the same upper surface level, and a part of the second electrode E2 may be located on the bank portion BK. In a plan view, the bank portion BK may overlap the first portion B1 of the base semiconductor portion 8. This makes it easier to mount (flip-chip mount) on a submount or the like. The structures (layer configurations) of the ridge portion RJ and the bank portion BK may be the same.

[0040] 12, the second electrode E2 may have a second region L2 located on the first-type semiconductor layer 9N and a third region L3 located on the second-type semiconductor layer 9P. The third region L3 may overlap with the first portion B1 of the base semiconductor portion 8 in a plan view.

[0041] Fig. 13 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 13, at least a part of the second electrode E2 may be located on the compound semiconductor portion 9, specifically, on the first type (n-type) semiconductor layer 9N of the compound semiconductor portion 9.

[0042] FIG. 14 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in FIG. 14, the second electrode E2 may be entirely overlapped with the first portion B1 in a plan view. Also, the first-type semiconductor layer 9N, the active layer 9K, the second-type semiconductor layer 9P (including the ridge portion RJ), and the first electrode E1 may be provided above the second portion B2 and the third portion B3 of the base semiconductor portion 8, respectively. By providing the ridge portions in both the second portion B2 and the third portion B3 in this way, the number of light emitters can be increased, the distance between the light emitting points of both is reduced when the light emitters are made into one chip, the light integration density increases, and the optical design becomes easier, and the difference in wavelength between the two can be used as a measure against speckle noise.

[0043] Fig. 15 is a cross-sectional view showing another configuration of the light emitter of Example 1. As shown in Fig. 15, the first electrode E1 may be located on the semi-polar plane PJ of the second-type semiconductor layer 9P, and the second electrode E2 may be located on the semi-polar plane NJ of the first-type semiconductor layer 9N. The semi-polar plane is, for example, an r-plane that is oblique to the c-plane, which is a polar plane. The first and second electrodes E1 and E2 may be provided on non-polar planes (a-plane, m-plane) that are perpendicular to the c-plane.

[0044] FIG. 16 is a perspective view showing another configuration of the light emitter of Example 1. FIG. 17 is a top view and a cross-sectional view of FIG. 16. In the example shown in FIG. 16 and FIG. 17, the second electrode E2 has a second region L2 located on the first contact layer 9A and a third region L3 located on the second-type semiconductor layer 9P. This reduces the difference in the upper surface levels between the first electrode E1 and the third region L3, making mounting easier. In this case, the second electrode E2 may have a recess UB on its surface.

[0045] FIG. 18 is a perspective view showing another configuration of the light emitter of Example 1. FIG. 19 is a top view and a cross-sectional view of FIG. 18. In the example shown in FIGS. 18 and 19, the compound semiconductor portion 9 has a bank portion BK, the ridge portion RJ and the bank portion BK are at the same upper surface level, and the second electrode E2 has a second region L2 located on the first contact layer 9A and a third region L3 located on the bank BK. In this way, the upper surface levels of the first electrode E1 and the third region L3 are the same, making mounting easier. In this case, the second electrode E2 has a recess UB on its surface.

[0046] FIG. 18 shows a case where the second type (p type) semiconductor layer is removed only near the sides of the ridge during the formation of the ridge. The second electrode E2 is made larger than the first electrode E1, and the area of ​​the third region L3 in particular is made larger. The larger the area of ​​the third region L3 (the larger the bonding area), the stronger the bonding to the support base becomes, and the easier the handling in the subsequent process becomes. An insulating film (silicon oxide, silicon nitride, etc.) is present on the sides of the ridge portion RJ where the first electrode E1 is in contact, but since the adhesive strength between metal and insulating film is generally weak, the electrode may peel off at that location when peeled off from the growth substrate (described later). Therefore, it is better to increase the area of ​​the third region L3 (the second electrode E2 at the location without the insulating film) rather than increasing the area of ​​the first electrode E1. The shape of the first electrode E1 or the second electrode E2 may be a shape that can be used for alignment (positioning) during bonding (for example, a shape having an alignment mark).

[0047] In the third region L3, the contact resistance between the second electrode E2, which is the cathode, and the second type (p-type) semiconductor layer 9P is sufficiently high so that no current flows and the two are not short-circuited.

[0048] 20 is a cross-sectional view showing the configuration of the light-emitting element according to Example 1. The light-emitting element 23 includes a light-emitting body 21 including a base semiconductor portion 8 and a compound semiconductor portion 9, and a support ST that holds the light-emitting body 21. Examples of materials for the support ST include Si, SiC, and AlN. The support ST is disposed such that the compound semiconductor portion 9 and the first and second electrodes E1 and E2 are located between the support ST and the base semiconductor portion 8. That is, the light-emitting body 21 is mounted on the support ST in a junction-down type.

[0049] The support ST includes a conductive first pad P1 and a second pad P2, the first electrode E1 is connected to the first pad P1 via a first joint A1, and the second electrode E2 is connected to the second pad P2 via a second joint A2. The second joint A2 is thicker than the first joint A1, and the difference in thickness between the first and second joints A1 and A2 is equal to or greater than the thickness of the compound semiconductor portion 9. This enables the first and second electrodes E1 and E2 to be connected to the first and second pads P1 and P2 located on the same plane. In other words, the light-emitting element 23 functions as a COS (Chip on Submount).

[0050] FIG. 21 is a perspective view showing the configuration of the light-emitting element according to the first embodiment. As shown in FIG. 21, the light-emitting element 23 includes a light-emitting body 21 and a support body ST. The support body ST has two wide portions SH having a width larger than the resonance length of the light-emitting body 21, and a mounting portion SB located between the two wide portions SH and having a width smaller than the resonance length. The light-emitting body 21 is located above the mounting portion SB so that the width direction (Y direction) of the mounting portion SB coincides with the direction of the resonance length, and a pair of resonance end faces F1 and F2 protrude from the mounting portion SB in a plan view. In other words, the mounting portion SB is formed between two cutout portions C1 and C2 facing each other in the direction (Y direction) that defines the resonance length, and the resonance end face F1 is located on the cutout portion C1, and the resonance end face F2 is located on the cutout portion C2. The shape of the cutout portions C1 and C2 can be, for example, rectangular in a plan view seen in the Z direction.

[0051] The support ST includes a first pad P1 and a second pad P2 each having a T-shape. The first pad P1 includes a mounting portion J1 located on the wide portion SH and having a length in the Y direction greater than the resonance length K1, and a contact portion Q1 located on the mounting portion SB and having a length in the Y direction smaller than the resonance length K1. The second pad P2 includes a mounting portion J2 located on the wide portion SH and having a length in the Y direction greater than the resonance length K1, and a contact portion Q2 located on the mounting portion SB and having a length in the Y direction smaller than the resonance length K1. The contact portions Q1 and Q2 are arranged in the X direction on the upper surface of the mounting portion SB, and a first joint portion A1 is formed on the contact portion Q1, and a second joint portion A2 is formed on the contact portion Q2. The first joint portion A1 contacts the first electrode E1 of the light emitter 21, and the second joint portion A2 contacts the second electrode E2 of the light emitter 21. Solder such as AuSi and AuSn can be used as the material for the first and second joint portions A1 and A2.

[0052] The resonant end faces F1 and F2 of the light emitter 21 are covered with a reflector film UF, but a dielectric film SF made of the same material as the reflector film UF may be formed on one of the side surfaces of the support ST that is parallel to the resonant end faces F1 and F2 (for example, the side surface of the mounting portion SB).

[0053] Fig. 22 is a cross-sectional view showing another configuration of the light-emitting element according to Example 1. In Fig. 21, the cutout portions C1 and C2 are rectangular in plan view in the Z direction, but are not limited thereto. As shown in Fig. 22, the cutout portions C1 and C2 may be trapezoidal with the shorter side facing the mounting portion SB.

[0054] 23 and 24 are cross-sectional views showing another configuration of the light-emitting element according to the first embodiment. In the light-emitting element 23 of FIG. 23, a plurality of light-emitting bodies 21 may be arranged on a support ST in a direction (X direction) perpendicular to the direction defining the resonance length so that the resonance lengths are aligned, and first and second pads P1 and P2 may be provided corresponding to each light-emitting body 21. As shown in FIG. 24, an optical device such as a photodiode PD may be provided in a cutout portion C1 of the support ST. In this way, the light emission intensity of the light-emitting body 21 can be feedback-controlled.

[0055] 25 is a perspective view showing a configuration of a light emitting substrate (semiconductor laser array) according to Example 1. The light emitting substrate 22 includes a support substrate SK and a plurality of light emitters 21. In the light emitting substrate 22, the plurality of light emitters 21 are arranged in a matrix on the support substrate SK in a direction that defines the resonance length (Y direction) and a direction perpendicular thereto (X direction) so that the directions of the resonance lengths are aligned, and first and second pads P1 and P2 and first and second bonding portions A1 and A2 may be provided corresponding to each of the light emitters 21.

[0056] The support substrate SK can be formed, for example, by providing a matrix of multiple recesses HL (rectangular in plan view) in a Si substrate, a SiC substrate, etc., and providing a plurality of first pads P1, a plurality of second pads P2, a plurality of first bonding portions A1, and a plurality of second bonding portions A2 in the non-recesses.

[0057] Fig. 26 is a perspective view showing another configuration of the light emitting substrate according to Example 1. A two-dimensional arrangement type light emitting substrate in which a plurality of light emitters 21 are arranged in a matrix as shown in Fig. 25 can be horizontally divided (divided into rows extending in the X direction) to form a one-dimensional arrangement type (bar-shaped) light emitting substrate 22 as shown in Fig. 26. The one-dimensional arrangement type makes it easy to form a reflector film UF on a pair of resonator end faces F1 and F2.

[0058] (Production method) Fig. 27 is a flowchart showing an example of a method for manufacturing the light emitting device according to Example 1. Fig. 28 is a schematic cross-sectional view showing a method for manufacturing the light emitting device of Fig. 27. Fig. 29 is a plan view showing a method for manufacturing the light emitting device of Fig. 27. The manufacturing method shown in Figures 27 to 29 includes the steps of preparing a template substrate 7 including a base substrate UK and a mask layer 6, a step of forming a first semiconductor layer S1 (and a third semiconductor layer S3) that will be the basis of a base semiconductor portion 8 by an ELO method (described later), a step of forming a second semiconductor layer S2 (and a fourth semiconductor layer S4) that will be the basis of a compound semiconductor portion 9, a step of forming a stacked body LB having the first semiconductor layer S1, the second semiconductor layer S2 including a ridge portion, and a first electrode E1 and a second electrode E2, etc., a step of bonding the stacked body LB to a support substrate SK and separating the first semiconductor layer S1 from the template substrate 7, a step of cleaving the stacked body LB on the support substrate SK to form a pair of resonant end faces F1 and F2 (an optical resonator LK including the resonant end faces F1 and F2), a step of forming a reflector film UF on each of the pair of resonant end faces F1 and F2, and a step of dividing the support substrate SK into a plurality of supports ST.

[0059] After the formation of the laminate LB, the mask layer 6 is etched away, and the laminate LB is bonded to the support substrate SK while the first and second bonding portions A1 and A2 (for example, solder) of the support substrate SK are heated and melted, whereby the bonding portion (downward protruding portion) of the back surface of the first semiconductor layer S1 with the base substrate UK is broken, and the first semiconductor layer S1 is separated from the template substrate 7. Then, the laminate LB is cleaved (m-plane cleavage of the first and second semiconductor layers S1 and S2, which are nitride semiconductor layers) on the support substrate SK to form a pair of resonant end faces F1 and F2. This forms a two-dimensionally arranged light emitting substrate 22 (see FIG. 25). Next, the two-dimensionally arranged light emitting substrate is divided into rows to form one-dimensionally arranged (rod-shaped) light emitting substrates 22 (see FIG. 26). Next, a reflector film UF is formed on the resonant end faces F1 and F2 of the one-dimensionally arranged light emitting substrate 22. Thereafter, the support substrate SK is divided into a plurality of supports ST, and each support ST is made to hold one or more light emitters 21, thereby forming a plurality of light emitting elements 23. The reflector film UF (e.g., a dielectric film) may be formed not only on the cleavage planes (m-planes) of the base semiconductor portion 8 and the compound semiconductor portion 9, but also on the side surfaces of the support ST (including the side surfaces of the mounting portion SB) that are parallel to the cavity end faces F1 and F2.

[0060] 30 and 31 are schematic cross-sectional views showing another example of the manufacturing method of the light emitting device according to Example 1. As shown in Fig. 30, a plurality of one-dimensionally arranged light emitting substrates 22 (see Fig. 26) can be stacked in the Z direction such that the rear surfaces of the base semiconductor portions 8 face each other, and a reflector film UF can be simultaneously formed on the cavity end faces F1 and F2 of each light emitting substrate 22. Also, as shown in Fig. 31, when dividing the support substrate SK into a plurality of supports ST, each support ST can be made to hold a plurality of light emitters 21, thereby forming the light emitting element 23 shown in Fig. 23 etc.

[0061] (Base semiconductor part) FIG. 32 is a cross-sectional view showing an example of lateral growth of the base semiconductor portion (ELO semiconductor layer) in Example 1. As shown in FIG. 32, the base substrate UK includes a main substrate 1 and an underlayer 4 on the main substrate 1, and a seed layer 3, which is a surface layer of the underlayer 4, is exposed from an opening K of a mask portion 5. In the ELO method, an initial growth layer SL is first formed on the seed layer 3, and then a first semiconductor layer S1 can be grown laterally from the initial growth layer SL. The initial growth layer SL is a starting point of the lateral growth of the first semiconductor layer S1 and is a part of the first portion B1 of the base semiconductor portion 8. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the first semiconductor layer S1 in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0062] Here, deposition of the initial growth layer SL can be stopped just before the edge of the initial growth layer SL rises onto the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or just after it rises onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions can be switched from the c-axis direction deposition conditions to the a-axis direction deposition conditions). In this way, the lateral deposition is performed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that the material is less likely to be consumed in the growth of the first semiconductor layer S1 in the thickness direction, and the first semiconductor layer S1 can be grown laterally at a high speed. The initial growth layer SL may be formed to a thickness of, for example, 2.0 μm or more and 3.0 μm or less.

[0063] In Example 1, the first semiconductor layer S1, which is the basis of the base semiconductor portion 8, is an n-type GaN layer, and Si-doped GaN (gallium nitride) is deposited on the template substrate 7 by ELO deposition using an MOCVD apparatus. As an example of the ELO deposition conditions, the following can be adopted: substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, V / III=6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied). Note that the lateral growth of the first and third semiconductor layers S1 and S3 growing laterally from both sides on the mask portion 5 was stopped before they met.

[0064] The width of the mask portion 5 was 50 μm, the width of the opening K was 5 μm, the lateral width of the first semiconductor layer S1 was 53 μm, the width (size in the X direction) of the low defect portions B2 and B3 was 24 μm, and the layer thickness of the first semiconductor layer S1 was 5 μm. The aspect ratio of the first semiconductor layer S1 was 53 μm / 5 μm=10.6, which is a high aspect ratio.

[0065] A heterogeneous substrate having a lattice constant different from that of the nitride semiconductor can be used for the main substrate 1 in Fig. 32. Examples of heterogeneous substrates include single crystal silicon (Si) substrates, sapphire (Al2O3) substrates, and silicon carbide (SiC) substrates. The surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, and the 6H-SiC (0001) surface of a SiC substrate.

[0066] As the underlayer 4 in FIG. 32, a buffer layer 2 and a seed layer 3 can be provided in order from the main substrate 1 side. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed layer 3, the two (main substrate and seed layer) melt together, and thus, for example, by providing a buffer layer 2 including at least one of an AlN layer and a SiC (silicon carbide) layer, melting is reduced. The buffer layer 2 may have at least one of an effect of increasing the crystallinity of the seed layer 3 and an effect of relaxing the internal stress of the first semiconductor layer S1. When a main substrate 1 that does not melt with the seed layer 3 is used, a configuration without providing the buffer layer 2 is also possible. Note that the configuration is not limited to the seed layer 3 overlapping the entire mask portion 5 as shown in FIG. 32. Since the seed layer 3 only needs to be exposed from the opening K, the seed layer 3 may be formed locally so as not to overlap a part or all of the mask portion 5.

[0067] The openings K of the mask layer 6 function as growth initiation holes that expose the seed layer 3 and start the growth of the first semiconductor layer S1, and the mask portions 5 of the mask layer 6 function as selective growth masks that grow the first semiconductor layer S1 laterally. The mask layer 6 may be a mask pattern that includes the mask portions 5 and the openings K.

[0068] The mask layer 6 may be, for example, a single layer film including any one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000°C or higher), or a laminated film including at least two of these.

[0069] For example, a silicon oxide film having a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed on the entire surface of the underlayer 4 by sputtering, and a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned by photolithography to form a resist having a plurality of stripe-shaped openings. Parts of the silicon oxide film are then removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings K, and the resist is removed by organic cleaning to form the mask layer 6.

[0070] The openings K are elongated (slit-shaped) and are periodically arranged in the a-axis direction (X direction) of the first semiconductor layer S1. The width of the openings K is approximately 0.1 μm to 20 μm. The smaller the width of each opening, the smaller the number of threading dislocations propagating from each opening to the first semiconductor layer S1. Also, the width (size in the X direction) of the low defect portions B2 and B3 can be increased.

[0071] While a small amount of silicon oxide film decomposes and evaporates during the formation of the ELO semiconductor layer and may be incorporated into the ELO semiconductor layer, silicon nitride film and silicon oxynitride film have the advantage of being less susceptible to decomposition and evaporation at high temperatures.

[0072] Therefore, the mask layer 6 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminate film in which a silicon oxide film and a silicon nitride film are formed in this order on the underlayer 4, or may be a laminate film in which a silicon nitride film and a silicon oxide film are formed in this order on the underlayer 4, or may be a laminate film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on the underlayer.

[0073] When the base semiconductor portion 8 is formed using the ELO method, a template substrate 7 including a main substrate 1 and a mask layer 6 (mask pattern) on the main substrate 1 may be used. The template substrate 7 may have a growth-inhibiting region (e.g., a region that inhibits crystal growth in the Z direction) corresponding to the mask portion 5, and a seed region corresponding to the opening K. For example, the growth-inhibiting region and the seed region may be formed on the main substrate 1, and the base semiconductor portion 8 may be formed on the growth-inhibiting region and the seed region using the ELO method.

[0074] (Compound Semiconductor Division, etc.) The compound semiconductor section 9 can be formed by using, for example, an MOCVD apparatus. The first contact layer 9A can be, for example, an n-type GaN layer, the first cladding layer 9B can be, for example, an n-type AlGaN layer, the first optical guide layer 9C can be, for example, an n-type GaN layer, the active layer 9K can be, for example, an MQW (Multi-Quantum Well) structure including an InGaN layer, the electron blocking layer 9D can be, for example, a p-type AlGaN layer, the second optical guide layer 9E can be, for example, a p-type GaN layer, the second cladding layer 9F can be, for example, a p-type AlGaN layer, and the second contact layer 9G can be, for example, a p-type GaN layer.

[0075] The thickness of each layer of the light emitter 21 can be expressed as: base semiconductor section 8>first cladding layer 9B>first optical guide layer 9C>active layer 9K, and base semiconductor section 8>second cladding layer 9F>second optical guide layer 9E>active layer 9K. Also, the refractive index of each layer of the compound semiconductor section 9 (the refractive index of light generated in the active layer 9K) can be expressed as:first cladding layer 9B<first optical guide layer 9C<active layer 9K, and insulating film DF<second cladding layer 9F<second optical guide layer 9E<active layer 9K.

[0076] The first and second electrodes E1 and E2 and the first and second pads P1 and P2 may be formed of a single layer or multilayer film including at least one of a metal film (which may be an alloy film) including at least one of Ni, Rh, Pd, Cr, Au, W, Pt, Ti, and Al, and a conductive oxide film including at least one of Zn, In, and Sn. The insulating film DF covering the ridge portion RJ may be formed of a single layer or multilayer film including an oxide or nitride of Si, Al, Zr, Ti, Nb, or Ta.

[0077] The first semiconductor layer S1 (ELO semiconductor layer) that will become the base semiconductor portion 8 and the second semiconductor layer S2 that will become the compound semiconductor portion 9 can also be successively formed in the same film formation apparatus (for example, an MOCVD apparatus). The intermediate substrate on which the first semiconductor layer S1 has been formed can be temporarily removed from the film formation apparatus, and the second semiconductor layer S2 can be formed on the first semiconductor layer S1 by a different apparatus. In this case, the second semiconductor layer S2 can be formed after forming an n-type GaN layer (for example, with a thickness of about 0.1 μm to about 3 μm) that serves as a buffer during regrowth on the first semiconductor layer S1.

[0078] The material of the reflector film UF covering the resonator facets F1 and F2 can be a dielectric material such as SiO2, Al2O3, AlN, AlON, Nb2O5, Ta2O5, ZrO2, etc. The reflector film UF may be a multilayer film. The reflector film UF can be formed by electron beam evaporation, electron cyclotron resonance sputtering, chemical vapor deposition, etc.

[0079] In the first embodiment, a silicon substrate can be used for each of the main substrate 1 used in the ELO of the base semiconductor portion 8, the support substrate SK, and the support body ST. This makes it difficult for bonding defects caused by differences in thermal expansion coefficients to occur during bonding, and is also advantageous in terms of large diameter, heat dissipation, processability, and cost.

[0080] Since the light emitter 21 has a structure in which the first and second electrodes E1 and E2 are provided on one side (single-sided electrode structure), the surface of the first-type semiconductor layer 9N connected to the second electrode E2 and the surface of the second-type semiconductor layer 9P connected to the first electrode E1 can both be the (0001) plane (c-plane) of a GaN-based semiconductor. In a GaN-based semiconductor laser, when the crystal growth substrate (e.g., a GaN substrate) is conductive, the semiconductor layer is fabricated so that the front surface is the (0001) plane, and the contact surface of the anode is the (0001) plane, and the contact surface of the cathode is the back surface of the crystal growth substrate, i.e., the (000-1) plane, in general, to adopt a double-sided electrode structure. With a single-sided electrode structure, a current flows laterally between the anode and the cathode, which may cause the current to be nonuniform in the ridge portion (ridge waveguide) and the threshold current to increase, or the current path to be longer than in the double-sided electrode structure and the driving voltage to increase. Therefore, the one-sided electrode structure of GaN-based semiconductor lasers has been used only in the past when the crystal growth substrate is insulating and an electrode cannot be formed on the back side (e.g., a sapphire substrate). It is known that when the (000-1) plane is used as the cathode connection surface, the contact resistance is higher than when the (0001) plane is used as the cathode connection surface, so a process is added in which the (000-1) plane of the crystal growth substrate is processed by etching or the like to expose various faces on the surface.

[0081] In the first embodiment, even when a double-sided electrode structure can be adopted because the crystal growth substrate (main substrate) is conductive or the main substrate is removed and the conductive base semiconductor portion is located on the back side, there is an advantage to adopting a single-sided electrode structure. In addition, the driving current is originally small with a short resonance length, and in applications such as AR (Augmented Reality) glasses that do not require high optical output, the driving current is near the threshold current, so the series resistance increase that causes a voltage increase according to the current value is not a major problem. On the other hand, by using the (0001) plane as the connection surface of the cathode, there is an advantage that the contact resistance is small (low power consumption), and further, mounting on a submount (support substrate SK, etc.) is also easy.

[0082] Example 2 FIG. 33 is a cross-sectional view showing the configuration of a light emitter according to Example 2. The light emitter 21 includes a base semiconductor portion 8, a compound semiconductor portion 9 located on the base semiconductor portion 8, a first electrode E1 which is an anode, and a second electrode E2 which is a cathode. The light emitter 21 can also be called an LED (light emitting diode) chip. The compound semiconductor portion 9 is formed by forming a first type (n-type) semiconductor layer 9N having a donor, an active layer 9K, and a second type (p-type) semiconductor layer 9P having an acceptor in this order. At least a part of the first electrode E1 is located on the (0001) plane of the second type semiconductor layer 9P, and at least a part of the second electrode E2 is located on the (0001) plane of the first type semiconductor layer 9N.

[0083] In plan view, the entire first electrode E1 overlaps with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 (the first electrode E1 does not overlap with the first portion B1). In this way, a current path from the first electrode E1 through the active layer 9K to the first-type semiconductor layer 9N is formed in the portion (low dislocation portion) overlapping with the second portion B2 in plan view, and the light emission efficiency in the active layer 9K is improved.

[0084] Example 3 In the first and second embodiments, the base semiconductor portion 8 (ELO semiconductor layer) may be a GaN layer, but is not limited thereto. An InGaN layer, which is a GaN-based semiconductor layer, may be formed as the ELO semiconductor layer. The lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000° C. This is because at high temperatures, the vapor pressure of indium increases and indium is not effectively incorporated into the film. The low deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. In addition, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. When indium is incorporated into the InGaN layer at an In composition level of 1% or more, the reactivity with the mask portion 5 is further reduced. Triethylgallium (TEG) can be used as the gallium source gas.

[0085] Example 4 FIG. 34 is a perspective view showing a configuration of a light emitting module of Example 4. The light emitting module 24 (light emitting device) of FIG. 34 is a surface mount type package, and includes a housing 35 and a light emitting element 23 (see, for example, FIG. 23). The light emitting element 23 includes a plurality of light emitters 21, and is provided such that a side surface (a surface parallel to the resonant end face) of the support body ST faces a bottom surface 37 of the housing 35. Therefore, an emission surface (a resonant end face on the emission side) of each light emitter 21 faces a top surface 34 (transparent plate) of the housing 35, and a laser light is emitted from the top surface 34 of the housing 35. The light emitting element 23 is connected to an external connection pin 33 via a wire 31.

[0086] Fig. 35 is a perspective view showing another configuration of the light emitting module of Example 4. The light emitting module 24 of Fig. 35 is a TO-CAN mounting type package, and includes a stem 38 and a light emitting element 23 (see Fig. 21, for example). The light emitting element 23 is disposed on a heat block 36 protruding from the base of the stem 38. First and second pads P1 and P2 of the light emitting element 23 are connected to an external connection pin 33 via a wire 31.

[0087] In the conventional technology, it was necessary to individually die-bond the semiconductor laser chip to a submount to fabricate a CoS (Chip on Submount), but in the first to fourth embodiments, the support ST of the light emitting element 23 functions as a submount, and the light emitting element 23 itself has a CoS structure, so die-bonding to the submount is not necessary. This makes it possible to solve the problem of difficulty in handling when the resonance length is short or the chip width is narrow. Specifically, the light emitting element 23 has first and second pads P1 and P2 that satisfy the size conditions required for wire bonding on the support ST. Since these first and second pads P1 and P2 are electrically connected to the first and second electrodes (anode and cathode) of the light emitting body 21 (semiconductor laser chip), it is sufficient to electrically connect the external connection pin 33 of the package to the first and second pads P1 and P2 with wires 31.

[0088] Example 5 Fig. 36 is a schematic diagram showing the configuration of an electronic device according to Example 5. An electronic device 50 in Fig. 36 includes a light-emitting device GD (21-24) according to Examples 1-4, and a control unit 80 including a processor and controlling the light-emitting device GD. Examples of the electronic device 50 include a lighting device, a display device, a communication device, an information processing device, a medical device, an electric vehicle (EV), and the like.

[0089] The above-described technical aspects are intended to be illustrative and explanatory, and not restrictive. Based on these examples and descriptions, many variations are possible, as will be apparent to those skilled in the art.

[0090] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-mentioned embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0091] 7 Template Substrate 8 Base Semiconductor Section 9. Compound Semiconductor Department 21 Light-emitting body (light-emitting device) 22 Light emitting substrate (light emitting device) 23 Light-emitting elements (light-emitting devices) 24 Light emitting module (light emitting device) S1 First semiconductor layer S2 Second semiconductor layer LK optical resonator RJ Ridge B1 Part 1 B2 Part 2 (low dislocation part) B2 Part 3 (low dislocation part) F1·F2 A pair of resonator faces P1 1st pad P2 2nd pad E1 1st electrode E1 2nd electrode UF reflective mirror film ST support SB placement section SK support board

Claims

1. a base semiconductor portion including a nitride semiconductor; a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion; and a first electrode and a second electrode; the base semiconductor portion has a first portion and a second portion in which a density of threading dislocations extending in a thickness direction is lower than that of the first portion; at least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor portion, and at least a portion of the first electrode is located above the second portion; an upper surface of the base semiconductor portion contacts the compound semiconductor portion; the lower surface of the base semiconductor portion is exposed, the base semiconductor portion has a third portion in which a density of threading dislocations extending in a thickness direction is lower than that of the first portion; The first portion is located between the second portion and the third portion, The second electrode and the third portion overlap in a plan view.

2. The light-emitting body according to claim 1 , wherein the threading dislocation density of the second portion is equal to or less than ⅕ of the threading dislocation density of the first portion.

3. The <11-20> direction of the nitride semiconductor included in the base semiconductor portion is defined as a first direction, and the <1-100> direction is defined as a second direction, The light emitter of claim 1 , wherein the first portion and the second portion are aligned in the first direction.

4. An illuminant as described in claim 1, wherein the threading dislocation density of the third portion is 1 / 5 or less of the threading dislocation density of the first portion.

5. The light-emitting body described in claim 1, wherein the entire second electrode is located above the third portion.

6. The light emitter of claim 1 , wherein the entire first electrode is located above the second portion.

7. The light emitter according to claim 1 , wherein at least a portion of the first electrode and at least a portion of the second electrode are located on a (0001) plane of the compound semiconductor portion.

8. The light emitter according to claim 3 , wherein the first electrode and the second electrode are aligned in the first direction in a plan view.

9. The light emitter according to claim 3 , wherein the first electrode and the second electrode are shaped such that a longitudinal direction of the first electrode and the second electrode is in the second direction.

10. The thickness of the second electrode is greater than the thickness of the first electrode, The light emitter according to any one of claims 1 to 9, wherein the first electrode and the second electrode have the same upper surface level.

11. 10. The light emitter according to claim 1, wherein the first electrode and the second electrode are made of different conductive materials.

12. A semiconductor device comprising: a base semiconductor portion including a nitride semiconductor; a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion; and a first electrode and a second electrode; the base semiconductor portion has a first portion and a second portion in which a density of threading dislocations extending in a thickness direction is lower than that of the first portion; at least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor portion, and at least a portion of the first electrode is located above the second portion; an upper surface of the base semiconductor portion contacts the compound semiconductor portion; the lower surface of the base semiconductor portion is exposed, At least a portion of the first electrode and at least a portion of the second electrode are located on a semipolar plane of the compound semiconductor portion.

13. The threading dislocation density of the second portion of the base semiconductor portion is 5×10 ６ / cm ２ The light emitter according to any one of claims 1 to 9 and 12, wherein:

14. The light emitter according to any one of claims 1 to 9 and 12, wherein the first electrode is a cathode and the second electrode is an anode.

15. A semiconductor device comprising: a base semiconductor portion including a nitride semiconductor; a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion; and a first electrode and a second electrode; the base semiconductor portion has a first portion and a second portion in which a density of threading dislocations extending in a thickness direction is lower than that of the first portion; at least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor portion, and at least a portion of the first electrode is located above the second portion; an upper surface of the base semiconductor portion contacts the compound semiconductor portion; the lower surface of the base semiconductor portion is exposed, the base semiconductor portion has a third portion in which a density of threading dislocations extending in a thickness direction is lower than that of the first portion; The first portion is located between the second portion and the third portion, The <11-20> direction of the nitride semiconductor included in the base semiconductor portion is defined as a first direction, and the <1-100> direction is defined as a second direction, A light emitter, wherein the size of the second electrode in the first direction is smaller than the size of the third portion in the first direction.

16. 16. The light emitter according to claim 1, wherein the sum of the thickness of said base semiconductor portion and the thickness of said compound semiconductor portion is 50 μm or less.

17. 16. The light emitter according to claim 1, wherein the compound semiconductor portion includes a first type semiconductor layer, an active layer, and a second type semiconductor layer in this order.

18. 16. The light emitter according to claim 1, wherein the compound semiconductor portion has an optical resonator including a pair of resonant end faces.

19. The light emitter according to claim 18 , wherein the compound semiconductor portion includes a ridge portion that confines a current.

20. The light emitter according to claim 19 , wherein insulating films are located on both sides of the ridge portion in a plan view.

21. the first electrode has a first region in contact with the ridge portion, The light emitter according to claim 19 , wherein the entire first region overlaps with the second portion in a plan view.

22. The <11-20> direction of the nitride semiconductor included in the base semiconductor portion is defined as a first direction, and the <1-100> direction is defined as a second direction, The light emitter of claim 21 , wherein the size of the first region in the first direction is smaller than the size of the second portion in the first direction.

23. the compound semiconductor portion has a bank portion, the ridge portion and the bank portion have the same upper surface level; The light emitter according to claim 19 , wherein a portion of the second electrode is located on the bank portion.

24. The light emitter according to claim 23 , wherein the bank portion overlaps with the first portion of the base semiconductor portion in a plan view.

25. The light emitter according to claim 18, wherein the resonant length of the optical resonator is 200 μm or less.

26. The light emitter according to claim 18 , wherein the base semiconductor portion and the compound semiconductor portion include a GaN-based semiconductor.

27. 27. The light emitter according to claim 26, wherein each resonator end facet is an m-plane of the GaN-based semiconductor.

28. the first electrode is in contact with a (0001) plane of the second type semiconductor layer; The light emitter of claim 17 , wherein the second electrode is in contact with a (0001) surface of the first type semiconductor layer.

29. 29. The light emitter according to claim 28, wherein the compound semiconductor portion has a recessed portion exposing a (0001) plane of the first-type semiconductor layer, and the second electrode is disposed in the recessed portion.

30. The light emitter of claim 17 , wherein the second electrode has a second region located on the first type semiconductor layer and a third region located on the second type semiconductor layer.

31. The light emitter according to claim 30 , wherein the third region overlaps with the first portion in a planar view.

32. A semiconductor device comprising: a base semiconductor portion including a nitride semiconductor; a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion; and a first electrode and a second electrode; the base semiconductor portion has a first portion and a second portion in which a density of threading dislocations extending in a thickness direction is lower than that of the first portion; at least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor portion, and at least a portion of the first electrode is located above the second portion; an upper surface of the base semiconductor portion contacts the compound semiconductor portion; the lower surface of the base semiconductor portion is exposed, the compound semiconductor portion includes a first type semiconductor layer, an active layer, and a second type semiconductor layer in this order; The second electrode entirely overlaps with the first portion in a plan view.

33. A light-emitting device comprising: the light-emitting body according to claim 18; and a support that supports the light-emitting body.

34. 34. The light-emitting device of claim 33, wherein the support comprises a substrate, a first pad and a second pad.

35. A first conductive joint and a second conductive joint are provided, the first electrode is connected to the first pad via the first conductive junction; The light-emitting element of claim 34 , wherein the second electrode is connected to the second pad via the second conductive junction.

36. 36. The light emitting device of claim 35, wherein the second conductive junction is thicker than the first conductive junction.

37. 35. The light-emitting device of claim 34, wherein the substrate comprises silicon or silicon carbide.

38. the support has a mounting portion having a width smaller than a resonance length of the optical resonator, The light-emitting element according to claim 34 , wherein the light-emitting body is positioned on the mounting portion such that a width direction of the mounting portion coincides with a direction that defines the resonance length.

39. 39. The light-emitting device according to claim 38, wherein at least one of the pair of cavity end faces protrudes from the mounting portion in a plan view.

40. the mounting portion is formed between two cutout portions facing each other in a direction that defines the resonance length, The light-emitting element according to claim 39 , wherein the pair of resonator end faces are located on the two notches.

41. The light-emitting element according to claim 34 , wherein the first pad and the second pad have a size in a direction that defines a resonance length of the optical cavity that is larger than the resonance length.

42. The light-emitting device according to claim 33 , further comprising a reflector film covering at least one of the pair of cavity end faces.

43. A light emitter according to any one of claims 1, 12, 15 and 32, A first conductive joint and a second conductive joint; a support having a first pad connected to the first electrode via the first conductive joint and a second pad connected to the second electrode via the second conductive joint, and a substrate; The base semiconductor portion includes a nitride semiconductor, and a surface opposite to a (0001) surface is exposed.

44. An electronic device comprising the light-emitting body according to any one of claims 1 to 9, 12, 15 and 32.

45. A method for manufacturing a light emitting device comprising: a base semiconductor portion including a nitride semiconductor; a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion; and a first electrode and a second electrode, the base semiconductor portion having a first portion and a second portion in which a density of threading dislocations extending in the thickness direction is lower than that of the first portion, at least a part of the first electrode and at least a part of the second electrode are located on the compound semiconductor portion and at least a part of the first electrode is located above the second portion, an upper surface of the base semiconductor portion is in contact with the compound semiconductor portion, and a lower surface of the base semiconductor portion is exposed, A method for manufacturing a light emitter, comprising the step of forming the base semiconductor portion by an ELO method.

46. forming the compound semiconductor portion including a first type semiconductor layer, an active layer, and a second type semiconductor layer in this order; The method for producing a light-emitting body according to claim 45, further comprising a step of exposing a (0001) plane of the first type semiconductor layer by etching a part of the compound semiconductor portion.

47. A method for manufacturing a light-emitting element comprising: a light-emitting body; and a support supporting the light-emitting body, the light-emitting body having a base semiconductor portion including a nitride semiconductor; a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion; and a first electrode and a second electrode, the base semiconductor portion having a first portion and a second portion having a lower density of threading dislocations extending in the thickness direction than the first portion, at least a part of the first electrode and at least a part of the second electrode being located on the compound semiconductor portion and at least a part of the first electrode being located above the second portion, an upper surface of the base semiconductor portion is in contact with the compound semiconductor portion, and a lower surface of the base semiconductor portion is exposed, forming the base semiconductor portion of the light emitter by an ELO method using a template substrate including a main substrate and a mask; and flip-chip mounting the light-emitting body on a supporting substrate including the support body.

48. The method for manufacturing a light-emitting element according to claim 47, wherein a silicon substrate is used for each of the main substrate and the support substrate.

49. An apparatus for manufacturing a light-emitting device comprising: a base semiconductor portion including a nitride semiconductor; a compound semiconductor portion including a nitride semiconductor and located above the base semiconductor portion; and a first electrode and a second electrode, the base semiconductor portion having a first portion and a second portion in which the density of threading dislocations extending in the thickness direction is lower than that of the first portion, at least a part of the first electrode and at least a part of the second electrode are located on the compound semiconductor portion and at least a part of the first electrode is located above the second portion, an upper surface of the base semiconductor portion is in contact with the compound semiconductor portion, and a lower surface of the base semiconductor portion is exposed, An apparatus for manufacturing a light emitter, comprising a semiconductor forming section for forming the base semiconductor section by an ELO method.

Images