Semiconductor device and test method thereof

Abstract

To reduce signal delay and the like in a signal path from an electrode pad to a functional block.SOLUTION: Input / output block A111 and input / output block B112 are connected to electrode pads 121 and 122, respectively. A functional block A101 is connected to the electrode pads 121 and 122 via the input / output block A111. A functional block B102 is connected to the electrode pads 121 and 122 via the input / output block B112. The functional block A101 and the functional block B102 are arranged at positions facing each other with the input / output block A111 and the input / output block B112 interposed therebetween.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a test method thereof, and a design method thereof, and more particularly to a semiconductor device having a plurality of functional blocks, and a test method and design method for such a semiconductor device. [Background technology]

[0002] As a related technique, Patent Document 1 discloses a method for designing a semiconductor device. In Patent Document 1, the semiconductor device is designed by combining a plurality of macrocells and arranging various element circuits on a semiconductor chip. The semiconductor device has a plurality of pads arranged at predetermined intervals along its outer periphery. The semiconductor device also has an AD (Analog to Digital) converter arranged in the center of the chip, and input / output buffer cells arranged on the periphery of the chip. The A / D converter and the input / output buffer cells are connected to each other, and the input / output buffer cells and the pads are connected to each other. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-34650 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, with the advancement of electronic devices in performance and functionality, multiple functional blocks are often mounted on a semiconductor chip. In such semiconductor chips, in order to reduce the number of pads mounted on the semiconductor chip, pads for inputting and outputting signals from each functional block to the outside may be shared among multiple functional blocks. Patent Document 1 does not take into consideration sharing of pads among multiple functional blocks. In Patent Document 1, if a pad is shared among multiple functional blocks, the length of the wiring from the pad to one functional block would be longer than the length of the wiring from the pad to another functional block.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device is provided. The semiconductor device has first and second input / output blocks, a first functional block, and a second functional block. The first functional block is connected to each of a plurality of electrode pads via the first input / output block. The second functional block is connected to each of a plurality of electrode pads via the second input / output block. In the semiconductor device, the first functional block and the second functional block are disposed at positions facing each other with the first and second input / output blocks interposed therebetween. Effect of the Invention

[0007] According to one embodiment, it is possible to reduce the resistance and capacitance of each signal path in a signal path from an electrode pad via a first input / output block to a first functional block, and in a signal path from an electrode pad via a second input / output block to a second functional block. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a portion of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a circuit diagram showing a circuit configuration in the semiconductor device. [Diagram 3] FIG. 3 is a cross-sectional view showing a cross section taken along line AA of FIG. [Figure 4] FIG. 4 is a plan view showing an example of the layout of a semiconductor chip. [Diagram 5] FIG. 5 is a plan view showing another example of the layout of a semiconductor chip. [Figure 6] FIG. 6 is a plan view showing yet another layout example of a semiconductor chip. [Figure 7] FIG. 7 is a flowchart showing a method for designing a semiconductor device. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of a computer device. [Figure 9] FIG. 9 is a block diagram showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 10] FIG. 10 is a block diagram showing a semiconductor device according to the third embodiment of the present disclosure. [Figure 11] FIG. 11 is a block diagram that illustrates a test of a semiconductor device. [Figure 12] FIG. 12 is a plan view showing an example of the layout of a semiconductor device used in the study. [Figure 13] FIG. 13 is a block diagram showing a portion of a semiconductor chip. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Prior to describing the embodiments, the background to the invention will be described. Fig. 12 shows an example of the layout of a semiconductor device (semiconductor chip) used in the study. This semiconductor chip 200 has a plurality of electrode pads 201, an input / output block (input / output circuit) 202, and an internal logic forming region 203. The plurality of electrode pads 201 are arranged side by side in the X direction and the Y direction on the periphery of the semiconductor chip 200. In the semiconductor chip 200, the plurality of electrode pads 201 are arranged stacked on the input / output circuit 202 in order to reduce the chip area.

[0010] A plurality of functional blocks are arranged in the internal logic formation region 203. The functional blocks include, but are not limited to, a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory), and peripheral circuits. In the example of Fig. 12, a functional block (functional block A) 211 and a functional block (functional block B) 212 are arranged in the internal logic formation region 203. At least some of the electrode pads 201 are shared by the functional blocks.

[0011] FIG. 13 shows a part of the semiconductor chip. In this example, two electrode pads 251 and 252 are shared by the functional block A211 and the functional block B212. The electrode pads 251 and 252 correspond to the electrode pad 201 shown in FIG. 12. The electrode pads 251 and 252 are connected to an input / output circuit (input / output circuit A) 221 of the functional block A211 and an input / output circuit (input / output circuit B) 222 for the functional block B212, respectively. The input / output circuit A221 and the input / output circuit B222 each include a block connected to the electrode pad 251 and a block connected to the electrode pad 252. The output circuit A221 and the input / output circuit B222 are arranged side by side in the X direction on the periphery of the semiconductor chip 200.

[0012] 13, the electrode pad 251 is stacked with the input / output circuit A221, and the electrode pad 252 is stacked with the input / output circuit B222. The electrode pad 251 is connected to the input / output circuit A221 via a contact, and is connected to the input / output circuit B222 via a wiring 261. On the other hand, the electrode pad 252 is connected to the input / output circuit B222 via a contact, and is connected to the input / output circuit A221 via a wiring 262. The functional block A211 is connected to the input / output circuit 221. The functional block B212 is connected to the input / output circuit B222.

[0013] Here, in the semiconductor chip, a voltage drop, a change in the timing of a signal change, and noise may occur in the wiring connecting the electrode pad and the input / output circuit and in the wiring connecting the functional block and the input / output circuit. In the design of the semiconductor chip 200, in order to reduce noise and the like, the design is performed so that the wiring does not have resistance and capacitance. In the example of FIG. 13, the electrode pad 251 is stacked on the input / output circuit A221, and the electrode pad 251 and the input / output circuit A221 are connected on the input / output circuit A221. Also, the electrode pad 252 is stacked on the input / output circuit B222, and the electrode pad 252 and the input / output circuit B222 are connected on the input / output circuit B222.

[0014] However, in order to avoid a short circuit between the electrode pad 251 and the input / output circuit B222, the electrode pad 251 is connected to the input / output circuit A221 and the input / output circuit B222 using a wiring 261 that passes through an area outside the input / output circuit A221 and the input / output circuit B222. The electrode pad 252 is also connected to the input / output circuit A221 using a wiring 262 that passes through an area outside the input / output circuit A221 and the input / output circuit B222. In the example of FIG. 13, a block connected to the electrode pad 251 of the input / output circuit A221 and a block connected to the electrode pad 252 are arranged in the X direction. Therefore, the wiring length of the wiring 261 in particular cannot be shortened, and a voltage drop occurs in the wiring 261, and noise also occurs. If the input / output circuit A221 and the input / output circuit B222 are arranged in the Y direction, the wiring length of the wiring 261 and 262 will be shorter than the wiring length in the example of FIG. 13. However, in that case, the wiring length of the wiring between the input / output circuit B222 and the functional block B212 will be longer. The present inventors have focused on the above-mentioned problems and have come up with the following embodiment.

[0015] Hereinafter, an embodiment to which the above-mentioned means for solving the problems are applied will be described in detail with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0016] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more than or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0017] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape or positional relationship of the components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, values, quantities, and ranges).

[0018] [Embodiment 1] 1 shows a part of a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device 100 includes a functional block A101, a functional block B102, an input / output block A111, an input / output block B112, an electrode pad 121, and an electrode pad 122. The functional block A101 and the functional block B102 are each a circuit block for performing a predetermined function. The functional block A101 and the functional block B102 each include circuit elements such as logic elements, active elements, and memory elements.

[0019] The input / output block A111 includes an input / output circuit for the functional block A101. The input / output block B112 includes an input / output circuit for the functional block B102. The electrode pads 121 and 122 are pads for signal input / output shared by the functional block A101 and the functional block B102, respectively. The input / output block A111 and the input / output block B112 each include a block connected to the electrode pad 121 and a block connected to the electrode pad 122. The electrode pad 121 is connected to one block of the input / output block A111 and one block of the input / output block B112. The electrode pad 122 is connected to the other block of the input / output block A111 and the other block of the input / output block B112. The input / output block A111 is connected to the functional block A101. The input / output block B112 is connected to the functional block B102. The electrode pads 121 and 122 are connected to the input / output block A111 and the input / output block B112, respectively, on the input / output block.

[0020] 2 shows a circuit configuration in the semiconductor device 100. Signals input from electrode pads 121 and 122 are branched to an input / output block A111 and an input / output block B112, respectively. The signal input from electrode pad 121 is input to functional block A101 via input / output block A111, and is input to functional block B102 via input / output block B112. The signal input from electrode pad 122 is input to functional block A101 via input / output block A111, and is input to functional block B102 via input / output block B112.

[0021] The selector 115 selectively outputs a signal output by the functional block A101 or a signal output by the functional block B102 in response to a control signal. When the signals input from the electrode pads 121 and 122 are used by the functional block A101, the selector 115 selects the signal output by the functional block A101. When the signals input from the electrode pads 121 and 122 are used by the functional block B102, the selector 115 selects the signal output by the functional block B102.

[0022] In the above, an example has been described in which signals input from the electrode pads 121 and 122 are input to the functional block A101 and the functional block B102, and the selector 115 selects one of the output of the functional block A101 and the output of the functional block B102. However, this embodiment is not limited to this. For example, the signal selection may be performed on the input side of the functional block, and the selector may be disposed between the electrode pads 121 and 122 and the functional block A101 and the functional block B102. In this case, the selector selectively inputs the signals input from the electrode pads 121 and 122 to the functional block A101 or the functional block B102.

[0023] The electrode pads 121 and 122 are formed at positions overlapping one of the input / output block A111 and the input / output block B112. As shown in FIG. 1, in this embodiment, the electrode pad 121 is disposed on the upper layer of the input / output block A111. Also, the electrode pad 122 is disposed on the upper layer of the input / output block B112. In other words, the electrode pad 121 is disposed stacked on the input / output block A111, and the electrode pad 122 is disposed stacked on the input / output block B112. The input / output block A111 and the input / output block B112 are disposed side by side in the Y direction. Also, the function block A101 and the function block B102 are disposed so as to sandwich the input / output block A111 and the input / output block B112 from the Y direction. In other words, the function block A101 and the function block B102 are disposed so as to face each other in the Y direction, sandwiching the input / output block A111 and the input / output block B112 therebetween.

[0024] 3 shows a cross section taken along line AA in FIG. 1. The electrode pad 122 is formed, for example, in an aluminum (AL) layer, which is the uppermost layer of the wiring layer. The wiring 151 is formed in the AL layer, and extracts a signal input from the electrode pad 122 to a region in which the input / output block A111 is formed. The input / output block A111 includes a gate 152 and a diffusion layer 155. The wiring 151 is connected to the gate 152 via a contact formed in the wiring layer. The output of the input / output block A111 is connected to a wiring 161 formed in the AL layer via a contact formed in the wiring layer. The function block A101 includes a gate 171 and a diffusion layer 175. The wiring 161 is connected to the gate 171 via a contact.

[0025] The input / output block B112 includes a gate 153 and a diffusion layer 156. The electrode pad 122 is connected to the gate 153 via a contact formed in the wiring layer in the region where the input / output block B112 is formed. The output of the input / output block B112 is connected to a wiring 162 formed in the AL layer via a contact formed in the wiring layer. The function block B102 includes a gate 172 and a diffusion layer 176. The wiring 162 is connected to the gate 172 via a contact.

[0026] Next, a layout example of a semiconductor chip having the structure shown in FIG. 1 will be described. FIG. 4 shows an example of the layout of a semiconductor chip including a portion of the semiconductor device shown in FIG. 1. In the example of FIG. 4, a semiconductor chip 150a has a function block A101, a function block B102, CPU0-CPU3 (130-133), and RAMs 135 and 136. The semiconductor chip 150a also has a plurality of electrode pads 140 arranged on the periphery in the X and Y directions, and an input / output block 141. In the semiconductor chip 150a, the electrode pads 140 are arranged in an upper layer of the input / output block (input / output circuit) 141, similar to the semiconductor chip 200 shown in FIG. 12. The electrode pads 121 and 122 for the function block A101 and the function block B102 are arranged inside the chip. In the example of FIG. 4, function block A101, function block B102, input / output block A111, and input / output block B112 are arranged near the center of semiconductor chip 150a in the X direction and on the periphery in the Y direction.

[0027] Fig. 5 shows another example of the layout of a semiconductor chip including a portion of the semiconductor device shown in Fig. 1. In the semiconductor chip 150b shown in Fig. 5, the functional block A101, the functional block B102, the input / output block A111, and the input / output block B112 are arranged in the corners of the semiconductor chip. The arrangement of the CPU0-CPU3 (130-133) and the RAMs 135 and 136 in the semiconductor chip 150b may be similar to their arrangement in the semiconductor chip 150a.

[0028] 4 and the semiconductor chip 150b shown in Fig. 5, the semiconductor chip 150a can increase the number of electrode pads 140 and input / output blocks 141 that can be arranged on the periphery of the chip compared to the semiconductor chip 150b. Therefore, when it is desired to arrange a large number of electrode pads 140, it is preferable to arrange the functional block A101, the functional block B102, the input / output block A111, and the input / output block B112 on the edge of the central part of the chip as in the semiconductor chip 150a.

[0029] However, in the semiconductor chip 150a, the functional block A101, the input / output block A111, and the input / output block B112 are arranged between the CPU1 (131) and the RAM 136. Therefore, when forming wiring (digital signal wiring) connecting the CPU1 (131) and the RAM 136, it is difficult to form the wiring in a straight line. In many cases, the digital signal wiring needs to detour around the functional block A101, the input / output block A111, and the input / output block B112. Therefore, in the semiconductor chip 150a, wiring congestion occurs and the degree of freedom of the floor plan is reduced. In contrast, in the semiconductor chip 150b, there is no influence of detouring the digital signal wiring, and the degree of freedom of the floor plan is high. Therefore, when the degree of freedom of the floor plan is prioritized, it is preferable to arrange the functional block A101, the functional block B102, the input / output block A111, and the input / output block B112 in the corners of the chip, as in the semiconductor chip 150b.

[0030] 4 and 5, the semiconductor chip 150a and the semiconductor chip 150b have electrode pads 121 and 122 formed inside the chip. When the semiconductor chip 150a or 150b is connected to a package substrate by wires, the length of the wires connected to the electrode pads 121 and 122 is longer than the length of the wires connected to the electrode pads arranged on the periphery. In this case, for example, there is an increased risk of wire sweep during molding, and there is a possibility of short circuits between the wires.

[0031] 6 shows yet another layout example of a semiconductor chip including the semiconductor device 100. The semiconductor chip 150c shown in FIG. 6 is a semiconductor chip that is flip-chip connected to a package substrate. The semiconductor chip 150c has a plurality of electrode pads 140 that are evenly arranged over the entire surface of the chip. When the semiconductor chip is a flip-chip, there is no risk of wire sweep even when the electrode pads 121 and 122 are arranged inside the chip. For this reason, the structure of this embodiment is well suited to flip-chips.

[0032] In the case of flip chip, if the pads are not evenly arranged, the resin filling the gap between the semiconductor chip and the frame of the package cannot be evenly injected, and the chip and the package cannot be tightly attached to each other. For this reason, the electrode pads may be arranged at positions overlapping the functional block A101 or the functional block B102, as shown in Fig. 6. The electrode pads 145-147 arranged at positions overlapping the functional block A101 or the functional block B102 may be dummy electrode pads that are not connected to anything.

[0033] 7 shows a method for designing the semiconductor device 100. In a functional block placement step, functional blocks are placed according to a floor plan of a semiconductor chip (step S1). Next, each input / output block is placed so as to be sandwiched between multiple functional blocks that share the same electrode pad, and the positions of the input / output blocks are adjusted so that the input / output blocks are lined up in one direction, for example, the Y direction (step S2). Next, an electrode pad shared by multiple functional blocks is placed on one of the input / output blocks (step S3). The electrode pad and the input / output block are connected at the shortest distance (step S4), and the functional block and the input / output block are connected at the shortest distance (step S5).

[0034] The design method shown in FIG. 7 can be implemented by a computer device. FIG. 8 shows an example of the configuration of a computer device. The computer device 500 has one or more processors 501 and one or more memories 502. The memories 502 store a program. The program includes a set of instructions (or software code) for causing the computer device 500 to perform each step of the design method shown in FIG. 7 when the program is loaded into the processor 501. In the computer device 500, the processor 501 reads the program from the memory 502 and executes processing according to the read program, thereby implementing each step of the design method shown in FIG. 7.

[0035] The program may be stored on a non-transitory computer-readable medium or tangible storage medium. By way of example and not limitation, computer-readable medium or tangible storage medium includes RAM, ROM, flash memory, solid-state drive (SSD) or other memory technology, Compact Disc (CD)-ROM, digital versatile disc (DVD), Blu-ray® disk or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or communication medium. By way of example and not limitation, transitory computer-readable medium or communication medium includes electrical, optical, acoustic or other form of propagated signal.

[0036] [effect] In this embodiment, the functional block A101 and the functional block B102 are arranged opposite to each other so as to sandwich the input / output block A111 and the input / output block B112. In this embodiment, the electrode pads 121 and 122 shared by the two functional blocks can be connected to the input / output block A111 and the input / output block B112 with short-distance wiring. In addition, the input / output block A111 and the input / output block B112 can be connected to the functional block A101 and the functional block B102 with short-distance wiring. Therefore, the resistance and capacitance of the wiring from the electrode pads 121 and 122 to the functional block A101 and the functional block B102 can be optimized, and the voltage drop and noise in the signal path can be reduced. In addition, in this embodiment, the electrode pads 121 and 122 are stacked on one of the input / output blocks. Therefore, this embodiment can suppress an increase in the wiring area in the semiconductor chip.

[0037] [Embodiment 2] 9 shows a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device 100a according to this embodiment has a functional block C103 and an input / output block C113 in addition to the configuration of the semiconductor device 100 described in the first embodiment shown in FIG. 1. The input / output block C113 includes an input / output circuit for the functional block C103. In this embodiment, the electrode pads 121 and 122 are shared by the functional block A101, the functional block B102, and the functional block C103. The other configuration may be similar to the configuration of the semiconductor device 100 described in the first embodiment.

[0038] The input / output block A111, the input / output block B112, and the input / output block C113 are arranged in a row along the Y direction. The input / output block C113 is arranged, for example, between the input / output block A111 and the input / output block B112. The electrode pad 121 is formed on any of the three input / output blocks, for example, the input / output block A111. The electrode pad 122 is formed on any of the three input / output blocks, for example, the input / output block B112. The functional block A101 and the functional block B102 are arranged opposite to each other in the Y direction so as to sandwich the input / output blocks therebetween. The functional block C103 is arranged next to the input / output block C113 in the X direction.

[0039] The electrode pad 121 is extended, for example, by wiring in the top layer of the wiring layer, to a region where the input / output block B112 and the input / output block C113 are formed. The electrode pad 122 is extended, for example, by wiring in the top layer of the wiring layer, to a region where the input / output block A111 and the input / output block C113 are formed. The electrode pads 121 and 122 are connected to gates in each input / output block via contacts provided in the wiring layer.

[0040] In this embodiment, the wiring to functional block C103 is slightly longer than the wiring to functional block A101 and functional block B102. However, the length of the wiring to each functional block can be shorter than when three functional blocks and three input / output blocks are arranged side by side in the X direction. In this way, in this embodiment, even if the number of functional blocks is more than two, the resistance and capacitance of the wiring can be optimized, as in the first embodiment, and the voltage drop and noise in the signal path can be reduced.

[0041] The number of functional blocks connected to the electrode pads 121 and 122 is not particularly limited to the above number. For example, the semiconductor device may have four functional blocks. In this case, the input / output block for the fourth functional block (functional block D) may be placed between the input / output block A111 and the input / output block B112. The functional block D may be placed on the opposite side in the X direction, for example, sandwiching the input / output block of the functional block C103 therebetween.

[0042] [Embodiment 3] 10 shows a semiconductor device according to the third embodiment of the present disclosure. The semiconductor device 100b according to this embodiment has test electrode pads (test pads) 125 and 126 in addition to the configuration of the semiconductor device 100 described in the first embodiment shown in FIG. 1. The test pads 125 and 126 are electrically connected to the electrode pads 121 and 122, respectively. The test pad 125 is formed on the input / output block B 112, and the test pad 126 is formed on the input / output block A 111. The other configurations may be similar to the configurations of the semiconductor device 100 described in the first embodiment.

[0043] In general, in a semiconductor chip test, the electrode pads may be damaged by the test needles. For example, if the electrode pads 121 and 122 are damaged, poor adhesion of the bonding wires is likely to occur. To avoid this, in this embodiment, the test pads 125 and 126 are used during testing. The test pads 125 and 126 are damaged by the test needles. However, the electrode pads 121 and 122 are not damaged, so that poor adhesion of the bonding wires can be avoided.

[0044] In the following, it is assumed that the electrode pad 121 and the test pad 125 are electrode pads for signal input, and the electrode pad 122 and the test pad 126 are electrode pads for signal output. In the input / output block A111, the electrode pad 121 and the test pad 125 are connected to an input buffer, and the electrode pad 122 and the test pad 126 are connected to an output buffer. In the input / output block B112, the electrode pad 121 and the test pad 125 are connected to an input buffer, and the electrode pad 122 and the test pad 126 are connected to an output buffer.

[0045] FIG. 11 shows a schematic diagram of a test of the semiconductor device 100c. In the case of an AC (Alternate Current) scan test, probe needles 401 and 402 are brought into contact with the test pad 125 for the input circuit and the test pad 126 for the output circuit, respectively, to perform the test. In FIG. 11, the functional block to be tested is assumed to be the functional block A101. A scan pattern (a test signal) is input from the probe needle 401 to the test pad 125. The scan pattern is input to the functional block A101 via the input / output block A111. The logic circuit part of the functional block A101 operates at the frequency of the product and outputs the operation result. The operation result (output signal) of the functional block A101 is output from the test pad 126 via the input / output block A111. The tester 400 acquires the operation result (signal pattern) via the needle 402. The tester 400 judges whether the functional block A101 is operating normally by determining whether the signal pattern (signal value) acquired from the test pad 126 matches an expected value.

[0046] If the resistance and capacitance of the wiring in the signal path from the test pad 125 to the functional block A101 is large, a delay occurs in the input scan pattern. As a result, the expected value may not be stored in the flip-flop in the functional block A101 operating at the product frequency. In that case, the result finally recognized by the tester will differ from the expected value, and the yield will deteriorate.

[0047] Furthermore, if the resistance and capacitance of the wiring in the signal path from the functional block A101 to the test pad 126 is large, a delay occurs in the signal output from the test pad 126. In that case, the result finally recognized by the tester will differ from the expected value, and the yield will deteriorate. Note that, although it is possible to adjust the sampling period in the tester, since manufacturing variations differ for each semiconductor chip, it is not easy to adjust the sampling time.

[0048] In this embodiment, the test pads 125 and 126 can be connected to the input / output block A111 and the input / output block B112 with short-distance wiring, similar to the electrode pads 121 and 122. Also, the input / output block A111 and the input / output block B112 can be connected to the function block A101 and the function block B102 with short-distance wiring. Therefore, the resistance and capacitance of the wiring from the test pads 125 and 126 to the function block A101 and the function block B102 can be optimized, and the voltage drop and noise in the signal path for testing can be reduced. As a result, the probability that the semiconductor device is determined to be defective in the test can be reduced, and the deterioration of the yield can be suppressed.

[0049] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention. [Explanation of symbols]

[0050] 101: Function block A 102: Function block B 103: Function block C 111: Input / Output Block A 112: Input / Output Block B 113: Input / Output Block C 121, 122: Electrode pads 125, 126: Test pad 115: Selector 130-133: CPU 135, 136: RAM 140: Electrode pad 141: Input / Output block 145-147: Dummy electrode pads 400: Tester 401, 402: Needle 500: Computer equipment 501: Processor 502: Memory

Claims

1. A plurality of electrode pads; first and second input / output blocks connected to the plurality of electrode pads; a first functional block connected to each of the plurality of electrode pads via the first input / output block; a second function block connected to each of the plurality of electrode pads via the second input / output block; a third input / output block connected to the plurality of electrode pads; a third function block connected to each of the plurality of electrode pads via the third input / output block; The semiconductor device, wherein the first functional block and the second functional block are disposed at positions facing each other with the first and second input / output blocks interposed therebetween.

2. 2. The semiconductor device according to claim 1, wherein each of the plurality of electrode pads is formed at a position overlapping one of the first and second input / output blocks.

3. the plurality of electrode pads include a first electrode pad and a second electrode pad; the first electrode pad is formed at a position overlapping one of the first and second input / output blocks; 2. The semiconductor device according to claim 1, wherein said second electrode pad is formed at a position overlapping the other of said first and second input / output blocks.

4. 2. The semiconductor device according to claim 1, wherein the plurality of electrode pads are part of a plurality of electrode pads formed over the entire surface of a chip.

5. 5. The semiconductor device according to claim 4, wherein, among a plurality of electrode pads formed over the entire surface of the chip, electrode pads formed at positions overlapping the first and second functional blocks are dummy electrode pads that are not connected to the first and second input / output blocks.

6. 2 . The semiconductor device according to claim 1 , wherein the first functional block and the second functional block are arranged in positions facing each other with the first input / output block, the second input / output block, and the third input / output block interposed therebetween.

7. A plurality of electrode pads; first and second input / output blocks connected to the plurality of electrode pads; a first functional block connected to each of the plurality of electrode pads via the first input / output block; a second function block connected to each of the plurality of electrode pads via the second input / output block; a plurality of test electrode pads each connected to the plurality of electrode pads and used during testing; the plurality of electrode pads include an electrode pad for signal input and an electrode pad for signal output, The semiconductor device, wherein the plurality of test electrode pads include a test electrode pad connected to the signal input electrode pad and a test electrode pad connected to the signal output electrode pad.

8. A method for testing a semiconductor device according to claim 7, comprising the steps of: a first probe needle is brought into contact with a test electrode pad connected to the signal input electrode pad, and a test signal is input from the first probe to the first functional block or the second functional block via the first and second input / output blocks; bringing a second probe needle into contact with a test electrode pad connected to the signal output electrode pad, and acquiring an output signal of the first functional block or the second functional block outputted from the second probe via the first and second input / output blocks; A test method comprising: comparing the output signal with an expected value of the test signal to determine whether the first functional block or the second functional block is operating normally.

9. A plurality of first electrode pads; first and second input / output blocks connected to the plurality of first electrode pads; a first functional block connected to each of the first electrode pads via the first input / output block; a second function block connected to each of the first electrode pads via the second input / output block; the first functional block and the second functional block are disposed in positions facing each other with the first and second input / output blocks interposed therebetween; the first functional block, the second functional block, the first input / output block, and the second input / output block are disposed in a center portion of a semiconductor chip in a first direction and at an end portion in a second direction perpendicular to the first direction; a plurality of second electrode pads arranged on a peripheral portion of the semiconductor chip; The semiconductor device further comprises a package substrate connected to the plurality of first and second electrode pads by wires.

10. A plurality of first electrode pads; first and second input / output blocks connected to the plurality of first electrode pads; a first functional block connected to each of the first electrode pads via the first input / output block; a second function block connected to each of the first electrode pads via the second input / output block; the first functional block and the second functional block are disposed in positions facing each other with the first and second input / output blocks interposed therebetween; the first functional block, the second functional block, the first input / output block, and the second input / output block are arranged in a corner portion of a semiconductor chip; a plurality of second electrode pads arranged on a peripheral portion of the semiconductor chip; The semiconductor device further comprises a package substrate connected to the plurality of first and second electrode pads by wires.

11. A plurality of first electrode pads; first and second input / output blocks connected to the plurality of first electrode pads; a first functional block connected to each of the first electrode pads via the first input / output block; a second function block connected to each of the first electrode pads via the second input / output block; the first functional block and the second functional block are disposed in positions facing each other with the first and second input / output blocks interposed therebetween; the first functional block, the second functional block, the first input / output block, and the second input / output block are arranged in a corner portion of a semiconductor chip; a plurality of second electrode pads disposed on an entire surface of the semiconductor chip; The semiconductor device further comprises a package substrate that is flip-chip connected to the plurality of first and second electrode pads.

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