Noise-Shaping Successive Approximation Register (SAR) Analog-to-Digital Converter

Abstract

In a particular aspect, an analog-to-digital converter (ADC) includes a comparator having a first input, a second input, and an output. The ADC also includes a digital-to-analog converter (DAC) coupled to the first input of the comparator, a switching circuit, a first capacitor coupled between the first input of the comparator and the switching circuit, a second capacitor coupled between the first input of the comparator and the switching circuit, and an amplifier circuit having an input and an output, the input of the amplifier circuit being coupled to the switching circuit. The ADC further includes a first switch coupled between the output of the amplifier circuit and the DAC, and a successive approximation register (SAR) having an input and an output, the input of the SAR being coupled to the output of the comparator and the output of the SAR being coupled to the DAC.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 385,709, filed in the United States Patent Office on July 26, 2021, the entire contents of which are incorporated herein as if fully set forth below and for all applicable purposes. [Background technology]

[0002] Field Aspects of the present disclosure relate generally to analog-to-digital converters (ADCs), and more specifically to successive approximation ADCs.

[0003] background Analog-to-digital converters (ADCs) are used to convert analog signals to digital signals. One type of ADC is the successive approximation ADC, which uses successive digital comparison to convert analog signals to digital signals. ADCs are popular in advanced technologies to implement low-power ADCs. Summary of the Invention [Means for solving the problem]

[0004] The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an exhaustive overview of all contemplated embodiments, and is not intended to identify key or critical elements of all embodiments or to delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0005] A first aspect relates to an analog-to-digital converter (ADC). The ADC includes a comparator having a first input, a second input, and an output. The ADC also includes a digital-to-analog converter (DAC) coupled to the first input of the comparator, a switching circuit, a first capacitor coupled between the first input of the comparator and the switching circuit, a second capacitor coupled between the first input of the comparator and the switching circuit, and an amplifier circuit having an input and an output, the input of the amplifier circuit being coupled to the switching circuit. The ADC further includes a first switch coupled between the output of the amplifier circuit and the DAC, and a successive approximation register (SAR) having an input and an output, the input of the SAR being coupled to the output of the comparator and the output of the SAR being coupled to the DAC.

[0006] A second aspect relates to a system. The system includes an analog-to-digital converter (ADC). The ADC includes a comparator having a first input, a second input, and an output, a digital-to-analog converter (DAC) coupled to the input of the ADC and the first input of the comparator, a switching circuit coupled to the input of the ADC, a first capacitor coupled between the first input of the comparator and the switching circuit, a second capacitor coupled between the first input of the comparator and the switching circuit, an amplifier circuit having an input and an output, the input of the amplifier circuit being coupled to the switching circuit, a first switch coupled between the output of the amplifier circuit and the DAC, and a successive approximation register (SAR) having an input, a first output, and a second output, the input of the SAR being coupled to the output of the comparator, the first output of the SAR being coupled to the DAC, and the second output being coupled to the output of the ADC. The system also includes a receiver coupled to the input of the ADC and a processor coupled to the output of the ADC.

[0007] A third aspect relates to a method of noise shaping in an analog-to-digital converter (ADC), the ADC including a digital-to-analog converter (DAC) having an output, a comparator having a first input coupled to the output of the DAC and a second input coupled to a common mode voltage or ground, a first capacitor, and an amplifier circuit, the method including coupling the first capacitor between the output of the DAC and an input of the ADC during a first sampling phase, coupling the first capacitor between the output of the DAC and ground during a first conversion phase, coupling the first capacitor between the output of the DAC and an input of the amplifier circuit during a second sampling phase, and coupling an output of the amplifier circuit to the output of the DAC. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 illustrates an example of a system including an ADC, in accordance with certain aspects of the present disclosure. [Diagram 2] FIG. 1 illustrates another example of a system including an ADC, in accordance with certain aspects of the present disclosure. [Diagram 3] FIG. 2 illustrates an example of a successive approximation ADC in accordance with certain aspects of the present disclosure. [Figure 4] FIG. 2 illustrates an example of an ADC including a capacitive digital-to-analog converter (DAC) in accordance with certain aspects of the present disclosure. [Diagram 5] FIG. 2 illustrates an exemplary embodiment of a capacitive DAC in accordance with certain aspects of the present disclosure. [Figure 6] FIG. 2 illustrates an example of an ADC with noise shaping using charge sharing, in accordance with certain aspects of the present disclosure. [Figure 7] 1 is a plot illustrating an example of noise shaping degradation due to charge sharing, in accordance with certain aspects of the present disclosure. [Figure 8] FIG. 2 illustrates an example of an ADC including a first capacitor and a second capacitor using noise shaping in accordance with certain aspects of the present disclosure. [Figure 9A]FIG. 9 illustrates an example of an equivalent circuit of the ADC of FIG. 8 during the sampling phase of the kth ADC cycle in accordance with certain aspects of the present disclosure. [Figure 9B] FIG. 9 illustrates an example of an equivalent circuit of the ADC of FIG. 8 during the conversion phase of the kth ADC cycle in accordance with certain aspects of the present disclosure. [Figure 9C] FIG. 9 illustrates an example of an equivalent circuit of the ADC of FIG. 8 during the sampling phase of the (k+1)th ADC cycle in accordance with certain aspects of the present disclosure. [Figure 9D] FIG. 9 illustrates an example of an equivalent circuit of the ADC of FIG. 8 during the conversion phase of the (k+1)th ADC cycle in accordance with certain aspects of the present disclosure. [Figure 10] FIG. 2 illustrates an exemplary embodiment of an amplifier circuit in accordance with certain aspects of the present disclosure. [Figure 11A] FIG. 11 illustrates an example of an equivalent circuit of the ADC of FIG. 10 during the sampling phase of the kth ADC cycle in accordance with certain aspects of the present disclosure. [Figure 11B] FIG. 11 illustrates an example of an equivalent circuit of the ADC of FIG. 10 during the conversion phase of the kth ADC cycle in accordance with certain aspects of the present disclosure. [Figure 11C] FIG. 11 illustrates an example of an equivalent circuit of the ADC of FIG. 10 during the sampling phase of the (k+1)th ADC cycle in accordance with certain aspects of the present disclosure. [Figure 11D] FIG. 11 illustrates an example of an equivalent circuit of the ADC of FIG. 10 during the conversion phase of the (k+1)th ADC cycle in accordance with certain aspects of the present disclosure. [Figure 12] FIG. 2 illustrates an exemplary embodiment of a switching circuit in accordance with certain aspects of the present disclosure. [Figure 13] FIG. 2 illustrates an exemplary embodiment of an amplifier circuit including an auto-zeroing circuit in accordance with certain aspects of the present disclosure. [Figure 14A] FIG. 2 illustrates an example of an equivalent circuit of an amplifier circuit during an auto-zeroing phase, in accordance with certain aspects of the present disclosure. [Figure 14B] FIG. 2 illustrates an example of an equivalent circuit of an amplifier circuit during a sampling phase in accordance with certain aspects of the present disclosure. [Figure 15] 1 is a flow chart illustrating a method of noise shaping in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The detailed description set forth below, in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0010] ADCs may be used in systems that convert analog signals to digital signals. In this regard, FIG. 1 illustrates an example of a system 110 including an ADC 140 having an input 142 and an output 144, according to certain aspects. The ADC 140 is configured to convert an analog signal at the input 142 of the ADC 140 to a digital signal at the output 144 of the ADC 140. The system 110 may also include a receiver 130 and a processor 150. The receiver 130 has an input 132 and an output 134 coupled to the input 142 of the ADC 140. The processor 150 is coupled to the output 144 of the ADC 140.

[0011] In one example, the system 110 may be part of a wireless communication device (e.g., a handset). In this example, an input 132 of the receiver 130 may be coupled to one or more antennas 120, and the receiver 130 is configured to receive a radio frequency (RF) signal at the input 132 via the one or more antennas 120. The RF signal may be transmitted from a base station, an access point, or another wireless communication device. The receiver 130 may be configured to process the received RF signal into an analog baseband signal and output the analog baseband signal to the ADC 140 for digital conversion. The processing performed by the receiver 130 may include frequency down-conversion, filtering, amplification, etc. The ADC 140 converts the analog baseband signal to a digital signal and output the digital signal to the processor 150. The processor 150 may process the digital signal to recover data from the digital signal. The processing performed by the processor 150 may include demodulation, decoding, etc. Processor 150 may include a processor core, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another programmable logic device, or any combination thereof.

[0012] 2 illustrates another example of a system 210 including an ADC 240 having an input 242 and an output 244, in accordance with certain aspects. The ADC 240 is configured to convert an analog signal at the input 242 of the ADC 240 to a digital signal at the output 244 of the ADC 240. The system 210 also includes a receiver 230 and a processor 250. The receiver 230 has an input 232 and an output 234 coupled to the input 242 of the ADC 240. The processor 250 is coupled to the output 244 of the ADC 240.

[0013] In this example, the input 232 of the receiver 230 is coupled to the wired channel 220 and may be configured to receive an analog signal via the wired channel 220. The wired channel 220 (also referred to as a wired link) may include one or more metal traces, one or more metal wires, a cable, or any combination thereof. In this example, the wired channel 220 is coupled between the device 225 and the input 232 of the receiver 230, and a transmit driver (not shown) in the device 225 transmits an analog signal via the wired channel 220 to the receiver 230. The device 225 may include a peripheral device, an audio device, a sensor device (e.g., a temperature sensor, a medical sensor, etc.), or another type of device.

[0014] In this example, receiver 230 may process analog signals from wired channel 220 into processed analog signals and output the processed analog signals to ADC 240 for digital conversion. The processing performed by receiver 230 may include amplification, equalization, etc. ADC 240 converts the processed analog signals to digital signals and outputs the digital signals to processor 250 for processing. Processor 250 may include a processor core, an audio codec, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another programmable logic device, or any combination thereof.

[0015] Each of the ADC 140 of FIG. 1 and the ADC 240 of FIG. 2 may be implemented using a successive approximation ADC (also called a successive approximation register (SAR) ADC). The successive approximation ADC may include a comparator, a digital-to-analog converter (DAC), and a successive approximation register (SAR). The SAR outputs a digital signal (also called a digital code) to the DAC, which converts the digital signal to an output voltage. The comparator compares the output voltage of the DAC with an analog input voltage and outputs a comparison signal based on the comparison with the SAR. The SAR sequentially resolves bits of the digital signal based on the comparison signal, and the resolved bits of the digital signal provide a digital value that is a digital representation of the analog input voltage. Various implementations of the SAR (e.g., using flip-flops and / or combinational logic) are well known in the art. The SAR is sometimes referred to as SAR logic.

[0016] FIG. 3 shows a simplified block diagram of an example of a successive approximation ADC 310. The ADC 310 receives a 1-bit ("V") analog input 312. in ") and outputs the analog input voltage V in is configured to convert the analog input voltage V in Provide a digital representation of the

[0017] The ADC 310 includes a sample and hold circuit 320, a comparator 330, a SAR 340, and a DAC 350. The sample and hold circuit 320 has an input 322 coupled to the analog input 312 of the ADC 310, and an output 324. The comparator 330 has a first input 332 coupled to the output 324 of the sample and hold circuit 320, a second input 334, and an output 336. The SAR 340 has an input 342 coupled to the output 336 of the comparator 330, a first output 344, and a second output 346 coupled to the digital output 315 of the ADC 310. The DAC 350 has an input 352 coupled to the first output 344 of the SAR 340, and an output 354 coupled to the second input 334 of the comparator 330.

[0018] A sample and hold circuit 320 receives an analog input voltage V at an input 322. in Receives the analog input voltage V in and the sampled analog input voltage V in at output 324. DAC 350 receives the N-bit digital signal from SAR 340 at input 352 and converts the digital signal into a DAC voltage ("V DAC ") at output 354, which is a DAC voltage V DAC The device is configured to output:

[0019] The comparator 330 detects the sampled analog input voltage V in at a first input 332 and a DAC voltage V DAC at a second input 334 and a sampled analog input voltage V in DAC voltage V DAC and outputting a comparison signal at output 336 based on the comparison. In certain aspects, the logic value (i.e., logic state) of the comparison signal is a function of the sampled analog input voltage V in is the DAC voltage V DACThe SAR 340 uses the comparison signal from the comparator 330 and the DAC 350 to calculate the sampled analog input voltage V in to a digital value at digital output 315.

[0020] The ADC310 converts an analog input voltage V in , which is converted to a digital value at the digital output 315. During the sampling phase, the sample and hold circuit 320 converts the analog input voltage V in During the conversion phase, the sample-and-hold circuit 320 is configured to sample the sampled analog input voltage V in to a first input 332 of the comparator 330.

[0021] During the conversion phase, the SAR 340 uses the comparison signal from the comparator 330 and the DAC 350 to convert the sampled analog input voltage V in , to a digital value. To do this, the SAR 340 outputs an N-bit digital signal to the DAC 350 via the first output 344 and sequentially resolves the N bits of the digital signal based on the comparison signal from the comparator 330 using a binary search or another search algorithm. The SAR 340 begins the binary search with a most significant bit (MSB) of the digital signal (also called a digital code). To resolve the MSB, the SAR 340 may set the MSB to 1 and set the remaining bits of the digital signal to 0. The SAR 340 may then resolve the MSB based on the comparison signal from the comparator 330. For example, if the comparison signal is DAC The sampled analog input voltage V in If it indicates less than, the SAR 340 may resolve the MSB to a bit value of 1, and the comparison signal is the DAC voltage V DAC The sampled analog input voltage V inIf it indicates greater than, SAR 340 may resolve the MSB to a bit value of 0.

[0022] After resolving the MSB, the SAR 340 repeats the above process for each of the remaining bits of the digital signal to resolve the remaining bits of the digital signal. After all N bits of the digital signal have been resolved, the SAR 340 outputs the resolved bits at the digital output 315 of the ADC 310 via the second output 346. The resolved bits of the digital signal are then converted into a digital signal based on the sampled analog input voltage V in provides a digital value that is a digital representation of

[0023] In certain aspects, the DAC 350 may be implemented using a capacitive DAC. In these aspects, a sample-and-hold function may be incorporated within the capacitive DAC, eliminating the need for a separate sample-and-hold circuit (e.g., the sample-and-hold circuit 320). In this regard, FIG. 4 illustrates an example of a successive approximation ADC 410 including a capacitive DAC 420. The capacitive DAC 420 may be implemented using any one of a variety of capacitive DACs known in the art. An exemplary embodiment of the capacitive DAC 420 is further described below with reference to FIG. 5. As discussed further below, the capacitive DAC 420 is configured to convert the digital signal from the SAR 340 to one of a finite number of voltages based on the bit values ​​of the digital signal (also referred to as a digital code).

[0024] The ADC 410 also includes the comparator 330 and the SAR 340 discussed above. The ADC 410 receives the signal at the analog input 412 ("V in ") and outputs the analog input voltage V in to a digital value and output the digital value at digital output 415.

[0025] In this example, the capacitive DAC 420 has a first input 422, a second input 424, and an output 426. The first input 422 is coupled to the analog input 412 of the ADC 410, and the second input 424 is coupled to the first output 344 of the SAR. The output 426 of the capacitive DAC 420 is coupled to the first input 332 of the comparator 330. The second input 334 of the comparator 330 is coupled to a common mode voltage V CM is bound to

[0026] The ADC410 performs an analog-to-digital conversion operation, which includes a sampling phase and a conversion phase, by converting an analog input voltage V in DAC 420 is configured to convert the analog input voltage V in During the conversion phase, the capacitive DAC 420 samples the digital signal from the SAR 340 as a DAC voltage V DAC It is configured to convert

[0027] The capacitive DAC 420 outputs a out In one example, the output voltage V out is the sampled analog input voltage V in and the DAC voltage V DAC The output voltage V out also depends on the common-mode voltage V, as discussed further below. CM In this example, the comparator 330 may include the output voltage V out is the common mode voltage V CM and outputs a comparison signal to the SAR 340 based on the comparison.

[0028] During the conversion phase, the SAR 340 sequentially resolves the N bits of the digital signal based on the comparison signal from the comparator 330 starting from the MSB using a binary search or another search algorithm. After all N bits of the digital signal are resolved, the SAR 340 outputs the resolved bits at the digital output 415 of the ADC 410 via the second output 346. The resolved bits of the digital signal are then converted into a digital signal based on the sampled analog input voltage V in provides a digital value that is a digital representation of

[0029] 5 illustrates an exemplary embodiment of a capacitive DAC 420 according to certain aspects. In this example, the capacitive DAC 420 includes a capacitor array 555, a switching circuit 570, and a switch 540. The capacitor array 555 includes a set of capacitors 560-1 to 560-N, each of which corresponds to a respective one of the bits of the digital signal from the SAR 340. More specifically, the capacitors 560-N correspond to the MSB and the capacitor 560-1 corresponds to the least significant bit (LSB) of the digital signal. Each of the capacitors 560-1 to 560-N has a respective first terminal 564-1 to 564-N coupled to the output 426 of the capacitive DAC 420.

[0030] In a particular embodiment, capacitors 560-1 through 560-N have binary weighted capacitances, with capacitor 560-N corresponding to the MSB having the largest capacitance and capacitor 560-1 corresponding to the LSB having the smallest capacitance. In this example, the capacitance of capacitor 560-1 corresponding to the LSB may be equal to unit capacitance. The capacitances of the other capacitors 560-2 through 560-N may be given by: C k =C u 2 k (1) In the formula, C uis the unit capacitance, and k is a capacitance index with values ​​from k=0 to k=N-1. In equation (1), k=0 corresponds to the capacitance of capacitor 560-1, and k=N-1 corresponds to the capacitance of capacitor 560-N. Therefore, capacitance C0 is the capacitance of capacitor 560-1 corresponding to the LSB, and capacitance C N-1 is the capacitance of capacitor 560-N corresponding to the MSB. In this example, each of capacitors 560-N through 560-2 shown in Figure 5 has a capacitance approximately equal to twice the capacitance of the capacitor immediately to its right. For example, capacitor 560-N has twice the capacitance of capacitor 560-(N-1), which has twice the capacitance of capacitor 560-(N-2), and so on.

[0031] Capacitor array 555 and common mode voltage V CM 5, the switch 540 is coupled between the first terminals 564-1 to 564-N of the capacitors 560-1 to 560-N and the common-mode voltage V CM In this example, first terminals 564-1 to 564-N of capacitors 560-1 to 560-N are coupled to output 426 of capacitive DAC 420, so switch 540 couples output 426 to common-mode voltage V CM is connected between

[0032] The switching circuit 570 includes switches 572-1 through 572-N, each coupled to a respective one of the capacitors 560-1 through 560-N in the capacitor array 555. Each of the switches 572-1 through 572-N is configured to selectively couple a second terminal 566-1 through 566-N of a respective capacitor 560-1 through 560-N to an input line 584, a reference line 586, or a ground line 588, as discussed further below. The input line 584 is coupled to the first input 422 of the capacitive DAC 420 to receive the analog input voltage V in The reference line 586 receives a reference voltage V refand ground line 588 is coupled to ground.

[0033] The switching circuit 570 also includes switch control logic 575 configured to receive the digital signal from the SAR 340 and control the switches 572-1 to 572-N based on the bit values ​​of the digital signal during the conversion phase. For ease of illustration, in FIG. 5, the individual connections between the switches 572-1 to 572-N and the switch control logic 575 are not shown. In one example, when the bit of the digital signal is a one, the switch control logic 575 causes the respective switch 572-1 to 572-N to couple the second terminal 566-1 to 566-N of the respective capacitor 560-1 to 560-N to the reference line 586. When the bit of the digital signal is a zero, the switch control logic 575 causes the respective switch 572-1 to 572-N to couple the second terminal 566-1 to 566-N of the respective capacitor 560-1 to 560-N to the ground line 588.

[0034] In this example, during the sampling phase, switch 540 is turned on (i.e., closed) and first terminals 564-1 to 564-N of capacitors 560-1 to 560-N are coupled to a common-mode voltage V CM The analog input voltage V in To sample the analog input voltage V, the switch control logic 575 couples each of the switches 572-1 to 572-N to the second terminals 566-1 to 566-N of the respective capacitors 560-1 to 560-N. in 5 is coupled to an input line 584 receiving an input signal 572-1 through 572-N. Note that FIG. 5 shows the positions of switches 572-1 through 572-N during the sampling phase.

[0035] During the conversion phase, switch 540 is turned off (i.e., open) and the first terminals 564-1 to 564-N of capacitors 560-1 to 560-N are coupled to a common-mode voltage V CMAlso during the conversion phase, the capacitive DAC 420 outputs an output voltage at the output 426 based on the digital signal from the SAR 340. The output voltage can be given by the following equation:

[0036]

number

[0037] In the formula, V out is the output voltage of the capacitive DAC420, and V in is the sampled analog input voltage V in and V CM is the common-mode voltage, and V ref is the reference voltage, and B k is a bit of the digital signal and k is the bit index. In this example, B N-1 is the MSB of the digital signal and B0 is the LSB of the digital signal.

[0038] During the conversion phase, the SAR 340 outputs the digital signal to the capacitive DAC 420 and sequentially resolves the N bits of the digital signal based on the comparison signal from the comparator 330. In a particular embodiment, the SAR 340 sequentially resolves the N bits of the digital signal using a binary search in which the SAR 340 starts from the MSB of the digital signal.

[0039] To resolve the MSB of a digital signal, the SAR440 selects the MSB (i.e., B N-1 ) to 1, and each of the remaining bits of the digital signal (i.e., B N-2 〜B0) to 0. Then, the SAR 340 resolves the MSB based on the comparison signal from the comparator 330. When the comparison signal is V out V CM To indicate greater than (i.e., V out -V CM is greater than 0), the SAR 340 resolves the MSB to a bit value of 0. out V CM To indicate that it is less than (i.e., Vout -V CM is less than 0), SAR 340 resolves the MSB to a bit value of 1.

[0040] MSB (i.e., B N-1 ), the SAR 340 extracts the second most significant bit (i.e., B N-2 To do this, the SAR 340 sets the MSB to the resolved bit value and the second most significant bit (i.e., B N-2 ) to 1, and the remaining bits (i.e., B N-3 1 to 10. Then, the SAR 340 resolves the second most significant bit based on the comparison signal from the comparator 330. When the comparison signal is V out V CM To indicate greater than (i.e., V out -V CM is greater than 0), the SAR 340 resolves the second most significant bit to a bit value of 0. out V CM To indicate that it is less than (i.e., V out -V CM is less than 0), SAR 340 resolves the second most significant bit to a bit value of 1.

[0041] The SAR340 converts the remaining bits of the digital signal (i.e., B N-3 The above process is repeated for each of the N bits of the digital signal (i.e., B N-1 After all of the inputs (B1 to B0) are resolved, the SAR 340 outputs the resolved bits at the digital output 415 of the ADC 410, and the resolved bits of the digital signal are proportional to the sampled analog input voltage V in provides a digital value that is a digital representation of

[0042] It should be understood that the capacitive DAC 420 is not limited to the exemplary embodiment shown in FIG. 5. In general, the capacitive DAC 420 can include a switching circuit and binary weighted capacitors, each of which has a respective first terminal and a respective second terminal. The first terminals of the capacitors may be coupled to the output 426 of the capacitive DAC 420. During the conversion phase, the switching circuit controls the switching of the second terminals of the binary weighted capacitors between two or more voltages based on the digital signal from the SAR 340. In one example, the two or more voltages include a reference voltage and a ground. In another example, the two or more voltages include a positive reference voltage and a negative reference voltage. In some embodiments, the capacitor array 550 may be implemented using a slip capacitor array, or another type of capacitor array. The capacitor array 550 may also be non-binary weighted in some embodiments. Thus, it should be understood that the capacitive DAC 420 is not limited to a particular embodiment.

[0043] In some embodiments, the common mode voltage V CM may be approximately 0. In these embodiments, the second input 334 of the comparator 330 may be coupled to ground, and the switch 540 in the capacitive DAC 420 may be coupled between the first terminals 564-1 through 564-N of the capacitors 560-1 through 560-N and ground.

[0044] The ADC410 receives the input analog voltage V in The analog-to-digital conversion operations discussed above may be performed periodically to track changes in. For example, the ADC 410 may perform multiple analog-to-digital conversion operations sequentially over multiple ADC cycles, one of the analog-to-digital conversion operations being performed in each of the ADC cycles.

[0045] The ADC 410 suffers from quantization noise in its digital output 415. This is because the ADC 410 inAt the end of each ADC cycle, the quantization results in a residual voltage V at the output 426 of the capacitive DAC 420. res Residual voltage V res is the sampled analog input voltage V in and the voltage corresponding to the resolved bits of the digital signal at the end of the conversion phase.

[0046] An ADC can use noise shaping to reduce quantization noise. For example, noise shaping can be used to reduce the quantization noise by shaping the residual voltage from the previous ADC cycle into the input analog voltage V sampled in the current ADC cycle. in This gives a given noise shaping in the z-domain: Y=X+(1-z -1 )Q (3) where Y corresponds to the output of the ADC, X corresponds to the input of the ADC, and Q corresponds to the quantization noise.

[0047] 6 shows an example of an ADC 605 that uses one approach for noise shaping based on equation (3). In this example, the ADC 605 includes the capacitive DAC 420, the comparator 330, and the SAR 340 discussed above. For noise shaping, the ADC 605 also includes an amplifier 610, a holding capacitor 630, a first switch 620, and a second switch 625. The amplifier 610 has a first input 612 coupled to the output 426 of the capacitive DAC 420 and a common-mode voltage V CM DAC 626 and a first terminal 632 of a holding capacitor 630, and a second terminal 634 of the holding capacitor 630 and an output 616 of the amplifier 610. A first switch 620 is coupled between the output 426 of the capacitive DAC and a first terminal 632 of a holding capacitor 630, and a second switch 625 is coupled between the first terminal 632 of the holding capacitor 630 and the output 616 of the amplifier 610. A second terminal 634 of the holding capacitor 630 is coupled to ground.

[0048] During the conversion phase of the ADC cycle, the second switch 625 is turned on (i.e., closed) and the first switch 620 is turned off (i.e., open), so that the holding capacitor 630 is coupled to the output 616 of the amplifier 610. At the end of the conversion phase, the amplifier 610 detects the residual voltage V res The residual voltage V res By charging the holding capacitor 630 based on res from a first input 612 of the amplifier 610 (coupled to the output 426 of the capacitive DAC 420) to a holding capacitor 630. In a particular embodiment, the output 616 of the amplifier 610 communicates a common-mode voltage V CM Thus, the holding capacitor 630 may be connected to the residual voltage V res and the common mode voltage V CM In these embodiments, the holding capacitor 630 may charge to a voltage including the common-mode voltage V CM , so that switch 540 shown in FIG. 5 is open during the sampling phase or is omitted in these embodiments.

[0049] During the sampling phase of the next ADC cycle, the second switch 625 is turned off (i.e., open) and the first switch 620 is turned on (i.e., closed), resulting in the holding capacitor 630 being coupled to the output 426 of the capacitive DAC 420. This in turn couples the holding capacitor 630 to the first terminals 564-1 to 564-N of the capacitors 560-1 to 560-N in the capacitive DAC 420, thereby coupling the residual voltage V res A portion of the sampled input analog voltage V in The sampled input analog voltage V in Residual voltage V added to res The magnitude of is given by:

[0050]

number

[0051] In the formula, V CS is the sampled input analog voltage V in Residual voltage V added to res where C1 is the capacitance of the holding capacitor 630, and C2 is the total capacitance of the capacitors 560-1 to 560-N in the capacitive DAC 420. res The magnitude of can be given by: V rt = α V res (5) In the formula, V rt is the residual voltage V transmitted to the capacitive DAC420 res , where α is less than 1 (e.g., due to charge sharing). Ideally, to fully implement noise shaping according to equation (3), α is equal to 1. In the example of FIG. 6, α is approximately equal to C1 / (C1+C2). Thus, charge sharing is a function of the residual voltage V res is reduced based on the capacitor ratio C1 / (C1+C2).

[0052] Noise shaping degrades as α decreases, an example of which is shown in FIG. 7. FIG. 7 shows an example quantization noise spectrum 715 for the ideal case where α is equal to 1, and an example quantization noise spectrum 720 for the case where α is less than 1. As shown in FIG. 7, when α is less than 1, the magnitude of the quantization noise is higher at lower frequencies compared to the ideal case. Therefore, it is desirable to keep α close to 1 to reduce noise shaping degradation. In FIG. 6, α is equal to the capacitor ratio C1 / (C1+C2), so to achieve a capacitor ratio C1 / (C1+C2) close to 1, it is necessary to make the holding capacitor 630 much larger (e.g., 10 times larger) than the capacitor in the capacitive DAC 420. The large size of the holding capacitor 630 significantly increases the area of ​​the ADC 605.

[0053] FIG. 8 illustrates an example of a successive approximation ADC 805 with noise shaping in accordance with certain aspects of the present disclosure. The ADC 805 receives a signal at its input 808 ("V in ") and outputs the analog input voltage V in to a digital value and output the digital value at output 815. The ADC 805 may be used to implement the ADC 140 of Figure 1, where the input 808 of the ADC 805 is coupled to the output 234 of the receiver 130 and the output 815 of the ADC 805 is coupled to the processor 150. The ADC 805 may also be used to implement the ADC 240 of Figure 2, where the input 808 of the ADC 805 is coupled to the output 234 of the receiver 230 and the output 815 of the ADC 805 is coupled to the processor 250.

[0054] The ADC 805 includes the above-discussed capacitive DAC 420, the comparator 330, and the SAR 340. For noise shaping, the ADC 805 further includes a first capacitor 840, a second capacitor 850, a switching circuit 810, an amplifier circuit 830, and a switch 860.

[0055] The switching circuit 810 includes a first terminal 812, a second terminal 814, a third terminal 816, a fourth terminal 818, and a fifth terminal 820. A first capacitor 840 is coupled between the output 426 of the capacitive DAC 420 and the switching circuit 810. In the example of FIG. 8, the first capacitor 840 has a first terminal 842 coupled to the output 426 of the capacitive DAC 420 and a second terminal 844 coupled to the first terminal 812 of the switching circuit 810. A second capacitor 850 is coupled between the output 426 of the capacitive DAC 420 and the switching circuit 810. In the example of FIG. 8, the second capacitor 850 has a first terminal 852 coupled to the output 426 of the capacitive DAC 420 and a second terminal 854 coupled to the second terminal 814 of the switching circuit 810. A third terminal 816 of the switching circuit 810 is coupled to an input 808 of the ADC 805 to receive an input analog voltage V in, and a fourth terminal 818 of the switching circuit 810 is coupled to ground.

[0056] The amplifier circuit 830 has an input 832 and an output 834. The input 832 of the amplifier circuit 830 is coupled to a fifth terminal 820 of the switching circuit 810. A switch 860 is coupled between an output 834 of the amplifier circuit 830 and the output 426 of the capacitive DAC 420. The amplifier circuit 830 may be implemented using one or more amplifiers, as discussed further below.

[0057] The switching circuit 810 is configured to selectively couple a second terminal 844 of the first capacitor 840 to one of the input 808 of the ADC 805, ground, and an input 832 of the amplifier circuit 830. The switching circuit 810 is also configured to selectively couple a second terminal 854 of the second capacitor 850 to one of the input 808 of the ADC 805, ground, and an input 832 of the amplifier circuit 830. The switching circuit 810 may be implemented using multiple switches, as discussed further below.

[0058] In certain embodiments, the switching of switching circuit 810 and the switching of switch 860 are controlled by a controller 870, as discussed further below. For ease of illustration, the individual connections between controller 870 and switching circuit 810, and between controller 870 and switch 860 are not shown in FIG.

[0059] An example operation of the ADC 805 will now be discussed with reference to Figures 9A-9D according to certain embodiments. Figures 9A and 9B show an example of an equivalent circuit of the ADC 805 during the sampling and conversion phases of the kth ADC cycle, respectively. Figures 9C and 9D show an example of an equivalent circuit of the ADC 805 during the sampling and conversion phases of the next ADC cycle (i.e., the (k+1)th ADC cycle), respectively. As will be discussed further below, the switch 540 shown in Figure 5 may be always open for noise shaping or may be omitted.

[0060] During the sampling phase of the kth ADC cycle shown in FIG. 9A, the controller 870 causes the switching circuit 810 (shown in FIG. 8) to couple the second terminal 844 of the first capacitor 840 to the input 808 of the ADC 805. This causes the first capacitor 840 to convert the input analog voltage V in The controller 870 also causes the switching circuit 810 to couple a second terminal 854 of the second capacitor 850 to the input 832 of the amplifier circuit 830. As discussed further below, the second capacitor 850 holds a residual voltage from the previous ADC cycle (i.e., the (k-1)th ADC cycle).

[0061] Also, during the sampling phase of the kth ADC cycle, the controller 870 turns on the switch 860 (shown in FIG. 8 ) to couple the output 834 of the amplifier circuit 830 to the output 426 of the capacitive DAC 420. As a result, the input 832 of the amplifier circuit 830 is coupled to the second terminal 854 of the second capacitor 850, and the output 834 of the amplifier circuit 830 is coupled to the output 426 of the capacitive DAC 420. This enables the amplifier circuit 830 to transfer the residual voltage from the previous ADC cycle (i.e., the (k-1)th ADC cycle) held in the second capacitor 850 to the output 426 of the capacitive DAC 420. As a result, the residual voltage from the previous ADC cycle (i.e., the (k-1)th ADC cycle) is transferred to the sampled input analog voltage V in which provides noise shaping according to equation (3).

[0062] During the conversion phase of the kth ADC cycle shown in FIG. 9B, the controller 870 causes the switching circuit 810 to couple the second terminal 844 of the first capacitor 840 to ground. The controller 870 also causes the switching circuit 810 to decouple the second terminal 854 of the second capacitor 850 from the input 832 of the amplifier circuit 830. As shown in the example of FIG. 9B, the second terminal 854 of the second capacitor 850 may be floating. The controller 870 also turns off the switch 860 to decouple the output 834 of the amplifier circuit 830 from the output 426 of the capacitive DAC 420.

[0063] During the conversion phase of the kth ADC cycle, the SAR 340 outputs a digital signal (also called a digital code) to the second input 424 of the capacitive DAC 420, as discussed above, and sequentially resolves the N bits of the digital signal based on the comparison signal from the comparator 330. At the end of the conversion phase, a residual voltage at the output 426 of the capacitive DAC 420 appears across the first capacitor 840 because the first capacitor 840 is coupled between the output 426 of the capacitive DAC 420 and ground. Thus, the first capacitor 840 captures a residual voltage at the end of the conversion phase of the kth ADC cycle. As will be discussed further below, the captured voltage present in the kth ADC cycle is a sampled input analog voltage V in to provide noise shaping.

[0064] During the sampling phase of the (k+1)th ADC cycle shown in FIG. 9C, the controller 870 causes the switching circuit 810 (shown in FIG. 8) to couple the second terminal 854 of the second capacitor 850 to the input 808 of the ADC 805. This causes the second capacitor 850 to use the capacitors in the capacitive DAC 420 (e.g., capacitors 560-1 through 560-N) to couple the input analog voltage V in The controller 870 also causes the switching circuit 810 to couple the second terminal 844 of the first capacitor 840 to the input 832 of the amplifier circuit 830. As discussed above, the first capacitor 840 holds a residual voltage from the kth ADC cycle, which is the previous ADC cycle for the (k+1)th ADC cycle.

[0065] Also, during the sampling phase of the (k+1)th ADC cycle, the controller 870 turns on the switch 860 (shown in FIG. 8 ) to couple the output 834 of the amplifier circuit 830 to the output 426 of the capacitive DAC 420. As a result, the input 832 of the amplifier circuit 830 is coupled to the second terminal 844 of the first capacitor 840, and the output 834 of the amplifier circuit 830 is coupled to the output 426 of the capacitive DAC 420. This enables the amplifier circuit 830 to transfer the residual voltage from the previous ADC cycle (i.e., the kth ADC cycle) held in the first capacitor 840 to the output 426 of the capacitive DAC 420. As a result, the residual voltage from the previous ADC cycle (i.e., the kth ADC cycle) is transferred to the sampled input analog voltage V in which provides noise shaping according to equation (3).

[0066] During the conversion phase of the (k+1)th ADC cycle shown in FIG. 9D, the controller 870 causes the switching circuit 810 to couple the second terminal 854 of the second capacitor 850 to ground. The controller 870 also causes the switching circuit 810 to decouple the second terminal 844 of the first capacitor 840 from the input 832 of the amplifier circuit 830. As shown in the example of FIG. 9D, the second terminal 844 of the first capacitor 840 may be floating. The controller 870 also turns off the switch 860 to decouple the output 834 of the amplifier circuit 830 from the output 426 of the capacitive DAC 420.

[0067] During the conversion phase of the (k+1)th ADC cycle, the SAR 340 outputs a digital signal to the second input 424 of the capacitive DAC 420 and sequentially resolves the N bits of the digital signal based on the comparison signal from the comparator 330, as discussed above. At the end of the conversion phase, a residual voltage at the output 426 of the capacitive DAC 420 appears across the second capacitor 850 because the second capacitor 850 is coupled between the output 426 of the capacitive DAC 420 and ground. Thus, the second capacitor 850 captures a residual voltage at the end of the conversion phase of the (k+1)th ADC cycle. The captured voltage present in the (k+1)th ADC cycle is the sampled input analog voltage V of the next ADC cycle (the (k+2)th ADC cycle). in to provide noise shaping. In this regard, the example operations shown in Figures 9A and 9B are repeated for the (k+2)th ADC cycle, the example operations shown in Figures 9C and 9D are repeated for the (k+3)th ADC cycle, and so on.

[0068] As discussed above, during the sampling phase of the kth ADC cycle, the second capacitor 850 holds a residual voltage from the previous ADC cycle (i.e., the (k-1)th ADC cycle). This can be achieved by performing the example operations shown in Figures 9C and 9D in the previous ADC cycle (i.e., the (k-1)th ADC cycle).

[0069] Therefore, the exemplary noise shaping technique shown in FIG. 8 instead uses a first capacitor 840 and a second capacitor 850 to filter out residual voltages from the previous ADC cycle to the sampled input analog voltage V in, and instead uses the first capacitor 840 and the second capacitor 850 to obtain a residual voltage at the end of the conversion phase. In the example shown in FIGS. 9A-9D , during the kth ADC cycle, the second capacitor 850 is used to add the residual voltage from the previous ADC cycle (i.e., the (k-1)th ADC cycle) to the sampled input analog voltage V in and the first capacitor 840 is used to obtain the residual voltage at the end of the conversion phase. During the next ADC cycle (i.e., the (k+1)th ADC cycle), the roles of the first capacitor 840 and the second capacitor 850 are switched and the first capacitor 840 is used to add the residual voltage from the previous ADC cycle (i.e., the kth ADC cycle) to the sampled input analog voltage V in and a second capacitor 850 is used to obtain the residual voltage at the end of the conversion phase.

[0070] Unlike the noise shaping scheme of FIG. 6, the exemplary noise shaping scheme according to an embodiment of the present disclosure shown in FIG. 8 does not use charge sharing between a holding capacitor and a capacitor in the capacitive DAC 420 (e.g., capacitors 560-1 through 560-N) to transfer the residual voltage from the previous ADC cycle to the output 426 of the capacitive DAC 420. Instead, the exemplary noise shaping scheme according to an embodiment of the present disclosure holds the residual voltage from the previous ADC cycle on the first capacitor 840 or the second capacitor 850 and uses an amplifier circuit 830 to transfer the held residual voltage to the output 426 of the capacitive DAC 420. Because the exemplary noise shaping scheme according to an embodiment of the present disclosure does not use charge sharing to transfer the residual voltage, the exemplary noise shaping scheme can achieve an α close to unity for improved noise shaping (e.g., low frequencies) without requiring a very large holding capacitor. This allows first capacitor 840 and second capacitor 850 to be significantly smaller than holding capacitor 630 of FIG. 6, thereby allowing the area of ​​ADC 805 to be significantly reduced compared to ADC 605 of FIG. 6.

[0071] A first capacitor 840 and a second capacitor 850 are used to generate a reference voltage V ref In one example, the first capacitor 840 and the second capacitor 850 may scale the reference voltage V ref can be scaled by 1 / m, where m is the scaling factor. In this example, the relationship between the capacitance of each of the first capacitor 840 and the second capacitor 850 and the scaling factor can be given by the following equation: C f =((m-1) 2 N +1)·C u (5) In the formula, C f is the capacitance of each of the first capacitor 840 and the second capacitor 850, and C u is the unit capacitance discussed above. In this example, the output voltage of the capacitive DAC 420 can be given by:

[0072]

number

[0073] Here, the reference voltage V ref is scaled by 1 / m. In this example, the first capacitor 840 and the second capacitor 850 each have unit capacitance C u Therefore, if the reference voltage V ref In a use case where is not scaled, the first capacitor 840 and the second capacitor 850 each have a unit capacitance C that is much smaller than the total capacitance of the capacitive DAC 420. u , and thus the area of ​​ADC 805 is significantly reduced as compared to ADC 605 of FIG. 6, which includes holding capacitor 630 that typically has a capacitance at least 10 times greater than the total capacitance of capacitive DAC 420.

[0074] 10 illustrates an exemplary embodiment of an amplifier circuit 830 according to certain aspects. In this example, the amplifier circuit 830 includes an amplifier 1010 having a first input 1012, a second input 1014, and an output 1016. As shown in the example of FIG. 10, the first input 1012 may be an inverting input and the second input 1014 may be a non-inverting input. In this example, the first input 1012 of the amplifier 1010 is coupled to an input 832 of the amplifier circuit 830, the second input 1014 of the amplifier 1010 is coupled to ground, and the output 1016 of the amplifier 1010 is coupled to an output 834 of the amplifier circuit 830.

[0075] 11A-11D show example equivalent circuits of ADC 805 during the sampling and conversion phases of the kth ADC cycle, respectively, for an example where amplifier circuit 830 includes amplifier 1010. FIGURES 11C-11D show example equivalent circuits of ADC 805 during the sampling and conversion phases of the next ADC cycle (i.e., the (k+1)th ADC cycle), respectively, for an example where amplifier circuit 830 includes amplifier 1010.

[0076] 11A, during the sampling phase of the kth ADC cycle, the second terminal 854 of the second capacitor 850 is coupled to the first input 1012 of the amplifier 1010, and the output 1016 of the amplifier 1010 is coupled to the output 426 of the capacitive DAC 420. This allows the amplifier 1010 to transfer the residual voltage from the previous ADC cycle (i.e., the (k-1)th ADC cycle) held on the second capacitor 850 to the output 426 of the capacitive DAC 420 for noise shaping, as discussed above.

[0077] During the conversion phase of the kth ADC cycle shown in FIG. 11B, the first input 1012 of the amplifier 1010 is disconnected from the second terminal 854 of the second capacitor 850, and the output 1016 of the amplifier 1010 is disconnected from the output 426 of the capacitive DAC 420.

[0078] 11C, during the sampling phase of the (k+1)th ADC cycle, the second terminal 844 of the first capacitor 840 is coupled to the first input 1012 of the amplifier 1010, and the output 1016 of the amplifier 1010 is coupled to the output 426 of the capacitive DAC 420. This allows the amplifier 1010 to transfer the residual voltage from the previous ADC cycle (i.e., the kth ADC cycle) held on the first capacitor 840 to the output 426 of the capacitive DAC 420 for noise shaping, as discussed above.

[0079] During the conversion phase of the (k+1)th ADC cycle shown in FIG. 11D, the first input 1012 of the amplifier 1010 is disconnected from the second terminal 844 of the first capacitor 840, and the output 1016 of the amplifier 1010 is disconnected from the output 426 of the capacitive DAC 420.

[0080] Thus, in this example, to provide noise shaping, the residual voltage from the previous ADC cycle held on the first capacitor 840 or the second capacitor 850 is transferred to the output 426 of the capacitive DAC 420 using amplifier 1010. The residual voltage is a signal that is amplified by the sampled analog input voltage V in The residual voltage has a relatively small voltage swing because it is the difference between the voltage corresponding to the resolved bit of the digital signal at the end of the conversion phase and the voltage corresponding to the resolved bit of the digital signal at the end of the conversion phase. Because the residual voltage has a small voltage swing, the amplifier 1010 does not need to be implemented using a high-performance amplifier that has high linearity over a large voltage swing. This relaxes the performance requirements of the amplifier 1010 and allows the amplifier 1010 to be implemented using a low-performance amplifier in advanced technologies that operate at a low supply voltage for reduced power consumption.

[0081] 12 illustrates an exemplary embodiment of a switching circuit 810 according to certain aspects. In this example, the switching circuit 810 includes a first switch 1210, a second switch 1220, a third switch 1230, a fourth switch 1240, a fifth switch 1250, and a sixth switch 1260. Each of the first switch 1210, the second switch 1220, the third switch 1230, the fourth switch 1240, the fifth switch 1250, and the sixth switch 1260 may be implemented using one or more transistors, transmission gates, or another type of switch.

[0082] The first switch 1210 is coupled between the first terminal 812 and the third terminal 816, the second switch 1220 is coupled between the first terminal 812 and the fourth terminal 818, and the third switch 1230 is coupled between the first terminal 812 and the fifth terminal 820. The fourth switch 1240 is coupled between the second terminal 814 and the third terminal 816, the fifth switch 1250 is coupled between the second terminal 814 and the fourth terminal 818, and the sixth switch 1260 is coupled between the second terminal 814 and the fifth terminal 820. A controller 870 (shown in FIG. 8 ) controls the switching of the first switch 1210, the second switch 1220, the third switch 1230, the fourth switch 1240, the fifth switch 1250, and the sixth switch 1260. For ease of illustration, the individual connections between the controller 870 and each of the first switch 1210, the second switch 1220, the third switch 1230, the fourth switch 1240, the fifth switch 1250, and the sixth switch 1260 are not shown in FIG. 12.

[0083] An exemplary switching operation according to certain aspects will now be discussed. During the sampling phase of the kth ADC cycle discussed above, the controller 870 turns on (i.e., closes) the first switch 1210 to couple the second terminal 844 of the first capacitor 840 to the input 808 of the ADC 805, and turns on (i.e., closes) the sixth switch 1260 to couple the second terminal 854 of the second capacitor 850 to the input 832 of the amplifier circuit 830. The controller 870 turns off the second switch 1220, the third switch 1230, the fourth switch 1240, and the fifth switch 1250.

[0084] During the conversion phase of the kth ADC cycle discussed above, the controller 870 turns on (i.e., closes) the second switch 1220 to couple the second terminal 844 of the first capacitor 840 to ground. The controller 870 turns off the first switch 1210, the third switch 1230, the fourth switch 1240, the fifth switch 1250, and the sixth switch 1260.

[0085] During the sampling phase of the (k+1)th ADC cycle discussed above, the controller 870 turns on (i.e., closes) the third switch 1230 to couple the second terminal 844 of the first capacitor 840 to the input 832 of the amplifier circuit 830 and turns on (i.e., closes) the fourth switch 1240 to couple the second terminal 854 of the second capacitor 850 to the input 808 of the ADC 805. The controller 870 turns off the first switch 1210, the second switch 1220, the fifth switch 1250, and the sixth switch 1260.

[0086] During the conversion phase of the (k+1)th ADC cycle discussed above, the controller 870 turns on (i.e., closes) the fifth switch 1250 to couple the second terminal 854 of the second capacitor 850 to ground. The controller 870 turns off the first switch 1210, the third switch 1230, the third switch 1230, the fourth switch 1240, and the sixth switch 1260.

[0087] In the above example, the sampling phase of the kth ADC cycle may be referred to as the first sampling phase, and the sampling phase of the (k+1)th ADC cycle may be referred to as the second sampling phase. Similarly, the conversion phase of the kth ADC cycle may be referred to as the first conversion phase, and the conversion phase of the (k+1)th ADC cycle may be referred to as the second conversion phase.

[0088] FIG. 13 illustrates another exemplary embodiment of an amplifier circuit 830 in accordance with certain aspects. In this example, the amplifier circuit 830 includes the amplifier 1010 discussed above. The amplifier circuit 830 also includes an auto-zeroing circuit to reduce offset and low frequency errors. The auto-zeroing circuit includes a first switch 1310, a second switch 1320, a third switch 1330, and a first capacitor 1340 ("C off "), and a second capacitor 1350 (labeled "C R ").

[0089] The first switch 1310 is coupled between the input 832 of the amplifier circuit 830 and ground. The first capacitor 1340 is coupled between the first input 1012 of the amplifier 1010 and the input 832 of the amplifier circuit 830. More specifically, a first terminal 1342 of the first capacitor 1340 is coupled to the input 832 of the amplifier circuit 830, and a second terminal 1344 of the first capacitor 1340 is coupled to the first input 1012 of the amplifier 1010. The second switch 1320 couples a first terminal 1352 of the second capacitor 1350 to a common-mode voltage V CMA second terminal 1354 of the second capacitor 1350 is coupled between the first terminal 1352 of the second capacitor 1350 and the first input 1012 of the amplifier 1010. The third switch 1330 is coupled between the first terminal 1352 of the second capacitor 1350 and the first input 1012 of the amplifier 1010. The switching of the first switch 1310, the second switch 1320, and the third switch 1330 may be controlled by the controller 870, as discussed further below.

[0090] An exemplary auto-zero operation will now be discussed below in accordance with aspects of the present disclosure.

[0091] During the auto-zeroing (AZ) phase, the controller 870 turns on (i.e., closes) the first switch 1310 and the third switch 1330 and turns off the second switch 1320. In this regard, FIG. 14A illustrates an example of an equivalent circuit of the amplifier circuit 830 in the AZ phase. The AZ phase occurs during the conversion phase when the input 832 of the amplifier circuit 830 is decoupled from the first capacitor 840 and the second capacitor 850 and the output 834 of the amplifier circuit 830 is decoupled from the output 426 of the capacitive DAC 420.

[0092] 14A, during the AZ phase, the output 1016 of the amplifier 1010 is coupled to the first input 1012 of the amplifier 1010 through a second capacitor 1350, which places the amplifier 1010 in a unity gain configuration. The second capacitor 1350 stores the offset and low frequency error. Due to the unity gain configuration of the amplifier 1010 during the AZ phase, negative values ​​of the offset and low frequency error appear on a first capacitor 1340 coupled between the first input 1012 of the amplifier 1010 and the input 832 of the amplifier circuit 830.

[0093] During a sampling phase following the AZ phase, the controller 870 turns off the first switch 1310 and the third switch 1330 and turns on the second switch 1320. In this regard, FIG. 14B illustrates an example of an equivalent circuit of the amplifier circuit 830 during the sampling phase. An input 832 of the amplifier circuit 830 is coupled to one of the first capacitor 840 and the second capacitor 850, and an output 834 of the amplifier circuit 830 is coupled to the output 426 of the capacitive DAC 420.

[0094] Because the first capacitor 1340 stores the negative value of the offset and low frequency error, as discussed above, the offset and low frequency error are subtracted from the charge stored in the first capacitor 840 or the second capacitor 850. As a result, the residual voltage from the first capacitor 840 or the second capacitor 850 is not affected by the offset and low frequency error in the amplifier 1010.

[0095] As shown in FIG. 14B, during the sampling phase, in this example, the common-mode voltage V CM is coupled to the output 1016 of the amplifier 1010 through a second capacitor 1350. As a result, the output of the amplifier circuit 830 is CM and the residual voltage from the previous ADC cycle at the output 426 of the capacitive DAC 420. In this example, the switch 540 shown in the example of FIG. 5 may be omitted because in this example, during the sampling phase, the common-mode voltage V CM is provided by amplifier circuit 830, or switch 540 may be always open for noise shaping.

[0096] The exemplary auto-zeroing operation shown in FIG. 14A may be performed during the conversion phase of each ADC cycle of the ADC 805.

[0097] 15 illustrates a method 1500 of noise shaping in an analog-to-digital converter (ADC) according to certain embodiments. The ADC (e.g., ADC 805) includes a digital-to-analog converter (DAC) (e.g., capacitive DAC 420) having an output (e.g., output 426), a comparator (e.g., comparator 330) having a first input (e.g., first input 332) coupled to the output of the DAC and a second input (e.g., second input 334) coupled to a common mode voltage or ground, a first capacitor (e.g., first capacitor 840) and an amplifier circuit (e.g., amplifier circuit 830).

[0098] In block 1510, during a first sampling phase, a first capacitor is coupled between the output of the DAC and the input of the ADC. For example, the first capacitor may be coupled between the output of the DAC and the input of the ADC (e.g., input 808) by the switching circuit 810. In certain aspects, the first sampling phase may correspond to the sampling phase of the kth ADC cycle.

[0099] In block 1520, during a first conversion phase, a first capacitor is coupled between the output of the DAC and ground. For example, the first capacitor may be coupled between the output of the DAC and ground by the switching circuit 810. This may be done, for example, to obtain a residual voltage at the output of the DAC at the end of the first conversion phase. In certain aspects, the first conversion phase may correspond to the conversion phase of the kth ADC cycle.

[0100] At block 1530, during a second sampling phase, the first capacitor is coupled between the output of the DAC and the input of the amplifier circuit, and the output of the amplifier circuit is coupled to the output of the DAC. For example, the first capacitor may be coupled between the output of the DAC and the input of the amplifier circuit (e.g., input 832) by the switching circuit 810, and the output of the amplifier circuit (e.g., output 834) may be coupled to the output of the DAC by the switch 860. In certain aspects, the second phase may correspond to the sampling phase of the (k+1)th ADC cycle.

[0101] In certain aspects, the ADC also includes a second capacitor (e.g., second capacitor 850). In these aspects, method 1500 may also include coupling the second capacitor between the output of the DAC and the input of the amplifier circuit during the first sampling phase, and coupling the output of the amplifier circuit to the output of the DAC. Method 1500 may also include coupling the second capacitor between the output of the DAC and the input of the ADC during the second sampling phase, and coupling the second capacitor between the output of the DAC and ground during the second conversion phase. The second conversion phase may correspond to the conversion phase of the (k+1)th ADC cycle. The coupling may be performed by switching circuit 810 and / or switch 860.

[0102] Method 1500 may also include, during each of the first and second conversion phases, outputting the digital signal to a DAC and resolving the N bits of the digital signal based on a comparison signal from an output of the comparator. For example, the digital signal may be output by SAR 340, and the N bits of the digital signal may be resolved by SAR 340 based on the comparison signal from an output of the comparator (e.g., output 336).

[0103] SAR 340 and controller 870 may each be implemented using an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, flip-flops, discrete hardware components (e.g., logic gates), state machines, or any combination thereof.

[0104] The following numbered clauses describe example implementations. 1. a comparator having a first input, a second input, and an output; a digital-to-analog converter (DAC) coupled to a first input of the comparator; A switching circuit; a first capacitor coupled between the first input of the comparator and the switching circuit; a second capacitor coupled between the first input of the comparator and the switching circuit; an amplifier circuit having an input and an output, the input of the amplifier circuit being coupled to a switching circuit; a first switch coupled between the output of the amplifier circuit and the DAC; an analog-to-digital converter (ADC) comprising: a successive approximation register (SAR) having an input and an output, the SAR input being coupled to the comparator output and the SAR output being coupled to the DAC; 2. The ADC of claim 1, wherein the second input of the comparator is coupled to a common-mode voltage or ground. 3. The ADC of clause 1 or 2, wherein the DAC comprises a capacitive DAC. 4. Amplification circuit: 4. The ADC of any one of clauses 1 to 3, comprising an amplifier having a first input, a second input, and an output, the first input of the amplifier being coupled to an input of the amplifier circuit, and the output of the amplifier being coupled to the output of the amplifier circuit. 5. The ADC of clause 4, wherein the second input of the amplifier is coupled to ground. 6. During the sampling phase, turn on the first switch; 6. The ADC of clause 4 or 5, further comprising a controller configured to turn off the first switch during the conversion phase. 7. During the conversion phase, the SAR Outputs a digital signal to the DAC. 7. The ADC of clause 6, configured to resolve N bits of the digital signal based on a comparison signal from an output of the comparator. 8. The ADC of any one of clauses 4-7, wherein the amplifier circuit further comprises a second switch coupled between the output of the amplifier and the first input of the amplifier. 9. The ADC of claim 8, wherein the amplifier circuit further comprises a third switch coupled between the first input of the amplifier and ground. 10. During the sampling phase, turn on the first switch, turn off the second switch, and turn off the third switch; 10. The ADC of clause 9, further comprising a controller configured to turn off the first switch, turn on the second switch, and turn on the third switch during a conversion phase. 11. During the conversion phase, the SAR Outputs a digital signal to the DAC. 11. The ADC of clause 10, configured to resolve N bits of the digital signal based on a comparison signal from an output of the comparator. 12. The ADC of any one of clauses 9-11, wherein the amplifier circuit further comprises a fourth switch coupled between the output of the amplifier and the common-mode voltage. 13. Switching circuits are a second switch coupled between the terminal of the first capacitor and the input of the ADC; a third switch coupled between the terminal of the second capacitor and the input of the ADC; a fourth switch coupled between the terminal of the first capacitor and the input of the amplifier circuit; and a fifth switch coupled between the terminal of the second capacitor and the input of the amplifier circuit. 14. During the first sampling phase, turn on the second switch, turn off the third switch, turn off the fourth switch, and turn on the fifth switch; 14. The ADC of claim 13, further comprising a controller configured to turn off the first switch, turn on the third switch, turn on the fourth switch, and turn off the fifth switch during a second sampling phase. 15. Switching circuits are a sixth switch coupled between the terminal of the first capacitor and ground; 15. The ADC of claim 13 or 14, further comprising a seventh switch coupled between the terminal of the second capacitor and ground. 16. During the first sampling phase, turn on the second switch, turn off the third switch, turn off the fourth switch, turn on the fifth switch, turn off the sixth switch, and turn off the seventh switch; During a first conversion phase, the second switch is turned off, the third switch is turned off, the fourth switch is turned off, the fifth switch is turned off, the sixth switch is turned on, and the seventh switch is turned off; During a second sampling phase, the second switch is turned off, the third switch is turned on, the fourth switch is turned on, the fifth switch is turned off, the sixth switch is turned off, and the seventh switch is turned off; 16. The ADC of claim 15, further comprising a controller configured to turn off the second switch, turn off the third switch, turn off the fourth switch, turn off the fifth switch, turn off the sixth switch, and turn on the seventh switch during a second conversion phase. 17. During each of the first conversion phase and the second conversion phase, the SAR: Outputs a digital signal to the DAC. 17. The ADC of clause 16 configured to resolve N bits of the digital signal based on a comparison signal from an output of the comparator. 18. The ADC of clause 16 or 17, wherein during each of the first sampling phase and the second sampling phase, the controller is configured to turn on the first switch. 19. The ADC of clause 18, wherein during each of the first conversion phase and the second conversion phase, the controller is configured to turn off the first switch. 20. A switching circuit is coupling a terminal of the first capacitor to an input of the ADC and a terminal of the second capacitor to an input of the amplifier circuit during a first sampling phase; 13. The ADC of any one of clauses 1 to 12, configured to couple a terminal of the second capacitor to an input of the ADC and a terminal of the first capacitor to an input of the amplifier circuit during a second sampling phase. 21. A switching circuit is coupling a terminal of a first capacitor to ground during a first conversion phase; 21. The ADC of clause 20, further configured to couple a terminal of the second capacitor to ground during a second conversion phase. 22. A switching circuit is floating a terminal of the second capacitor during the first conversion phase; 22. The ADC of claim 21, further configured to float a terminal of the first capacitor during the second conversion phase. 23. During each of the first conversion phase and the second conversion phase, the SAR: Outputs a digital signal to the DAC. 23. The ADC of clause 21 or 22, configured to resolve N bits of the digital signal based on a comparison signal from an output of the comparator. 24. An analog-to-digital converter (ADC), comprising: a comparator having a first input, a second input, and an output; a digital-to-analog converter (DAC) coupled to an input of the ADC and to a first input of the comparator; a switching circuit coupled to an input of the ADC; a first capacitor coupled between the first input of the comparator and the switching circuit; a second capacitor coupled between the first input of the comparator and the switching circuit; an amplifier circuit having an input and an output, the input of the amplifier circuit being coupled to a switching circuit; a first switch coupled between the output of the amplifier circuit and the DAC; an analog-to-digital converter (ADC) comprising: a successive approximation register (SAR) having an input, a first output, and a second output, the input of the SAR being coupled to the output of the comparator, the first output of the SAR being coupled to the DAC, and the second output being coupled to the output of the ADC; a receiver coupled to an input of the ADC; a processor coupled to an output of the ADC. 25. A method of noise shaping in an analog-to-digital converter (ADC), the ADC including a digital-to-analog converter (DAC) having an output, a comparator having a first input coupled to the output of the DAC and a second input coupled to a common mode voltage or ground, a first capacitor, and an amplifier circuit, the method comprising: During the first sampling phase, coupling a first capacitor between an output of the DAC and an input of the ADC; During the first conversion phase, coupling a first capacitor between an output of the DAC and ground; During the second sampling phase, coupling a first capacitor between an output of the DAC and an input of the amplifier circuit; coupling an output of the amplifier circuit to an output of the DAC. 26. The ADC also includes a second capacitor, and the method further comprises: During the first sampling phase, coupling a second capacitor between the output of the DAC and the input of the amplifier circuit; coupling an output of the amplifier circuit to an output of the DAC; During the second sampling phase, coupling a second capacitor between the output of the DAC and the input of the ADC; During the second conversion phase, 26. The method of claim 25, further comprising coupling a second capacitor between the output of the DAC and ground. 27. During each of the first conversion phase and the second conversion phase, outputting a digital signal to the DAC; 27. The method of claim 26, further comprising: resolving the N bits of the digital signal based on a comparison signal from an output of the comparator.

[0105] It should be understood that the present disclosure is not limited to the exemplary terms used above to describe aspects of the present disclosure. For example, a sampling phase may be referred to as an acquisition phase or another term. In another example, a digital signal may be referred to as a digital code or another term. In another example, a SAR may be referred to as a SAR logic, a SAR circuit, or another term.

[0106] Any reference to an element using a designation such as "first", "second" etc. in this specification does not generally limit the quantity or order of those elements. Rather, these designations are used in this specification as a convenient way to distinguish between two or more elements or instances of an element. Thus, a reference to a first and a second element does not mean that only two elements may be employed or that the first element must precede the second element. It should also be understood that the numerical designations in the claims do not necessarily match the numerical designations in the specification.

[0107] In this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage or mode of operation. The term "approximately" as used herein with respect to a stated value or property is intended to indicate within 10% of the stated value or property.

[0108] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. An analog-to-digital converter (ADC), comprising: a comparator having a first input, a second input, and an output; a digital-to-analog converter (DAC) coupled to the first input of the comparator; A switching circuit; a first capacitor coupled between the first input of the comparator and the switching circuit; a second capacitor coupled between the first input of the comparator and the switching circuit; an amplifier circuit having an input and an output, the input of the amplifier circuit being coupled to the switching circuit; a first switch coupled between the output of the amplifier circuit and the DAC; a successive approximation register (SAR) having an input and an output, the input of the SAR being coupled to the output of the comparator and the output of the SAR being coupled to the DAC; A controller; Equipped with The switching circuit includes: a second switch coupled between a terminal of the first capacitor and an input of the ADC; a third switch coupled between a terminal of the second capacitor and the input of the ADC; a fourth switch coupled between the terminal of the first capacitor and the input of the amplifier circuit; a fifth switch coupled between the terminal of the second capacitor and the input of the amplifier circuit; a sixth switch coupled between the terminal of the first capacitor and ground; a seventh switch coupled between the terminal of the second capacitor and ground; and Equipped with The controller: during a first sampling phase, turning on the second switch, turning off the third switch, turning off the fourth switch, turning on the fifth switch, turning off the sixth switch, and turning off the seventh switch; during a first conversion phase, turning off the second switch, turning off the third switch, turning off the fourth switch, turning off the fifth switch, turning on the sixth switch, and turning off the seventh switch; during a second sampling phase, turning off the second switch, turning on the third switch, turning on the fourth switch, turning off the fifth switch, turning off the sixth switch, and turning off the seventh switch; during a second conversion phase, turning off the second switch, turning off the third switch, turning off the fourth switch, turning off the fifth switch, turning off the sixth switch, and turning on the seventh switch. Analog-to-Digital Converter (ADC).

2. The ADC of claim 1 , wherein the second input of the comparator is coupled to a common-mode voltage or ground.

3. The ADC of claim 1 , wherein the DAC comprises a capacitive DAC.

4. The amplifier circuit includes:

2. The ADC of claim 1 comprising an amplifier having a first input, a second input, and an output, the first input of the amplifier being coupled to the input of the amplifier circuit and the output of the amplifier being coupled to the output of the amplifier circuit.

5. The ADC of claim 4 , wherein the second input of the amplifier is coupled to ground.

6. During a sampling phase, turning on the first switch; The ADC of claim 4 , further comprising a controller configured to turn off the first switch during a conversion phase.

7. During the conversion phase, the SAR outputting a digital signal to the DAC; 7. The ADC of claim 6 configured to resolve N bits of the digital signal based on a comparison signal from the output of the comparator.

8. The ADC of claim 4 , wherein the amplifier circuit further comprises a second switch coupled between the output of the amplifier and the first input of the amplifier.

9. The ADC of claim 8 , wherein the amplifier circuit further comprises a third switch coupled between the first input of the amplifier and ground.

10. During a sampling phase, turning on the first switch, turning off the second switch, and turning off the third switch; 10. The ADC of claim 9, further comprising: a controller configured to turn off the first switch, turn on the second switch, and turn on the third switch during a conversion phase.

11. During the conversion phase, the SAR outputting a digital signal to the DAC; The ADC of claim 10 configured to resolve N bits of the digital signal based on a comparison signal from the output of the comparator.

12. 10. The ADC of claim 9, wherein the amplifier circuit further comprises a fourth switch coupled between the output of the amplifier and a common-mode voltage.

13. During each of the first conversion phase and the second conversion phase, the SAR: outputting a digital signal to the DAC; The ADC of claim 1 configured to resolve N bits of the digital signal based on a comparison signal from the output of the comparator.

14. The ADC of claim 1 , wherein the controller is configured to turn on the first switch during each of the first sampling phase and the second sampling phase.

15. The ADC of claim 14 , wherein during each of the first conversion phase and the second conversion phase, the controller is configured to turn off the first switch.

16. The switching circuit includes: coupling a terminal of the first capacitor to an input of the ADC and a terminal of the second capacitor to the input of the amplifier circuit during a first sampling phase; 2. The ADC of claim 1 configured to couple the terminal of the second capacitor to the input of the ADC and the terminal of the first capacitor to the input of the amplifier circuit during a second sampling phase.

17. The switching circuit includes: coupling the terminal of the first capacitor to ground during a first conversion phase; 17. The ADC of claim 16, further configured to couple the terminal of the second capacitor to the ground during a second conversion phase.

18. The switching circuit includes: floating the terminal of the second capacitor during the first conversion phase; 20. The ADC of claim 17, further configured to float the terminal of the first capacitor during the second conversion phase.

19. During each of the first conversion phase and the second conversion phase, the SAR: outputting a digital signal to the DAC; 20. The ADC of claim 17 configured to resolve N bits of the digital signal based on a comparison signal from the output of the comparator.

20. 1. An analog-to-digital converter (ADC), comprising: a comparator having a first input, a second input, and an output; a digital-to-analog converter (DAC) coupled to an input of the ADC and to the first input of the comparator; a switching circuit coupled to the input of the ADC; a first capacitor coupled between the first input of the comparator and the switching circuit; a second capacitor coupled between the first input of the comparator and the switching circuit; an amplifier circuit having an input and an output, the input of the amplifier circuit being coupled to the switching circuit; a first switch coupled between the output of the amplifier circuit and the DAC; an analog-to-digital converter (ADC) comprising: a successive approximation register (SAR) having an input, a first output, and a second output, the input of the SAR being coupled to the output of the comparator, the first output of the SAR being coupled to the DAC, and the second output being coupled to an output of the ADC; A controller; a receiver coupled to the input of the ADC; a processor coupled to the output of the ADC; The switching circuit includes: a second switch coupled between a terminal of the first capacitor and an input of the ADC; a third switch coupled between a terminal of the second capacitor and the input of the ADC; a fourth switch coupled between the terminal of the first capacitor and the input of the amplifier circuit; a fifth switch coupled between the terminal of the second capacitor and the input of the amplifier circuit; a sixth switch coupled between the terminal of the first capacitor and ground; a seventh switch coupled between the terminal of the second capacitor and ground; and Equipped with The controller: during a first sampling phase, turning on the second switch, turning off the third switch, turning off the fourth switch, turning on the fifth switch, turning off the sixth switch, and turning off the seventh switch; during a first conversion phase, turning off the second switch, turning off the third switch, turning off the fourth switch, turning off the fifth switch, turning on the sixth switch, and turning off the seventh switch; during a second sampling phase, turning off the second switch, turning on the third switch, turning on the fourth switch, turning off the fifth switch, turning off the sixth switch, and turning off the seventh switch; During a second conversion phase, the second switch is turned off, the third switch is turned off, the fourth switch is turned off, the fifth switch is turned off, the sixth switch is turned off, and the seventh switch is turned on.

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