Electronic devices and wiring boards

Abstract

Increases resistance to external electromagnetic noise. The electronic device includes a semiconductor device having a plurality of terminals to which the same voltage is applied, and a wiring substrate having a mounting area on which the semiconductor device is mounted. The wiring substrate has wiring on the substrate that runs from a connection portion to which one of the plurality of terminals is connected, through the inside of the mounting area, to a connection portion to which another of the plurality of terminals is connected.

Description

[Technical field]

[0001] The present invention relates to an electronic device and a wiring board. [Background technology]

[0002] 2. Description of the Related Art The following techniques are known as techniques for suppressing noise in electronic equipment that includes a semiconductor device in which a semiconductor chip is packaged and a wiring board on which the semiconductor device is mounted.

[0003] For example, Patent Document 1 describes a multilayer printed wiring board on which an LSI having multiple power pins and multiple signal pins is mounted, in which some or all of the multiple power pins are connected to the power pattern via an inductance pattern. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-326451 Summary of the Invention [Problem to be solved by the invention]

[0005] A semiconductor device in which a semiconductor chip is packaged may have a plurality of power supply terminals to which the same voltage potential is applied in order to strengthen the power supply. A semiconductor device having a plurality of power supply terminals may include a conductive path from one of the plurality of power supply terminals to another of the plurality of power supply terminals via a wire, an in-chip wiring formed inside the semiconductor chip, and a wire. A wiring board on which a semiconductor device having such a conductive path is mounted may include wiring on the board that connects each of the plurality of power supply terminals to each other. Here, in order to increase the resistance to noise coming from the outside, a ground pattern that covers the mounting area on which the semiconductor device is mounted may be provided on the wiring board. When a ground pattern is provided on the mounting area on which the semiconductor device is mounted, the wiring on the board that connects each of the plurality of power supply terminals to each other is arranged so as to bypass the mounting area on which the semiconductor device is mounted. In this case, a conductive loop is formed by the conductive path formed inside the semiconductor device and the wiring on the board that connects each of the plurality of power supply terminals to each other, and there is a risk that the resistance to electromagnetic noise coming from the outside will be reduced. For example, if the magnetic flux passing through the inside of a conductive loop changes, the power supply voltage fluctuates due to electromagnetic induction, which may cause the circuit operation to become unstable or the circuit elements to be destroyed.

[0006] The present invention has been made in view of the above-mentioned points, and has an object to improve resistance to electromagnetic noise coming from the outside. [Means for solving the problem]

[0007] An electronic device according to a first aspect of the present invention is an electronic device including a semiconductor device having a plurality of terminals to which the same potential voltage is applied, and a wiring board having a mounting area on which the semiconductor device is mounted, the wiring board having on-board wiring that runs from a connection portion to which one of the plurality of terminals is connected, through the inside of the mounting area, to a connection portion to which another of the plurality of terminals is connected. An electronic device according to a second aspect of the present invention is an electronic device including a semiconductor device having a rectangular outer shape and having a plurality of terminals arranged along an outer periphery, a plurality of power supply terminals among the plurality of terminals to which a power supply voltage of the same potential is applied in order to drive the semiconductor device, and a conductive path connecting the plurality of power supply terminals to each other internally, and a wiring board having a mounting area on which the semiconductor device is mounted, wherein the wiring board has on-board wiring that connects the plurality of power supply terminals to each other via the inside of the mounting area, and the on-board wiring overlaps with the conductive path when viewed from above the semiconductor device.

[0008] The wiring board of the present invention has a mounting area for mounting a semiconductor device having a plurality of terminals to which the same potential voltage is applied, and wiring on the board that runs from a connection portion to which one of the plurality of terminals is connected, through the inside of the mounting area, to a connection portion to which another of the plurality of terminals is connected. Effect of the Invention

[0009] According to the present invention, it is possible to improve resistance to electromagnetic noise coming from the outside. [Brief description of the drawings]

[0010] [Figure 1A] FIG. 1 is a plan view showing an example of a schematic configuration of an electronic device 1 according to a first embodiment of the present invention. [Figure 1B] FIG. 1B is a cross-sectional view taken along line 1B-1B in FIG. 1A. [Diagram 2] 1 is a plan view showing an example of an internal structure of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a plan view showing an example of a wiring pattern formed on a wiring board according to an embodiment of the present invention; [Figure 4A] 1 is a plan view showing an internal structure of a semiconductor device according to an embodiment of the present invention, conductive paths formed in the semiconductor device, and on-substrate wiring formed on a wiring substrate; [Figure 4B]4B is a plan view showing conductive paths and on-substrate wiring extracted from the elements shown in FIG. 4A. FIG. [Figure 5A] FIG. 1 is a plan view showing an example of a configuration of an electronic device according to a comparative example. [Figure 5B] 5B is a plan view showing conductive paths and on-substrate wiring extracted from the elements shown in FIG. 5A. FIG. [Figure 6A] FIG. 11 is a plan view showing an example of a configuration of an electronic device according to a second embodiment of the present invention. [Figure 6B] 6B is a plan view showing conductive paths and on-substrate wiring extracted from the elements shown in FIG. 6A. FIG. [Figure 7A] FIG. 11 is a plan view showing an example of a configuration of an electronic device according to a third embodiment of the present invention. [Figure 7B] 7B is a plan view showing conductive paths and on-substrate wiring extracted from the elements shown in FIG. 7A. FIG. [Figure 8A] FIG. 11 is a plan view showing an example of a configuration of an electronic device according to a fourth embodiment of the present invention. [Figure 8B] 8B is a plan view showing conductive paths and on-substrate wiring extracted from the elements shown in FIG. 8A. FIG. [Figure 9A] FIG. 13 is a plan view showing an example of a configuration of an electronic device according to a fifth embodiment of the present invention. [Figure 9B] 2 is a plan view showing an example of a wiring pattern formed on a first surface of the wiring board according to the embodiment of the present invention. FIG. [Figure 9C] 4 is a plan view showing an example of a wiring pattern formed on a second surface of the wiring board according to the embodiment of the present invention. FIG. [Figure 9D] FIG. 9D is a cross-sectional view taken along line 9D-9D in FIG. 9A. [Figure 10A] FIG. 13 is a plan view showing an example of a configuration of an electronic device according to a sixth embodiment of the present invention. [Figure 10B] 1 is a plan view showing an example of a wiring pattern formed on a first surface of a wiring board according to an embodiment of the present invention. [Figure 10C] 4 is a plan view showing an example of a wiring pattern formed on a second surface of the wiring board according to the embodiment of the present invention. FIG. [Figure 10D] FIG. 10B is a cross-sectional view taken along line 10D-10D in FIG. 10A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals.

[0012] [First embodiment] Fig. 1A is a plan view showing an example of a schematic configuration of an electronic device 1 according to a first embodiment of the present invention. Fig. 1B is a cross-sectional view taken along line 1B-1B in Fig. 1A. The electronic device 1 includes a wiring board 10 and a semiconductor device 20 mounted on the wiring board 10.

[0013] 2 is a plan view showing an example of the internal structure of the semiconductor device 20. The semiconductor device 20 includes a semiconductor chip 21 on which an integrated circuit is formed, a plurality of terminals 23 connected to the semiconductor chip 21 via wires 22, and a sealing member 24 that seals the semiconductor chip 21. In this embodiment, the outer shape of the semiconductor device 20 in a plan view is approximately rectangular. The semiconductor device 20 may have a package form of, for example, QFP (Quad Flat Package).

[0014] In this embodiment, the multiple terminals 23 include two power supply terminals 23Pa and 23Pb to which a power supply voltage VDD of the same potential is applied. The power supply terminal 23Pa is disposed near a corner portion 25A of the semiconductor device 20, and is connected to the semiconductor chip 21 via a wire 22. The power supply terminal 23Pb is disposed near a corner portion 25B diagonally opposite the corner portion 25A of the semiconductor device 20, and is connected to a portion of the semiconductor chip different from the portion to which the power supply terminal 23Pa is connected via a wire 22. By having the multiple power supply terminals 23Pa and 23Pb in the semiconductor device 20, the uniformity of the power supply voltage within the surface of the semiconductor chip 21 can be improved.

[0015] The semiconductor device 20 has a conductive path 26 that reaches the power terminal 23Pb via the power terminal 23Pa, the wire 22, internal chip wiring (not shown) formed in the semiconductor chip 21, and the wire 22. Note that the portion of the conductive path 26 that passes through the inside of the semiconductor chip 21 is not necessarily limited to a straight line as exemplified in FIG. 2, and may be curved.

[0016] 3 is a plan view showing an example of a wiring pattern formed on the wiring board 10. The wiring board 10 has a plurality of lands 11 as connection parts to which a plurality of terminals 23 of the semiconductor device 20 are connected. The plurality of lands 11 include a land 11Pa to which a power terminal 23Pa is connected and a land 11Pb to which a power terminal 23Pb is connected. The wiring board 10 has the land 11Pa, the inside of the mounting area 30, and an on-board wiring 12 that passes through the land 11Pb. In this way, by connecting the lands 11Pa and 11Pb to each other by the on-board wiring 12, it becomes possible to supply a power supply voltage VDD having the same potential to the power supply terminals 23Pa and 23Pb of the semiconductor device 20, respectively.

[0017] FIG. 4A is a plan view showing the internal structure of the semiconductor device 20, the conductive path 26 formed in the semiconductor device 20, and the on-substrate wiring 12 formed on the wiring board 10. FIG. 4B is a plan view showing the conductive path 26 and the on-substrate wiring 12 extracted from each element shown in FIG. 4A. According to the electronic device 1 of this embodiment, the conductive path 26 formed in the semiconductor device 20 and the on-substrate wiring 12 formed on the wiring board 10 are electrically connected to each other, thereby forming a conductive loop 40. The conductive loop 40 may act as a loop antenna, and when the magnetic flux penetrating the inside of the conductive loop 40 changes due to electromagnetic noise coming from the outside, the potential of the conductive path 26 and the on-substrate wiring 12 (i.e., the potential of the power supply voltage VDD) fluctuates due to electromagnetic induction. In order to suppress such potential fluctuation, it is preferable to make the area of ​​the inner region of the conductive loop 40 (the region indicated by hatching in FIG. 4B) as small as possible.

[0018] Here, FIG. 5A is a plan view showing an example of the configuration of an electronic device 1X according to a comparative example. In FIG. 5A, the internal structure of the semiconductor device 20, the conductive path 26 formed in the semiconductor device 20, and the on-substrate wiring 12X formed on the wiring board 10 are also shown. FIG. 5B is a plan view showing the conductive path 26 and the on-substrate wiring 12X extracted from each element shown in FIG. 5A. In the electronic device 1X according to the comparative example, the on-substrate wiring 12X is routed differently from the on-substrate wiring 12 according to the embodiment of the present invention. That is, the on-substrate wiring 12X according to the comparative example extends from the land 11Pa to which the power terminal 23Pa is connected, via the outside of the mounting area 30, to the land 11Pb to which the power terminal 23Pb is connected.

[0019] In the electronic device 1X of the comparative example, the portion of the on-substrate wiring 12X from the land 11Pa to the land 11Pb passes outside the mounting area 30 of the semiconductor device 20, so that the area of ​​the inner region (the region shown by hatching in FIG. 5B) of the conductive loop 40X formed by the conductive path 26 formed in the semiconductor device 20 and the on-substrate wiring 12X is larger than that of the conductive loop 40 of the embodiment of the present invention.

[0020] On the other hand, according to the electronic device 1 of the embodiment of the present invention, the portion of the on-board wiring 12 from the land 11Pa to the land 11Pb passes inside the mounting region 30 of the semiconductor device 20, so the area of ​​the inner region of the conductive loop 40 can be made smaller than that of the conductive loop 40X of the comparative example. Therefore, according to the electronic device 1 of the embodiment of the present invention, it is possible to improve resistance to electromagnetic noise coming from the outside compared to the electronic device 1X of the comparative example. Note that the area of ​​the inner region of the conductive loop 40 is preferably half (50%) or less of the area of ​​the mounting region 30 of the semiconductor device 20.

[0021] Furthermore, according to the electronic device 1 according to the embodiment of the present invention, the portion of the on-board wiring 12 that passes inside the mounting area 30 is covered by the wires 22 and terminals 23 of the semiconductor device 20. Since the wires 22 and terminals 23 function as a shield against electromagnetic noise, by covering the portion of the on-board wiring 12 that passes inside the mounting area 30 with the wires 22 and terminals 23, it is possible to further increase resistance to electromagnetic noise.

[0022] Furthermore, according to the electronic device 1 according to the embodiment of the present invention, it is possible to increase resistance to electromagnetic noise without mounting electromagnetic noise suppression components such as capacitors to reduce the effects of electromagnetic noise, which makes it possible to reduce manufacturing costs compared to electronic devices that mount electromagnetic noise suppression components.

[0023] [Second embodiment] Fig. 6A is a plan view showing an example of the configuration of an electronic device 1A according to a second embodiment of the present invention. Fig. 6A also shows the internal structure of a semiconductor device 20, a conductive path 26 formed in the semiconductor device 20, and on-substrate wiring 12A formed on a wiring board 10. Fig. 6B is a plan view showing the conductive path 26 and on-substrate wiring 12A extracted from the elements shown in Fig. 6A.

[0024] In the electronic device 1A according to the second embodiment of the present invention, the wiring on the substrate 12A is different from the wiring on the substrate 12 according to the first embodiment. The wiring on the substrate 12A according to the second embodiment extends from the land 11Pa to which the power terminal 23Pa is connected, through the inside of the mounting region 30 of the semiconductor device 20, to the land 11Pb to which the power terminal 23Pb is connected. The part of the wiring on the substrate 12A passing through the inside of the mounting region 30 is arranged along the conductive path 26 formed in the semiconductor device 20. More specifically, the part of the wiring on the substrate 12A passing through the inside of the mounting region 30 is arranged directly below the conductive path 26 so as to overlap with the conductive path 26.

[0025] According to the electronic device 1A of the second embodiment of the present invention, it is possible to make the area of ​​the inner region of the conductive loop 40 formed by the conductive path 26 formed in the semiconductor device 20 and the on-board wiring 12A formed on the wiring board 10 approximately zero. This makes the magnetic flux penetrating the inside of the conductive loop 40 approximately zero, making it possible to further increase the resistance to electromagnetic noise.

[0026] [Third embodiment] Fig. 7A is a plan view showing an example of the configuration of an electronic device 1B according to a third embodiment of the present invention. Fig. 7A also shows the internal structure of a semiconductor device 20, a conductive path 26B formed in the semiconductor device 20, and on-substrate wiring 12B formed on a wiring substrate 10. Fig. 7B is a plan view showing the conductive path 26B and on-substrate wiring 12B extracted from the elements shown in Fig. 7A.

[0027] In electronic device 1B according to the third embodiment of the present invention, power terminal 23Pa and power terminal 23Pb of semiconductor device 20 are provided along one side of semiconductor device 20. Therefore, conductive path 26B that passes through power terminal 23Pa, wire 22, in-chip wiring (not shown) formed in semiconductor chip 21, and wire 22 to power terminal 23Pb is bent as shown in FIGS.

[0028] The on-substrate wiring 12B extends from the land 11Pa to which the power supply terminal 23Pa is connected, through the inside of the mounting region 30 of the semiconductor device 20, to the land 11Pb to which the power supply terminal 23Pb is connected. The portion of the on-substrate wiring 12B that passes through the inside of the mounting region 30 is disposed along the conductive path 26B formed in the semiconductor device 20. More specifically, the portion of the on-substrate wiring 12B that passes through the inside of the mounting region 30 is disposed directly below the conductive path 26B so as to overlap with the conductive path 26B.

[0029] According to the electronic device 1B of the third embodiment of the present invention, it is possible to make the area of ​​the inner region of the conductive loop 40 formed by the conductive path 26B formed in the semiconductor device 20 and the on-board wiring 12B formed on the wiring board 10 approximately zero. This makes the magnetic flux penetrating the inside of the conductive loop 40 approximately zero, and it is possible to further increase the resistance to electromagnetic noise.

[0030] [Fourth embodiment] Fig. 8A is a plan view showing an example of the configuration of an electronic device 1C according to a fourth embodiment of the present invention. Fig. 8A also shows the internal structure of a semiconductor device 20, a conductive path 26C formed in the semiconductor device 20, and on-substrate wiring 12C formed on a wiring substrate 10. Fig. 8B is a plan view showing the conductive path 26C and on-substrate wiring 12C extracted from the elements shown in Fig. 8A.

[0031] A semiconductor device 20 according to a fourth embodiment of the present invention has four power supply terminals 23Pa, 23Pb, 23Pc, and 23Pd to which a power supply voltage VDD of the same potential is applied. The power supply terminals 23Pa, 23Pb, 23Pc, and 23Pd are disposed near each corner of the semiconductor device 20. The semiconductor device 20 has a conductive path 26C that interconnects the power supply terminals 23Pa, 23Pb, 23Pc, and 23Pd. The conductive path 26C includes a wire 22 and an internal chip wiring (not shown) formed in the semiconductor chip 21.

[0032] The wiring board 10 has a land 11Pa to which the power supply terminal 23Pa is connected, a land 11Pb to which the power supply terminal 23Pb is connected, a land 11Pc to which the power supply terminal 23Pc is connected, and a land 11Pd to which the power supply terminal 23Pd is connected. The wiring board 10 has an on-board wiring 12C that runs from the land 11Pa to the other lands 11Pb, 11Pc, and 11Pd via the inside of the mounting region 30 of the semiconductor device 20. In this way, by connecting the lands 11Pa, 11Pb, 11Pc, and 11Pd to each other by the on-board wiring 12C, it becomes possible to supply a power supply voltage VDD having the same potential to each of the power supply terminals 23Pa, 23Pb, 23Pc, and 23Pd of the semiconductor device 20.

[0033] The portion of the on-substrate wiring 12C that passes inside the mounting region 30 is disposed along the conductive path 26C formed in the semiconductor device 20. More specifically, the portion of the on-substrate wiring 12C that passes inside the mounting region 30 is disposed directly below the conductive path 26C so as to overlap with the conductive path 26C.

[0034] According to the electronic device 1C of the fourth embodiment of the present invention, it is possible to make the area of ​​the inner region of the conductive loop 40 formed by the conductive path 26C formed in the semiconductor device 20 and the on-substrate wiring 12C formed on the wiring substrate 10 approximately zero. This makes the magnetic flux penetrating the inside of the conductive loop 40 approximately zero, and it is possible to further increase the resistance to electromagnetic noise.

[0035] [Fifth embodiment] Fig. 9A is a plan view showing an example of the configuration of an electronic device 1D according to a fifth embodiment of the present invention. Fig. 9A also shows the internal structure of a semiconductor device 20, a conductive path 26 formed in the semiconductor device 20, and a wiring pattern formed on a wiring board 10. Fig. 9B is a plan view showing an example of a wiring pattern formed on a first surface S1 of the wiring board 10 on which the semiconductor device 20 is mounted. Fig. 9C is a plan view showing an example of a wiring pattern formed on a second surface S2 of the wiring board 10 opposite to the first surface S1. Fig. 9D is a cross-sectional view taken along line 9D-9D in Fig. 9A.

[0036] The semiconductor device 20 has power supply terminals 23Pa and 23Pb, as well as ground terminals 23Ga and 23Gb and a plurality of signal terminals 23S.

[0037] The first surface S1 of the wiring board 10 is provided with lands 11Pa and 11Pb to which the power supply terminals 23Pa and 23Pb are respectively connected, as well as lands 11Ga and 11Gb to which the ground terminals 23Ga and 23Gb are respectively connected, and a plurality of lands 11S to which the signal terminals 23S are respectively connected. The first surface S1 of the wiring board 10 is also provided with a plurality of signal wirings 12s connected to each of the lands 11S.

[0038] A power supply wiring 12p is provided on the second surface S2 of the wiring board 10. The signal wiring 12s and the power supply wiring 12p are wirings constituting the on-board wiring 12. The power supply wiring 12p is connected to a land 11Pa provided on the first surface S1 of the wiring board 10 via a through hole 13Pa. The power supply wiring 12p is also connected to a land 11Pb provided on the first surface S1 of the wiring board 10 via a through hole 13Pb. The power supply wiring 12p extends from the land 11Pa to the land 11Pb via the inside of the mounting area 30. In this way, by connecting the lands 11Pa and 11Pb to each other via the power supply wiring 12p, it is possible to supply a power supply voltage VDD having the same potential to the power supply terminals 23Pa and 23Pb of the semiconductor device 20, respectively.

[0039] Conductive patterns 14a and 14b are provided on the second surface S2 of the wiring board 10, and are separated from each other by a gap 15. Most of the area (e.g., 70% or more) of the second surface S2 of the wiring board 10, including the mounting area 30, is covered by the conductive patterns 14a and 14b. A ground potential is applied to the conductive patterns 14a and 14b. The conductive pattern 14a is connected to a land 11Ga provided on the first surface S1 of the wiring board 10 via a through hole 13Ga. The conductive pattern 14b is connected to a land 11Gb provided on the first surface S1 of the wiring board 10 via a through hole 13Gb. The gap 15 separating the conductive patterns 14a and 14b extends so as to pass through the inside of the mounting area 30. The power supply wiring 12p is disposed in the gap 15.

[0040] The portion of the power supply wiring 12p that passes inside the mounting region 30 is disposed along the conductive path 26 formed in the semiconductor device 20. More specifically, the portion of the power supply wiring 12p that passes inside the mounting region 30 is disposed directly below the conductive path 26 so as to overlap with the conductive path 26.

[0041] According to the electronic device 1D of the fifth embodiment of the present invention, it is possible to make the area of ​​the inner region of the conductive loop formed by the conductive path 26 formed in the semiconductor device 20 and the power supply wiring 12p formed in the wiring board 10 approximately zero. This makes the magnetic flux penetrating the inside of the conductive loop approximately zero, thereby making it possible to increase resistance to electromagnetic noise.

[0042] Moreover, most of the area of ​​the second surface S2 of the wiring board 10, including the mounting area 30, is covered by the conductor patterns 14a and 14b to which a ground potential is applied. The conductor patterns 14a and 14b to which a ground potential is applied function as a shield against electromagnetic noise, so by covering most of the area of ​​the second surface S2 of the wiring board 10, including the mounting area 30, with the conductor patterns 14a and 14b, it is possible to further increase resistance to electromagnetic noise.

[0043] Furthermore, the ground terminal 23Ga of the semiconductor device 20 is connected via a through hole 13Ga to the conductor pattern 14a arranged directly below it, and the ground terminal 23Gb of the semiconductor device 20 is connected via a through hole 13Gb to the conductor pattern 14b arranged directly below it. This makes it possible to connect the ground terminals 23Ga and 23Gb to the ground potential via the shortest path.

[0044] Both the ground terminals 23Ga and 23Gb may be connected to the same conductor pattern 14a (or conductor pattern 14b), which can further improve resistance to electromagnetic noise.

[0045] [Sixth embodiment] Fig. 10A is a plan view showing an example of the configuration of an electronic device 1E according to a sixth embodiment of the present invention. Fig. 10A also shows the internal structure of a semiconductor device 20, a conductive path 26 formed in the semiconductor device 20, and a wiring pattern formed on a wiring board 10. Fig. 10B is a plan view showing an example of a wiring pattern formed on a first surface S1 of the wiring board 10 on which the semiconductor device 20 is mounted. Fig. 10C is a plan view showing an example of a wiring pattern formed on a second surface S2 of the wiring board 10 opposite to the first surface S1. Fig. 10D is a cross-sectional view taken along line 10D-10D in Fig. 10A.

[0046] The semiconductor device 20 has power supply terminals 23Pa and 23Pb, as well as ground terminals 23Ga and 23Gb and a plurality of signal terminals 23S.

[0047] The first surface S1 of the wiring board 10 is provided with lands 11Pa and 11Pb to which the power terminals 23Pa and 23Pb are respectively connected, and a plurality of lands 11S to which the signal terminals 23S are respectively connected. The first surface S1 of the wiring board 10 is also provided with a plurality of signal wirings 12s connected to the lands 11S. The first surface S1 of the wiring board 10 is also provided with a power wiring 12p connected to the lands 11Pa and 11Pb. The power wiring 12p runs from the land 11Pa to the land 11Pb via the inside of the mounting area 30. In this way, by connecting the lands 11Pa and 11Pb to each other via the power wiring 12p, it is possible to supply the power voltage VDD having the same potential to the power terminals 23Pa and 23Pb of the semiconductor device 20. The signal wiring 12s and the power wiring 12p are wirings that constitute the on-board wiring 12.

[0048] The first surface S1 of the wiring board 10 is provided with conductor patterns 14a and 14b to which the ground terminals 23Ga and 23Gb are connected, respectively. The conductor patterns 14a and 14b are separated from each other by a gap 15. The conductor regions 14a and 14b extend inside and outside the mounting region 30 of the semiconductor device 20, and most of the mounting region 30 (e.g., 70% or more) on the first surface S1 of the wiring board 10 is covered by the conductor patterns 14a and 14b. A ground potential is applied to the conductor patterns 14a and 14b. The gap 15 separating the conductor patterns 14a and 14b extends to pass through the inside of the mounting region 30. The power supply wiring 12p is disposed in the gap 15.

[0049] A conductor pattern 16 is provided on the second surface S2 of the wiring board 10. Most of the area (e.g., 70% or more) of the second surface S2 of the wiring board 10, including the mounting area 30, is covered with the conductor pattern 16. The conductor pattern 16 is arranged in the mounting area 30 of the semiconductor device 20 so as to overlap with the gap 15 separating the conductor pattern 14a and the conductor pattern 14b. A ground potential is applied to the conductor pattern 16.

[0050] The portion of the power supply wiring 12p that passes inside the mounting region 30 is disposed along the conductive path 26 formed in the semiconductor device 20. More specifically, the portion of the power supply wiring 12p that passes inside the mounting region 30 is disposed directly below the conductive path 26 so as to overlap with the conductive path 26.

[0051] According to the electronic device 1E of the sixth embodiment of the present invention, it is possible to make the area of ​​the inner region of the conductive loop formed by the conductive path 26 formed in the semiconductor device 20 and the power supply wiring 12p formed in the wiring board 10 approximately zero. This makes the magnetic flux penetrating the inside of the conductive loop approximately zero, thereby making it possible to increase resistance to electromagnetic noise.

[0052] Moreover, on the first surface S1 of the wiring board 10, most of the mounting area 30 is covered by the conductor patterns 14a and 14b to which a ground potential is applied. The conductor patterns 14a and 14b to which a ground potential is applied function as a shield against electromagnetic noise, so that by covering most of the mounting area 30 on the first surface S1 of the wiring board 10 with the conductor patterns 14a and 14b, it is possible to further increase the resistance to electromagnetic noise. Here, the gap 15 separating the conductor patterns 14a and 14b from each other is disposed inside the mounting area 30, which may reduce the shielding effect. However, on the second surface S2 of the wiring board 10, the conductor pattern 16 is provided at a position overlapping with the gap 15, so that it is possible to suppress the reduction in the shielding effect caused by the gap 15 being disposed inside the mounting area 30. [Explanation of symbols]

[0053] 1, 1A, 1B, 1C, 1D, 1E, 1X Electronics 10 Wiring board 11, 11Ga, 11Gb, 11Pa, 11Pb, 11Pc, 11Pc, 11S Land 12, 12A, 12B, 12C, 12X On-board wiring 12p power wiring 12s signal wiring 14a, 14b, 16 Conductor patterns 15 Gap 20 Semiconductor Devices 21 Semiconductor Chips 22 Wire 23 Terminal 23Ga, 23Gb Ground Terminal 23Pa, 23Pb, 23Pc, 23Pd power terminal 23S signal terminal 26, 26B, 26C Conductive Path 30 Loading area 40, 40X Conductive Loop

Claims

[Claim 1] A semiconductor device having a rectangular outer shape, the semiconductor device having a plurality of terminals arranged along an outer periphery, a plurality of power supply terminals among the plurality of terminals to which a power supply voltage of the same potential is applied in order to drive the semiconductor device, and conductive paths internally connecting the plurality of power supply terminals to each other; a wiring substrate having a mounting area on which the semiconductor device is mounted; An electronic device comprising: the wiring board has on-board wiring that connects the plurality of power supply terminals to each other via an inside of the mounting area, The on-substrate wiring overlaps with the conductive path when viewed from above the semiconductor device. electronic equipment.

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