Transistor, electronic device, and method for manufacturing transistor

Abstract

This transistor has a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, wherein: the gate insulating film is a laminated film obtained by alternately laminating a SiOx film and a SiCyNz film; the total number of the films constituting the laminated film is 3 to 18; and the film thickness of each of the films constituting the laminated film is 25 to 150 nm.

Description

[Technical field]

[0001] The present invention relates to a transistor, an electronic device, and a method for manufacturing a transistor. This application claims priority based on Japanese Patent Application No. 2020-027134, filed on February 20, 2020, the contents of which are incorporated herein by reference. [Background technology]

[0002] 2. Description of the Related Art Thin film transistors (TFTs) are widely used in liquid crystal display devices, organic electroluminescence (EL) display devices, and the like. Oxide semiconductors have been attracting attention as semiconductor film materials for thin-film transistors, particularly thin-film transistors using amorphous oxide semiconductors such as In-Ga-Zn-O (IGZO).

[0003] Furthermore, the gate insulating layer of the thin film transistor is formed by a chemical vapor deposition (CVD) method, as described in, for example, Patent Document 1. In recent years, there has been a demand for display devices with even higher performance, and thin film transistors with high insulating properties and high reliability are in demand. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-107952 A Summary of the Invention

[0005] One aspect of the present invention is a thin film transistor having a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, the gate insulating film being made of SiO x Membrane and SiC y N zthe total number of films constituting the laminated film is 3 to 18, and the thickness of each film constituting the laminated film is 25 nm to 150 nm. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of an example of a thin film transistor according to an embodiment of the present invention. [Diagram 2] 1 is a diagram showing the transistor characteristics of a thin film transistor manufactured in Example 1. [Diagram 3] FIG. 13 is a diagram showing the transistor characteristics of the thin film transistor produced in Example 2. [Figure 4] FIG. 13 is a diagram showing the transistor characteristics of the thin film transistor produced in Example 3. [Diagram 5] FIG. 13 is a diagram showing the transistor characteristics of the thin film transistor produced in Example 4. [Figure 6] FIG. 1 is a diagram showing the transistor characteristics of a thin film transistor produced in Comparative Example 1. [Figure 7] FIG. 13 is a graph showing the transistor characteristics of a thin film transistor produced in Comparative Example 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] <Thin-film transistor> This embodiment is a thin film transistor having a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode. In this embodiment, the gate insulating film is SiO x Membrane and SiC y N z The film is a laminated film in which the films are alternately laminated.

[0008] 1 is a bottom-gate type thin film transistor formed on the surface of a substrate 11. The thin film transistor 1 includes a gate electrode 12, a gate insulating film 13, a semiconductor film 14, a source electrode 15a, and a drain electrode 15b. Each configuration will be described below.

[0009] <Substrate> Examples of materials for the substrate 11 include metals, crystalline materials, amorphous materials, conductors, semiconductors, insulators, fibers, glasses, ceramics, zeolites, plastics, thermosetting and thermoplastic materials, etc. The substrate 11 may also be an optical element, a coated substrate, a film, etc.

[0010] Crystalline materials include, for example, monocrystalline, polycrystalline, or partially crystalline materials.

[0011] Thermoplastic materials include, for example, polyacrylates, polycarbonates, polyurethanes, polystyrenes, cellulose polymers, polyolefins, polyamides, polyimides, polyesters, polyphenylenes, polyethylene, polyethylene terephthalate, polyethylene naphthalate, polypropylene, ethylene vinyl copolymers, polyvinyl chloride, etc. These materials may be doped.

[0012] In this embodiment, the material of the substrate 11 is preferably polyimide or polyethylene naphthalate. The softening point of polyimide is 290°C. The softening point of polyethylene naphthalate is 120°C.

[0013] In this embodiment, the substrate 11 is preferably a flexible substrate. Here, flexibility refers to the property that substrate 11 can be bent without breaking or breaking even when a force equivalent to its own weight is applied to substrate 11. The flexibility also includes the property of bending under a force of about its own weight. In this embodiment, the flexibility of the substrate 11 varies depending on the material, size, thickness, and environment such as temperature of the substrate 11.

[0014] As the flexible substrate 11, a substrate made of a resin material is preferable. A single long substrate can be used as the substrate 11. In this embodiment, the substrate 11 may be formed into a long shape by connecting a plurality of unit substrates.

[0015] <Gate electrode> The gate electrode 12 is formed on the surface of the substrate 11. The gate electrode 12 is conductive. There is no particular limitation on the material constituting the gate electrode 12. In this embodiment, examples of the material include Al, Mo, Cu, Ti, Au, and Ni. The gate electrode 12 may be a laminate using any one of these alone or a laminate using two or more of them in combination. Furthermore, an alloy containing these elements may be used. The alloy used for the gate electrode 12 may be, for example, an alloy of nickel and phosphorus.

[0016] The shape of the gate electrode 12 is not particularly limited, but from the viewpoint of controllability of the channel length and channel width, a rectangular shape in plan view with the channel length and channel width directions of the thin film transistor as its length and width are preferable.

[0017] The size of the gate electrode 12 may be any size that ensures the channel length and channel width of the thin film transistor.

[0018] Here, the channel length direction of the thin film transistor is the opposing direction of the source electrode 15a and the drain electrode 15b of the thin film transistor. The channel width direction of the thin film transistor is a direction perpendicular to the channel length direction of the thin film transistor and parallel to the surface of substrate 11.

[0019] The average thickness of the gate electrode 12 is, for example, 50 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. In order to improve the coverage of the gate insulating film 13, the cross section of the gate electrode 12 in the thickness direction may be tapered so as to expand toward the substrate 11. When the gate electrode 12 is tapered, the taper angle is preferably 30° or more and 40° or less.

[0020] <Gate insulating film> The gate insulating film 13 is formed on one surface of the substrate 11 so as to cover the gate electrode 12. In this embodiment, the surface of the substrate 11 on which the gate electrode 12 is provided is referred to as the upper main surface. In this embodiment, the gate insulating film 13 is made of SiO x Membrane and SiC y N z The film is a laminated film in which the films are alternately formed.

[0021] SiO x The x of the film is preferably 1.7 or more and 2.4 or less, and more preferably 1.9 or more and 2.1 or less.

[0022] Silicon Carbide y N z The film has an index of y of preferably 1.0 or more and 3.5 or less, and more preferably 1.0 or more and 2.0 or less. Silicon Carbide y N z The film has z preferably greater than 0 and equal to or less than 1.0, and more preferably equal to or greater than 0.2 and equal to or less than 0.7.

[0023] The total number of films constituting the laminated film is 3 to 18, and preferably 4 to 16. In this embodiment, the total number of films constituting the laminated film may be an odd number or an even number, but is more preferably an even number.

[0024] When the total number of films constituting the laminated film is odd, the layer in contact with the semiconductor film 14 is SiO x It is preferable to form the SiO x membrane, SiC y N z membrane, SiO x It is preferable to provide the film in this order.

[0025] The laminated film is formed by stacking a SiC y N z membrane, SiO xIt is preferable to alternately form the layers in this order. x It is preferable to form it into a film. That is, in the case of the bottom gate type, the top layer of the laminated film on the semiconductor film 14 side is SiO x It is preferable to form it into a film. In the case of the top gate type, the bottom layer on the semiconductor film 14 side is SiO x It is preferable to form it into a film.

[0026] SiO x The membrane is water (H 2 O) and hydrogen (H 2 In this embodiment, the laminated film having the above-mentioned layer structure has a barrier property against impurities that affect the thin film transistor characteristics, such as SiO x The number of interfaces between the films increases. These impurities are trapped at each interface. This improves the barrier properties and makes it difficult for impurities to diffuse into the semiconductor film. As a result, highly reliable devices can be realized. In addition, the stacked film is SiC y N z By providing the film, flexibility is imparted to the device, and the device can have improved resistance to stress.

[0027] SiO by plasma CVD equipment 2 Conventional methods for forming silicon-based thin films include a method in which the film is formed at a high temperature of about 200° C. to 300° C. in order to improve the insulating properties of the gate insulating film. In addition, there is a method in which a post-annealing treatment at a high temperature is essential. When high-temperature heat treatment is required as in conventional methods, the selectivity of the substrate material is low, and there are problems such as the inability to use resin substrates.

[0028] According to this embodiment, SiC y N z Membrane and SiO x By forming the gate insulating film by alternating the gate insulating film and the gate insulating film, a high-quality gate insulating film can be obtained at a processing temperature of, for example, less than 200° C. without high-temperature heat treatment.

[0029] Furthermore, by forming a laminated film having the above-mentioned layer structure, the film stress of the gate insulating film can be reduced, and therefore the present invention can be applied to flexible substrates that can be repeatedly bent.

[0030] The thickness of each of the films constituting the laminated film is 25 nm or more and 150 nm or less, preferably 26 nm or more and 90 nm or less, and more preferably 27 nm or more and 80 nm or less. When the thickness of each film constituting the laminated film is equal to or greater than the lower limit, high insulating properties can be exhibited, whereas when the thickness of each film constituting the laminated film is equal to or less than the upper limit, hysteresis can be reduced or eliminated, resulting in a highly reliable device.

[0031] In this embodiment, the total thickness of the laminated film is preferably 500 nm or less. In addition, it is preferable that the thickness of each film constituting the laminated film is approximately the same. The thickness of each layer may be appropriately adjusted depending on the total number of films. In this embodiment, it is preferable that the thickness of each film constituting the laminated film is approximately the same. The shape of the gate insulating film 13 is not limited as long as it covers the gate electrode 12 . For example, the gate insulating film 13 may cover the entire surface of the substrate 11 .

[0032] The gate insulating film is SiO x Membrane and SiC y N z It can be confirmed by the following method that the laminate film is a laminated film in which the layers and the insulating film are alternately formed, the total number of films constituting the laminate film is 3 to 18, and the thickness of each film constituting the laminate film is 25 nm to 150 nm.

[0033] The concentration of oxygen atoms in each layer that makes up the gate insulating film can be measured by composition analysis using Rutherford backscattering spectroscopy and hydrogen forward scattering spectroscopy, sometimes abbreviated as "RBS" and "HFS," respectively. The silicon atom concentration and carbon atom concentration in each layer constituting the gate insulating film can also be measured by RBS or HFS.

[0034] The concentration of hydrogen atoms, which are impurities present in each layer constituting the gate insulating film, can be measured by HFS.

[0035] RBS uses fast ions (He + , H + The device irradiates a target with a neutron (e.g., neutrons) and measures the energy and yield of the scattered ions for some of the incident ions that are elastically (Rutherford) scattered by the atomic nuclei of the target. The energy of the scattered ions varies depending on the mass and position (depth) of the target atom. Therefore, the elemental composition in the depth direction of the target can be obtained from the energy and yield of the scattered ions.

[0036] The HFS is a method to measure high-speed ions (He + By irradiating the target with a laser beam (such as a neutron beam), hydrogen in the target is scattered forward due to elastic recoil, and the depth distribution of elements can be obtained from the energy and yield of this recoiled hydrogen.

[0037] The silicon and oxygen atomic concentrations were measured by RBS or HFS to determine the SiO x The presence of the SiC film can be confirmed. In addition, the silicon atom concentration, carbon atom concentration, and nitrogen atom concentration can be measured by RBS or HFS. y N z By checking the distribution of these, it is possible to confirm the presence of the SiO x Membrane and SiC y N z It is possible to confirm whether the film is a laminated film in which the layers are alternately formed, and also to confirm the total number of films constituting the laminated film.

[0038] Semiconductor film The semiconductor material constituting the semiconductor film 14 is, for example, IGZO (In-Ga-Zn-O type), which has high carrier mobility and is relatively easy to form into a film, transparent amorphous oxide semiconductor (TAOS (Transparent Amorphous Oxide Semiconductor)), zinc oxide (ZnO), nickel oxide (NiO), tin oxide (SnO 2 ), titanium dioxide (TiO2 ), vanadium oxide (VO 2 ), indium oxide (In 2 O 3 ), strontium titanate (SrTiO 3 ) etc. can be mentioned as examples.

[0039] Moreover, an organic semiconductor may be used as the semiconductor material constituting the semiconductor film 14. As the organic semiconductor material, a p-type semiconductor, fullerenes, or an n-type semiconductor may be used.

[0040] Examples of p-type semiconductors include copper phthalocyanine (CuPc), pentacene, rubrene, tetracene, and P3HT (poly(3-hexylthiophene-2,5-diyl)).

[0041] An example of the fullerenes is C60.

[0042] Examples of n-type semiconductors include perylene derivatives such as PTCDI-CH (N,N'-dioctyl-3,4,9,10-perylene tetracarboxylic diimide).

[0043] Among the semiconductor materials constituting the semiconductor film 14, soluble pentacene and organic semiconductor polymers are soluble in organic solvents. Therefore, the semiconductor film can be formed by a wet process. An example of the soluble pentacene is TIPS pentacene (6,13-Bis(triisopropylsilylethynyl)pentacene). An example of the organic semiconductor polymer is poly(3-hexylthiophene-2,5-diyl) (P3HT). As the organic solvent, toluene is preferably used.

[0044] <Source electrode and drain electrode> The source electrode 15 a and the drain electrode 15 b cover a part of the gate insulating film 13 and are electrically connected to the semiconductor film 14 at both ends of the channel of the thin film transistor 1 . A drain current of the thin film transistor 1 flows between the source electrode 15a and the drain electrode 15b in response to the voltage between the gate electrode 12 and the source electrode 15a and the voltage between the source electrode 15a and the drain electrode 15b.

[0045] The material constituting the source electrode 15a and the drain electrode 15b is not particularly limited as long as it has conductivity, and for example, the same material as that of the gate electrode 12 can be used. The average thickness of the source electrode 15a and the drain electrode 15b is, for example, 100 nm or more and 400 nm or less, or 150 nm or more and 300 nm or less.

[0046] The opposing distance between the source electrode 15a and the drain electrode 15b, ie, the channel length of the thin film transistor 1, is, for example, 5 μm or more and 50 μm or less, or 10 μm or more and 30 μm or less.

[0047] The length of the source electrode 15a and the drain electrode 15b in the channel width direction, ie, the channel width of the thin film transistor 1, may be 100 μm or more and 300 μm or less, or 150 μm or more and 250 μm or less.

[0048] Although the thin film transistor 1 has been described as a bottom-gate thin film transistor, it may be a top-gate thin film transistor in another embodiment.

[0049] (Thin-film transistor characteristics) The lower limit of the threshold voltage of the thin film transistor of this embodiment is preferably −1 V, and more preferably 0 V. On the other hand, the upper limit of the threshold voltage of the thin film transistor is preferably 3 V, and more preferably 2 V.

[0050] <Electronic devices> The present embodiment relates to an electronic device including the thin film transistor of the present embodiment. The electronic device may be a display element such as a liquid crystal display element.

[0051] <Method of manufacturing thin film transistor> The present embodiment relates to a method for manufacturing a thin film transistor. The method for producing a thin film transistor according to the present embodiment is to form a SiO x Membrane and SiC y N z The method includes a step of forming a gate insulating film by alternately forming a gate insulating film and a gate insulating film. The film formation temperature in the gate insulating film formation step is a temperature below the softening point of the material constituting the substrate.

[0052] The method for manufacturing a thin film transistor of this embodiment preferably includes, in this order, a gate electrode forming step, a gate insulating film forming step, a semiconductor film forming step, a source and drain electrode forming step, and an annealing step.

[0053] <Gate electrode film formation process> In the gate electrode formation step, the gate electrode 12 is formed on the surface of the substrate 11 .

[0054] Specifically, a conductive film is first formed to a desired thickness by a known method, such as a sputtering method, on the surface of the substrate 11. The conditions for forming the conductive film by the sputtering method are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C. and a film formation power density of 3 W / cm. 2 More than 4W / cm 2 The conditions are as follows: pressure is 0.1 Pa or more and 0.4 Pa or less, and carrier gas is Ar.

[0055] Next, the conductive film is patterned to form the gate electrode 12. The patterning method is not particularly limited, but for example, a method of performing photolithography followed by wet etching can be used. At this time, it is preferable to etch the cross section of the gate electrode 12 into a tapered shape that expands toward the substrate 11 so as to improve the coverage of the gate insulating film 13.

[0056] <Gate insulating film formation process> In the gate insulating film forming step, the gate insulating film 13 is formed on the front surface side of the substrate 11 so as to cover the gate electrode 12 .

[0057] Specifically, first, a SiC y N z Forming a film, SiC y N z Film formation process and SiC y N z On top of the film, SiO x Film-forming SiO x The film formation process is carried out in this order. y N z Film formation process and SiO x By alternately repeating the film formation process, SiC y N z Membrane and SiO x A laminated film can be formed by alternately stacking the above films.

[0058] Silicon Carbide y N z Membrane and SiO x The film can be formed by a chemical vapor deposition (CVD) method using a film forming apparatus described in, for example, Japanese Patent No. 5967983.

[0059] [SiC y N z Film formation process] Silicon Carbide y N z In the film formation process, a raw material gas is used to form a SiC film on the substrate 11 by plasma CVD. y N zForms a film. SiC y N z The source gas used in the film formation process may be a source gas consisting of an organosilicon compound and a compound containing hydrogen atoms. Specifically, a source gas containing hexamethyldisilazane may be used. Hexamethyldisilazane is abbreviated as "HMDS."

[0060] Specifically, for example, a mixture of hydrogen gas and argon gas and a source gas such as HMDS are introduced into the deposition chamber to form a SiC y N z The introduction rate of the source gas is, for example, 3 sccm or more and 100 sccm or less. It is preferable that the mixed gas and the source gas are simultaneously introduced into the deposition chamber. The introduction rate of the mixed gas is, for example, 20 sccm or more and 1000 sccm or less.

[0061] By generating plasma while introducing the mixed gas and the raw material gas, a surface reaction proceeds on the surface of the substrate 11, and SiC y N z A film is formed.

[0062] [SiO x Film formation process] SiO x The film formation process uses raw material gas and is performed by plasma CVD. y N z On top of the film, SiO x Forms SiO x The source gas used in the film formation process may be a source gas consisting of an organosilicon compound and a compound containing oxygen atoms. Specifically, a source gas containing hexamethyldisilazane may be used. Hexamethyldisilazane is referred to as "HMDS."

[0063] Specifically, for example, oxygen gas and source gas such as HMDS are introduced into the deposition chamber to form SiO x The introduction rate of the source gas is, for example, 3 sccm or more and 20 sccm or less. The oxygen gas introduction rate is, for example, 20 sccm or more and 1000 sccm or less.

[0064] By generating plasma while introducing oxygen gas and raw material gas, SiC y N z A surface reaction occurs on the surface of the film, forming SiC y N z SiO on top of the membrane x A film is formed.

[0065] In addition, on the substrate 11, SiC y N z Before forming the SiC film, an undercoat film may be formed on the substrate 11 as an optional step. When the undercoat film is formed, the gate electrode and the SiC y N z Film, substrate and SiC y N z The adhesion to the film can be improved. In the present embodiment, the base film that may be formed as an optional step is a film formed by plasma CVD and containing at least silicon atoms and oxygen atoms. The base film preferably has an oxygen atom concentration of 10 to 35 atomic %.

[0066] In this embodiment, the gate insulating film forming step is carried out at a temperature below the softening point of the material constituting the substrate. Specifically, the temperature is preferably at least 20° C. lower than the softening point of the material constituting the substrate, and more preferably at least 40° C. lower. In this embodiment, SiC y N z Membrane and SiO x By forming a composite insulating film in which the insulating film and the insulating film are alternately formed, it is possible to form the film at a low temperature lower than the softening point of the material constituting the substrate.

[0067] <Semiconductor film formation process> In the semiconductor film formation step, a semiconductor film 14 is formed on the surface of the gate insulating film 13 and directly above the gate electrode 12 . Specifically, after a semiconductor layer is formed on the surface of the gate insulating film 13, the semiconductor layer is patterned to form the semiconductor film .

[0068] (Formation of semiconductor layer) Specifically, first, for example, a known sputtering device is used to form a semiconductor layer on the surface of the gate insulating film 13 by sputtering. By using the sputtering method, a semiconductor layer having excellent in-plane uniformity in terms of its components and film thickness can be easily formed.

[0069] The sputtering target used in the sputtering method may be an oxide target containing In, Ga, and Zn (IGZO target).

[0070] The conditions for forming a semiconductor layer by sputtering are not particularly limited, but for example, the substrate temperature is 20° C. or higher and 50° C. or lower, and the deposition power density is 2 W / cm. 2 More than 3W / cm 2 The conditions are as follows: pressure is 0.1 Pa to 0.3 Pa, and carrier gas is Ar. In addition, oxygen may be contained in the atmosphere as an oxygen source. The oxygen content in the atmosphere may be 3 volume % to 5 volume %.

[0071] The method for forming the semiconductor layer is not limited to the sputtering method, and a chemical film formation method such as a coating method may also be used.

[0072] (Patterning) Next, this semiconductor layer is patterned to form the semiconductor film 14. The method for patterning the thin semiconductor layer is not particularly limited, but for example, a method of performing photolithography followed by wet etching can be used.

[0073] <Source and drain electrode film formation process> In the source and drain electrode film formation step, a source electrode 15a and a drain electrode 15b that are electrically connected to the semiconductor film 14 on both ends of the channel of the thin film transistor are formed.

[0074] Specifically, a conductive film is first formed to a desired thickness by a known method, such as a sputtering method, on the surface of the substrate 11. The conditions for forming the conductive film by the sputtering method are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C. and a film formation power density of 3 W / cm. 2 More than 4W / cm 2 The conditions are as follows: pressure is 0.1 Pa or more and 0.4 Pa or less, and carrier gas is Ar.

[0075] Next, the conductive film is patterned to form the source electrode 15a and the drain electrode 15b. The patterning method is not particularly limited, but may be, for example, a method of performing photolithography and then wet etching.

[0076] <Annealing process> After the gate insulating film is formed, it is preferable to further include an annealing step of annealing at 300° C. or less. The annealing temperature is more preferably 200° C. or lower. The annealing step is preferably carried out at the above temperature for 10 minutes to 8 hours. EXAMPLES

[0077] The present invention will be explained in more detail below with reference to examples, but the present invention is not limited to the following examples.

[0078] <Example 1> [Gate electrode film formation process] A polyimide film (softening point: 290°C) with a thickness of 125 μm was used as the substrate 11. A metal mask (SUS430 with a thickness of 0.08 mm) having a pattern corresponding to the gate electrode was placed on one surface of the cleaned substrate 11, and a conductive film (Al film: 50 nm) which is the material for forming the gate electrode 12 was formed by a resistance heating vacuum deposition method. Thus, the gate electrode 12 was formed on the substrate 11.

[0079] [Gate insulating film deposition process] Next, a gate insulating film 13 was formed on the entire upper main surface of the substrate 11 so as to cover the gate electrode 12. The gate insulating film 13 was formed by chemical vapor deposition (CVD) using a SiO x Membrane and SiC y N z The films were alternately formed.

[0080] [Gate insulating film deposition process] In the gate insulating film formation step, a gate insulating film 13 was formed on the front surface side of the substrate 11 so as to cover the gate electrode 12 .

[0081] Silicon Carbide y N z Membrane and SiO x The film was formed by a chemical vapor deposition (CVD) method using the film forming apparatus described in Japanese Patent No. 5967983.

[0082] [SiC y N z Film formation process] A SiC film is formed on the substrate 11 by plasma CVD using a raw material gas. y N z A film was formed. SiC y N z In the film formation process, HMDS gas was used as the source gas.

[0083] A mixture of hydrogen gas and argon gas and HMDS gas were introduced into the deposition chamber, and SiC y N z The introduction rate of the source gas was set to 3 to 100 sccm. The mixed gas and the source gas were simultaneously introduced into the deposition chamber at a rate of 20 to 1000 sccm.

[0084] By generating plasma while introducing the mixed gas and the raw material gas, a SiC y N z The plasma was generated at a plasma power of 1 to 20 kW, and the SiCy N z The film was allowed to develop to the desired thickness.

[0085] [SiO x Film formation process] Using the raw gas, the plasma CVD method is used to produce SiC y N z On top of the film, SiO x SiO x In the film formation process, HMDS gas was used as the source gas.

[0086] By introducing oxygen gas and HMDS gas into the deposition chamber, SiO x The HMDS gas was introduced at a rate of 10 to 100 sccm. The oxygen gas was introduced at a rate of 20 to 1000 sccm.

[0087] By generating plasma while introducing oxygen gas and raw material gas, SiC y N z SiO on top of the membrane x The plasma was generated at a plasma power of 1 to 20 kW, and the SiO x The film was allowed to develop to the desired thickness.

[0088] The film formation temperature in the gate insulating film formation process was set to 82°C. In Example 1, SiC y N z Film formation process and SiO x A set of the film formation process was counted as one step, and the process was carried out twice to form a four-layer gate insulating film. y N z Film formation process and SiO x A set including the film formation process is counted as one time.

[0089] The four-layer gate insulating film 13 manufactured in Example 1 was analyzed by RBS or HFS. y N z In the film, y was 1.0 or more and 2.0 or less, and z was 0.2 or more and 0.7 or less. xIn the membrane, x was 1.9 or more and 2.1 or less. When the gate insulating film 13 having a four-layer structure manufactured in Example 1 was analyzed by RBS or HFS, it was found that the gate insulating film 13 had a thickness of 100 nm and a thickness of 100 nm. y N z Membrane, SiO with a thickness of 100 nm x Film, 100nm thick SiC y N z Membrane, SiO with a thickness of 100 nm x The membrane was made up of four layers.

[0090] [Semiconductor film formation process] Next, a semiconductor film 14 was formed on the gate insulating film 13 . The oxide semiconductor film, which is the material for forming the semiconductor film 14, is formed by using an InGaZnO target [In 2 O 3 ·Ga 2 O 3 (ZnO) 2 The semiconductor film 14 was formed by sputtering using a metal mask, in the same manner as the gate electrode 12. As a result, a 20 nm thick InGaZnO film was formed.

[0091] [Source and drain electrode film formation process] Next, a conductive film (Al film: 50 nm) was formed as the material for the source electrode 15a and the drain electrode 15b by a resistance heating vacuum deposition method. This film formation was also performed through a metal mask, and the source electrode 15a and the drain electrode 15b having the desired pattern shape were obtained.

[0092] The source electrode 15a and the drain electrode 15b were formed so as to overlap the gate insulating film 13 and the semiconductor film 14, respectively. The semiconductor film 14 was formed so as to be partly exposed between the source electrode 15a and the drain electrode 15b.

[0093] [Annealing process] After the gate insulating film was formed, an annealing step was further carried out for 8 hours at a temperature of 105° C. or less, thereby obtaining the thin film transistor of Example 1.

[0094] <Example 2> Silicon Carbide y N z Film formation process and SiO x The film formation process was performed four times, with one set including the film formation process being counted as one time, and a 50 nm thick SiC y N z Membrane, SiO with a thickness of 50 nm x Film, 50 nm thick SiC y N z Membrane, SiO with a thickness of 50 nm x Film, 50 nm thick SiC y N z Membrane, SiO with a thickness of 50 nm x Film, 50 nm thick SiC y N z Membrane, SiO with a thickness of 50 nm x A thin-film transistor was manufactured in the same manner as in Example 1, except that the gate insulating film 13 having an eight-layer structure was formed.

[0095] <Example 3> Silicon Carbide y N z Film formation process and SiO x The film formation process was performed 7 times, with one set including the film formation process being counted as one time, and a 30 nm thick SiC y N z The film and SiO with a thickness of 30 nm x A thin film transistor was manufactured in the same manner as in Example 1, except that the gate insulating film 13 having a 14-layer structure was formed by alternately forming the layers in this order.

[0096] <Example 4> SiO x Film formation process and SiC y N z Film formation process and SiO x The film formation steps are performed in this order, and a SiO 2 film having a thickness of 50 nm is formed on the gate electrode 12 side. x Film, 300nm thick SiC y N zMembrane, SiO with a thickness of 50 nm x A thin-film transistor was manufactured in the same manner as in Example 1, except that a gate insulating film 13 having a three-layer structure, i.e., a SiO 2 film, was formed.

[0097] <Comparative Example 1> 400nm thick SiC y N z A thin film transistor was manufactured in the same manner as in Example 1, except that the gate insulating film 13 was formed.

[0098] <Comparative Example 2> Silicon Carbide y N z Film formation process and SiO x A set of the film formation process is counted as one set, and the process is repeated 10 times. y N z The film and 20 nm thick SiO x A thin film transistor was manufactured in the same manner as in Example 1, except that the gate insulating film 13 having a 20-layer structure was formed by alternately forming the layers in this order.

[0099] <Evaluation of thin-film transistor characteristics> The thin film transistors produced in Examples 1 to 4 and Comparative Examples 1 and 2 were evaluated for their characteristics. The thin film transistors produced in Examples 1 to 4 and Comparative Examples 1 and 2 were subjected to transistor performance evaluation using a semiconductor parameter analyzer (Keithley, 4200A-SCS). The voltage between the source and drain electrodes, Vds, was set to 10 V, and the gate voltage, Vg, was changed from -10 V to +20 V to evaluate the current-voltage characteristics (transfer characteristics). The results are shown in Figures 2 to 7, and the results of Examples 1 to 4 are shown in Figures 2 to 5, respectively. The results of Comparative Examples 1 and 2 are shown in Figures 6 to 7, respectively. 2 to 7, the vertical axis represents the drain current, and the horizontal axis represents the gate voltage.

[0100] 2 to 5, the lower limit of the threshold voltage was near 0 V, and the negative shift of the threshold voltage was suppressed. Furthermore, in Examples 1 to 4 shown in Figures 2 to 5, good thin film transistor characteristics with small hysteresis were obtained. In particular, it was confirmed that Example 2 shown in FIG. 3 and Example 3 shown in FIG. 4 did not cause hysteresis and had high reliability in the initial characteristics.

[0101] On the other hand, in Comparative Example 1, the lower limit of the threshold voltage was shifted to the negative side as shown in Fig. 6. Also, in Comparative Example 2 shown in Fig. 7, the operation was defective. This is believed to be because the thicknesses of the layers constituting the gate insulating film were too thin. [Explanation of symbols]

[0102] 1: Thin-film transistor 11: Substrate 12: Gate electrode 13: Gate insulating film 14: Semiconductor film (oxide semiconductor) 15a: Source electrode 15b: Drain electrode

Claims

1. A transistor having a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, The gate insulating film is made of SiO ｘ Membrane and SiC ｙ N ｚ a laminated film in which a film and a film are alternately formed, x in the SiO x film is 1.7 or more and 2.4 or less, In the SiC y N z film, y is 1.0 or more and 3.5 or less, and z is more than 0 and 1.0 or less; The total number of films constituting the laminated film is 3 to 18, A transistor, wherein each film constituting the laminated film has a thickness of 25 nm or more and 150 nm or less.

2. 2. The transistor according to claim 1, wherein the total thickness of the laminated film is 500 nm or less.

3. The laminated film has a layer in contact with the semiconductor film, which is made of SiO ｘ The transistor according to claim 1 or 2, which is a film.

4. 4. The transistor according to claim 1, wherein each film constituting the laminated film has a substantially uniform thickness.

5. 5. The transistor according to claim 1, which is formed on a flexible substrate.

6. 6. The transistor according to claim 1, which is formed on a substrate made of a resin material.

7. An electronic device comprising the transistor according to any one of claims 1 to 6.

8. A method for manufacturing a transistor according to any one of claims 1 to 6, comprising the steps of: The SiO ｘ The film and the SiC ｙ N ｚ a gate insulating film forming step of forming the gate insulating film by alternately forming a gate insulating film and a gate insulating film; A method for manufacturing a transistor, wherein a film formation temperature in the gate insulating film formation step is a temperature lower than a softening point of a material constituting the substrate.

9. 9. The method for producing a transistor according to claim 8, further comprising, after the gate insulating film forming step, an annealing step of annealing at a temperature lower than the softening point.

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