Stacked memory and manufacturing method thereof

Abstract

Provided is a stacked memory with an improved yield rate and with which suitable operation timing control is possible. Also provided is a manufacturing method therefor.　Provided is a stacked memory 1 obtained by stacking a plurality of memory chips, wherein the memory chips each include a plurality of memory cells, and comprise: a memory unit 20 that is capable of storing data and has a normal memory block 21 used mainly for reading and writing data and a spare memory block 22 substituted for a defective memory cell in the normal memory block 21; an address storage unit 30 that, for each of two or more stacked memory chips, stores a slice address identifying a memory chip serving as an object to undergo substitution of the normal memory block 21 with the spare memory block 22 as a substitution source slice address, and stores a memory address serving as the object to undergo substitution as a substitution source memory address; a comparison unit 50 that compares a request address indicating the slice address and memory address of an access request destination, and the substitution source address; a specification unit 60 that, on the basis of the comparison results, specifies the memory unit 20 that is actually to be accessed and generates an access timing; a timing control unit 80 that selects one from among the generated access timing and access timings transmitted from the other memory chips, and controls access to the memory unit 20 at the selected access timing; and an execution unit 70 that executes reading and writing to the specified memory unit 20 at the selected access timing.

Description

[Technical field]

[0001] The present invention relates to a stacked memory and a method for manufacturing the same. [Background technology]

[0002] Volatile memories (RAMs) such as DRAMs (Dynamic Random Access Memory) have been known as storage devices. DRAMs are required to have larger capacities to withstand the increasing performance of arithmetic units (hereinafter referred to as logic chips) and the increasing amount of data. To address this issue, efforts have been made to increase capacity by miniaturizing memories (memory cell arrays, memory chips) and adding cells in a planar manner. However, this type of capacity increase is reaching its limit due to factors such as vulnerability to noise caused by miniaturization and increased die area.

[0003] In response to this, technology has been developed recently to realize large capacity by stacking multiple planar memories to create a three-dimensional (3D) memory. A semiconductor module has also been proposed that electrically connects multiple stacked modules (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2012-505491 Summary of the Invention [Problem to be solved by the invention]

[0005] The semiconductor module of Patent Document 1 includes multiple dies having non-defective cells, defective cells, and spare cells. In the semiconductor module of Patent Document 1, one of the multiple dies functions as an interface die. The interface die includes components such as an I / O circuit and an interface I / O circuit. The interface die also includes a comparison circuit that compares the addresses of the access targets for all the dies with the addresses of the defective cells.

[0006] On the other hand, in Patent Document 1, the interface die controls all the dies. Therefore, the number of signal lines (the number of TSVs or microbumps) from the interface die to each die increases. This reduces the yield of the semiconductor module. In addition, Patent Document 1 also discloses a semiconductor module having a comparison circuit in each die, but the interface die does not have information about which die is being accessed. Therefore, it does not disclose how to control the operation timing of the I / O of each die.

[0007] The present invention has been made in view of the above-mentioned problems, and has an object to provide a stacked memory capable of improving yield and controlling suitable operation timing, and a manufacturing method thereof. [Means for solving the problem]

[0008] The present invention relates to a stacked memory having a plurality of memory chips stacked, the memory chip including a plurality of memory cells, a memory section capable of storing data, the memory section having a regular memory block mainly used in reading and writing data and a spare memory block replacing a defective memory cell of the regular memory block, an address storage section storing a slice address identifying a memory chip to be replaced with the spare memory block for two or more of the stacked memory chips as a replacement source slice address and storing the memory address to be replaced as a replacement source memory address, a comparison section comparing a request address indicating the slice address and memory address of an access request destination with the replacement source slice address and the replacement source memory address, an identification section identifying the memory section to be actually accessed based on a comparison result and generating an access timing, a timing control section selecting either the generated access timing or an access timing transmitted from another memory chip, and controlling access to the memory section at the selected access timing, and an execution section executing read / write at the selected access timing for the identified memory section.

[0009] The present invention also relates to a stacked memory in which a plurality of memory chips are stacked, each of the memory chips including a plurality of memory cells, the stacked memory comprising: a memory section capable of storing data; a determination section that generates an access timing to the memory section; a timing control section that selects either the generated access timing or an access timing transmitted from another memory chip, and controls access at the selected access timing; and an execution section that executes read / write at the selected access timing.

[0010] The present invention also relates to a stacked memory in which a plurality of memory chips are stacked, each of the memory chips including a plurality of memory cells and a memory section capable of storing data, the memory section having a regular memory block mainly used in reading and writing data and a spare memory block replacing defective memory cells of the regular memory block, an address storage section for storing, for all of the stacked memory chips, a slice address that identifies the memory chip to be replaced by the spare memory block for the regular memory block as a replacement source slice address, and storing the memory address to be replaced as a replacement source memory address, a comparison section for comparing the slice address and a request address indicating the memory address of the access request destination with the replacement source slice address and the replacement source memory address, an identification section for identifying the memory section to actually be accessed based on the comparison result, and an execution section for executing read / write to the identified memory section.

[0011] It is also preferable that the timing control section specifies the slice to be accessed based on a slice address of the slice to be accessed output from the other memory chip.

[0012] It is also preferable that the timing control section obtains timing generated by another of the memory chips as an instruction for execution timing from outside.

[0013] It is also preferable that the comparison section outputs, as a comparison result, a signal indicating whether or not the normal memory block or the spare memory block of its own memory chip is to be used.

[0014] In addition, it is preferable that the memory chip further includes a chip identification information storage unit that stores an individual slice address, which is a slice address that identifies the memory chip itself, as chip identification information, and the comparison unit includes a chip comparison unit that compares whether the individual slice address matches a slice address included in the request address, and an address comparison unit that compares whether the request address matches the replacement source address, and the identification unit identifies the access destination address based on the comparison result.

[0015] It is also preferable that the normal memory block and the spare memory block each have a redundant memory cell capable of replacing a defective memory cell therein.

[0016] The present invention also relates to a method for manufacturing the above-mentioned stacked memory, comprising: a stacking step of stacking semiconductor wafers each including a plurality of the memory chips; a replacement step of replacing defective memory cells of the normal memory blocks included in the stacked semiconductor wafers with memory cells of the spare memory blocks; and, after the replacement step, a singulation step of singulating the stacked memory chips.

[0017] In addition, it is preferable that the manufacturing method of a stacked memory further includes, prior to the stacking step, a wiring layer formation step of determining, using a wiring layer, which semiconductor wafer among all the semiconductor wafers to be stacked constitutes a master chip capable of sending access requests and timing signals to the other memory chips to be stacked.

[0018] In addition, it is preferable that the manufacturing method of a stacked memory further includes a master chip determination step, after the stacking step and before the replacement step, of determining, from among all the semiconductor wafers to be stacked, a semiconductor wafer that constitutes a master chip capable of sending command signals and timing signals to other memory chips to be stacked. Effect of the Invention

[0019] According to the present invention, it is possible to provide a stacked memory that improves yield and allows suitable control of operation timing, and a method for manufacturing the same. [Brief description of the drawings]

[0020] [Figure 1] 1 is a block diagram showing a configuration of a stacked memory according to an embodiment of the present invention; [Diagram 2] 2 is a schematic diagram showing memory cells of a normal memory block and a spare memory block of a stacked memory according to one embodiment; [Diagram 3] FIG. 2 is a circuit diagram showing an address comparison unit of a stacked memory according to an embodiment; [Figure 4] 4 is a circuit diagram showing a fuse comparison unit which is an element of FIG. 3. [Diagram 5] 1 is a circuit diagram showing a read / write slice address generation circuit in a master chip of a stacked memory according to an embodiment. [Figure 6] 1 is a flowchart illustrating a manufacturing process of a stacked memory according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, a stacked memory 1 according to one embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. The stacked memory 1 according to the present embodiment is configured by stacking a plurality of memory chips, for example. As shown in FIG. 1, the stacked memory 1 is configured by stacking n (n is a natural number equal to or greater than 2) memory chips. In the present embodiment, one of the memory chips operates as a master slice 10 having an input / output circuit capable of transmitting / receiving an input / output signal DQ to / from the outside. The master slice 10 operates so as to be capable of transmitting a slice address in which a memory unit 20 selected by a comparison unit 50 exists to another memory chip. The master slice 10 operates so as to be capable of transmitting a timing signal indicating the timing of read / write to another memory chip. The other memory chip operates as a slave slice 11 capable of receiving a slice address and a timing signal transmitted from the master slice 10.

[0022] In this embodiment, each of the memory chips has a spare memory area (spare memory block) that can be used in place of a defective memory cell in the main memory area (normal memory block 21) of the memory chip. In particular, in this embodiment, each of the memory chips substitutes the defective memory cell in the normal memory block 21 of the memory chip with the spare memory block 22 of its own memory chip or the spare memory block 22 of another memory chip. Each of the memory chips selects whether to use the normal memory block 21 or the spare memory block 22 of its own or the other memory chip in response to an input of an address of the access destination. Each of the memory chips executes an access in response to the selection of its own normal memory block 21 or the spare memory block 22. As a result, each of the memory chips individually determines the address of the access destination without relying on the master slice 10.

[0023] The configuration of the master slice 10 differs from that of the slave slice 11 in that it has external terminals (input circuits for C: command, A: address, and SA: slice address) that enable communication with the outside. The configuration of the master slice 10 also differs from that of the slave slice 11 in that it can transmit to the slave slice 11 a slice address of an access destination (the slice address of a semiconductor chip to be read / written) and a timing signal. In the following configuration description, the configuration common to the master slice 10 and the slave slice 11 will be described as the configuration of the slave slice 11. In the following embodiment, the stacked memory 1 will be described by taking an example in which eight memory chips are stacked. Among the configurations of the slave slice 11, the configuration unique to the master slice 10 will be described separately.

[0024] Next, the structure of the memory chip of the stacked memory 1 according to this embodiment will be described. As shown in FIG. 1, the memory chip includes a memory section 20, an address storage section 30, a chip identification information storage section 40, a comparison section 50, a specification section 60, a timing control section 80, and an execution section .

[0025] The memory unit 20 is, for example, a memory block configured by memory cells. That is, the memory unit 20 is configured to be able to store data. The memory unit 20 includes a normal memory block 21 and a spare memory block 22.

[0026] The normal memory block 21 is a memory area mainly used in reading and writing data. Therefore, the normal memory block 21 has the largest storage capacity in the memory chip. In this embodiment, the normal memory block 21 has a normal memory cell area and a redundant memory cell area as shown in FIG. 2. The normal memory cell area is an area used for normal reading and writing. The redundant memory cell area is an area in which a defective memory cell in the normal memory cell area can be replaced. That is, the normal memory block 21 has a redundant memory cell capable of replacing its own defective memory cell. For example, when a defective memory cell in the normal memory cell area cannot be replaced by the redundant memory cell area, the normal memory block 21 can be replaced by using the spare memory block 22 described below.

[0027] The spare memory block 22 is a memory area that substitutes for defective memory cells of the regular memory block 21. Therefore, the spare memory block 22 has a smaller storage capacity than the regular memory block 21. In this embodiment, the spare memory block 22 is configured to be able to substitute for, for example, a certain percentage of the memory area of ​​the regular memory block 21. The spare memory block 22 is configured to be able to substitute for, for example, a memory area of ​​1 / 16 capacity including defective memory cells of the memory area of ​​the regular memory block 21. The spare memory block 22 has redundant memory cells like the regular memory block 21. For example, the spare memory block 22 substitutes for a defective memory cell area of ​​the regular memory block 21 using its own spare memory cell area. When a defective memory cell exists in its own spare memory cell area, the spare memory block 22 substitutes for the defective memory cell using its own redundant memory cell area.

[0028] The address storage unit 30 includes, for example, a fuse element. The address storage unit 30 stores, for all stacked memory chips, slice addresses that identify memory chips to be substituted for the normal memory block 21 by the spare memory block 22 as replacement source slice addresses, and stores the memory addresses to be substituted as replacement source addresses. FIG. 3 shows these stored information as slice 1 repair information to slice 8 repair information. Furthermore, for each slice, the address storage unit 30 stores, as replacement source slice addresses, slice addresses that identify memory chips to be substituted by the slices themselves. Specifically, for each slice, the address storage unit 30 stores, as replacement source slice addresses, slice addresses that identify memory chips having normal memory blocks 21 to be substituted for areas including defective memory cells to be substituted by the slices themselves. Furthermore, for each slice, the address storage unit 30 stores, as replacement source slice addresses, access addresses to normal memory blocks 21 to be substituted for areas including defective memory cells to be substituted by the slices themselves. FIG. 3 shows these stored information as own slice repair information.

[0029] In this embodiment, the address storage unit 30 stores, for example, an 8-bit address as a defective address indicating an area including a defective memory cell to be replaced. This is shown in FIG. 3 as relief information. The address storage unit 30 stores, for example, an address consisting of 1 bit indicating whether the address stored in the address storage unit 30 is valid or invalid, 3 bits indicating an address corresponding to an address specifying a memory chip to be replaced (hereinafter also referred to as a defective slice address), and 4 bits indicating a memory address specifying a memory area to be replaced (hereinafter also referred to as a defective memory address). The address storage unit 30 stores, for example, the upper 4 bits of the address of the defective memory cell as an address specifying a memory area to be replaced. As a result, the address storage unit 30 stores an address corresponding to 1 / 16 of the area including the defective memory cell of the normal memory block 21. The address storage unit 30 of each slice stores a total of 72-bit addresses including 64 bits (8 slices×8 bits) of relief information of all slices and 8 bits of own slice relief information which is the relief information of the original to be replaced by the slice itself.

[0030] The chip identification information storage unit 40 includes, for example, a fuse element. The chip identification information storage unit 40 stores chip identification information for identifying a memory chip. The chip identification information storage unit 40 stores, for example, an individual slice address that is a slice address for identifying its own memory chip, as the chip identification information.

[0031] The comparison unit 50 is, for example, an electronic circuit. The comparison unit 50 compares a request address indicating a slice address and a memory address of an access request destination with an alternative source address. The comparison unit 50 acquires information of the memory chip of the access destination (hereinafter also referred to as slice address SA) and a memory address (hereinafter also referred to as memory address A). The comparison unit 50 acquires, for example, a slice address SA and a memory address A of an access target requested from outside. The comparison unit 50 also compares the acquired slice address SA with its own slice address included in the chip identification information. Then, the comparison unit 50 compares the memory address A of the access destination with the alternative source memory address. As a result, the comparison unit 50 outputs a signal indicating whether or not to use the regular memory block 21 or the spare memory block 22 of its own memory chip as a comparison result. Specifically, the comparison unit 50 outputs, for example, whether or not to access the regular memory block 21 of its own or another memory chip and whether or not to access the spare memory block 22 of its own or another memory chip as a comparison result. The comparison unit 50 includes a chip comparison unit 52 and an address comparison unit 51 .

[0032] The chip comparison unit 52 acquires its own slice address included in the chip identification information from the chip identification information storage unit 40. The chip comparison unit 52 compares the acquired slice address identifying its own memory chip with the slice address SA of the memory chip requested as the access destination. The chip comparison unit 52 outputs the comparison result indicating whether or not its own memory chip is to be accessed. When the slice address SA and the information of the memory chip to be accessed are the same, the chip comparison unit 52 outputs a comparison result OSH (Own Slice Hit) signal indicating that the access is to its own memory chip. On the other hand, when the slice address stored in the chip identification information storage unit is different from the slice address SA of the memory chip requested as the access destination, the chip comparison unit 52 does not output the comparison result OSH signal since the access is not to its own memory chip.

[0033] The address comparison unit 51 compares the address A and slice address SA of the access destination memory chip acquired from outside with the source address of substitution of its own slice and the source address of substitution of another slice acquired from the address storage unit 30. In this embodiment, the address comparison unit 51 compares the upper 4 bits of the access destination address A acquired from outside with the source memory address. The address comparison unit 51 also compares the slice address A with the source slice address of substitution. The address comparison unit 51 outputs, as a comparison result, whether or not to use the spare memory block 22 of its own memory chip (hereinafter also referred to as Own Redundancy Hit (ORH signal)) and whether or not to use the regular memory block 21 of its own memory chip (Any Redundancy Hit (ARH signal)).

[0034] As an example, the address comparison unit 51 includes a plurality of comparison circuits as shown in FIG. 3. The comparison circuits are provided according to the number of memory chips. In this embodiment, the address comparison unit 51 is configured using one comparison circuit for ORH output and eight comparison circuits for ARH output in accordance with the eight stacked memory chips. Specifically, the address comparison unit 51 has a first comparison circuit that compares whether or not to use the spare memory block 22 of its own memory chip, and second to ninth comparison circuits that compare whether or not to use any of the spare memory blocks 22 of the eight memory chips. The address comparison unit 51 outputs the result of the first comparison circuit as an ORH signal. In addition, the address comparison unit 51 uses a gate circuit to output the logical sum of the output results of the second comparison circuit to the ninth comparison circuit as an ARH signal.

[0035] The first comparison circuit 511 outputs a comparison result indicating whether or not to use the spare memory block 22 of its own memory chip. The first comparison circuit 511 acquires a request address and also acquires a replacement source fuse address that its own slice will replace from the address storage unit 30. The first comparison circuit 511 compares the request address with the replacement source fuse address, and outputs a comparison result ORH signal indicating whether or not to use the spare memory block 22 of its own memory chip. Specifically, when the request memory address hits the replacement source slice address and the replacement source memory address, the first comparison circuit 511 outputs an ORH signal (High signal) indicating that its own spare memory block 22 will be used, as the comparison result.

[0036] The second comparison circuit 512 to the ninth comparison circuit 519 output as a comparison result whether or not the spare memory block 22 provided in the stacked memory 1 including the own memory chip is used. In this embodiment, each of the second comparison circuit 512 to the ninth comparison circuit 519 outputs as a comparison result whether or not the spare memory block 22 of any memory chip among the eight stacked memory chips is used. Each of the second comparison circuit 512 to the ninth comparison circuit 519 is provided corresponding to each of the eight memory chips. The second comparison circuit 512 to the ninth comparison circuit 519 output as a comparison result whether or not the spare memory block 22 is used in any of the first memory chip (master slice 10), the second memory chip (slave slice 11), to the eighth memory chip (slave slice 11), which are stacked in order. The second comparison circuit 512 to the ninth comparison circuit 519 compare whether or not the request address, the replacement source slice address to be replaced by each of the eight memory chips, and the replacement source memory address match. In the fuse information stored in the address storage unit 30 of each chip, bits 0 to 7 corresponding to the first comparison circuit 511 are the original addresses to be substituted by each chip and have unique values ​​for each of the eight memory chips. Meanwhile, bits 8 to 71 corresponding to the second comparison circuit 512 to the ninth comparison circuit 519 have the same values ​​for all eight memory chips.

[0037] For example, the second comparison circuit 512 compares whether the request address, the original slice address to be substituted by slice 1, and the original memory address match. When the original memory address and the original slice address match the request address, the second comparison circuit 512 outputs a signal HIT1 indicating High as a comparison result. The third comparison circuit to the ninth comparison circuit 519 output High or Low as a comparison result based on a comparison between the request address, the original address to be substituted by slices 2 to 8, and the original slice address. That is, when any of the spare memory blocks 22 of the stacked memory 1 is used, any of the second comparison circuit 512 to the ninth comparison circuit 519 outputs a High signal. As a result, the second comparison circuit 512 to the ninth comparison circuit 519 output a High signal as the ARH signal. On the other hand, when the spare memory block 22 of the stacked memory 1 is not used, the second comparison circuit 512 to the ninth comparison circuit 519 all output a Low signal. As a result, the second comparison circuit 512 to the ninth comparison circuit 519 output a Low signal as the ARH signal. ~ When the ninth comparator circuit 519 outputs a High signal as the ARH signal for a requested address, this indicates that one of the spare memory blocks 22 in the stacked memory 1 is used and therefore no normal memory blocks 21 are used in any of the eight memory chips. On the other hand, when the ninth comparator circuit 519 outputs a Low signal as the ARH signal, this indicates that one of the normal memory blocks 21 in the stacked memory 1 is used.

[0038] As shown in FIG. 4, each of the first comparison circuit 511 to the ninth comparison circuit 519 is composed of a combination of an XNOR gate, a NAND gate, a NOR gate, and a NOT gate. The address comparison unit 51 outputs a signal (ORH signal in FIG. 3) for selecting a replacement block of its own memory chip, a signal (ARH signal in FIG. 3) indicating whether its own regular block is to be used, and, in the master slice 10 only, a slice address of a replacement destination when a spare block is used, and a requested slice address SA (RWSA<2:0> in FIG. 5) when a spare block is not used. The address comparison unit 51 outputs valid (HIT0 in FIG. 4 is a value of 1) when there is a replacement in its own spare memory block 22. Then, the first address comparison circuit outputs a signal (ORH signal) for selecting the spare memory block 22 of its own memory chip, as shown in FIG. 3. Also, the second to ninth comparison circuits 512 to 519 output a signal (ARH signal) indicating that the spare memory block 22 of any memory chip has been selected. Here, the Fuse <7> indicates enable information that is Low when the spare block is not used in the corresponding slice and High when the spare block is used.

[0039] In the master slice 10, the comparison circuit has a chip identification circuit for identifying a memory chip to actually read / write, as shown in FIG. 5. The chip identification circuit identifies a memory chip to actually execute read / write by encoding the remaining signals excluding HIT1 based on HIT1 to HIT8. The chip comparison circuit is configured using a NOR gate, a NAND gate, and a multiplexer. When a signal (ARH) indicating that the spare memory block 22 of any memory chip is selected is High, the chip comparison circuit identifies an individual slice address to actually access instead of a chip address requested from the outside. When a signal (ARH) selecting the spare memory block 22 of any memory chip is Low, the chip comparison circuit outputs a slice address SA requested from the outside.

[0040] The identification unit 60 is, for example, an electronic circuit. Based on the comparison result, the identification unit 60 identifies the memory unit 20 to actually access. The identification unit 60 also generates access timing for the identified memory unit 20. The identification unit 60 also sends the generated access timing to the timing control unit 80 (RWSC: R / W Slave Control). The identification unit 60 identifies the memory unit 20 to be accessed based on the output ORH signal, ARH signal, ASH signal, command, and memory address of the access request destination. The operation of the identification unit 60 can be classified as follows.

[0041] (i) When ORH=High When the ORH signal is High, the identification unit 60 identifies the spare memory block 22 of its own memory chip as the memory unit 20 to be accessed. Regardless of the output result of the OSH signal, the identification unit 60 identifies the spare memory block 22 of its own memory chip as the memory unit 20 to be accessed.

[0042] (ii) ORH (use of the spare memory block 22 of the own memory chip)=Low, ARH (use of the spare memory block 22 of another memory chip)=High When the ORH signal is Low and the ARH signal is High, the identifying unit 60 identifies that the spare memory block 22 of its own memory chip will not be used, and that the spare memory block 22 of another memory chip will be used. In this case, the identifying unit 60 identifies that its own memory chip will not be accessed. Regardless of the output result of the OSH signal, the identifying unit 60 identifies that the memory unit 20 of its own memory chip will not be used.

[0043] (iii) ORH=LOW, ARH=Low, OSH (use of own memory chip)=High ORH signal is Low, ARH signal is Low , and the OSH signal is High, the identifying unit 60 identifies the normal memory block 21 of its own memory chip as the memory unit 20 to be accessed. The identifying unit 60 identifies the memory address included in the request address as the memory address to be accessed.

[0044] (iv) When ORH=Low, ARH=Low, and OSH=Low ORH signal is Low, ARH signal is Low , and when the OSH signal is Low, the identifying unit 60 identifies that the memory unit 20 of its own memory chip is not used, and that the normal memory block 21 of another memory chip is used. In this case, the identifying unit 60 identifies that its own memory chip is not being accessed.

[0045] In the master slice 10, the identification unit 60 is configured to be able to transmit access timing to the slave slice 11 as well (RWMC: R / W Master Control). The identification unit 60 is configured to be able to transmit access timing to a timing control unit 80 of the master slice 10. In addition, the identification unit 60 executes read / write to the memory unit 20 in accordance with a read / write command from the outside.

[0046] The execution unit 70 is, for example, an electronic circuit. The execution unit 70 transmits and receives read / write data to and from the identified access destination address. The execution unit 70 also transmits and receives read / write data to and from an input / output circuit of the master slice 10. The execution unit 70, for example, acquires information on the access destination memory block identified by the identification unit 60, and accesses the acquired access destination memory block. The execution unit 70 is also configured to be able to transmit and receive read / write data to and from the input / output circuit of the master slice 10 (RWBS: R / W Bus).

[0047] The timing control unit 80 is, for example, an electronic circuit. The timing control unit 80 outputs a timing signal RWC (R / W Control) to control the execution timing of the execution unit 70. The timing control unit 80 obtains timing generated by another memory chip as the execution timing from the outside. The timing control unit 80 obtains, for example, a read / write command (RWMC: R / W Master Control in FIG. 1) output from the master slice 10 as the execution timing from the outside. The timing control unit 80 also receives, for example, an access timing specific to each slice (RWSC: R / W Slave Control in FIG. 1) output from the specification unit 60. The timing control unit 80 causes the execution unit 70 to transmit and receive read / write data at a predetermined (preselected) timing of either an instruction signal RWMC of execution timing from the outside or an instruction signal RWSC of execution timing output from its own specification unit 60. That is, the timing control unit 80 controls the timing so that the read / write is executed at the timing of receiving a signal from the predetermined side after specifying the access destination address. The timing control unit 80 controls the timing so that the read / write data is transmitted and received at the later signal reception timing. Also, the timing control unit 80 controls the transmission and reception of the read / write data by the execution unit 70 based on the slice address of the access destination output from the specification unit 60 of the master slice 10 as shown in FIG.

[0048] In the master slice 10, the execution unit 70 is connected to an input / output circuit (RWBS: R / W Bus). In addition, the timing control unit 80 is connected to the execution unit 70 (RWC: R / W Control). The input / output circuit is connected to the outside so as to be able to transmit and receive data (DQ).

[0049] Next, the operation of the stacked memory 1 of this embodiment will be described with reference to the flowchart of FIG. First, the comparing section 50 acquires a request address (step S1). Next, the comparing section 50 acquires a fuse address (step S2). Next, the comparing section 50 compares the request address with the fuse address (step S3).

[0050] The identifying unit 60 judges whether the access is to its own slice based on the comparison result (step S4). If the access is to its own slice (step S4: YES), the process proceeds to step S5. On the other hand, if the access is not to its own slice address (step S4: NO), the process proceeds to step S8.

[0051] In step S5, the identifying unit 60 identifies a memory address of a regular memory block or a memory address of a spare memory block. Next, the timing control unit 80 controls the access timing to the identified memory address (step S6). Next, the execution unit 70 executes transmission and reception of read / write data to the identified memory address at the controlled access timing, and transmission and reception of read / write data to and from the input / output circuit of the master slice 10 (step S7). This ends the processing according to this flow.

[0052] In step S8, read / write is executed in the other memory chips, and the process of this flow ends.

[0053] Next, a method for manufacturing the stacked memory 1 will be described. The stacked memory 1 undergoes a simple test in the wafer state to determine the wafers to be used for the stacked memory 1. After that, wiring patterns are formed on each wafer to identify the master chip and slice addresses, or programming is performed using fuse elements or the like. After that, a repair determination is performed for the regular blocks and spare blocks in the slice. If further repair is necessary, a repair determination is performed between slices. Specifically, the method for manufacturing the stacked memory 1 includes a wafer testing step, a wiring layer forming step or a programming step using fuses or the like, a stacking step, a replacement step, and a singulation step.

[0054] In the wafer testing process, a simple test is performed on the single-layer wafer. In the wafer testing process, for example, a test for checking for large current defects is performed. In the wafer testing process, wafers with a high defect rate are removed.

[0055] In the wiring layer forming process or the programming process, among all the semiconductor wafers to be stacked, a semiconductor wafer constituting a master chip capable of sending an access request and a timing signal to other stacked memory chips is determined. In the wiring layer forming process or the programming process, among the semiconductor wafers to be stacked, a wafer to be a master chip is determined by making a wiring mask layer different for the master chip. Also, in the wiring layer forming process or the programming process, slice addresses are determined for all the semiconductor wafers to be stacked.

[0056] In the stacking process, semiconductor wafers including a plurality of memory chips are stacked. In the stacking process, for example, a wafer including a master chip and a wafer including a slave chip are stacked.

[0057] In the replacement process, defective memory cells in normal memory blocks 21 included in the stacked semiconductor wafers are replaced with memory cells in spare memory blocks 22. In the replacement process, a wafer test is performed to detect defective memory cells in normal memory blocks 21 in a chip. In the replacement process, the defective memory cells are replaced with spare memory cells in the same chip, for example. In addition, in the replacement process, if replacement with spare memory cells in the same chip is not possible, the defective memory cells are replaced with spare memory cells in other stacked memory chips. Then, in the replacement process, replacement source addresses are stored in address storage units 30 of all stacked chips.

[0058] The singulation fixation is performed after the replacement process. In the singulation process, the stacked memory chips are singulated. In the singulation process, the singulated stacked memory 1 is tested. In the singulation process, if a defective memory cell is detected in the normal memory block 21, it is determined whether or not it can be replaced with a spare memory cell in the stacked chip. In the singulation process, if replacement is possible, the address storage unit 30 stores the replacement source address. On the other hand, in the singulation process, if replacement is not possible, the stacked memory 1 is determined to be defective. In the singulation process, if no defective memory cell is detected and if replacement is possible, the stacked memory 1 is determined to be a non-defective product.

[0059] The stacked memory 1 and the manufacturing method thereof according to the above embodiment provide the following advantages.

[0060] (1) A stacked memory 1 in which a plurality of memory chips are stacked, the memory chip includes a memory section 20 including a plurality of memory cells and capable of storing data, the memory section 20 including a regular memory block 21 used mainly in reading and writing data and a spare memory block 22 replacing a defective memory cell of the regular memory block 21, an address storage section 30 storing a slice address for identifying a memory chip to be replaced with the spare memory block 22 as a replacement source slice address for the two or more stacked memory chips, and storing a memory address to be replaced as a replacement source memory address, a comparison section 50 comparing a request address indicating the slice address and memory address of an access request destination with the replacement source slice address and the replacement source memory address, a specification section 60 specifying the memory section 20 to be actually accessed based on the comparison result and generating an access timing, a timing control section 80 selecting either the generated access timing or an access timing transmitted from another memory chip, and controlling access to the memory section 20 at the selected access timing, and an execution section 70 executing read / write at the selected access timing for the specified memory section 20. This can improve the yield. Moreover, by selecting the access timing, it is possible to control the operation timing appropriately.

[0061] (2) A stacked memory 1 in which multiple memory chips are stacked, each of the memory chips includes a memory section 20 including multiple memory cells and capable of storing data, a specification section 60 that generates an access timing to the memory section 20, a timing control section 80 that selects either the generated access timing or an access timing transmitted from another memory chip and controls access at the selected access timing, and an execution section 70 that executes read / write at the selected access timing. This makes it possible to select a timing suitable for reading and writing from and to the memory chips, thereby improving flexibility.

[0062] (3) A stacked memory 1 in which a plurality of memory chips are stacked, each of the memory chips includes a memory section 20 including a plurality of memory cells and capable of storing data, the memory section 20 including a regular memory block 21 used mainly in reading and writing data and a spare memory block 22 replacing a defective memory cell of the regular memory block 21, an address storage section 30 storing a slice address for identifying a memory chip to be replaced with the spare memory block 22 for replacing the regular memory block 21 as a replacement source slice address for all stacked memory chips, and storing a memory address to be replaced as a replacement source memory address, a comparison section 50 comparing a request address indicating the slice address and memory address of an access request destination with the replacement source slice address and the replacement source memory address, an identification section 60 identifying the memory section 20 to be actually accessed based on the comparison result, and an execution section 70 executing a read / write to the identified memory section 20. This allows a defective memory cell of the regular memory block 21 to be replaced with a spare memory block 22 of any of the plurality of memory chips. This improves the yield of the stacked memory 1.

[0063] (4) The timing control unit 80 identifies the slice to be accessed based on the slice address of the slice to be accessed output from another memory chip. This makes it possible to easily identify the slice to be accessed based on a command from another memory block.

[0064] (5) The timing control unit 80 obtains timing generated by other memory chips as instructions on execution timing from the outside, thereby improving the flexibility of memory access according to the characteristics of the memory.

[0065] (6) Comparator 50 outputs a signal indicating whether normal memory block 21 or spare memory block 22 of its own memory chip is to be used as a comparison result. This allows each memory chip to determine whether to use memory unit 20. Therefore, the number of communication paths between memory chips can be reduced.

[0066] The memory chip further includes a chip identification information storage unit 40 that stores an individual slice address, which is a slice address that identifies the memory chip itself, as chip identification information, and the comparison unit 50 includes a chip comparison unit 52 that compares whether the individual slice address matches a slice address included in a request address, and an address comparison unit 51 that compares whether the request address matches an alternative source address, and the specification unit 60 specifies the access destination address based on the comparison result. This makes it easy to determine whether the access is to the memory chip itself.

[0067] The normal memory block 21 and the spare memory block 22 each have a redundant memory cell capable of replacing a defective memory cell of the normal memory block 21 and the spare memory block 22. This allows the redundant memory block to be used before the spare memory block 22 is used when the number of defective memory cells is small. This further improves the yield of the stacked memory 1.

[0068] Although a preferred embodiment of the stacked memory 1 and the manufacturing method thereof according to the present invention has been described above, the present invention is not limited to the above-mentioned embodiment and can be modified as appropriate.

[0069] For example, in the above embodiment, the master chip and the slave chip are determined in the wiring layer forming step, but the present invention is not limited to this. Instead of the wiring mask forming step, a master chip determination step may be provided after the stacking step and before the replacement step, in which a semiconductor wafer constituting a master chip capable of sending command signals and timing signals to other memory chips to be stacked is determined from among all the semiconductor wafers to be stacked.

[0070] In the above embodiment, the other wafer chip is, for example, a master chip. The master chip may control access with the access destination address and timing generated by its own specification unit 60 and timing control unit 80 without acquiring the timing and access destination address from the slave chip. [Explanation of symbols]

[0071] 1. Stacked Memory 20 Memory section 21 Regular Memory Blocks 22 Reserve Memory Blocks 30 Address storage section 40 Chip identification information storage section 50 Comparison section 51 Address comparison section 52 Chip comparison section 60 Specific section 70 Executive Department 80 Timing control section

Claims

1. A stacked memory in which a plurality of memory chips are stacked, The memory chip includes: a memory section including a plurality of memory cells and capable of storing data, the memory section having a normal memory block mainly used in reading and writing data and a spare memory block for substituting a defective memory cell of the normal memory block; an address storage unit that stores, as a source slice address, a slice address for identifying a memory chip that is to be substituted for the normal memory block by the spare memory block with respect to two or more stacked memory chips, and stores, as a source memory address, a memory address that is to be substituted; a comparison unit that compares a request address indicating the slice address and the memory address of an access request destination with the substitution source slice address and the substitution source memory address; a specification unit that specifies the memory unit to be actually accessed based on a comparison result and generates an access timing; a timing control unit that selects either the generated access timing or an access timing transmitted from another memory chip, and controls access to the memory unit at the selected access timing; an execution unit that executes a read / write operation on the specified memory unit at a selected access timing; A stacked memory comprising:

2. A stacked memory in which a plurality of memory chips are stacked, one of the plurality of memory chips is a master slice that includes an input / output circuit capable of transmitting / receiving input / output signals to / from an external device and transmits access timing indicating read / write timing to another of the plurality of memory chips; Each of the other memory chips among the plurality of memory chips is A memory section including a plurality of memory cells and capable of storing data; a specifying unit that generates an access timing to the memory unit; a timing control unit that selects either the access timing generated by the specifying unit or the access timing transmitted from the master slice; an execution unit that executes transmission and reception of read / write data to the memory unit and transmission and reception of read / write data to the input / output circuit of the master slice at the selected access timing; A stacked memory comprising:

3. A stacked memory in which a plurality of memory chips are stacked, Each of the memory chips comprises: a memory section including a plurality of memory cells and capable of storing data, the memory section having a normal memory block mainly used in reading and writing data and a spare memory block for substituting a defective memory cell of the normal memory block; an address storage unit that stores, for all of the stacked memory chips, slice addresses that identify the memory chips whose normal memory blocks are to be replaced by the spare memory blocks as replacement slice addresses and stores the memory addresses that are to be replaced as replacement memory addresses; a comparison unit that compares a request address indicating the slice address and the memory address of an access request destination with the substitution source slice address and the substitution source memory address; a determining unit that determines the memory unit to actually be accessed based on a result of the comparison; an execution unit that executes read / write to the specified memory unit; A stacked memory comprising:

4. The stacked memory according to claim 1 , wherein the timing control section identifies the slice to be accessed based on a slice address of the slice to be accessed output from another of the memory chips.

5. 2 . The stacked memory according to claim 1 , wherein the timing control section acquires timing generated by another of the memory chips as an instruction of execution timing from outside.

6. 4. The stacked memory according to claim 1, wherein the comparison section outputs, as a comparison result, a signal indicating whether the normal memory block or the spare memory block of the memory chip itself is to be used.

7. the memory chip further includes a chip identification information storage unit that stores an individual slice address, which is a slice address for identifying the memory chip itself, as chip identification information; The comparison unit is a chip comparator that compares whether the individual slice address matches a slice address included in the request address; an address comparison unit that compares whether the request address matches the replacement source slice address and the replacement source memory address; Equipped with The stacked memory according to claim 1 , wherein the specifying unit specifies the memory unit to actually be accessed based on a result of the comparison.

8. 4. The stacked memory according to claim 1, wherein the normal memory block and the spare memory block each have a redundant memory cell capable of replacing a defective memory cell of the normal memory block and the spare memory block.

9. A method for manufacturing a stacked memory according to claim 1 or 3, comprising the steps of: a stacking step of stacking semiconductor wafers including a plurality of the memory chips; a replacement step of replacing defective memory cells of the normal memory blocks included in the stacked semiconductor wafers with memory cells of the spare memory blocks; a singulation step of singulating the stacked memory chips after the replacement step; A method for manufacturing a stacked memory comprising:

10. 10. The method for manufacturing a stacked memory according to claim 9, further comprising, before the stacking step, a wiring layer formation step of determining, using a wiring layer, which semiconductor wafer, among all the semiconductor wafers to be stacked, constitutes a master chip capable of sending an access request and a timing signal to the other memory chips to be stacked.

11. 10. The method for manufacturing a stacked memory according to claim 9, further comprising a master chip determination step of determining, after the stacking step and before the replacement step, a semiconductor wafer constituting a master chip capable of sending command signals and timing signals to other memory chips to be stacked, among all the semiconductor wafers to be stacked.

Images