Semiconductor Device

Abstract

Provided is a semiconductor device having a novel configuration. The semiconductor device comprises an accelerator. The accelerator has a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit has a first transistor. The second memory circuit has a second transistor. The first transistor and second transistor each have a semiconductor layer having a metal oxide in a channel forming region. The arithmetic circuit has a third transistor. The third transistor has a semiconductor layer having silicon in a channel forming region. The first transistor and second transistor are provided in different layers. The layer having the first transistor is provided above the layer having the third transistor. The layer having the second transistor is provided above the layer having the first transistor. The first memory circuit has data retention characteristics that are different from those of the second memory circuit.

Description

[Technical field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like are in widespread use. In order to process a large amount of data at high speed in such electronic devices, there has been active technological development to improve the performance of the semiconductor devices. One technology that achieves high performance is, for example, the so-called SoC (System on Chip) in which an accelerator such as a GPU (Graphics Processing Unit) is tightly coupled with a CPU. In a semiconductor device with high performance due to the SoC, heat generation and increased power consumption become problems.

[0004] In AI (Artificial Intelligence) technology, the amount of calculations and the number of parameters are enormous, so the amount of calculations increases. Since the increase in the amount of calculations causes an increase in heat generation and power consumption, architectures for reducing the amount of calculations have been actively proposed. Representative architectures include Binary Neural Network (BNN) and Ternary Neural Network (TNN), which are particularly effective for reducing circuit size and power consumption (see, for example, Patent Document 1). For example, in BNN, data originally expressed with 32-bit or 16-bit precision is compressed into two values, "+1" or "-1," which can significantly reduce the amount of calculations and the number of parameters. Since BNN is effective for reducing circuit size and power consumption, it is considered to be compatible with applications that require low power consumption with limited hardware resources, such as embedded chips. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 078924 Summary of the Invention [Problem to be solved by the invention]

[0006] When performing AI technology calculations using an accelerator, the weight data used in the calculations is transmitted to the accelerator at high speed from chips such as DRAM and SRAM, which are manufactured in a process separate from the accelerator. In order to reduce the frequency of data transfers, the accelerator requires a large memory capacity to hold the weight data or intermediate data. If the accelerator has a small memory capacity, high-speed data transmission is required. Furthermore, if the accelerator is far from the chip that stores the weight data, the parasitic capacitance or resistance of the wiring increases, which may result in high power consumption.

[0007] An object of one embodiment of the present invention is to reduce power consumption in a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to suppress heat generation in a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to reduce the size of a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to reduce the number of data transfers between a CPU and a semiconductor device functioning as a memory in a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to improve the data transfer rate between a storage memory and a semiconductor device functioning as a cache memory in a semiconductor device including an accelerator. Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure.

[0008] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but only needs to solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including a CPU and an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. The first transistor and the second transistor each include a semiconductor layer having a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer having silicon in a channel formation region. The CPU includes a CPU core having a flip-flop provided with a backup circuit. The backup circuit includes a fourth transistor. The fourth transistor includes a semiconductor layer having a metal oxide in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer having the first transistor and the layer having the second transistor are provided over a layer having the third transistor.

[0010] In one embodiment of the present invention, the backup circuit preferably has a function of retaining data retained in the flip-flop in a state where the supply of the power supply voltage is stopped during power gating of the CPU.

[0011] In one aspect of the present invention, the first memory circuit and the second memory circuit preferably have a function of holding data to be input to the arithmetic circuit.

[0012] In one aspect of the present invention, the second memory circuit preferably has a different circuit configuration from the first memory circuit.

[0013] One embodiment of the present invention is a semiconductor device including a CPU and an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. The first transistor and the second transistor each include a semiconductor layer having a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer having silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer having the first transistor is provided over a layer having the third transistor. The layer having the second transistor is provided over a layer having the first transistor. The first memory circuit has data retention characteristics different from those of the second memory circuit.

[0014] In one embodiment of the present invention, the first memory circuit is preferably a semiconductor device having a function of holding data input to an arithmetic circuit or data output from the arithmetic circuit.

[0015] In one aspect of the present invention, the amplitude voltage for driving the first transistor is preferably smaller than the amplitude voltage for driving the second transistor.

[0016] In one aspect of the present invention, the thickness of the gate insulating film of the first transistor is preferably smaller than the thickness of the gate insulating film of the second transistor.

[0017] In one aspect of the present invention, the second memory circuit preferably has a different circuit configuration from the first memory circuit.

[0018] In one aspect of the present invention, the arithmetic circuit is preferably a circuit that performs a product-sum operation.

[0019] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0020] Other aspects of the present invention will be described in the following embodiment and in the drawings. Effect of the Invention

[0021] One embodiment of the present invention can reduce power consumption in a semiconductor device including an accelerator. Alternatively, one embodiment of the present invention can suppress heat generation in a semiconductor device including an accelerator. Alternatively, one embodiment of the present invention can reduce the size of a semiconductor device including an accelerator. Alternatively, one embodiment of the present invention can reduce the number of data transfers between a CPU and a semiconductor device functioning as a memory in a semiconductor device including an accelerator. Alternatively, one embodiment of the present invention can improve the data transfer rate between a storage memory and a semiconductor device functioning as a cache memory in a semiconductor device including an accelerator. Alternatively, a semiconductor device having a novel structure can be provided.

[0022] The description of multiple effects does not preclude the existence of other effects. In addition, one embodiment of the present invention does not necessarily have all of the exemplified effects. In addition, problems, effects, and novel features other than those described above regarding one embodiment of the present invention will become apparent from the description and drawings in this specification. [Brief description of the drawings]

[0023] 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. 2A and 2B are diagrams illustrating a configuration example of a semiconductor device. 3A and 3B are diagrams illustrating a configuration example of a semiconductor device. 4A and 4B are diagrams illustrating a configuration example of a semiconductor device. 5A to 5E are diagrams for explaining configuration examples of a semiconductor device. 6A and 6B are diagrams illustrating a configuration example of a semiconductor device. 7A and 7B are diagrams showing various types of memories by hierarchy. 8A to 8C are diagrams illustrating configuration examples of a semiconductor device. 9A to 9C are diagrams illustrating a configuration example of a semiconductor device. FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. 12A and 12B are diagrams illustrating a configuration example of a semiconductor device. FIG. 13 is a diagram illustrating a configuration example of a semiconductor device. 14A and 14B are diagrams illustrating a configuration example of a semiconductor device. 15A and 15B are diagrams illustrating a configuration example of a semiconductor device. FIG. 16 is a diagram illustrating a configuration example of a semiconductor device. FIG. 17 is a diagram illustrating an example of the configuration of a CPU. 18A and 18B are diagrams for explaining an example of the configuration of a CPU. FIG. 19 is a diagram illustrating an example of the configuration of a CPU. 20A and 20B are a top view and a cross-sectional view of a memory device according to one embodiment of the present invention. 21A and 21B are a top view and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 22 is a top view of a memory device according to one embodiment of the present invention. FIG. 23 is a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 24 is a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 25 is a cross-sectional view of a memory device according to one embodiment of the present invention. Fig. 26A is a diagram for explaining the classification of IGZO crystal structures, Fig. 26B is a diagram for explaining the XRD spectrum of silica glass, and Fig. 26C is a diagram for explaining the XRD spectrum of crystalline IGZO. FIG. 27 is a diagram for explaining a configuration example of an integrated circuit. 28A and 28B are diagrams for explaining a configuration example of an integrated circuit. 29A and 29B are diagrams for explaining an application example of an integrated circuit. 30A and 30B are diagrams for explaining an application example of an integrated circuit. 31A to 31C are diagrams for explaining an application example of an integrated circuit. FIG. 32 is a diagram for explaining an application example of an integrated circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the embodiment and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0025] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0026] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0027] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0028] Furthermore, when the same reference symbol is used for multiple elements, particularly when it is necessary to distinguish between them, identification symbols such as “_1”, “_2”, "[n]”, "[m,n]”, etc. may be added to the reference symbol. For example, the second wiring GL is written as wiring GL[2].

[0029] (Embodiment 1) The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0030] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0031] 1A and 1B are diagrams illustrating a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes a CPU 10, an accelerator 20, and a bus 30. The accelerator 20 includes an arithmetic processing unit 21 and a memory unit 22. The arithmetic processing unit 21 includes an arithmetic circuit 23. The memory unit 22 includes a memory circuit 24. The memory unit 22 may be referred to as a device memory or a shared memory. The memory circuit 24 includes a transistor 25 including a semiconductor layer 29 having a channel formation region. The arithmetic circuit 23 and the memory circuit 24 are electrically connected to each other via a wiring 31.

[0032] The CPU 10 has a function of performing general-purpose processing such as executing an operating system, controlling data, and executing various calculations and programs. The CPU 10 has one or more CPU cores. The CPU 10 has, for example, transistors (Si transistors) having silicon in their channel formation regions. The Si transistors can be made into complementary transistors to form a CMOS circuit (SiCMOS). The CPU 10 is connected to the accelerator 20 via a bus 30.

[0033] Each CPU core is preferably configured to have a data retention circuit capable of retaining data even when the supply of power supply voltage is stopped. With this configuration, the supply of power supply voltage can be controlled by electrically disconnecting it from the power supply domain (power domain) using a power switch or the like. The power supply voltage may also be called a drive voltage. As the data retention circuit, for example, a memory having a transistor (OS transistor) having an oxide semiconductor in a channel formation region is suitable. The configuration of a CPU core including a data retention circuit having an OS transistor will be described in the third embodiment.

[0034] The accelerator 20 has a function of executing a program (also called a kernel or a kernel program) called from a host program. The accelerator 20 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0035] The memory unit 22 has a function of storing data to be processed by the accelerator 20. Specifically, the memory unit 22 can store data to be input to or output from the arithmetic processing unit 21, such as weight data used in parallel processing of product-sum operations of a neural network.

[0036] The memory unit 22 is provided across multiple memory circuit layers 22_1 to 22_N (N is a natural number of 2 or more). Each of the multiple memory circuit layers 22_1 to 22_N has a memory circuit 24. The memory circuit 24 in each of the multiple memory circuit layers 22_1 to 22_N is electrically connected to an arithmetic circuit 23 in the arithmetic processing unit 21 via wiring 31 and has a function of holding a binary or ternary digital value. In the memory circuit 24, a semiconductor layer 29 in the transistor 25 is an oxide semiconductor. That is, the transistor 25 is an OS transistor. The memory circuit 24 is preferably a memory having an OS transistor (hereinafter also referred to as an OS memory).

[0037] Since the band gap of metal oxide is 2.5 eV or more, OS transistors have extremely small off-state current. For example, when the voltage between the source and drain is 3.5 V and the temperature is at room temperature (25 °C), the off-state current per 1 μm of channel width is 1 × 10 -20 Less than A, 1×10 -22 Less than A or 1×10 -24 A or less. That is, the on / off current ratio of the drain current can be set to 20 to 150 digits. Therefore, the amount of charge leaked from the retention node via the OS transistor in the OS memory is extremely small. Therefore, the OS memory can function as a non-volatile memory circuit. Also, power gating of the accelerator becomes possible.

[0038] High-density integrated semiconductor devices may generate heat due to the operation of the circuits. This heat increases the temperature of the transistor, which may change the characteristics of the transistor, causing a change in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so that the field-effect mobility is less likely to change due to temperature changes and the operating frequency is less likely to decrease. Furthermore, OS transistors tend to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage, even when the temperature rises. Therefore, the use of OS transistors allows stable operation in high temperature environments.

[0039] Metal oxides applicable to OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In particular, metal oxides using Ga as M are preferably used for OS transistors because they can be made into transistors with excellent electrical characteristics such as field effect mobility by adjusting the ratio of elements. In addition, the oxide containing indium and zinc may contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0040] In order to improve the reliability and electrical characteristics of the OS transistor, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystalline part, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0041] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0042] CAC-OS has the function of flowing electrons (or holes) that act as carriers, and the function of not flowing electrons that act as carriers. By separating the function of flowing electrons from the function of not flowing electrons, it is possible to maximize both functions. In other words, by using CAC-OS in the channel formation region of an OS transistor, it is possible to achieve both a high on-current and an extremely low off-current.

[0043] Metal oxides have a large band gap, electrons are less likely to be excited, and the effective mass of holes is large, so that OS transistors are less likely to experience avalanche breakdown and the like compared to general Si transistors. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. Suppressing hot carrier degradation allows OS transistors to be driven at a high drain voltage.

[0044] OS transistors are accumulation-type transistors that use electrons as majority carriers. Therefore, they are less susceptible to drain-induced barrier lowering (DIBL), which is one of the short-channel effects, compared to inversion-type transistors (typically, Si transistors) that have a pn junction. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0045] Because OS transistors have high resistance to short channel effects, their channel length can be reduced without degrading their reliability, and so their use can increase the degree of circuit integration. As the channel length is reduced, the drain electric field becomes stronger, but as mentioned above, OS transistors are less susceptible to avalanche breakdown than Si transistors.

[0046] In addition, because OS transistors have high resistance to short channel effects, it is possible to make the gate insulating film thicker than that of Si transistors. For example, even in a minute transistor with a channel length and width of 50 nm or less, it may be possible to provide a thick gate insulating film of about 10 nm. By making the gate insulating film thicker, the parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. Furthermore, by making the gate insulating film thicker, the leakage current through the gate insulating film is reduced, which leads to a reduction in static current consumption.

[0047] As described above, the accelerator 20 can retain data even when the supply of power supply voltage is stopped by having the memory circuit 24, which is an OS memory. This enables power gating of the accelerator 20, and allows a significant reduction in power consumption.

[0048] The memory circuit 24, which is made up of OS transistors, can be stacked with the arithmetic circuit 23, which can be made up of Si CMOS. That is, the memory circuit layers 22_1 to 22_N are provided on a substrate on which the arithmetic processing unit 21 is provided. The memory circuit layers 22_1 to 22_N can be stacked. Therefore, they can be arranged without increasing the circuit area, and the memory capacity required for the arithmetic processing in the accelerator 20 can be increased. The number of times data required for the arithmetic processing can be transferred can be reduced, so that low power consumption can be achieved. The memory circuit layers 22_1 to 22_N, which have the memory circuits 24, are electrically connected to the arithmetic circuit 23 via wiring 31 that is provided so as to extend in a direction substantially perpendicular to the surface of the substrate on which the arithmetic circuit 23 is provided (z direction perpendicular to the xy plane in FIG. 1B). Note that "substantially perpendicular" refers to a state in which they are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0049] Note that, although an OS transistor is exemplified as a transistor included in the memory circuit 24, any transistor that can be stacked with a Si transistor included in the lower arithmetic circuit 23 may be used. For example, a Si transistor stacked on a substrate having a Si transistor by using a bonding technique or the like may be used as the upper transistor. In this case, it is preferable that the Si transistor provided in the upper layer has a longer channel length than the Si transistor in the lower layer so that the transistor has a small off-current.

[0050] The memory circuit 24 of the accelerator 20 may be a single layer, or may be a stacked structure such as multiple memory circuit layers 22_1 to 22_N. The single layer memory circuit layer 22_1 having an OS transistor can be stacked with the arithmetic circuit 23 that can be composed of Si CMOS. Therefore, by shortening the physical distance between the arithmetic circuit 23 and the memory circuit 24, the wiring distance can be shortened, and the parasitic capacitance generated in the signal line can be reduced, resulting in low power consumption.

[0051] In the accelerator 20, by adopting a stacked transistor configuration, it is possible to suppress an increase in the circuit area, and therefore it is possible to increase and arrange the number of arithmetic circuits 23. Since it is possible to increase the number of circuits (number of cores) that perform arithmetic in the arithmetic circuit 23, it is possible to lower the frequency of the signal for driving the arithmetic circuit 23. In addition, it is possible to reduce the power supply voltage for driving the arithmetic circuit 23. As a result, it is possible to reduce the power consumption required for arithmetic by a ratio of several tens of times.

[0052] The memory circuit 24 may have a NOSRAM circuit configuration. "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM." NOSRAM refers to a memory in which the memory cell is a two-transistor type (2T) or three-transistor type (3T) gain cell, and the access transistor is an OS transistor. The memory circuit 24 may be provided by stacking the memory circuit layers 22_1 to 22_N using OS transistors. In addition, the current flowing between the source and drain in the off state, that is, the leakage current, is extremely small. NOSRAM can be used as a nonvolatile memory by retaining a charge corresponding to data in the memory circuit using the characteristic of extremely small leakage current. In particular, NOSRAM can read out the retained data without destroying it (nondestructive readout), and is therefore suitable for parallel processing of product-sum operations in neural networks, which repeats a large amount of data readout operations alone.

[0053] The arithmetic processing unit 21 has a function of performing arithmetic processing using digital values. Digital values ​​are not easily affected by noise. Therefore, the accelerator 20 is suitable for performing arithmetic processing that requires highly accurate arithmetic results. The arithmetic processing unit 21 is preferably configured with a Si CMOS, that is, a transistor having silicon in a channel formation region (Si transistor). With this configuration, it can be stacked with an OS transistor.

[0054] The arithmetic circuit 23 has a function of performing any one of processes such as integer arithmetic, single-precision floating-point arithmetic, and double-precision floating-point arithmetic using digital value data held in each of the memory circuits 24 of the multiple memory circuit layers 22_1 to 22_N. The arithmetic circuit 23 has a function of repeatedly executing the same process such as a multiply-add operation.

[0055] The arithmetic circuit 23 is configured to be provided for each read bit line of the memory circuit 24, that is, for each column (column-parallel calculation). This configuration allows data for one row (maximum all bit lines) of the memory circuit 24 to be arithmetically processed in parallel. Compared with the multiply-and-accumulate operation using the CPU 10, the column-parallel calculation is not limited by the data bus size (32 bits, etc.) between the CPU and the memory, so that the degree of parallelism of the operation can be significantly increased, and the efficiency of calculations related to massive calculation processing such as learning (deep learning) of deep neural networks, which is an AI technology, and scientific and technological calculations that perform floating-point calculations can be improved. In addition, since the calculation of data output from the memory circuit 24 can be completed and read out, the power generated by memory access (data transfer between the CPU and memory and calculations by the CPU) can be reduced, and the increase in heat generation and power consumption can be suppressed. Furthermore, by shortening the physical distance between the arithmetic circuit 23 and the memory circuit 24, for example, by shortening the wiring distance by stacking, the parasitic capacitance generated in the signal line can be reduced, and therefore low power consumption is possible.

[0056] The sum-of-products operation in the inference process requires a large amount of data, and therefore a huge bandwidth (data transfer rate) is required. As shown in the configuration of FIG. 1B, a wide bandwidth can be secured by arranging multiple memory circuit layers 22_1 to 22_N on the arithmetic circuit 23. In addition, the distance between the circuits can be reduced, so the transfer speed of multiple data can be increased. Therefore, the power consumption required for the sum-of-products operation in the inference process can be reduced by a factor of several tens of times.

[0057] Inference processing based on deep neural networks is optimized for data with a bit length of preferably 32 bits or less, more preferably 16 bits or less, and even more preferably 8 bits or less, rather than calculations using data with a large bit length such as 64 bits, thereby enabling low power consumption without reducing calculation accuracy.

[0058] The bus 30 electrically connects the CPU 10 and the accelerator 20. That is, the CPU 10 and the accelerator 20 can transmit data via the bus 30.

[0059] 2A is a schematic diagram illustrating reading of data from the memory circuits 24 of the stacked memory circuit layers 22_1 to 22_N to the arithmetic circuit 23 in the accelerator 20 illustrated in FIG. 1B. In FIG. 2A, arrows indicate the movement of data. As illustrated in FIG. 2A, the semiconductor device of one embodiment of the present invention can read data from the memory circuits 24 included in the stacked memory circuit layers 22_1 to 22_N via wirings 31. The physical distance between the arithmetic circuit 23 and the memory circuit 24, which are stacked in position, is very short, and therefore the wiring distance is short. Therefore, parasitic capacitance generated in the wiring 31 can be reduced, leading to low power consumption.

[0060] As the number of stacked memory circuit layers 22_1 to 22_N increases, the parasitic capacitance generated in the wiring 31 increases. Therefore, it is preferable to provide switches SW_1 to SW_N in each of the memory circuit layers 22_1 to 22_N between the wiring 31 and the wiring to which the memory circuit 24 is connected, for example, a read bit line. The switches SW_1 to SW_N are controlled to be turned off in the memory circuit layers 22_1 to 22_N from which data is not read, and turned on in the memory circuit layers 22_1 to 22_N from which data is read. This configuration can reduce the parasitic capacitance of the wiring 31 caused by increasing the number of memory circuit layers 22_1 to 22_N, thereby achieving low power consumption.

[0061] Further, the number of memory circuits 24 may be varied by varying the circuit layout, the channel length, the channel width, or the density of the transistors in each of the stacked memory circuit layers 22_1 to 22_N. For example, as shown in FIG. 3A, the memory circuits 24 in the lower layers (e.g., the memory circuit layer 22_1) of the memory circuit layers 22_1 to 22_N may have a circuit layout in which the transistor density is high, and the transistor density decreases toward the upper layers (z direction in the figure). With this configuration, it is possible to increase the number of memory circuits that are physically close to the arithmetic circuit 23, and to improve the data retention characteristics of the memory circuits 24 in the upper layers.

[0062] 3B, the memory circuits 24 in the upper layers (e.g., the memory circuit layer 22_N) of the memory circuit layers 22_1 to 22_N may have a circuit layout in which the transistor density is high, and the transistor density is decreased toward the lower layers (the memory circuit layer 22_1 side in the figure). By adopting such a configuration, the data retention characteristics of the memory circuits that are physically close to the arithmetic circuit 23 can be improved, and the data density can be increased.

[0063] One embodiment of the present invention can reduce the power consumption of a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters. Alternatively, one embodiment of the present invention can reduce the size of a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters. Alternatively, one embodiment of the present invention can suppress heat generation in a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters. Alternatively, one embodiment of the present invention can reduce the number of data transfers between a CPU and a semiconductor device that functions as a memory in a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters. In other words, a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters, has a non-von Neumann architecture, and can perform parallel processing with extremely low power consumption compared to a von Neumann architecture in which power consumption increases as the processing speed increases.

[0064] Fig. 4A is a diagram for explaining an example of a circuit configuration applicable to each of memory circuit layers 22_1 to 22_N of the semiconductor device 100 of the present invention. Fig. 4A illustrates write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and read bit lines RBL_1 to RBL_N arranged in a matrix direction of M rows and N columns (M and N are natural numbers of 2 or more). Also illustrated is a memory circuit 24 connected to each word line and bit line.

[0065] 4B is a diagram illustrating an example of a circuit configuration applicable to the memory circuit 24. The memory circuit 24 includes a transistor 25, a transistor 26, a transistor 27, and a capacitor 28 (also referred to as a capacitor).

[0066] One of the source or drain of the transistor 25 is connected to the write bit line WBL. The gate of the transistor 25 is connected to the write word line WWL. The other of the source or drain of the transistor 25 is connected to one electrode of the capacitance element 28 and the gate of the transistor 26. One of the source or drain of the transistor 26 and the other electrode of the capacitance element 28 are connected to a wiring that provides a fixed potential, such as a ground potential. The other of the source or drain of the transistor 26 is connected to one of the source or drain of the transistor 27. The gate of the transistor 27 is connected to the read word line RWL. The other of the source or drain of the transistor 27 is connected to the read bit line RBL. As described above, the read bit line RBL is connected to the arithmetic circuit 23 via the wiring 31 or the like that is provided extending in a direction approximately perpendicular to the substrate surface on which the arithmetic circuit 23 is provided.

[0067] The circuit configuration of the memory circuit 24 shown in FIG. 4B corresponds to a NOSRAM of a three-transistor type (3T) gain cell. Transistors 25 to 27 are OS transistors. In the off state, the current flowing between the source and drain of an OS transistor, that is, the leakage current, is extremely small. NOSRAM can be used as a non-volatile memory by using the characteristic of extremely small leakage current to hold charges corresponding to data in the memory circuit.

[0068] The circuit configuration applicable to the memory circuit 24 in FIG. 4A is not limited to the 3T type NOSRAM in FIG. 4B. For example, a circuit equivalent to the DOSRAM illustrated in FIG. 5A may be used. Note that DOSRAM is a RAM having 1T1C type memory cells, and is an abbreviation of Dynamic Oxide Semiconductor RAM. FIG. 5A illustrates a memory circuit 24A having a transistor 25A and a capacitance element 28A. The transistor 25A is an OS transistor. The memory circuit 24A is illustrated as an example connected to a bit line BL, a word line WL, and a back gate line BGL.

[0069] The circuit configuration applicable to the memory circuit 24 of FIG. 4A may be a circuit corresponding to a 2T-type NOSRAM illustrated in FIG. 5B. FIG. 5B illustrates a memory circuit 24B having a transistor 25B, a transistor 26B, and a capacitance element 28B. The transistors 25B and 26B are OS transistors. The transistors 25B and 26B may be OS transistors having semiconductor layers arranged in different layers, or may be OS transistors having semiconductor layers arranged in the same layer. The memory circuit 24B is illustrated as an example connected to a write bit line WBL, a read bit line RBL, a write word line WWL, a read word line RWL, a source line SL, and a back gate line BGL.

[0070] The circuit configuration applicable to the memory circuit 24 of FIG. 4A may be a circuit combining 3T-type NOSRAMs shown in FIG. 5C. FIG. 5B illustrates a memory circuit 24C having a memory circuit 24_P and a memory circuit 24_N that can hold data with different logic. FIG. 5B illustrates a memory circuit 24_P having a transistor 25_P, a transistor 26_P, a transistor 27_P, and a capacitive element 28_P, and a memory circuit 24_N having a transistor 25_N, a transistor 26_N, a transistor 27_N, and a capacitive element 28_N. Each transistor in the memory circuit 24_P and the memory circuit 24_N is an OS transistor. Each transistor in the memory circuit 24_P and the memory circuit 24_N may be an OS transistor having a semiconductor layer arranged in different layers, or may be an OS transistor having a semiconductor layer arranged in the same layer. The memory circuit 24C is illustrated as being connected to a write bit line WBL_P, a read bit line RBL_P, a write bit line WBL_N, a read bit line RBL_N, a write word line WWL, and a read word line RWL. The memory circuit 24C holds data of different logic, reads the data of different logic to the read bit line RBL_P and the write bit line WBL_N, and amplifies the data with a sense amplifier or the like, thereby enabling high-speed data reading.

[0071] 5C, an exclusive OR circuit (XOR circuit) may be provided so that data equivalent to the multiplication of data held in the memory circuit 24_P and the memory circuit 24_N is output to the read bit line RBL. This configuration can omit the operation equivalent to the multiplication in the arithmetic circuit 23, thereby achieving low power consumption.

[0072] A circuit configuration applicable to the memory circuit 24 of FIG. 4A may be a NAND type memory circuit having a charge storage layer, such as a MONOS type shown in FIG. 5D. FIG. 5D illustrates a memory circuit 24D having transistors 32[1] to 32[n] and transistors SW1 and SW2. The transistors 32[1] to 32[n] and the transistors SW1 and SW2 are OS transistors. The transistors 32[1] to 32[n] and the transistors SW1 and SW2 may be OS transistors having semiconductor layers provided in the same layer or may be OS transistors having semiconductor layers provided in different layers. The transistors 32[1] to 32[n] have a configuration including a control gate electrode and a charge storage layer or a floating gate electrode.

[0073] 5D, the transistors 32[1] to 32[n] may be string-type (also called macaroni-type) NAND-type memories in which an opening is provided in a stack of alternately stacked conductive layers and insulating layers, and conductors, insulators, semiconductors, etc. are stacked concentrically on the inner wall of the opening. The memory circuit 24D illustrates an example in which the transistors 32[1] to 32[n] are connected to word lines WL[1] to WL[n] and back gate lines BGL[1] to BGL[n], and the transistors SW1 and SW2 are connected to control lines SEL1 and SEL2, the read bit line, and the source line SL.

[0074] A circuit configuration applicable to the memory circuit 24 of FIG. 4A may be a NAND type memory circuit combining NOSRAMs as shown in FIG. 5E. FIG. 5E illustrates a memory circuit 24E including transistors 25[1] to 25[n], transistors 26[1] to 26[n], and transistors SW1 and SW2. The transistors 25[1] to 25[n], transistors 26[1] to 26[n], and transistors SW1 and SW2 are OS transistors. The transistors 25[1] to 25[n], transistors 26[1] to 26[n], and transistors SW1 and SW2 may be OS transistors having semiconductor layers provided in the same layer or may be OS transistors having semiconductor layers provided in different layers. The circuit including the transistors 25[1] to 25[n] and the transistors 26[1] to 26[n] includes nodes ND[1] to ND[n] in which charges corresponding to data are held by turning off the transistors 25[1] to 25[n].

[0075] In FIG. 5E, the transistors 25[1] to 25[n] and the transistors 26[1] to 26[n] may be vertical channel type (also called macaroni type) NAND type memories in which an opening is provided in a laminate in which conductive layers and insulating layers are alternately stacked, and conductors, insulators, semiconductors, etc. are stacked concentrically on the inner wall of the opening. Note that a NAND type memory composed of OS transistors that can be fabricated on a layer having a Si transistor has a function as a main memory in addition to a function as a storage memory, and can be called a universal memory. The universal memory may be capable of constructing a computer system that does not require DRAM by combining the functions of a main memory such as a DRAM (Dynamic RAM) provided as a separate chip. The memory circuit 24E illustrates an example in which the transistors 25[1] to 25[n] are connected to the word lines WL[1] to WL[n], respectively, and the transistors 26[1] to 26[n] are connected to the nodes ND[1] to ND[n], which are data storage nodes of the NOSRAM, respectively. Moreover, the memory circuit 24E illustrates an example in which the transistors SW1 and SW2 are connected to the control lines SEL1 and SEL2, the read bit line RBL, and the source line SL.

[0076] Furthermore, the circuit configuration of the memory circuit applicable to each layer of the memory circuit layers 22_1 to 22_N of the semiconductor device 100 of the present invention may be different for each layer. For example, as shown in Fig. 6A, the memory circuit in the lower layer (e.g., memory circuit layer 22_1) of the memory circuit layers 22_1 to 22_N is the memory circuit 24A, and the memory circuit in the upper layer (e.g., memory circuit layer 22_2, memory circuit layer 22_N) is the memory circuit 24B. The memory circuit 24A, which is physically close to the arithmetic circuit 23, is applied with a NOSRAM circuit configuration, and the memory circuit 24B can be applied with other circuit configurations such as DOSRAM and NAND type memory.

[0077] In the configuration shown in FIG. 6B, which is different from the configuration shown in FIG. 6A, the memory circuit in the upper layer (for example, memory circuit layers 22_2 to 22_N) is a memory circuit 24N of a universal memory of a vertical channel type. The memory circuit 24A, which is physically close to the arithmetic circuit 23, can be applied with a circuit configuration of NOSRAM. By making the memory circuit 24N a universal memory of a vertical channel type with a high storage density, an external memory such as a DRAM can be omitted. In addition, the arithmetic processing can be performed at high speed by storing data required for the arithmetic processing in the NOSRAM, which has a higher write speed and read speed than the universal memory. With such a configuration, the data stored in the universal memory (memory circuit 24N) can be processed through the NOSRAM (memory circuit 24A), so that the storage capacity of the data used for the arithmetic processing in the semiconductor device 100 can be significantly increased. In addition, the gap in the delay time required for reading and writing data can be alleviated.

[0078] Generally, various memory devices are used in semiconductor devices such as computers depending on the purpose. Figure 7A shows various memory devices used in semiconductor devices by hierarchy. The higher the layer, the faster the operating speed is required for the memory device, and the lower the layer, the larger the memory capacity and the higher the recording density are required for the memory device. Figure 7A shows, from the top layer, memories embedded as registers in a processing unit (PU), memories that can be used as caches such as NOSRAM, and memories that can be used as storage memories such as OS Memory or main memory (storage).

[0079] 7A and 7B, a three-dimensional NAND type universal memory using OS transistors is referred to as an “OS Memory.” Note that the “OS Memory” is preferably an OS transistor with a larger storage capacity than NOSRAM.

[0080] Since the universal memory is randomly accessible and has a very small off-state current of the OS transistor, the universal memory can retain written information for one year or even ten years even if the power supply is stopped, and therefore the universal memory can be considered as a nonvolatile memory.

[0081] In addition, since the amount of electric charge written into the universal memory is unlikely to change over a long period of time, the universal memory can hold not only binary (1 bit) information but also multi-value (multi-bit) information.

[0082] In addition, since the universal memory writes charge to the node via the OS transistor, it does not require the high voltage required for conventional NAND flash memory, and can achieve high-speed write operations. In addition, the erase operation before rewriting data, which is required for NAND flash memory, is not required for universal memory. In addition, since no charge is injected or extracted from the floating gate or charge trapping layer, universal memory can write and read data an unlimited number of times. Universal memory is less susceptible to deterioration and has high reliability compared to conventional NAND flash memory.

[0083] The semiconductor device according to one embodiment of the present invention can significantly increase the storage capacity of data used in arithmetic processing. In addition, the gap in delay time required for reading and writing data can be alleviated. As shown in FIG. 7B, memory circuits having different data retention characteristics or storage capacities are stacked in the z direction (the direction perpendicular to the substrate on which the arithmetic processing unit 21 is provided), and data can be input and output through each layer. Since data can be input and output using wiring between each layer, the parasitic capacitance or resistance of the wiring can be reduced, and an increase in power consumption due to data input and output can be suppressed.

[0084] In one embodiment of the present invention, some of the memory circuit layers 22_1 to 22_N may be circuits having different functions. For example, as illustrated in FIG. 8A, a circuit 24F having a function different from that of a memory circuit may be provided in the memory circuit layer 22_N in the uppermost layer of the accelerator 20.

[0085] The circuit 24F is a circuit that can be provided with an OS transistor. For example, it can be an amplifier circuit or an amplifier circuit that can amplify the potential of the input IN at the output OUT as shown in FIG. 8B. The transistor 33B can be configured with an OS transistor. In addition to the configuration of FIG. 8B, the circuit 24F may have an antenna 34 as shown in FIG. 8C. The antenna 34 can be formed by arranging a conductive layer used in the circuit 24F so as to function as an antenna. For example, in the case of an antenna for a fifth generation mobile communication system (5G), the antenna 34 uses communication frequencies of 3.7 GHz, 4.5 GHz, and 28 GHz in Japan.

[0086] In one embodiment of the present invention, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N are made different. The data retention characteristics correspond to the time during which written data can be retained (data retention time). In the schematic diagram shown in FIG. 9A, the data retention characteristics of the memory circuit 24A and the memory circuit 24B are made different. When the memory circuit 24A is used as a cache memory, the data retention time of the memory circuit 24A may be several ms. When the memory circuit 24B is used as a main memory or a storage memory, the data retention time of the memory circuit 24B is preferably longer than that of the cache memory.

[0087] As a configuration for making the retention times different, as shown in FIG. 9A, the drive voltages V1 and V2 for driving each memory circuit output by the drive circuit 35 are made different. For example, as shown in FIG. 9B, the amplitude voltages for driving the transistors of the memory circuits are made different by the drive voltages V1 and V2. In FIG. 9B, the potential for turning off the transistors of the memory circuits 24A and 24B is set to potential Voff. In FIG. 9B, the potential Von1 for turning on the transistors of the memory circuit 24A is set to be smaller than the potential Von2 for turning on the transistors of the memory circuit 24B. By setting the drive voltages V1 and V2 in this way, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be made different. By making the drive voltages V1 and V2 for driving each memory circuit different, the S value (subthreshold swing value) and the field effect mobility of the transistors of each memory circuit can be made different.

[0088] As another example, as shown in Fig. 9C, a potential for turning on the transistors in the memory circuits 24A and 24B is set as a potential Von. In Fig. 9C, a potential Voff1 for turning off the transistors in the memory circuit 24A is set to be higher than a potential Voff2 for turning on the transistors in the memory circuit 24B. By setting the drive voltages V1 and V2 in this manner, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be made different.

[0089] The retention time may be varied by varying the thickness of the insulator functioning as the gate insulating film of the transistor in the memory circuit for each layer. For example, as shown in FIG. 10, the thickness of the insulator 36A functioning as the gate insulating film of the transistor 25A in the memory circuit 24A in the memory circuit layer 22_1 is made smaller than the thickness of the insulator 36B functioning as the gate insulating film of the transistor 25B in the memory circuit 24B in the memory circuit layers 22_2 to 2_N. By varying the thickness of the insulator functioning as the gate insulating film of the transistor in the memory circuit for each layer in this manner, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be varied.

[0090] As a configuration for making the retention times different, a configuration for making the channel lengths of the transistors in the memory circuits different for each layer may be used. For example, as shown in FIG. 11, the channel length L1 of the transistor 25A in the memory circuit 24A in the memory circuit layer 22_1 is made smaller than the channel length L2 of the transistor 25B in the memory circuit 24B in the memory circuit layers 22_2 to 2_N. By making the channel lengths of the transistors in the memory circuits different for each layer in this way, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be made different. Note that, although FIG. 11 describes a configuration for making the channel lengths different for each layer, a configuration for making the channel widths of the transistors different, or the ratio of the channel length to the channel width (W / L), or a configuration for making the driving frequency different for each layer may be used in combination.

[0091] 12A is a diagram for explaining a circuit configuration example applicable to the arithmetic processing unit 21 of the semiconductor device 100 of the present invention. The arithmetic processing unit 21 has N arithmetic circuits 23_1 to 23_N. The N arithmetic circuits 23_1 to 23_N each receive a signal from one of N read bit lines RBL_1 to RBL_N, and output output signals Q_1 to Q_N. The signals from the read bit lines RBL_1 to RBL_N may be amplified by a sense amplifier or the like and read out. The output signals Q_1 to Q_N correspond to data obtained by performing a product-sum operation using data held in a memory circuit 24.

[0092] Fig. 12B is a diagram for explaining a circuit configuration example of the arithmetic circuit 23 applicable to the arithmetic circuits 23_1 to 23_N. Fig. 13 is a circuit for executing arithmetic processing based on the architecture of a binary neural network (BNN). The arithmetic circuit 23 has a read circuit 41 to which a signal of a read bit line RBL is applied, a bit product-sum calculator 42, an accumulator 43, a latch circuit 44, and an encoding circuit 45 that outputs an output signal Q.

[0093] FIG. 13 shows a detailed configuration example of the arithmetic circuit 23 shown in FIG. 12B. FIG. 13 shows an example of a configuration in which a multiplication and addition operation is performed on 8-bit signals (W[0] to W[7], A[0] to A[7]) and a 1-bit output signal Q and an 11-bit output signal (accout[10:0]) are output. In FIG. 12B, since one row is selected per clock for memory access, M (=1 bit×M rows) products and their sums are executed in M ​​clocks. In the arithmetic circuit of FIG. 13, the same M products and their sums can be executed in 8 parallel×1 bit×M / 8 rows, so M / 8 clocks are required. Therefore, the configuration of FIG. 13 can shorten the calculation time by executing the multiplication and addition operation in parallel, thereby improving the calculation efficiency.

[0094] 12A and 12B, the circuit area of ​​the arithmetic circuit 23 can be reduced by configuring the circuit to perform product-sum operations specialized for inference processing. Therefore, the power consumption required for transmitting and receiving data using multiple accelerators 20 can be reduced by a factor of several tens of times.

[0095] In addition to reducing power consumption in the calculations described above, reducing power consumption through calculations specialized for product-sum calculations during inference processing, and reducing power consumption through miniaturization of circuit area, it is possible to reduce the power consumption of existing data centers or supercomputers by a factor of one thousand by optimizing the computer architecture, software, and driving methods.

[0096] 13, the bit-product-sum calculator 42 has an accumulator to which an 8-bit signal (W[0] through W[7], A[0] through A[7]) is input, and an adder to which the value obtained by the accumulator is input. As shown in FIG 13, the products of 1-bit signals calculated in eight parallel operations are illustrated as WA0 through WA7, their sums as WA10, WA32, WA54, and WA76, and their further sums as WA3210 and WA7654.

[0097] 13, the accumulator 43 functioning as an adder outputs the sum of the signal of the bit sum-of-products calculator 42 and the output signal of the latch circuit 44 to the latch circuit 44. The accumulator 43 switches the signal to be input to the adder according to the control signal TxD_EN. When the control signal TxD_EN is 0 (TxD_EN=0), the accumulator 43 outputs the sum of the signal of the bit sum-of-products calculator 42 and the output signal of the latch circuit 44 to the latch circuit 44. When the control signal TxD_EN is 1 (TxD_EN=1), the accumulator 43 outputs the sum of the signal of the logic circuit 47 (11-bit selector) and the output signal of the latch circuit 44 to the latch circuit 44.

[0098] In FIG. 13, after completing the multiplication and accumulation operation of signals A[0] to A[7] and signals W[0] to W[7], logic circuit 47, which is composed of AND circuits, adds data for batch normalization, specifically signal W[7], while switching with a switching signal (th select[10:0]). Note that data for batch normalization may be configured to simultaneously read and select signals W[0] to W[6] other than signal W[7], for example. Batch normalization is an operation for adjusting the distribution of output data of each layer in a neural network so that it is constant. For example, image data often used for calculations in a neural network may differ from the distribution of predicted data (input data) because the distribution of data used for learning is prone to variation. Batch normalization can improve the accuracy of learning in a neural network by normalizing the distribution of input data to the intermediate layer of the neural network to a Gaussian distribution with a mean of 0 and a variance of 1. In a Binary Neural Network (BNN), the output results of each layer are binarized by activation, so by suppressing the bias in data distribution relative to a threshold value, it becomes possible to properly activate, i.e., separate information.

[0099] The latch circuit 44 holds the output signal (accout[10:0]) of the accumulator 43. The binary data to be passed to the next layer (NN layer) in the neural network by batch normalization becomes the most significant bit of the product-sum operation result held by the latch circuit 44. In the output signal (accout[10:0]), the most significant bit signal (accout10) represents the sign of the latch data calculated in two's complement, and in order to pass the positive data as 1 and the negative data as 0 to the next NN layer, it is inverted by the inverter circuit 46 functioning as a coding circuit and output as the output signal Q. Since Q is the output of the intermediate layer, it is temporarily held in a buffer memory (also called an input buffer) in the accelerator 20 and then used for the operation of the next layer.

[0100] FIG. 14A illustrates a hierarchical neural network based on the architecture of a binary neural network (BNN). FIG. 14A illustrates a fully connected neural network consisting of a neuron 50, one input layer (I1), three intermediate layers (M1 to M3), and one output layer (O1). If the number of neurons in the input layer I1 is 786, the number of neurons in the intermediate layers M1 to M3 is 256, and the number of neurons in the output layer O1 is 10, the number of connections in each layer (layer 51, layer 52, layer 53, and layer 54) is (786×256)+(256×256)+(256×256)+(256×10), which is a total of 334336. In other words, the weight parameters required for neural network calculation are about 330K bits in total, so that the memory capacity can be sufficiently implemented even in a small-scale system.

[0101] Next, FIG. 14B shows a detailed block diagram of a semiconductor device 100 capable of performing the neural network calculations shown in FIG. 14A.

[0102] FIG. 14B illustrates an example configuration of peripheral circuits for driving each component illustrated in FIGS. 1A and 1B, in addition to the arithmetic processing unit 21, the arithmetic circuit 23, the memory circuit layer 22_1 of the memory unit 22, the memory circuit 24, and the wiring 31, which are described in FIGS. 1A and 1B.

[0103] FIG. 14B illustrates a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, a precharge circuit 66, a sense amplifier 67, a selector 68, an input buffer 71, and an arithmetic control circuit 72.

[0104] Fig. 15A is a diagram in which blocks for controlling the memory circuit layers 22_1 to 22_N of the memory unit 22 are extracted from each configuration shown in Fig. 14B. Fig. 15A extracts and illustrates a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, a precharge circuit 66, a sense amplifier 67, and a selector 68.

[0105] The controller 61 processes an external input signal to generate control signals for the row decoder 62 and the column decoder 64. The external input signal is a control signal such as a write enable signal or a read enable signal for controlling the memory circuit layers 22_1 to 22_N of the memory unit 22. The controller 61 also inputs and outputs data to be written to the memory circuit layers 22_1 to 22_N of the memory unit 22 or data to be read from the memory circuit layers 22_1 to 22_N of the memory unit 22 via a bus between the controller 61 and the CPU 10.

[0106] The row decoder 62 generates a signal for driving the word line driver 63. The word line driver 63 generates a signal to be provided to the write word line WWL and the read word line RWL. The column decoder 64 generates a signal for driving the sense amplifier 67 and the write driver 65. The sense amplifier 67 amplifies the potential of the read bit line RBL. The write driver generates a signal for controlling the read bit line RBL and the write bit line WBL. The precharge circuit 66 has a function of precharging the read bit line RBL and the like. The signal read from the memory circuit 24 of the memory circuit layers 22_1 to 22_N of the memory unit 22 can be input to the arithmetic circuit 23 and can also be output via the selector 68. The selector 68 can sequentially read data corresponding to the bus width and output the necessary data to the CPU 10 or the like via the controller 61.

[0107] FIG. 15B is a diagram in which blocks for controlling the arithmetic processing unit 21 are extracted from each configuration shown in FIG. 14B.

[0108] The controller 61 processes an input signal from the outside and generates a control signal for the calculation control circuit 72. The controller 61 also generates various signals for controlling the calculation circuit 23 of the calculation processing unit 21. The controller 61 also inputs and outputs data related to the calculation result via the input buffer 71. By using this buffer memory, parallel calculation of the number of bits greater than the data bus width of the CPU is possible. In addition, the number of times a huge number of weight parameters are transferred between the CPU 10 can be reduced, thereby reducing power consumption.

[0109] One embodiment of the present invention can reduce the size of a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters. Alternatively, one embodiment of the present invention can reduce the power consumption of a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters. Alternatively, one embodiment of the present invention can suppress heat generation in a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters. Alternatively, one embodiment of the present invention can reduce the number of data transfers between a CPU and a semiconductor device that functions as a memory in a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters. In other words, a semiconductor device that functions as an accelerator for AI technology or the like, which has a huge amount of calculations and a large number of parameters, has a non-von Neumann architecture, and can perform parallel processing with extremely low power consumption compared to a von Neumann architecture in which power consumption increases as the processing speed increases.

[0110] (Embodiment 2) In this embodiment, an example of an operation in the case where part of the calculations of the program executed by the CPU 10 described in the above embodiment is executed by the accelerator 20 will be described.

[0111] FIG. 16 is a diagram for explaining an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator.

[0112] The host program is executed by the CPU (step S1).

[0113] When the CPU confirms an instruction to secure a data area required for performing a calculation using the accelerator in the memory unit (step S2), the CPU secures the data area in the memory unit (step S3). For example, in the above-mentioned embodiment 1, data required for the accelerator 20 to perform a calculation in the calculation processing unit 21 is secured in the memory unit 22.

[0114] Next, the CPU transmits input data from the main memory to the memory unit (step S4). The memory unit receives the input data and stores the input data in the area secured in step S2 (step S5).

[0115] When the CPU confirms an instruction to start the kernel program (step S6), the accelerator starts executing the kernel program (step S7).

[0116] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state in which it performs calculations to a PG (power gating) state (step S8). In this case, the CPU is switched from the PG state to a state in which it performs calculations immediately before the accelerator finishes executing the kernel program (step S9). By keeping the CPU in the PG state during the period from step S8 to step S9, it is possible to suppress power consumption and heat generation in the semiconductor device as a whole.

[0117] When the accelerator finishes the execution of the kernel program, the output data is stored in the memory unit (step S10).

[0118] After the execution of the kernel program is completed, if the CPU requests an instruction to send output data stored in the memory unit to the main memory (step S11), the accelerator sends the output data to the main memory, and the output data is stored in the main memory (step S12).

[0119] When the CPU issues a command to release the data area secured on the memory unit (step S13), the data area secured on the memory unit is released (step S14).

[0120] By repeating the above operations from step S1 to step S14, it is possible to suppress the power consumption and heat generation of the CPU and accelerator, while allowing the accelerator to execute part of the calculations of the program executed by the CPU.

[0121] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0122] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described.

[0123] 17 shows an example of the configuration of the CPU 10. The CPU 10 has a CPU core (CPU Core) 200, an L1 (level 1) cache memory device (L1 Cache) 202, an L2 cache memory device (L2 Cache) 203, a bus interface unit (Bus I / F) 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 has a flip-flop 220.

[0124] The CPU core 200 , the L1 cache memory device 202 , and the L2 cache memory device 203 are interconnected via a bus interface unit 205 .

[0125] The PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals in response to interrupt signals (Interrupts) input from outside and signals such as a signal SLEEP1 issued by the CPU 10. The clock signal GCLK1 and the PG control signals are input to the CPU 10. The PG control signals control the power switches 210 to 212 and the flip-flop 220.

[0126] The power switches 210 and 211 respectively control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line). The power switch 212 controls the supply of voltage VDDH to a virtual power line V_VDH (hereinafter referred to as a V_VDH line). The voltage VSSS is input to the CPU 10 and the PMU 193 without passing through a power switch. The voltage VDDD is input to the PMU 193 without passing through a power switch.

[0127] The voltages VDDD and VDD1 are drive voltages for the CMOS circuits. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is a drive voltage for the OS transistors and is higher than the voltage VDDD.

[0128] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain that can be power-gated. The power domain that can be power-gated is provided with one or more power switches. These power switches are controlled by a PG control signal.

[0129] The flip-flop 220 is used as a register. A backup circuit is provided in the flip-flop 220. The flip-flop 220 will be described below.

[0130] 18A shows an example of the circuit configuration of the flip-flop 220. The flip-flop 220 includes a scan flip-flop 221 and a backup circuit 222.

[0131] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0132] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. Analog switches of scan flip-flop 221 are connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for a reset signal.

[0133] A signal SCE is a scan enable signal, and is generated by the PMU 193. The PMU 193 generates signals BK and RC. A level shifter 214 shifts the levels of the signals BK and RC to generate signals BKH and RCH. The signals BK and RC are a backup signal and a recovery signal.

[0134] The circuit configuration of the scan flip-flop 221 is not limited to that shown in Fig. 18A, and any flip-flop provided in a standard circuit library can be used.

[0135] The backup circuit 222 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitor C11.

[0136] The node SD_IN is an input node for scan test data, and is connected to the node Q1 of the scan flip-flop 221. The node SN11 is a storage node of the backup circuit 222. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0137] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0138] The transistors M11 to M13 are OS transistors, similar to the transistors 25 to 27 included in the memory circuit 24. The transistors M11 to M13 are illustrated as having back gates. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0139] At least the transistors M11 and M12 are preferably OS transistors. OS transistors have an extremely small off-state current, which can suppress a voltage drop at the node SN11 and consume almost no power to retain data, so that the backup circuit 222 has nonvolatile characteristics. Since data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and can write and read data with low energy.

[0140] It is highly preferable that all the transistors in the backup circuit 222 are OS transistors. As shown in Fig. 18B, the backup circuit 222 can be stacked on a scan flip-flop 221 that is configured with a silicon CMOS circuit.

[0141] Since the backup circuit 222 has a very small number of elements compared to the scan flip-flop 221, there is no need to change the circuit configuration and layout of the scan flip-flop 221 in order to stack the backup circuit 222. In other words, the backup circuit 222 is a highly versatile backup circuit. In addition, since the backup circuit 222 can be provided so as to overlap within the region in which the scan flip-flop 221 is formed, even if the backup circuit 222 is incorporated, the area overhead of the flip-flop 220 can be reduced to zero. Therefore, by providing the backup circuit 222 in the flip-flop 220, power gating of the CPU core 200 becomes possible. Since little energy is required for power gating, the CPU core 200 can be power gated with high efficiency.

[0142] By providing the backup circuit 222, a parasitic capacitance due to the transistor M11 is added to the node Q1, but since it is small compared to the parasitic capacitance due to the logic circuit connected to the node Q1, it does not affect the operation of the scan flip-flop 221. In other words, even if the backup circuit 222 is provided, the performance of the flip-flop 220 does not substantially deteriorate.

[0143] For example, a clock gating state, a power gating state, or a pause state can be set as the low power consumption state of the CPU core 200. The PMU 193 selects the low power consumption mode of the CPU core 200 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operation state to a clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0144] For example, when transitioning from a normal operation state to a hibernation state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 to input the voltage VDD1 to the CPU core 200. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 221. When performing frequency scaling, the PMU 193 reduces the frequency of the clock signal GCLK1.

[0145] When the CPU core 200 is transitioned from a normal operation state to a power gating state, an operation is performed to back up the data of the scan flip-flop 221 in the backup circuit 222. When the CPU core 200 is returned from the power gating state to the normal operation state, a recovery operation is performed to write the data of the backup circuit 222 back to the scan flip-flop 221.

[0146] Fig. 19 shows an example of a power gating sequence of the CPU core 200. In Fig. 19, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 210 to 212, and are generated by the PMU 193. When the signal PSE0 is "H" / "L", the power switch 210 is on / off. The same applies to the signals PSE1 and PSE2.

[0147] Before time t1, the state is normal operation. The power switch 210 is on, and the voltage VDDD is input to the CPU core 200. The scan flip-flop 221 performs normal operation. At this time, since the level shifter 214 does not need to operate, the power switch 212 is off, and the signals SCE, BK, and RC are "L". Since the node SE is "L", the scan flip-flop 221 stores the data of the node D1. Note that in the example of FIG. 19, at time t1, the node SN11 of the backup circuit 222 is "L".

[0148] The operation during backup will be described. At operation time t1, the PMU 193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to "H." The level shifter 214 becomes active and outputs the signal BKH at "H" to the backup circuit 222.

[0149] The transistor M11 of the backup circuit 222 turns on, and the data of the node Q1 of the scan flip-flop 221 is written to the node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0150] The PMU 193 sets signals PSE2 and BK to "L" at time t2, and sets signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 200 transitions to a power gating state. Note that signal PSE0 may also fall at the same timing as signal BK falls.

[0151] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at the node Q1 is lost. The node SN11 continues to hold the data at the node Q1 at time t3.

[0152] The operation during recovery will be explained below. At time t4, the PMU 193 changes the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage of the V_VDD line reaches VDDD (time t5), the PMU 193 changes the signals PSE2, RC, and SCE to "H".

[0153] The transistor M12 turns on, and the charge of the capacitive element C11 is distributed to the nodes SN11 and SD. If the node SN11 is "H", the voltage of the node SD rises. Since the node SE is "H", the data of the node SD is written to the input side latch circuit of the scan flip-flop 221. When the clock signal GCLK1 is input to the node CK at time t6, the data of the input side latch circuit is written to the node Q1. In other words, the data of the node SN11 is written to the node Q1.

[0154] At time t7, the PMU 193 sets the signals PSE2, SCE, and RC to "L," and the recovery operation ends.

[0155] The backup circuit 222 using OS transistors has low dynamic and static power consumption and is therefore very suitable for normally-off computing. Even if the flip-flop 220 is installed, the performance degradation of the CPU core 200 and the increase in dynamic power consumption are hardly caused.

[0156] The CPU core 200 may have multiple power domains that can be power-gated. The multiple power domains are provided with one or more power switches for controlling the input of voltage. The CPU core 200 may also have one or more power domains in which power gating is not performed. For example, a power gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212 may be provided in the power domain in which power gating is not performed.

[0157] The application of the flip-flop 220 is not limited to the CPU 10. In a computing device, the flip-flop 220 can be applied to a register provided in a power domain capable of power gating.

[0158] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0159] (Embodiment 4) An example of the semiconductor device according to the above embodiment will be described below with reference to Fig. 20 to Fig. 25. First, a configuration example of a memory circuit (memory cell) included in the semiconductor device will be described.

[0160] <Memory circuit configuration example> 20A and 20B show a structure of a memory circuit 860 constituting a semiconductor device according to one embodiment of the present invention. FIG. 20A is a top view of the memory circuit 860 and its periphery. FIG. 20B is a cross-sectional view of the memory circuit 860, and FIG. 20B corresponds to a portion indicated by a dashed line A1-A2 in FIG. 20A. FIG. 20B shows a cross section of the transistor 600 in the channel length direction and a cross section of the transistor 700 in the channel width direction. Note that in the top view of FIG. 20A, some elements are omitted for clarity. Note that the X direction, Y direction, and Z direction shown in FIG. 20A are directions that are orthogonal to or intersect each other. Here, it is preferable that the X direction and the Y direction are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0161] The memory circuit 860 shown in this embodiment includes a transistor 600, a transistor 700, and a capacitor 655. The memory circuit 860 corresponds to the memory circuit 24 shown in the above embodiment, and the transistor 600, the transistor 700, and the capacitor 655 correspond to the transistor 25, the transistor 26, and the capacitor 28 shown in the above embodiment 1, respectively, and correspond to a 2T NOSRAM in which the transistor 27 is omitted. One of the source and drain of the transistor 600, the gate of the transistor 700, and one electrode of the capacitor 655 are electrically connected to each other.

[0162] 20A and 20B, in memory circuit 860, transistors 600 and 700 are arranged on insulator 614, insulator 680 is arranged on parts of transistors 600 and 700, insulator 682 is arranged on transistor 600, transistor 700, and insulator 680, insulator 685 is arranged on insulator 682, capacitor 655 is arranged on insulator 685, and insulator 688 is arranged on capacitor 655. Insulator 614, insulator 680, insulator 682, insulator 685, and insulator 688 function as interlayer films.

[0163] Here, transistor 600 includes an insulator 616 on an insulator 614, a conductor 605 (conductor 605a and conductor 605b) arranged so as to be embedded in insulator 616, an insulator 622 on insulator 616 and on conductor 605, an insulator 624 on insulator 622, an oxide 630a on insulator 624, an oxide 630b on oxide 630a, an oxide 643a and an oxide 643b on oxide 630b, a conductor 642a on oxide 643a, and a conductor 642b on oxide 643b. The semiconductor device includes an insulator 672 in contact with a part of the insulator 624, a side surface of the oxide 630a, a side surface of the oxide 630b, a side surface of the oxide 643a, a side surface of the conductor 642a, an upper surface of the conductor 642a, a side surface of the oxide 643b, a side surface of the conductor 642b, and an upper surface of the conductor 642b, an insulator 673 on the insulator 672, an oxide 630c on the oxide 630b, an insulator 650 on the oxide 630c, and a conductor 660 (conductor 660a and conductor 660b) located on the insulator 650 and overlapping with the oxide 630c. The oxide 630c also contacts the side surface of the oxide 643a, the side surface of the oxide 643b, the side surface of the conductor 642a, and the side surface of the conductor 642b. 20B, the upper surface of the conductor 660 is disposed so as to substantially coincide with the upper surface of the insulator 650, the upper surface of the oxide 630c, and the upper surface of the insulator 680. The insulator 682 contacts the upper surfaces of the conductor 660, the insulator 650, the oxide 630c, and the insulator 680.

[0164] In the following, the oxide 630a, the oxide 630b, and the oxide 630c may be collectively referred to as the oxide 630. The oxide 643a and the oxide 643b may be collectively referred to as the oxide 643. The conductor 642a and the conductor 642b may be collectively referred to as the conductor 642.

[0165] In the transistor 600, the conductor 660 functions as a gate, and the conductors 642a and 642b function as a source and a drain, respectively. The conductor 605 functions as a backgate. The transistor 600 is formed in a self-aligned manner such that the conductor 660 functioning as a gate fills an opening formed by the insulator 680 or the like. In this manner, in the semiconductor device according to this embodiment, the conductor 660 can be reliably disposed in the region between the conductors 642a and 642b without alignment.

[0166] Transistor 700 also includes an insulator 616 on an insulator 614, a conductor 705 (conductor 705a and conductor 705b) arranged to be embedded in insulator 616, an insulator 622 on insulator 616 and on conductor 705, an insulator 624 on insulator 622, an oxide 730a on insulator 624, an oxide 730b on oxide 730a, an oxide 743a and an oxide 743b on oxide 730b, a conductor 742a on oxide 743a, and a conductor 742b on oxide 743b. The semiconductor device includes an insulator 672 in contact with a part of the edge 624, a side surface of the oxide 730a, a side surface of the oxide 730b, a side surface of the oxide 743a, a side surface of the conductor 742a, a top surface of the conductor 742a, a side surface of the oxide 743b, a side surface of the conductor 742b, and a top surface of the conductor 742b, an insulator 673 on the insulator 672, an oxide 730c on the oxide 730b, an insulator 750 on the oxide 730c, and a conductor 760 (conductor 760a and conductor 760b) located on the insulator 750 and overlapping with the oxide 730c. The oxide 730c also contacts the side surface of the oxide 743a, the side surface of the oxide 743b, the side surface of the conductor 742a, and the side surface of the conductor 742b. 20B, the upper surface of the conductor 760 is disposed so as to substantially coincide with the upper surface of the insulator 750, the upper surface of the oxide 730c, and the upper surface of the insulator 680. Also, the insulator 682 contacts the upper surfaces of the conductor 760, the insulator 750, the oxide 730c, and the insulator 680.

[0167] In the following, the oxide 730a, the oxide 730b, and the oxide 730c may be collectively referred to as the oxide 730. The oxide 743a and the oxide 743b may be collectively referred to as the oxide 743. The conductor 742a and the conductor 742b may be collectively referred to as the conductor 742.

[0168] In the transistor 700, the conductor 760 functions as a gate, and the conductors 742a and 742b function as a source and a drain, respectively. The conductor 705 functions as a backgate. The transistor 700 is formed in a self-aligned manner such that the conductor 760 functioning as a gate fills an opening formed by the insulator 680 or the like. In this manner, in the semiconductor device of this embodiment, the conductor 760 can be reliably disposed in the region between the conductor 742a and the conductor 742b without alignment.

[0169] Here, the transistor 700 is formed in the same layer as the transistor 600 and has the same structure. Thus, although a cross section of the transistor 700 in the channel length direction is not shown, the transistor 700 has a structure similar to that of the cross section of the transistor 600 in the channel length direction shown in FIG. 20B. That is, the oxide 743 and the conductor 742, which are not shown in the cross-sectional view, also have a structure similar to that of the oxide 643 and the conductor 642 shown in FIG. 20B. Although a cross section of the transistor 600 in the channel width direction is not shown, the transistor 700 has a structure similar to that of the cross section of the transistor 700 in the channel width direction shown in FIG. 20B.

[0170] Therefore, the oxide 730 has a structure similar to that of the oxide 630, and the description of the oxide 630 can be referred to. The conductor 705 has a structure similar to that of the conductor 605, and the description of the conductor 605 can be referred to. The oxide 743 has a structure similar to that of the oxide 643, and the description of the oxide 643 can be referred to. The conductor 742 has a structure similar to that of the conductor 642, and the description of the conductor 642 can be referred to. The insulator 750 has a structure similar to that of the insulator 650, and the description of the insulator 650 can be referred to. The conductor 760 has a structure similar to that of the conductor 660, and the description of the conductor 660 can be referred to. Hereinafter, unless otherwise specified, the description of the structure of the transistor 600 can be referred to for the structure of the transistor 700 as described above.

[0171] Here, in the transistors 600 and 700, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the oxides 630 and 730 including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0172] For example, a metal oxide that functions as an oxide semiconductor has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large energy gap, the leakage current (off-state current) of the transistor 600 in a non-conducting state can be extremely small.

[0173] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. In particular, element M may be aluminum, gallium, yttrium, or tin. Also, as the oxide semiconductor, In-M oxide, In-Zn oxide, or M-Zn oxide may be used.

[0174] The transistor 600 and the transistor 700, which use an oxide semiconductor for the channel formation region, have extremely low off-state current, and therefore a semiconductor device with low power consumption can be provided. Furthermore, the off-state current of the transistor 600 and the transistor 700 hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. Thus, a semiconductor device that operates stably and has high reliability even in a high-temperature environment can be provided.

[0175] Since the off-state current of the transistor 600 is extremely small, the capacitance value of the capacitor 655 can be set small. As a result, the area occupied by the memory circuit 860 can be reduced, and the semiconductor device can be highly integrated.

[0176] 20A, the conductor 742a, the conductor 660, the conductor 605, and the conductor 705 preferably extend in the Y direction. The conductor 660 functions as the write word line WWL shown in the previous embodiment.

[0177] The capacitor 655 includes a conductor 646a over an insulator 685, an insulator 686 covering the conductor 646a, and a conductor 656 arranged over the insulator 685 and overlapping at least a portion of the conductor 656. Here, the conductor 646a functions as one electrode of the capacitor 655, and the conductor 646b functions as the other electrode of the capacitor 655. The insulator 686 functions as a dielectric of the capacitor 655.

[0178] Moreover, openings are formed in the insulators 622, 624, 672, 673, 680, 682, and 685, and the conductors 640 (conductors 640a, 640b, 640c, and 640d) functioning as plugs are provided so as to be embedded in the openings. The conductors 640 are provided so as to be exposed on the upper surface of the insulator 685.

[0179] The bottom surface of the conductor 640a is in contact with the conductor 642a and the top surface is in contact with the conductor 646a. The bottom surface of the conductor 640c is in contact with the conductor 760 and the top surface is in contact with the conductor 646a. In this manner, one of the source and drain of the transistor 600, the gate of the transistor 700, and one electrode of the capacitor 655 are electrically connected to each other.

[0180] The conductor 640b is provided in contact with the side surface of the conductor 642b. The conductor 615 and the conductor 607 are provided below the conductor 640b, and the conductor 646b and the conductor 657 are provided above the conductor 640b. The conductor 607 is provided in an opening formed in the insulator 614. Here, the conductor 615 is formed in the same layer as the conductor 605 and has a similar structure. The conductor 646b is formed in the same layer as the conductor 646a and has a similar structure. The conductor 657 is provided in an opening formed in the insulator 686 and the insulator 688.

[0181] The conductor 640b is electrically connected to the conductor 640b of the lower memory circuit 860 by the conductor 607 and the conductor 615. The conductor 640b is also electrically connected to the conductor 640b of the upper memory circuit 860 by the conductor 646b and the conductor 657. In this manner, the conductor 607, the conductor 615, the conductor 640b, the conductor 646b, and the conductor 657 extend in the Z direction, and function as the write bit line WBL shown in the previous embodiment.

[0182] Although not shown in the cross-sectional view, the conductor 640d is provided in contact with the side surface of the conductor 742b. The conductor 715 is provided below the conductor 640d. Conductors having the same structure as the conductors 607, 646b, and 657 are provided, and the conductor 640d is electrically connected to the conductors 640d in the upper and lower layers. In this way, the conductor 715, the conductor 640d, etc. extend in the Z direction and function as the read bit line RBL shown in the previous embodiment.

[0183] 20B, by forming the transistors 600 and 700 in the same layer, the transistors 600 and 700 can be formed in the same process, thereby shortening the process of manufacturing the semiconductor device and improving productivity.

[0184] Note that in the memory circuit 860, the transistor 600, the transistor 700, and the capacitor 655 are provided so that the channel length direction of the transistor 600 and the channel length direction of the transistor 700 are parallel to each other, but the semiconductor device described in this embodiment is not limited to this. The memory circuit 860 illustrated in FIG. 20 and the like is an example of the configuration of a semiconductor device, and transistors or capacitors having appropriate structures may be appropriately arranged depending on the circuit configuration and driving method.

[0185] [Detailed configuration of memory circuit] The detailed configuration of the memory circuit 860 according to one embodiment of the present invention will be described below. In the following description, the description of the components of the transistor 600 can be referred to for the components of the transistor 700.

[0186] 20B, the oxide 630 preferably includes an oxide 630a on the insulator 624, an oxide 630b on the oxide 630a, and an oxide 630c disposed on the oxide 630b and at least a portion of which is in contact with the upper surface of the oxide 630b. Here, the side surface of the oxide 630c is preferably in contact with the oxide 643a, the oxide 643b, the conductor 642a, the conductor 642b, the insulator 672, the insulator 673, and the insulator 680.

[0187] That is, the oxide 630 has an oxide 630a, an oxide 630b on the oxide 630a, and an oxide 630c on the oxide 630b. By having the oxide 630a below the oxide 630b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 630a to the oxide 630b. Also, by having the oxide 630c on the oxide 630b, it is possible to suppress the diffusion of impurities from structures formed above the oxide 630c to the oxide 630b.

[0188] Note that, in the transistor 600, a three-layer structure of the oxide 630a, the oxide 630b, and the oxide 630c is shown in the channel formation region and its vicinity, but the present invention is not limited to this. For example, a single layer of the oxide 630b, a two-layer structure of the oxide 630b and the oxide 630a, a two-layer structure of the oxide 630b and the oxide 630c, or a stacked structure of four or more layers may be provided. For example, the oxide 630c may be a two-layer structure, and a stacked structure of four layers may be provided.

[0189] In addition, the oxide 630 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 630a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 630b. In addition, in the metal oxide used for the oxide 630a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 630b. In addition, in the metal oxide used for the oxide 630b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 630a. In addition, the oxide 630c can be a metal oxide that can be used for the oxide 630a or the oxide 630b. In addition, in the metal oxide used for the oxide 630c, the atomic ratio of In to element M may be larger than the atomic ratio of In to element M in the metal oxide used for the oxide 630b.

[0190] Specifically, the oxide 630a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition close thereto, or an atomic ratio of 1:1:0.5 or a composition close thereto.

[0191] Also, the oxide 630b may be a metal oxide having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, or a composition of 1:1:1 [atomic ratio] or a composition close thereto. Also, the oxide 630b may be a metal oxide having a composition of In:Ga:Zn=5:1:3 [atomic ratio] or a composition close thereto, or a composition of In:Ga:Zn=10:1:3 [atomic ratio] or a composition close thereto. Also, the oxide 630b may be an In-Zn oxide (for example, a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto, a composition of In:Zn=5:1 [atomic ratio] or a composition close thereto, or a composition of In:Zn=10:1 [atomic ratio] or a composition close thereto). Also, the oxide 630b may be an In oxide.

[0192] The oxide 630c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition close thereto, an atomic ratio of Ga:Zn=2:1 or a composition close thereto, or an atomic ratio of Ga:Zn=2:5 or a composition close thereto. The oxide 630c may be formed as a single layer or a multilayer by using a material that can be used for the oxide 630b. For example, specific examples of the oxide 630c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto and In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto, a layered structure of Ga:Zn=2:1 [atomic ratio] or a composition close thereto and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, a layered structure of Ga:Zn=2:5 [atomic ratio] or a composition close thereto and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, and a layered structure of gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto.

[0193] In addition, by increasing the ratio of indium in the oxides 630b and 630c, the on-state current or the field effect mobility of the transistor can be increased, which is preferable. In addition, the above-mentioned vicinity composition includes a range of ±30% of the desired atomic ratio.

[0194] The composition of elements contained in the metal oxide may be changed depending on the operating frequency required for the transistor. For example, in a transistor included in a memory circuit, the metal oxide may have a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, and in other transistors, the metal oxide may have a composition of In:Ga:Zn=5:1:3 [atomic ratio] or a composition close thereto. Note that in other transistors, the metal oxide may have a composition of In:Ga:Zn=10:1:3 [atomic ratio] or a composition close thereto, or In:Zn=2:1 [atomic ratio] or a composition close thereto.

[0195] The oxide 630b may have crystallinity. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies) and have a dense structure with high crystallinity. This can suppress the source electrode or drain electrode from extracting oxygen from the oxide 630b. Even when a heat treatment is performed, the transistor 600 is stable against high temperatures (so-called thermal budget) in the manufacturing process because the extraction of oxygen from the oxide 630b can be suppressed.

[0196] Moreover, the oxide 630c is preferably provided in an opening provided in an interlayer film including the insulator 680. Thus, the insulator 650 and the conductor 660 have a region overlapping with the stacked structure of the oxide 630b and the oxide 630a via the oxide 630c. With this structure, the oxide 630c and the insulator 650 can be formed by successive film formation, and the interface between the oxide 630 and the insulator 650 can be kept clean. Thus, the effect of interface scattering on carrier conduction is reduced, and the transistor 600 can obtain high on-state current and high frequency characteristics.

[0197] It is preferable to use an oxide semiconductor with a low carrier concentration for the oxide 630 (for example, the oxide 630b). In order to reduce the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in an oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0198] In particular, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water, which creates oxygen vacancies (V O In addition, defects in which hydrogen is inserted into the oxygen vacancy (hereafter referred to as V O H.) can function as a donor and generate electrons that serve as carriers. Some of the hydrogen can bond with oxygen that bonds to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a lot of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field; therefore, if an oxide semiconductor contains a lot of hydrogen, the reliability of the transistor may be deteriorated.

[0199] V OH can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in an oxide semiconductor, the oxide semiconductor may be evaluated by the carrier concentration instead of the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

[0200] From the above, when an oxide semiconductor is used for the oxide 630, V in the oxide 630 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (sometimes referred to as oxygen addition treatment). O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0201] For example, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) of oxide 630b is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using the oxide 630 in which impurities such as hydrogen are sufficiently reduced for the channel formation region of the transistor 600, the transistor 600 can have normally-off characteristics, and thus the transistor can have stable electrical characteristics and improved reliability.

[0202] In the case where an oxide semiconductor is used for the oxide 630, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0203] Therefore, it is preferable to use a material that suppresses diffusion of impurities (hereinafter also referred to as a barrier material for impurities) as the insulators 614, 622, 672, 673, and 682 to reduce diffusion of impurities such as hydrogen into the oxide 630. Note that in this specification and the like, the term "barrier property" refers to a function of suppressing diffusion of a corresponding substance (also referred to as having low permeability). Alternatively, it refers to a function of capturing and fixing (also referred to as gettering) a corresponding substance. In this specification and the like, an insulating film having a barrier property may be referred to as a barrier insulating film.

[0204] For example, materials having a function of suppressing the diffusion of hydrogen and oxygen include aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, etc. In particular, silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, and is therefore preferably used as a sealing material.

[0205] Furthermore, for example, materials having the function of capturing and fixing hydrogen include metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.

[0206] For example, aluminum oxide, hafnium oxide, or the like is preferably used as the insulator 614. This can prevent impurities such as water or hydrogen from diffusing from the substrate side to the transistor 600 side. Alternatively, oxygen contained in the insulator 624, or the like, can be prevented from diffusing to the substrate side.

[0207] The conductor 605 is disposed so as to overlap the oxide 630 and the conductor 660. In addition, the conductor 605 is preferably embedded in the insulator 616.

[0208] When the conductor 605 functions as a gate electrode, the threshold voltage (Vth) of the transistor 600 can be controlled by changing the potential applied to the conductor 605 independently of the potential applied to the conductor 660. In particular, applying a negative potential to the conductor 605 can increase the Vth of the transistor 600 and reduce the off-current. Therefore, applying a negative potential to the conductor 605 can reduce the drain current when the potential applied to the conductor 660 is 0 V, compared to not applying a negative potential.

[0209] Note that the conductor 605 is preferably larger than the size of a region of the oxide 630 that does not overlap with the conductors 642a and 642b, as shown in FIG. 20A. In particular, as shown in FIG. 20B, the conductor 605 preferably extends also in a region outside the end of the oxide 630 that intersects with the channel width direction. That is, outside the side surface of the oxide 630 in the channel width direction, the conductor 605 and the conductor 660 preferably overlap with each other through an insulator. Alternatively, by providing the conductor 605 to be large, local charging (referred to as charge-up) can be alleviated in a process using plasma in a manufacturing process after the formation of the conductor 605. However, one embodiment of the present invention is not limited thereto. The conductor 605 may overlap with at least the oxide 630 located between the conductor 642a and the conductor 642b.

[0210] Furthermore, it is preferable that, with respect to the bottom surface of insulator 624, the height of the bottom surface of conductor 660 in the area where oxide 630a and oxide 630b do not overlap with conductor 660 is positioned at a lower position than the height of the bottom surface of oxide 630b.

[0211] As shown in FIG. 20B, the conductor 660 functioning as a gate has a structure that covers the side and top surfaces of the oxide 630b in the channel formation region via the oxide 630c and the insulator 650, so that the electric field generated from the conductor 660 can be easily applied to the entire channel formation region generated in the oxide 630b. Therefore, the on-current of the transistor 600 can be increased, and the frequency characteristics can be improved. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the gate (first gate) and the back gate (second gate) is called a surrounded channel (S-channel) structure.

[0212] The conductor 605a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen, and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. The conductor 605b is preferably a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 605 is illustrated as having two layers, it may have a multi-layer structure of three or more layers.

[0213] The insulators 616, 680, 685, and 688 preferably have a lower dielectric constant than the insulator 614. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 616, 680, 685, and 688.

[0214] Furthermore, the insulators 616, 680, 685, and 688 may be formed by a CVD method or an ALD method using a compound gas that does not contain hydrogen atoms or has a small amount of hydrogen atoms. The CVD method may be either a thermal CVD method or a plasma enhanced CVD (PECVD). The ALD method may be either a thermal ALD method or a plasma enhanced ALD (PEALD). However, a film formation method using plasma, such as PECVD or PEALD, is preferable because it is more suitable for mass production.

[0215] In the deposition of the insulating film, a gas having a molecule containing silicon atoms is mainly used as the deposition gas. In order to reduce the hydrogen contained in the insulating film, it is preferable that the molecule containing silicon atoms contains fewer hydrogen atoms, and it is more preferable that the molecule containing silicon atoms does not contain hydrogen atoms. Of course, deposition gases other than the gas having the molecule containing silicon atoms also preferably contain fewer hydrogen atoms, and it is more preferable that they do not contain hydrogen atoms.

[0216] The above silicon-containing molecules are called Si x -R y For example, the functional group R can be at least one of an isocyanate group (-N=C=O), a cyanate group (-OC≡N), a cyano group (-C≡N), a diazo group (=N2), an azide group (-N3), a nitroso group (-NO), and a nitro group (-NO2). For example, 1≦x≦3 and 1≦y≦8 may be satisfied. As such a molecule containing a silicon atom, for example, tetraisocyanate silane, tetracyanate silane, tetracyano silane, hexaisocyanate silane, octaisocyanate silane, etc. can be used. Here, a molecule in which the same type of functional group is bonded to a silicon atom is exemplified, but the present embodiment is not limited to this. A configuration in which different types of functional groups are bonded to a silicon atom may also be used.

[0217] Also, for example, a halogen (Cl, Br, I, or F) may be used as the functional group R. For example, 1≦x≦2 and 1≦y≦6 may be used. For example, tetrachlorosilane (SiCl4), hexachlorodisilane (Si2Cl6), etc. may be used as such a molecule containing a silicon atom. Although an example in which chlorine is used as the functional group has been shown, halogens other than chlorine, such as bromine, iodine, and fluorine, may also be used as the functional group. Also, a different type of halogen may be bonded to the silicon atom.

[0218] The insulator 622 and the insulator 624 function as gate insulators.

[0219] Here, the insulator 624 in contact with the oxide 630 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 624 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced and the reliability of the transistor 600 can be improved.

[0220] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 624. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0221] The insulator 622 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 600 from the substrate side. For example, the insulator 622 preferably has lower hydrogen permeability than the insulator 624. By surrounding the insulator 624 and the oxide 630 with the insulator 622 and the insulator 683, impurities such as water or hydrogen can be prevented from entering the transistor 600 from the outside.

[0222] Furthermore, it is preferable that the insulator 622 has a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). For example, it is preferable that the insulator 622 has lower oxygen permeability than the insulator 624. The insulator 622 is preferable because it has a function of suppressing diffusion of oxygen and impurities, thereby reducing the diffusion of oxygen contained in the oxide 630 below the insulator 622. Furthermore, it is possible to suppress reaction of the conductor 605 with the insulator 624 and oxygen contained in the oxide 630.

[0223] The insulator 622 may be an insulator containing an oxide of one or both of insulating materials, aluminum and hafnium. As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 622 is formed using such a material, the insulator 622 functions as a layer that suppresses release of oxygen from the oxide 630 and the intrusion of impurities such as hydrogen from the periphery of the transistor 600 into the oxide 630.

[0224] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0225] The insulator 622 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0226] The insulator 622 and the insulator 624 may have a layered structure of two or more layers. In that case, the insulators are not limited to a layered structure made of the same material, and may have a layered structure made of different materials.

[0227] Furthermore, the oxide 643 (oxide 643a and oxide 643b) may be disposed between the oxide 630b and the conductor 642 (conductor 642a and conductor 642b) functioning as a source electrode or a drain electrode. Since the conductor 642 and the oxide 630 are not in contact with each other, it is possible to prevent the conductor 642 from absorbing oxygen from the oxide 630. In other words, by preventing the oxidation of the conductor 642, it is possible to prevent a decrease in the conductivity of the conductor 642. Therefore, it is preferable that the oxide 643 has a function of preventing the oxidation of the conductor 642.

[0228] Therefore, the oxide 643 preferably has a function of suppressing oxygen permeation. By disposing the oxide 643 having a function of suppressing oxygen permeation between the conductor 642 functioning as a source electrode or a drain electrode and the oxide 630b, the electrical resistance between the conductor 642 and the oxide 630b can be reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 600 can be improved.

[0229] A metal oxide having element M may be used as the oxide 643. In particular, the element M may be aluminum, gallium, yttrium, or tin. The oxide 643 preferably has a higher concentration of element M than the oxide 630b. Gallium oxide may be used as the oxide 643. A metal oxide such as In-M-Zn oxide may be used as the oxide 643. Specifically, in the metal oxide used for the oxide 643, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 630b. The film thickness of the oxide 643 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. The oxide 643 is preferably crystalline. When the oxide 643 is crystalline, the release of oxygen in the oxide 630 can be suitably suppressed. For example, if the oxide 643 has a crystal structure such as a hexagonal crystal structure, the release of oxygen in the oxide 630 may be suppressed.

[0230] Note that the oxide 643 is not necessarily provided. In that case, when the conductor 642 (conductor 642a and conductor 642b) comes into contact with the oxide 630, oxygen in the oxide 630 may diffuse into the conductor 642, and the conductor 642 may be oxidized. When the conductor 642 is oxidized, the conductivity of the conductor 642 is likely to decrease. Note that the diffusion of oxygen in the oxide 630 into the conductor 642 can be rephrased as the conductor 642 absorbing the oxygen in the oxide 630.

[0231] Furthermore, oxygen in the oxide 630 may diffuse into the conductor 642 (conductor 642a and conductor 642b), forming a foreign layer between the conductor 642a and the oxide 630b and between the conductor 642b and the oxide 630b. Since the foreign layer contains more oxygen than the conductor 642, the foreign layer is presumed to have insulating properties. In this case, the three-layer structure of the conductor 642, the foreign layer, and the oxide 630b can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0232] In addition, the above-mentioned different layer is not limited to being formed between the conductor 642 and the oxide 630b. For example, the different layer may be formed between the conductor 642 and the oxide 630c, between the conductor 642 and the oxide 630b, and between the conductor 642 and the oxide 630c.

[0233] A conductor 642 (a conductor 642a and a conductor 642b) functioning as a source electrode and a drain electrode is provided over the oxide 643. The thickness of the conductor 642 is, for example, 1 nm to 50 nm, preferably 2 nm to 25 nm.

[0234] As the conductor 642, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed.

[0235] The insulator 672 is preferably provided in contact with the top surface of the conductor 642 and functions as a barrier insulating film. Moreover, an insulator 673 functioning as a barrier insulating film is preferably provided over the insulator 672. Such a structure can suppress absorption of excess oxygen contained in the insulator 680 by the conductor 642. Furthermore, suppressing oxidation of the conductor 642 can suppress an increase in contact resistance between the transistor 600 and the wiring. Thus, the transistor 600 can have good electrical characteristics and reliability.

[0236] Therefore, the insulators 672 and 673 preferably have a function of suppressing oxygen diffusion. For example, the insulator 672 preferably has a function of suppressing oxygen diffusion more than the insulator 680. As the insulator 672, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. As the insulator 673, for example, silicon nitride, silicon nitride oxide, or the like may be used.

[0237] Furthermore, it is possible to suppress diffusion of impurities such as water or hydrogen from the insulator 680 or the like disposed between the insulators 672 and 673 to the transistor 600. In this manner, it is preferable to have a structure in which the transistor 600 is surrounded by the insulators 672 and 673, which have a function of suppressing diffusion of impurities such as water or hydrogen, and oxygen.

[0238] The insulator 650 functions as a gate insulator. The insulator 650 is preferably disposed in contact with the upper surface of the oxide 630c. The insulator 650 can be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0239] Like the insulator 624, the insulator 650 is preferably formed using an insulator that releases oxygen when heated. By providing the insulator that releases oxygen when heated as the insulator 650 in contact with the top surface of the oxide 630c, oxygen can be effectively supplied to the channel formation region of the oxide 630b. Similarly to the insulator 624, the concentration of impurities such as water or hydrogen in the insulator 650 is preferably reduced. The thickness of the insulator 650 is preferably 1 nm or more and 20 nm or less.

[0240] Furthermore, a metal oxide may be provided between the insulator 650 and the conductor 660. The metal oxide preferably suppresses oxygen diffusion from the insulator 650 to the conductor 660. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 650 to the conductor 660 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 630 can be suppressed. Furthermore, oxidation of the conductor 660 by oxygen from the insulator 650 can be suppressed.

[0241] Moreover, the metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 650, it is preferable to use a metal oxide that is a high-k material having a high relative dielectric constant. By forming the gate insulator into a laminated structure of the insulator 650 and the metal oxide, it is possible to obtain a laminated structure that is stable against heat and has a high relative dielectric constant. Therefore, it is possible to reduce the gate potential applied during the operation of the transistor while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0242] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0243] Alternatively, the metal oxide may function as a part of the gate. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0244] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate. The conductive material containing the metal element and nitrogen described above may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Or, hydrogen mixed in from an external insulator may be captured.

[0245] Conductor 660 is disposed such that its bottom and side surfaces are in contact with insulator 650. Conductor 660 is shown as having a two-layer structure in Fig. 20B, but may have a single-layer structure or a laminated structure of three or more layers.

[0246] The conductor 660a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0247] Furthermore, since the conductor 660a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 660b caused by oxygen contained in the insulator 650. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0248] The conductor 660b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 660 also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 660b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0249] The insulator 680 is preferably made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating. The insulator 680 may also have a structure in which the above materials are stacked, for example, a stacked structure of silicon oxide formed by sputtering and silicon oxynitride formed by CVD on the silicon oxide. Silicon nitride may also be stacked on top of the silicon oxide.

[0250] Here, the insulator 680 preferably contains excess oxygen. For example, the insulator 680 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing the insulator 680 containing excess oxygen in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced and the reliability of the transistor 600 can be improved. To allow the insulator 680 to contain excess oxygen, for example, the insulator 682 can be formed by a sputtering method in an atmosphere containing oxygen. By forming the insulator 682 by a sputtering method in an atmosphere containing oxygen, oxygen can be added to the insulator 680 during the film formation.

[0251] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 680. In addition, the top surface of the insulator 680 may be planarized.

[0252] The insulator 682 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the insulator 680 from above. The insulator 682 preferably functions as a barrier insulating film that suppresses oxygen transmission. The insulator 682 may be, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 682 may be made of aluminum oxide, which has a high barrier property against oxygen.

[0253] 20B, the insulator 682 is in direct contact with the oxide 630c. This structure can suppress diffusion of oxygen contained in the insulator 680 to the conductor 660. Therefore, oxygen contained in the insulator 680 can be efficiently supplied to the oxide 630a and the oxide 630b through the oxide 630c, thereby reducing oxygen vacancies in the oxide 630a and the oxide 630b and improving the electrical characteristics and reliability of the transistor 600.

[0254] It is preferable to provide an insulator 685 functioning as an interlayer film over the insulator 682. Like the insulator 624, the insulator 685 preferably has a reduced concentration of impurities such as water or hydrogen.

[0255] The conductor 640 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 640 may have a laminated structure. In FIG. 20A, the conductor 640 has a circular shape when viewed from above, but this is not limited to this. For example, the conductor 640 may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners when viewed from above.

[0256] In addition, when the conductor 640 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. In addition, the conductive material having a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen may be used in a single layer or a laminated layer. By using the conductive material, it is possible to further reduce impurities such as water or hydrogen diffusing from the insulator 680 and the like from being mixed into the oxide 630 through the conductor 640. In addition, it is possible to prevent the oxygen added to the insulator 680 from being absorbed by the conductor 640.

[0257] Conductor 646a is disposed in contact with the upper surface of conductor 640a and the upper surface of conductor 640c, and conductor 646b is disposed in contact with the upper surface of conductor 640b. Conductor 646a and conductor 646b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Conductor 646a and conductor 646b may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0258] An insulator 686 is provided to cover the insulator 685, the conductor 646a, and the conductor 646b. The insulator 686 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, or the like, and can be provided as a stacked layer or a single layer.

[0259] For example, a stacked structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material may be used for the insulator 686. With this structure, the capacitor 655 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 655 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitor 655.

[0260] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0261] Alternatively, the insulator 686 may be a single layer or a multilayer insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST). For example, when the insulator 686 is a multilayer, a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide are formed in this order, or a four-layer stack in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are formed in this order may be used. Alternatively, the insulator 686 may be a compound containing hafnium and zirconium. As semiconductor devices become finer and more highly integrated, problems such as leakage current in transistors and capacitors may occur due to the thinning of the gate insulator and the dielectric used in the capacitor. By using a high-k material for the gate insulator and the insulator that functions as the dielectric used in the capacitor, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor while maintaining the physical film thickness.

[0262] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with voids, etc.

[0263] The conductor 656 is arranged to overlap at least a portion of the conductor 646a with the insulator 686 interposed therebetween. The conductor 656 may be any conductor that can be used for the conductor 646.

[0264] It is also preferable to provide an insulator 688 functioning as an interlayer film over the insulator 686 and the conductor 646b. Like the insulator 624, the insulator 688 preferably has a reduced concentration of impurities such as water or hydrogen.

[0265] <<Modification of memory circuit>> In the following, a modified example of the memory circuit will be described with reference to FIG. 21A and FIG. 21B. FIG. 21A is a top view of the memory circuit 860 and its periphery. FIG. 21B is a cross-sectional view of the memory circuit 860, and FIG. 21B corresponds to the portion indicated by the dashed line A1-A2 in FIG. 21A. FIG. 21B shows a cross section of the transistor 600 in the channel length direction and a cross section of the transistor 700 in the channel width direction. Note that in the top view of FIG. 21A, some elements are omitted for clarity. Note that the X direction, Y direction, and Z direction shown in FIG. 21A are directions that are orthogonal or intersect each other. Here, it is preferable that the X direction and the Y direction are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0266] 21A and 21B differs from the memory circuit 860 shown in FIGS. 20A and 20B in that transistors 690 and 790 are used instead of transistors 600 and 700. Here, transistor 790 is formed in the same layer as transistor 690 and has the same configuration. In the following, the components of transistor 790 can be described with reference to the description of the components of transistor 690.

[0267] Transistor 690 differs from transistor 600 in that oxide 630c is formed in a U-shape to fit along openings formed in insulator 680, insulator 672, insulator 673, conductor 642 (conductor 642a, conductor 642b), and oxide 630b.

[0268] For example, when the channel length of the transistor is miniaturized (typically 5 nm or more and less than 60 nm, preferably 10 nm or more and 30 nm or less), the effective L length can be increased by the transistor 600 having the above structure. As an example, when the distance between the conductor 642a and the conductor 642b is 20 nm, the effective L length can be increased to 40 nm or more and 60 nm or less, which is about two to three times longer than the distance between the conductor 642a and the conductor 642b, i.e., the minimum processing dimension. Therefore, the memory circuit 860 shown in FIGS. 21A and 21B has a structure including the transistor 690, the transistor 790, and the capacitor 655, which are excellent in miniaturization.

[0269] <<Metal oxides>> A metal oxide that functions as an oxide semiconductor is preferably used as the oxide 630. Metal oxides that can be used as the oxide 630 according to the present invention will be described below.

[0270] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0271] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, there are cases where the element M may be a combination of multiple elements mentioned above.

[0272] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0273] [Metal oxide composition] Here, as an example of a metal oxide configuration, CAC-OS (Cloud-Aligned Composite Oxide Semiconductor) or CAC-metal oxide will be described.

[0274] CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) as carriers, and the insulating function is a function of not flowing electrons as carriers. By making the conductive function and the insulating function act complementarily, it is possible to impart a switching function (on / off function) to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, it is possible to maximize both functions.

[0275] Moreover, the CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected in a cloud shape with a blurred periphery.

[0276] In addition, in the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may each be dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

[0277] Also, the CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this configuration, when carriers are caused to flow, the carriers mainly flow in the component having the narrow gap. Also, the component having the narrow gap acts complementarily on the component having the wide gap, and carriers also flow in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on-state of the transistor.

[0278] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0279] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0280] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of crystal structures in oxide semiconductors will be described with reference to Fig. 26A. Fig. 26A is a diagram for explaining the classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0281] As shown in Figure 26A, IGZO is roughly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes CAAC, nc, and CAC. Crystal includes single crystal and poly crystal.

[0282] The structure in the bold frame in Fig. 26A belongs to the new crystalline phase. This structure is in the boundary region between amorphous and crystalline. In other words, this structure is completely different from the energetically unstable amorphous and crystalline.

[0283] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) image. Here, XRD spectra of quartz glass and IGZO (also called crystalline IGZO) having a crystal structure classified as Crystalline are shown in Fig. 26B and Fig. 26C. Fig. 26B shows the XRD spectrum of quartz glass, and Fig. 26C shows the XRD spectrum of crystalline IGZO. The crystalline IGZO shown in Fig. 26C has a composition of In:Ga:Zn=4:2:3 [atomic ratio]. The crystalline IGZO shown in Fig. 26C has a thickness of 500 nm.

[0284] As shown by the arrows in Figure 26B, the peaks in the XRD spectrum of silica glass are nearly symmetric. On the other hand, as shown by the arrows in Figure 26C, the peaks in the XRD spectrum of crystalline IGZO are asymmetric. The asymmetric peaks in the XRD spectrum clearly indicate the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetric, it cannot be said to be amorphous.

[0285] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a portion where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0286] Nanocrystals are basically hexagonal, but may be non-regular hexagonal. In addition, the lattice arrangement may be pentagonal or heptagonal due to the distortion. In CAAC-OS, it is difficult to confirm clear grain boundaries even near the distortion. In other words, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of dense arrangement of oxygen atoms in the ab-plane direction and the change in the bond distance between atoms due to the substitution of metal elements.

[0287] A crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor or a decrease in field-effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. A structure containing Zn is preferable for forming a CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0288] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M can be substituted for each other, and when element M in an (M, Zn) layer is substituted for indium, it can also be expressed as an (In, M, Zn) layer. When indium in an In layer is substituted for element M, it can also be expressed as an (In, M) layer.

[0289] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is difficult to confirm clear crystal boundaries in CAAC-OS, so it can be said that the decrease in electron mobility caused by crystal boundaries is unlikely to occur. In addition, since the crystallinity of metal oxides can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be a metal oxide with few impurities and defects (oxygen vacancies, etc.). Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0290] The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0291] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, may have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty in crystal growth in the atmosphere, it may be structurally more stable when made into small crystals (for example, the above-mentioned nanocrystals) rather than large crystals (here, crystals of several mm or several cm).

[0292] The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0293] Oxide semiconductors (metal oxides) have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0294] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0295] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are included in the channel formation region, the transistor is likely to have normally-on characteristics.

[0296] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0297] Furthermore, when impurities are present in a channel formation region of an oxide semiconductor, the crystallinity of the channel formation region may be reduced, or the crystallinity of an oxide provided in contact with the channel formation region may be reduced. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to be degraded. When the crystallinity of an oxide provided in contact with the channel formation region is low, an interface state may be formed, which may degrade the stability or reliability of the transistor.

[0298] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the concentration of impurities in the channel formation region of the oxide semiconductor and in its vicinity. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0299] Specifically, the concentration of the impurities in the channel formation region of the oxide semiconductor and its vicinity, which is obtained by SIMS, is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 or less. Alternatively, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity, which is obtained by elemental analysis using EDX, is set to 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the concentration of the impurity is calculated, or may be the concentration in the oxide semiconductor.

[0300] Furthermore, since a metal oxide with a reduced impurity concentration has a low defect state density, the trap state density may also be low.

[0301] In addition, when hydrogen enters an oxygen vacancy in a metal oxide, the oxygen vacancy and hydrogen combine to form V O May form H. V O H can act as a donor, generating carrier electrons, and some of the hydrogen can combine with oxygen, which in turn combines with metal atoms, generating carrier electrons.

[0302] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. In addition, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field, and therefore, when an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.

[0303] That is, V in metal oxide O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (sometimes referred to as oxygen addition treatment). O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0304] In addition, it is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. In order to reduce the carrier concentration of an oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as being highly pure intrinsic or substantially highly pure intrinsic. Examples of impurities in an oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0305] In particular, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in a channel formation region in an oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond to oxygen that is bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

[0306] A defect in which hydrogen has entered an oxygen vacancy (V O H) can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Thus, in an oxide semiconductor, evaluation may be performed using the carrier concentration instead of the donor concentration. Thus, in this specification and the like, as a parameter of an oxide semiconductor, the carrier concentration assuming a state in which no electric field is applied may be used instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

[0307] Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0308] The carrier concentration of the oxide semiconductor in the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0309] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0310] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 630 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide 630. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material, a two-dimensional material, or the like) is preferably used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0311] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0312] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0313] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 630. Specific examples of transition metal chalcogenides that can be used as the oxide 630 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0314] <Example of memory circuit layout> Next, an example of the arrangement of the memory circuit 860 described above will be described with reference to FIG. 22 and FIG. 23. FIG. 22 and FIG. 23 show a memory circuit block in which 2×2×2 pieces of the memory circuits 860 described above are arranged. FIG. 22 is a top view of the memory circuit block. FIG. 23 is a cross-sectional view of the memory circuit block, and FIG. 23 corresponds to the portion shown by the dashed line B1-B2 in FIG. 22. FIG. 23 shows a cross section of the transistor 600 in the channel length direction and a cross section of the transistor 700 in the channel width direction. Note that in the top view of FIG. 22, some elements are omitted for clarity. Note that the X direction, Y direction, and Z direction shown in FIG. 22 are directions that are orthogonal to or intersect each other. Here, it is preferable that the X direction and the Y direction are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0315] 22 and 23, a memory circuit 860_2 is arranged adjacent to the memory circuit 860_1 in the X direction. Further, memory circuits 860_3 and 860_4 are arranged adjacent to the memory circuits 860_1 and 860_2 in the Y direction. Further, memory circuits 860_5 and 860_6 are arranged adjacent to the memory circuits 860_1 and 860_2 in the Z direction.

[0316] As shown in FIG. 22 and FIG. 23, the components of the memory circuits 860_1 and 860_2 can be arranged in line symmetry. In this case, it is preferable that the side of the conductor 640b contacts the conductor 642b of the memory circuit 860_1 and the conductor 642b of the memory circuit 860_2. In other words, it is preferable that the conductor 607, the conductor 615, the conductor 640b, the conductor 646b, and the conductor 657 functioning as the bit line WBL are electrically connected to one of the source and drain of the transistor 600 of the memory circuit 860_1 and one of the source and drain of the transistor 600 of the memory circuit 860_2. In this way, by sharing the wiring connected to the memory circuits 860_1 and 860_2, the area occupied by the memory circuits can be further reduced.

[0317] As shown in FIG. 23, the conductors 607, 615, 640b, 646b, and 657 functioning as the write bit lines WBL are also electrically connected to the transistors 600 of the memory circuits 860_5 and 860_6 arranged in the upper layer. As shown in FIG. 23, the conductors 657 of the memory circuits 860_1 and 860_2 correspond to the conductors 607 of the memory circuits 860_5 and 860_6. In this manner, the bit lines WBL can be extended in the Z direction. Although not shown in the cross-sectional view, the conductors 640d and the like functioning as the read bit lines RBL can also be extended in the Z direction.

[0318] 22, the conductor 660 of the memory circuit 860_1 is provided so as to extend to the memory circuit 860_3. In this manner, the word line WWL can be extended in the Y direction. In addition, as shown in FIG. 22, the conductor 742a of the memory circuit 860_1 is provided so as to extend to the memory circuit 860_3. In this manner, the selection line SL can be extended in the Y direction. The selection line SL may be shared with the memory circuit 860 adjacent in the X direction. In addition, as shown in FIG. 22, the conductor 605 of the memory circuit 860_1 is provided so as to extend to the memory circuit 860_3. In this manner, the wiring BGL1 can be extended in the Y direction. In addition, as shown in FIG. 22, the conductor 705 of the memory circuit 860_1 is provided so as to extend to the memory circuit 860_3. In this manner, the wiring BGL1 can be extended in the Y direction.

[0319] 22, the oxide 630c extends to overlap the conductor 660; however, the semiconductor device described in this embodiment is not limited to this. For example, the oxide 630c may be patterned for each memory circuit 860, and the oxide 630c may be provided separately for each transistor 600. In addition, for example, when the oxide 630c has a two-layer stacked structure, either the upper layer or the lower layer of the oxide 630c may be provided separately for each transistor 600.

[0320] <Example of semiconductor device configuration> Next, an example of a semiconductor device in which the above-mentioned memory circuits 860 are stacked will be described with reference to Fig. 24. Fig. 24 is a cross-sectional view of a semiconductor device in which a plurality of memory circuit layers 870 including memory circuits 860 are stacked on a silicon layer 871. The semiconductor device shown in Fig. 24 corresponds to the accelerator 20 shown in Fig. 1 etc., the silicon layer 871 corresponds to the arithmetic processing unit 21, and the memory circuit layer 870 corresponds to the memory unit 22.

[0321] First, a description will be given of the silicon layer 871. A plurality of transistors 800 are provided in the silicon layer 871, and constitute the arithmetic circuit 23 shown in FIG.

[0322] The transistor 800 is provided over a substrate 811 and includes a conductor 816 functioning as a gate, an insulator 815 functioning as a gate insulator, a semiconductor region 813 formed of a part of the substrate 811, and low-resistance regions 814a and 814b functioning as source and drain regions. The transistor 800 may be either a p-channel type or an n-channel type.

[0323] Here, in the transistor 800 shown in FIG. 24, a semiconductor region 813 (a part of a substrate 811) in which a channel is formed has a convex shape. A conductor 816 is provided so as to cover the side and top surface of the semiconductor region 813 via an insulator 815. Note that the conductor 816 may be made of a material that adjusts the work function. Such a transistor 800 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that is in contact with an upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0324] Note that the transistor 800 illustrated in FIG. 24 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0325] In addition, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. In addition, a plurality of wiring layers may be provided according to the design. Here, a conductor having a function as a plug or wiring may be collectively given the same symbol as a plurality of structures. In addition, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring and cases where a part of the conductor functions as the plug.

[0326] For example, an insulator 820, an insulator 822, an insulator 824, and an insulator 826 are stacked in this order as an interlayer film over the transistor 800. A conductor 828, a conductor 830, and the like which function as a plug or a wiring are embedded in the insulator 820, the insulator 822, the insulator 824, and the insulator 826.

[0327] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 822 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0328] A wiring layer may be provided over the insulator 826 and the conductor 830. For example, in FIG. 24, an insulator 850, an insulator 852, and an insulator 854 are stacked in this order. A conductor 856 is formed in the insulator 850, the insulator 852, and the insulator 854. The conductor 856 functions as a plug or a wiring.

[0329] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0330] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0331] For example, the insulator 820, the insulator 822, the insulator 826, the insulator 852, the insulator 854, and the like preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen has been added, or silicon oxide having voids, and a resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with a resin to form a laminated structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, and the like), polyimide, polycarbonate, and acrylic.

[0332] Furthermore, when a transistor including an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stabilized. Therefore, an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen may be used for the insulator 824, the insulator 850, and the like.

[0333] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0334] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0335] For example, the conductor 828, the conductor 830, the conductor 856, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form the conductor from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0336] An insulator 611 and an insulator 612 are disposed over a silicon layer 871, and memory circuit layers 870_1 to 870_n are stacked over the insulators 611 and 612. Note that the value of n is not particularly limited, but is 2 to 200, preferably 2 to 100, and more preferably 2 to 10. For example, 1≦n≦10, preferably 1≦n≦50, and more preferably 1≦n≦100.

[0337] In each memory circuit layer 870, memory circuits 860 and various wirings are arranged in a matrix, similar to Fig. 22. Moreover, each memory circuit layer 870 adjacent in the stacking direction is electrically connected by wirings such as write bit lines WBL, as shown in Fig. 23.

[0338] 24, in the bottom memory circuit layer 870_1, a conductor 607 is disposed so as to be embedded in an insulator 611 and an insulator 612. The conductor 607 is in contact with a conductor 857 provided in the same layer as the conductor 856.

[0339] In addition, the memory circuit layers 870_1 to 870_n are preferably sealed with an insulator 611, an insulator 612, an insulator 687, an insulator 683, and an insulator 684. Here, the insulator 611 is disposed on the silicon layer 871, and the insulator 612 is disposed on the insulator 611. The memory circuit layers 870_1 to 870_n are disposed on the insulator 612, and the insulator 612 is also formed in the same pattern as the memory circuit layers 870_1 to 870_n when viewed from above. The insulator 687 is disposed in contact with the upper surface of the insulator 611, the side surface of the insulator 612, and the side surface of the memory circuit layers 870_1 to 870_n. That is, the insulator 687 is formed in a sidewall shape with respect to the memory circuit layers 870_1 to 870_n. An insulator 683 is disposed to cover the insulator 611, the insulator 687, and the memory circuit layers 870_1 to 870_n. Further, an insulator 684 is disposed to cover the insulator 683.

[0340] It is preferable that insulators 611, 612, 687, 683, and 684 be made of a barrier material, similar to insulator 682 and the like.

[0341] Here, each memory circuit layer 870 is sealed by an insulator 687 and an insulator 683. It is preferable to use the same material for the insulators 687 and 683. It is also preferable to form the insulators 687 and 683 under the same conditions. When the insulators 687 and 683, which have the same film quality, are in contact with each other, a sealing structure with high airtightness can be obtained.

[0342] A material capable of capturing and fixing hydrogen is preferably used for the insulators 687 and 683. Specifically, a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide can be used.

[0343] Furthermore, the insulator 687 and the insulator 683 , which are structures that seal the memory circuit layer 870 , are further covered with an insulator 684 .

[0344] A material having a function of suppressing diffusion of hydrogen and oxygen is preferably used for the insulators 611, 612, and 683. In particular, silicon nitride or silicon nitride oxide is preferably used as a sealing material because it has high barrier properties against hydrogen.

[0345] An insulator 684 with high coverage is preferably provided above an insulator 683 covering the upper side of the transistor 600. Note that the insulator 684 is preferably made of the same material as the insulators 612 and 683.

[0346] For example, the insulators 612 and 683 can be formed by a sputtering method, whereby a sealing structure can be provided using a film having a relatively low hydrogen concentration.

[0347] On the other hand, a film formed by a sputtering method has a relatively low coverage. Therefore, by forming the insulators 611 and 684 by a CVD method or the like which has a high coverage, the sealing performance can be improved.

[0348] Therefore, it is preferable that insulators 612 and 683 have a lower hydrogen concentration than insulators 611 and 684.

[0349] In this manner, by sealing the memory circuit layers 870_1 to 870_n with a barrier insulating film, hydrogen diffusing into the oxide semiconductor included in each memory circuit 860 can be reduced, and a highly reliable memory device can be provided.

[0350] Preferably, a material having a barrier property against oxygen may be used for the insulators 611, 612, 682, 687, 683, and 684. When the sealing structure has a barrier property against oxygen, the outward diffusion of excess oxygen contained in the insulator 680 can be suppressed and the excess oxygen can be efficiently supplied to the transistor 600.

[0351] An insulator 674 is preferably provided to bury the memory circuit layers 870_1 to 870_n and the insulator 684. The insulator 674 may be any insulator that can be used for the insulator 680. As shown in FIG. 24, the insulators 674 and 684 preferably have approximately the same height at their top surfaces.

[0352] 24, openings may be provided in the insulators 674, 684, 683, and 611, and a conductor 876 may be disposed in the opening. The bottom surface of the conductor 876 is in contact with the conductor 856. A conductor 878 that functions as a wiring may be provided in contact with the top surface of the conductor 876. It is also preferable to provide an insulator 689 that functions as an interlayer film, covering the memory circuit layer 870_n, the insulator 674, and the conductor 878. With this structure, the upper wiring (conductor 878) and the circuit of the silicon layer 871 can be electrically connected without going through the memory circuit layer 870.

[0353] 24 shows a configuration in which the memory circuit layers 870_1 to 870_n are collectively sealed with the insulators 611, 612, 687, 683, and 684, but the semiconductor device according to the present embodiment is not limited to this. For example, as shown in FIG. 25, each memory circuit layer 870 may be sealed with the insulators 611, 612, 687, 683, and 684.

[0354] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0355] (Embodiment 5) In this embodiment, the configuration of an integrated circuit including the configuration of the semiconductor device 100 described in the above embodiment will be described with reference to FIGS.

[0356] FIG. 27 is an example of a block diagram for explaining an example of the configuration of an integrated circuit including the configuration of the semiconductor device 100.

[0357] The integrated circuit 390 shown in FIG. 27 includes a CPU 10, an accelerator 20, an on-chip memory 131, a DMAC (Direct Memory Access Controller) 141, a power supply circuit 160, a power management unit (PMU) 142, a security circuit 147, a memory controller 143, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) controller 144, a USB (Universal Serial Bus) interface circuit 145, a display interface circuit 146, a bridge circuit 150, an interrupt control circuit 151, an interface circuit 152, a battery control circuit 153, and an ADC (Analog-to-digital converter) / DAC (Digital-to-analog converter) interface circuit 154.

[0358] The CPU 10 includes, for example, a CPU core 111, an instruction cache 112, a data cache 113, and a bus interface circuit 114. The accelerator 20 includes a memory circuit 121, an arithmetic circuit 122, and a control circuit 123.

[0359] The CPU core 111 has multiple CPU cores. The instruction cache 112 may be a circuit configuration that temporarily stores instructions to be executed by the CPU core 111. The data cache 113 may be a circuit configuration that temporarily stores data to be processed by the CPU core 111 or data obtained by the processing. The bus interface circuit 114 may be a circuit configuration that can transmit and receive signals such as data and addresses to and from a bus that connects the CPU 10 to other circuits in the semiconductor device.

[0360] The memory circuit 121 corresponds to a configuration including the memory circuit 24 described in the first embodiment. The memory circuit 121 may have a circuit configuration for storing data to be processed by the accelerator 20. The arithmetic circuit 122 corresponds to a configuration including the arithmetic circuit 23 described in the first embodiment. The arithmetic circuit 122 may have a circuit configuration for performing arithmetic processing of data held in the memory circuit 121. The control circuit 123 may have a circuit configuration for controlling each circuit in the accelerator 20, as shown in FIG. 14B.

[0361] The high-speed bus 140A is a bus for transmitting and receiving various signals at high speed between the CPU 10, the accelerator 20, the on-chip memory 131, the DMAC 141, the power management unit 142, the security circuit 147, the memory controller 143, the DDR SDRAM controller 144, the USB interface circuit 145, and the display interface circuit 146. As an example, an AMBA (Advanced Microcontroller Bus Architecture)-AHB (Advanced High-performance Bus) can be used as the bus.

[0362] The on-chip memory 131 has a circuit configuration for storing data or programs to be input / output to / from the circuitry included in the integrated circuit 390, such as the CPU 10 or the accelerator 20.

[0363] The DMAC 141 is a direct memory access controller. By including the DMAC 141, peripheral devices other than the CPU 10 can access the on-chip memory 131 without going through the CPU 10.

[0364] The power management unit 142 has a circuit configuration for controlling power gating of circuits such as a CPU core included in the integrated circuit 390.

[0365] The security circuit 147 has a circuit configuration for enhancing the confidentiality of signals, such as by encrypting signals before transmitting and receiving signals between the integrated circuit 390 and an external circuit.

[0366] The memory controller 143 has circuitry for writing or reading a program to be executed by the CPU 10 or the accelerator 20 from a program memory external to the integrated circuit 390 .

[0367] The DDR SDRAM controller 144 includes circuitry for reading and writing data to and from a main memory, such as a DRAM, external to the integrated circuit 390 .

[0368] The USB interface circuit 145 has a circuit configuration for transmitting and receiving data to and from a circuit external to the integrated circuit 390 via a USB terminal.

[0369] The display interface circuit 146 comprises circuitry for sending and receiving data to and from a display device external to the integrated circuit 390 .

[0370] The power supply circuit 160 is a circuit for generating a voltage used in the integrated circuit 390. For example, it is a circuit for generating a negative voltage to be applied to the back gate of an OS transistor in order to stabilize the electrical characteristics.

[0371] The low-speed bus 140B is a bus for transmitting and receiving various signals at low speed between the interrupt control circuit 151, the interface circuit 152, the battery control circuit 153, and the ADC / DAC interface circuit 154. As an example, an AMBA-APB (Advanced Peripheral Bus) can be used as the bus. Various signals are transmitted and received between the high-speed bus 140A and the low-speed bus 140B via a bridge circuit 150.

[0372] The interrupt control circuit 151 has a circuit configuration for carrying out interrupt processing in response to a request received from a peripheral device.

[0373] The interface circuit 152 has a circuit configuration for operating interfaces such as a universal asynchronous receiver / transmitter (UART), an inter-integrated circuit (I2C), or a serial peripheral interface (SPI).

[0374] The battery control circuit 153 has circuitry for transmitting and receiving data relating to charging and discharging of the battery external to the integrated circuit 390 .

[0375] The ADC / DAC interface circuit 154 has a circuit configuration for transmitting and receiving data to and from a device that outputs an analog signal, such as a MEMS (Micro Electro Mechanical Systems) device, located outside the integrated circuit 390 .

[0376] 28A and 28B are diagrams showing an example of the layout of circuit blocks when implemented as an SoC. As in the integrated circuit 390 shown in FIG. 28A, each configuration shown in the block diagram of FIG. 27 can be arranged in separate regions on a chip.

[0377] 27 can be configured with a memory circuit configured with OS transistors, such as NOSRAM. That is, the on-chip memory 131 and the memory circuit 121 have the same circuit configuration. Therefore, when fabricated into an SoC, the on-chip memory 131 and the memory circuit 121 can be integrated and arranged in the same area, as in the integrated circuit 390E illustrated in FIG. 28B.

[0378] According to the above-described embodiment of the present invention, a novel semiconductor device and electronic device can be provided. According to another embodiment of the present invention, a semiconductor device and electronic device with low power consumption can be provided. According to another embodiment of the present invention, a semiconductor device and electronic device in which heat generation can be suppressed can be provided.

[0379] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0380] (Embodiment 6) In this embodiment mode, an electronic device, a mobile object, and a computing system to which the integrated circuit 390 described in the above embodiment mode can be applied will be described with reference to FIGS. 29A to 32. FIG.

[0381] Fig. 29A shows an external view of an automobile as an example of a moving body. Fig. 29B shows a simplified diagram of data exchange within the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also includes various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.

[0382] In an automobile 590, the above-mentioned integrated circuit 390 can be used for a camera 591, etc. In the automobile 590, a plurality of images obtained by a camera 591 in a plurality of imaging directions 592 are processed by the integrated circuit 390 described in the above embodiment, and the plurality of images are collectively analyzed by a host controller 594, etc. via a bus 593, etc., so that the automobile 590 can determine the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and perform automatic driving. The automobile 590 can also be used in a system that performs road guidance, hazard prediction, etc.

[0383] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0384] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, a moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc., and a computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0385] Fig. 30A is an external view showing an example of a portable electronic device. Fig. 30B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0386] In portable electronic device 595, the integrated circuit 390 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by speaker 597, camera 598, microphone 599, etc., using integrated circuit 390 described in the above embodiment. Also, the portable electronic device can be used in a system that performs voice guidance, image search, etc.

[0387] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0388] A portable game machine 1100 shown in FIG. 31A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are removable. By attaching the connection unit 1105 provided in the housing 1101 to the housing 1108, a video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated to function as an operation unit. The integrated circuit 390 described in the above embodiment can be incorporated in a chip provided on a substrate of the housings 1102 and 1103.

[0389] 31B shows a stick-type electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated in the controller chip 1126 of the board 1124, etc.

[0390] 31C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the integrated circuit 390 shown in the previous embodiment can be incorporated into the control circuit 2110.

[0391] The integrated circuit 390 described in the above embodiment can be used in a server that communicates with the electronic device instead of being built into the electronic device. In this case, the electronic device and the server constitute a computing system. Figure 32 shows an example of the configuration of a system 3000.

[0392] The system 3000 is configured with an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via an Internet line 3003.

[0393] Server 3002 has a plurality of racks 3004. A plurality of boards 3005 are provided in the plurality of racks, and integrated circuits 390 described in the above embodiment can be mounted on the boards 3005. This forms a neural network in server 3002. Server 3002 can perform neural network calculations using data input from electronic device 3001 via internet line 3003. Results of calculations by server 3002 can be transmitted to electronic device 3001 via internet line 3003 as necessary. This can reduce the calculation load on electronic device 3001.

[0394] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0395] (Additional notes regarding the present specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0396] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments or examples to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0397] In addition, the content (or a part of the content) described in one embodiment can be applied to, combined with, or replaced by another content (or a part of the content) described in that embodiment, and / or the content (or a part of the content) described in one or more other embodiments.

[0398] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0399] In addition, a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and / or with a figure (or a part of it) described in one or more other embodiments to form even more figures.

[0400] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0401] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0402] In addition, the positional relationship of components shown in the drawings is relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" that indicate the positional relationship may be used for convenience. The positional relationship of components is not limited to the contents described in this specification, and can be rephrased appropriately depending on the situation.

[0403] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is used as the "other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. The source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, etc. depending on the situation.

[0404] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0405] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0406] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0407] In this specification, A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection in which an electrical signal between A and B can be transmitted when an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring) exists between A and B. Note that when A and B are electrically connected, this includes a case in which A and B are directly connected. Here, A and B are directly connected means a connection in which an electrical signal between A and B can be transmitted through wiring (or electrodes) between A and B without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

[0408] In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0409] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between the source and drain in a region where a channel is formed.

[0410] In this specification, the channel width refers to, for example, the length of the region where a semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap, or the length of the portion where a source and a drain face each other in a region in which a channel is formed.

[0411] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". [Explanation of symbols]

[0412] BGL1: wiring, C11: capacitance element, CK1: node, D1: node, GCLK1: clock signal, I1: input layer, M1: middle layer, M3: middle layer, M11: transistor, M12: transistor, M13: transistor, O1: output layer, PSE0: signal, PSE1: signal, PSE2: signal, Q_N: output signal, Q_1: output signal, Q1: node, RBL_N: read bit line, RBL_1: read bit line, RWL_M: read word line, RWL_1: read word line, SLEEP1: signal, SN11: node, SW_N: switch, SW_1: switch ,SW1: transistor, t1: time, t2: time, t3: time, t4: time, t5: time, t6: time, t7: time, WBL_1: write bit line, WWL_M: write word line, WWL_1: write word line, 10: CPU, 20: accelerator, 21: arithmetic processing unit, 22: memory unit, 22_N: memory circuit layer, 22_1: memory circuit layer, 22_2: memory circuit layer, 23: arithmetic circuit, 23_N: arithmetic circuit, 23_1: arithmetic circuit, 24: memory circuit, 24_N: memory circuit, 24_P: memory circuit, 24A: memory circuit, 24B: memory circuit, 24C: : memory circuit, 24D: memory circuit, 24E: memory circuit, 25: transistor, 25_N: transistor, 25_P: transistor, 25A: transistor, 25B: transistor, 26: transistor, 26_N: transistor, 26_P: transistor, 26B: transistor, 27: transistor, 27_N: transistor, 27_P: transistor, 28: capacitance element, 28_N: capacitance element, 28_P: capacitance element, 28A: capacitance element, 28B: capacitance element, 29: semiconductor layer, 30: bus, 31: wiring, 32: transistor, 33A: transistor, 33B: transistor, 34: antenna, 35: driver circuit, 36A: insulator, 36B: insulator, 41: readout circuit, 42: bit sum-of-products calculator, 43: accumulator, 44: latch circuit, 45: encoding circuit, 46: inverter circuit, 47: logic circuit, 50: neuron, 51: layer, 52: layer, 53: layer, 54: layer, 61: controller, 62: row decoder, 63: word line driver, 64: column decoder, 65: driver, 66: precharge circuit, 67: sense amplifier, 68: selector, 71: input buffer, 72: arithmetic control circuit, 76: WA,100: semiconductor device, 110: drive circuit layer, 111: CPU core, 112: instruction cache, 113: data cache, 114: bus interface circuit, 121: memory circuit, 122: arithmetic circuit, 123: control circuit, 131: on-chip memory, 140A: high-speed bus, 140B: low-speed bus, 141: DMAC, 142: power management unit, 143: memory controller, 144: controller, 145: interface circuit, 146: display interface circuit, 147: security circuit, 150: bridge circuit, 15 1: control circuit, 152: interface circuit, 153: battery control circuit, 154: interface circuit, 160: power supply circuit, 193: PMU, 200: CPU core, 202: cache memory device, 203: cache memory device, 205: bus interface unit, 210: power switch, 211: power switch, 212: power switch, 214: level shifter, 220: flip-flop, 221: scan flip-flop, 221A: clock buffer circuit, 222: backup circuit, 390: integrated circuit, 390E: integrated circuit, 590: automobile, 591: camera, 592: imaging direction, 593: bus, 594: host controller, 595: portable electronic device, 596: printed wiring board, 597: speaker, 598: camera, 599: microphone, 600: transistor, 605: conductor, 605a: conductor, 605b: conductor, 607: conductor, 611: insulator, 612: insulator, 614: insulator, 615: conductor, 616: insulator, 622: insulator, 624: insulator, 630: oxide, 630a: oxide, 630b: oxide, 630c: oxide, 640: conductor, 640a : conductor, 640b: conductor, 640c: conductor, 640d: conductor, 642: conductor, 642a: conductor, 642b: conductor, 643: oxide, 643a: oxide, 643b: oxide, 646: conductor, 646a: conductor, 646b: conductor, 650: insulator, 655: capacitance element, 656: conductor, 657: conductor, 660: conductor, 660a: conductor, 660b: conductor, 672: insulator, 673: insulator, 674: insulator, 680: insulator, 682: insulator, 683: insulator, 684: insulator, 685: insulator, 686: insulator, 687: insulator,688: insulator, 689: insulator, 690: transistor, 700: transistor, 705: conductor, 705a: conductor, 705b: conductor, 715: conductor, 730: oxide, 730a: oxide, 730b: oxide, 730c: oxide, 742: conductor, 742a: conductor, 742b: conductor, 743: oxide, 743a: oxide, 743b: oxide, 750: insulator, 760: conductor, 760a: conductor, 760b: conductor, 7 90: transistor, 800: transistor, 811: substrate, 813: semiconductor region, 814a: low resistance region, 814b: low resistance region, 815: insulator, 816: conductor, 820: insulator, 822: insulator, 824: insulator, 826: insulator, 828: conductor, 830: conductor, 850: insulator, 852: insulator, 854: insulator, 856: conductor, 857: conductor, 860: memory circuit, 860_1: memory circuit, 860_2: memory memory circuit, 860_3: ​​memory circuit, 860_4: memory circuit, 860_5: memory circuit, 860_6: memory circuit, 870: memory circuit layer, 870_n: memory circuit layer, 870_1: memory circuit layer, 871: silicon layer, 876: conductor, 878: conductor, 1100: portable game machine, 1101: housing, 1102: housing, 1103: housing, 1104: display unit, 1105: connection unit, 1107: operation keys, 1108: housing, 1109: housing Body, 1120: electronic device, 1121: housing, 1122: cap, 1123: USB connector, 1124: board, 1125: memory chip, 1126: controller chip, 1130: robot, 2101: sensor, 2106: sensor, 2110: control circuit, 3000: system, 3001: electronic device, 3002: server, 3003: internet line, 3004: rack, 3005: board, 3210: WA, 7654: WA,

Claims

1. The present invention has a CPU and an accelerator, the accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit; the first memory circuit includes a first transistor; the second memory circuit includes a second transistor; each of the first transistor and the second transistor has a semiconductor layer having a metal oxide in a channel formation region; the arithmetic circuit includes a third transistor; the third transistor has a semiconductor layer having silicon in a channel formation region; The CPU has a CPU core having a flip-flop provided with a backup circuit, the backup circuit includes a fourth transistor; the fourth transistor has a semiconductor layer having a metal oxide in a channel formation region; a transistor density of the second memory circuit is higher than a transistor density of the first memory circuit; a channel length direction of the transistor of the first memory circuit is parallel to an upper surface of a substrate; a channel length direction of the transistor of the second memory circuit is perpendicular to an upper surface of the substrate; a layer having the second transistor is provided on a layer having the first transistor; A semiconductor device, wherein a layer having the first transistor and a layer having the second transistor are provided on a layer having the third transistor.

2. In claim 1, The backup circuit has a function of retaining the data retained in the flip-flop in a state where the supply of a power supply voltage is stopped when the CPU is power-gated.

3. In claim 1 or 2, The first memory circuit and the second memory circuit have a function of holding data input to the arithmetic circuit.

4. In any one of claims 1 to 3, The second memory circuit has a circuit configuration different from that of the first memory circuit.

5. The present invention has a CPU and an accelerator, the accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit; the first memory circuit includes a first transistor; the second memory circuit includes a second transistor; each of the first transistor and the second transistor has a semiconductor layer having a metal oxide in a channel formation region; the arithmetic circuit includes a third transistor; the third transistor has a semiconductor layer having silicon in a channel formation region; a transistor density of the second memory circuit is higher than a transistor density of the first memory circuit; a channel length direction of the transistor of the first memory circuit is parallel to an upper surface of a substrate; a channel length direction of the transistor of the second memory circuit is perpendicular to an upper surface of the substrate; a layer having the first transistor is provided on a layer having the third transistor; a layer having the second transistor is provided on a layer having the first transistor; The first memory circuit has a data retention characteristic different from that of the second memory circuit.

6. In claim 5, The first memory circuit has a function of holding data input to the arithmetic circuit or data output from the arithmetic circuit.

7. In claim 5 or 6, A semiconductor device, wherein an amplitude voltage for driving the first transistor is smaller than an amplitude voltage for driving the second transistor.

8. In any one of claims 5 to 7, a thickness of a gate insulating film of the first transistor is smaller than a thickness of a gate insulating film of the second transistor.

9. In any one of claims 5 to 8, The second memory circuit has a circuit configuration different from that of the first memory circuit.

10. In any one of claims 1 to 9, The semiconductor device, wherein the arithmetic circuit is a circuit that performs a product-sum operation.

11. In any one of claims 1 to 10, The metal oxide comprises In, Ga, and Zn.

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