Method for manufacturing semiconductor element and semiconductor device

Abstract

To provide a manufacturing method of a semiconductor element, capable of reducing damages of a base substrate and a semiconductor layer when separating the semiconductor layer from the base substrate, manufacturing a semiconductor element with a high quality, and improving a production efficiency of the semiconductor element.SOLUTION: In a semiconductor element, a first semiconductor part SL1 includes a convex part TS projected toward a base substrate UK. The convex part contains a nitride semiconductor, and is bonded to the base substrate. A semiconductor substrate HK includes a hollow part TK positioned to between the base substrate and a first semiconductor part. The hollow part is contacted to a side surface of the convex part, and is communicated to an external part of the semiconductor substrate. A manufacturing method of the semiconductor element, performs an irradiation of a laser beam LZ to the convex part TS before the first semiconductor part is separated from the semiconductor substrate, and performs an anisotropic etching that is progressed to an inner part from the side surface of the convex part. Since the width of the convex part TS is smaller than the width of the first semiconductor part, the first semiconductor part can be easily separated from the base substrate UK.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In a method for manufacturing a semiconductor device, various techniques have been proposed for separating a semiconductor layer formed on a substrate from the substrate (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent No. 4638958 Summary of the Invention

[0004] The manufacturing method of a semiconductor element disclosed herein includes a formation step of forming a plurality of semiconductor layers by epitaxial growth on a first surface of an underlying substrate so that adjacent semiconductor layers in a direction along the first surface are at least partially separated from each other in a direction along the first surface, a weakening step of irradiating a connection portion between each of the plurality of semiconductor layers and the first surface with laser light to weaken the connection portion, and a separation step of separating the plurality of semiconductor layers from the underlying substrate. [Brief description of the drawings]

[0005] [Figure 1] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] 1A to 1C are diagrams for explaining a forming step in a method for manufacturing a semiconductor element according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a plan view showing the pattern shapes of a plurality of semiconductor layers formed on an underlying substrate. [Figure 4] 11A to 11D are views for explaining a modified example of a separation step in a manufacturing method of a semiconductor element according to an embodiment of the present disclosure. [Diagram 5]2 is a flowchart showing steps of a manufacturing method for a semiconductor device according to an embodiment of the present disclosure. [Figure 6A] 1 is a cross-sectional view showing a state in which a semiconductor element is formed on an underlying substrate via a mask layer. [Figure 6B] FIG. 4 is a cross-sectional view showing a state in which the mask has been removed. [Figure 6C] 11A to 11C are cross-sectional views for explaining a step of weakening the connection portion. [Figure 7] FIG. 2 is a plan view showing a pattern shape of a mask. [Figure 8A] FIG. 11 is a cross-sectional view for explaining a separation step. [Figure 8B] FIG. 11 is a cross-sectional view for explaining a separation step. [Figure 8C] FIG. 11 is a cross-sectional view for explaining a separation step. [Figure 9A] FIG. 4 is a cross-sectional view showing an etching shape of a connection portion. [Figure 9B] FIG. 4 is a cross-sectional view showing an etching shape of a connection portion. [Figure 9C] FIG. 4 is a cross-sectional view showing an etching shape of a connection portion. [Figure 10] 11A to 11C are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 11] 11A to 11C are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 12] 2 is a cross-sectional view showing an example of the configuration of a base substrate. FIG. [Figure 13] FIG. 2 is a plan view showing a configuration example of a semiconductor substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Embodiment 1] Hereinafter, a first embodiment of the present disclosure will be described with reference to the drawings. The drawings are shown in a schematic manner for ease of illustration. The description will be given with reference to Figs. 1 to 4.

[0007] In Fig. 1, "step a" indicates a forming step, "step b" indicates a weakening step, and "step c" indicates a separation step. In Fig. 2, "step a1" indicates a mask forming step, "step a2" indicates a semiconductor layer forming step, and "step a3" indicates a mask removing step. In Fig. 4, "step c1" indicates a preparation step, "step c2" indicates a bonding step, and "step c3" indicates a peeling step.

[0008] The method for manufacturing a semiconductor device according to this embodiment includes a forming step a, a weakening step b, and a separating step c. The forming step a is a step of forming a plurality of semiconductor layers 3, each connected to the base substrate 1 by a connecting portion 2, on the base substrate 1 by, for example, an epitaxial lateral overgrowth (ELO) method, which is one of the epitaxial vapor phase growth methods. The weakening step b is a step of irradiating the connecting portions 2 with laser light 5 to weaken the connecting portions 2. Furthermore, the separating step c is a step of separating the plurality of semiconductor layers 3 from the base substrate 1.

[0009] Each semiconductor layer 3 has, for example, a cleavage plane formed thereon, and further has electrodes, wiring conductors, etc. arranged thereon to become one or a plurality of semiconductor elements S. Examples of the semiconductor elements S include, but are not limited to, light emitting diodes (LEDs), semiconductor lasers (LDs), and photodiodes (PDs).

[0010] The base substrate 1 has one flat principal surface (hereinafter also referred to as the first surface) 1a including the starting point of the growth of the semiconductor crystal, the other flat principal surface (hereinafter also referred to as the second surface) 1b opposite to the first surface 1a, and a side surface (hereinafter also referred to as the third surface) 1c connecting the first surface 1a and the second surface 1b. At least the first surface 1a of the base substrate 1 is made of a nitride semiconductor. The base substrate 1 may be a substrate made of a nitride semiconductor such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or the like.

[0011] The base substrate 1 used in this embodiment is a GaN substrate cut from a GaN single crystal ingot. The base substrate 1 is cut from the single crystal ingot so that a first surface 1a including the starting point of the growth of the semiconductor crystal is in a predetermined plane direction. The base substrate 1 may be an n-type substrate in which GaN is doped with an impurity such as Si, or a p-type substrate in which GaN is doped with an impurity such as Mg. The impurity density in the base substrate 1 is, for example, 1×10 19 cm -3 It is below that level.

[0012] (a) Formation process The formation step a is a step of forming a plurality of semiconductor layers 3 by the ELO method on the first surface 1a of the base substrate 1. In the formation step a, the plurality of semiconductor layers 3 are formed such that adjacent semiconductor layers 3 in the direction along the first surface 1a are at least partially separated from each other in the direction along the first surface 1a.

[0013] The forming step a includes a mask forming step a1, a semiconductor layer forming step a2, and a mask removing step a3, which will be described below.

[0014] (a1) Mask formation process The mask forming step a1 is a step of forming a deposition suppression mask (hereinafter, simply referred to as a mask) 6 that suppresses crystallization of semiconductor crystals on the base substrate 1. In the mask forming step a1, first, silicon oxide (e.g., SiO2, etc.) that is the material of the mask 6 is laminated on the first surface 1a of the base substrate 1 by a plasma chemical vapor deposition (PCVD) method or the like to a thickness of, for example, about 100 nm. Next, the silicon oxide layer is patterned by, for example, photolithography and wet etching with buffered hydrofluoric acid (Buffered Hydrogen Fluoride (BHF)). In this way, the mask 6 is formed in a predetermined pattern on the first surface 1a.

[0015] The mask 6 may be, for example, in the form of stripes having a plurality of band-shaped portions 61 arranged in parallel at a predetermined interval. The width of an opening 62, also called a mask window, between two adjacent band-shaped portions 61 is, for example, about 2 μm to 20 μm. The width of the band-shaped portions 61 is, for example, about 50 μm to 200 μm.

[0016] The edge region of the first surface 1a of the base substrate 1 near the third surface 1c may also be covered with the mask 6. This makes it possible to cleanly and reliably separate the semiconductor layer 3 growing on the edge region of the first surface 1a from the base substrate 1. Furthermore, abnormal growth of semiconductor crystals on the edge region of the first surface 1a can be suppressed.

[0017] (a2) Semiconductor layer formation process In the semiconductor layer forming step a2, GaN crystals are grown by vapor phase growth from the regions of the first surface 1a of the base substrate 1 that are not covered by the mask 6 and are exposed in the openings 62.

[0018] As a method for growing the semiconductor crystal, for example, vapor phase epitaxy (VPE) by a chloride transport method using chloride as a group III raw material, or metal organic chemical vapor deposition (MOCVD) using an organic metal as a group III raw material can be used. For example, by changing the ratio of the source gas of the group III element and the ratio of the source gas of the impurity during the growth of the GaN crystal, the semiconductor layer 3 can be formed as a multilayer film that functions as a light emitting diode (LED) or a semiconductor laser (LD), etc.

[0019] When the grown semiconductor crystal exceeds the opening 62 of the mask 6, the semiconductor crystal also grows laterally along the upper surface of the mask 6. The growth of the semiconductor crystal may be terminated before the semiconductor crystal grown from the first surface 1a overlaps with the adjacent semiconductor crystals. In this manner, a plurality of semiconductor layers 3 are obtained, each of which is connected to the first surface 1a by a connecting portion 2, as shown in, for example, FIGS. 1 and 2. The connecting portion 2 is made of, for example, GaN crystal, like the semiconductor layer 3. The connecting portion 2 has, for example, a width of about 2 μm to 20 μm and a height of about 100 nm to 500 nm. Each semiconductor layer 3 has, for example, a width of about 50 μm to 200 μm and a height of about 10 μm to 50 μm. The growth of the semiconductor crystal may be continued until the semiconductor crystal growing laterally along the upper surface of the mask 6 overlaps with the adjacent semiconductor crystals. In this case, a semiconductor layer connected to the first surface 1a by a plurality of connecting portions 2 is obtained.

[0020] (a3) Mask removal process The mask removing step a3 is a step of removing the mask 6 after the semiconductor layer forming step a2 is completed. In the mask removing step a3, the base substrate 1 on which the semiconductor layer 3 is formed is taken out of the vapor phase growth apparatus (epitaxial apparatus), and the mask 6 is removed using an etchant that does not substantially attack the semiconductor layer 3.

[0021] For example, when the mask 6 is made of a silicon oxide film, wet etching using BHF is performed to remove the mask 6. In this manner, a plurality of semiconductor layers 3, each connected to the first surface 1a by a connecting portion 2, is obtained, for example, as shown in FIG.

[0022] Each of the multiple semiconductor layers 3 may extend in a predetermined direction in plan view. The multiple semiconductor layers 3 may form a pattern as shown in FIG. 3 in plan view. The multiple semiconductor layers 3 may form a stripe pattern extending in a predetermined direction, as shown in FIG. 3(a). The multiple semiconductor layers 3 may be arranged in a staggered manner, as shown in FIG. 3(b), to form a so-called repeat pattern. The multiple semiconductor layers 3 may form a lattice pattern in which each semiconductor layer 3 is connected to adjacent semiconductor layers 3 at both ends, as shown in FIG. 3(c).

[0023] (b) Weakening process The weakening step b is a step of irradiating the connection portion 2 with laser light 5 to weaken the connection portion 2. In the weakening step b, for example, the connection portion 2 can be thermally denatured by the irradiation of the laser light 5, and the crystal structure of the connection portion 2 can be changed. This can cause, for example, cracks, breaks, etc. in the connection portion 2, and reduce the mechanical strength of the connection portion 2. In the weakening step b, the connection portion 2 can be completely or partially cut by the irradiation of the laser light 5.

[0024] The wavelength of the laser light 5 may be, for example, 370 nm or less. As a light source that outputs the laser light 5, for example, an AlGAN semiconductor laser, a KrF excimer laser, an ArF excimer laser, a YAG laser (third harmonic), etc. can be used. The focal length and spot size of the laser light 5 can be appropriately selected depending on the dimensions of the base substrate 1, the connection portion 2, and the semiconductor layer 3, etc.

[0025] The laser light 5 may be applied from the first surface 1a side of the base substrate 1, or from the second surface 1b side of the base substrate 1. The laser light 5 may be applied from the third surface 1c side of the base substrate 1.

[0026] (c) Separation process The separation step c is a step of separating the multiple semiconductor layers 3 from the base substrate 1. In the separation step c, a force is applied to the weakened connection parts 2, for example, by bringing a blade into contact with the semiconductor layers 3 or by irradiating the connection parts 2 with ultrasonic waves. This breaks the connection parts 2, and the semiconductor layers 3 can be separated from the base substrate 1.

[0027] In the weakening step b, if the connection portion 2 is completely cut by irradiation with the laser light 5, the separating step c can be omitted.

[0028] According to the method for manufacturing a semiconductor device of this embodiment, the semiconductor layers 3 formed on the first surface 1a of the base substrate 1 are at least partially separated from each other in the direction along the first surface 1a. Therefore, decomposition product gas or evaporated gas, which is generated by irradiation of the connection portion 2 with the laser light 5 and fills the space between the semiconductor layer 3 and the base substrate 1, can be discharged to the outside. The gas can be discharged to the outside through the gap (hereinafter also referred to as the discharge path) G between the adjacent semiconductor layers 3, as shown by the arrow in FIG. 1, for example. This reduces damage to the semiconductor layer 3 and the base substrate 1 caused by the pressure of the decomposition product gas or evaporated gas. As a result, it becomes possible to manufacture a high-quality semiconductor device S. In addition, the base substrate 1 can be reused without polishing to remove damaged portions or after only a small amount of polishing. This makes it possible to improve the production efficiency of the semiconductor device S and provide a semiconductor device S that can increase the number of times the base substrate 1 can be reused.

[0029] Moreover, in the method for manufacturing a semiconductor device according to the present embodiment, it is not necessary to irradiate the entire base substrate 1 with the laser light 5, but it is sufficient to irradiate only the connection portion 2 connecting each semiconductor layer 3 and the first surface 1a. This makes it possible to prevent the semiconductor layer 3 and the base substrate 1 from being excessively heated, and to reduce thermal damage to the semiconductor layer 3 and the base substrate 1. As a result, it becomes possible to manufacture a high-quality semiconductor device S. Furthermore, the base substrate 1 can be reused without polishing to remove damaged portions, or after only a small amount of polishing. This makes it possible to improve the production efficiency of the semiconductor device S and reduce the manufacturing cost of the semiconductor device S.

[0030] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the base substrate 1, the connection portion 2, and the semiconductor layer 3 are made of GaN crystals, and therefore their refractive indices are substantially the same. This makes it possible to reduce refraction and reflection of the laser light 5 at the interface between the base substrate 1 and the connection portion 2, and at the interface between the connection portion 2 and the semiconductor layer 3. As a result, the laser light 5 can be irradiated onto the connection portion 2 with high accuracy and high efficiency. This in turn makes it possible to manufacture a high-quality semiconductor device S. Furthermore, it becomes possible to improve the production efficiency of the semiconductor device S.

[0031] In the semiconductor layer forming step a2, when the growth of the semiconductor crystals is continued until adjacent semiconductor crystals overlap each other to form a semiconductor layer connected to the first surface 1a by a plurality of connecting parts 2, a through hole penetrating the semiconductor layer in the thickness direction may be formed before the weakening step b is performed. This allows decomposition product gas or evaporated gas filling the space between the semiconductor layer and the base substrate 1 to be released to the outside through the through hole. As a result, even when a semiconductor layer connected to the first surface 1a by a plurality of connecting parts 2 is formed, it is possible to manufacture a high-quality semiconductor element S and improve the production efficiency of the semiconductor element S.

[0032] In the weakening step b, the laser light 5 may be irradiated from the second surface 1b side of the base substrate 1 and made incident on the base substrate 1 from the second surface 1b. The base substrate 1 is not a heterogeneous substrate formed by forming a GaN layer on the surface of a sapphire substrate, SiC substrate, or the like, but is a substrate made of approximately the same material, so the refractive index of the base substrate 1 is substantially constant. Therefore, by making the laser light 5 incident on the second surface 1b of the base substrate 1, the laser light 5 can be focused on the connection portion 2 with high accuracy. In addition, by irradiating the laser light 5 from the second surface 1b side on which the semiconductor layer 3 is not formed, the risk of the irradiation of the laser light 5 modifying the semiconductor layer 3 can be reduced. Furthermore, since the refractive index of the base substrate 1 is substantially constant, a lens optical system with a simple configuration can be used as an optical system for focusing the laser light 5 on the connection portion 2. This can improve the production efficiency of the semiconductor element S. Note that this description does not exclude the use of heterogeneous substrates such as sapphire substrates and SiC substrates as the base substrate 1 in this disclosure.

[0033] In the weakening step b, the connection 2 may be irradiated with picosecond pulsed laser light or femtosecond pulsed laser light. This makes it possible to induce an ablation phenomenon due to multiphoton absorption at the connection 2, which is the focal point of the laser light 5. This makes it possible to weaken the connection 2 with high precision while suppressing the occurrence of thermal damage in the semiconductor layer 3 and the base substrate 1.

[0034] In the weakening step b, subnanosecond pulsed laser light or nanosecond pulsed laser light may be irradiated to the connection portion 2. This increases the material removal rate compared to when the pulse width of the laser light 5 is picoseconds or femtoseconds, thereby improving the processing efficiency in the weakening step b.

[0035] When the pulse width of the laser light 5 is sub-nanoseconds or nanoseconds, a large amount of decomposition product gas or evaporated gas may be generated compared to when the pulse width of the laser light 5 is picoseconds or femtoseconds. By optimizing the emission path G, it is possible to effectively emit the decomposition product gas and evaporated gas to the outside even when the pulse width of the laser light 5 is sub-nanoseconds or nanoseconds. The optimization of the emission path G may be, for example, as shown in FIG. 1, by forming each semiconductor layer 3 to have a cross-sectional shape in which the corners of the lower surface are rounded. The optimization of the emission path G may be, for example, as shown in FIG. 3(b), by forming a plurality of semiconductor layers 3 arranged in a staggered pattern and adjusting the intervals between adjacent semiconductor layers 3 in two different directions.

[0036] The scanning path of the laser light 5 in the weakening step b may be selected so as to improve the production efficiency of the semiconductor element S depending on the pattern shape of the multiple semiconductor layers 3 formed on the base substrate 1. In the weakening step b, for example, the laser light 5 may be scanned from the outer periphery of the base substrate 1 to the center while rotating the base substrate 1 around an axis perpendicular to the first surface 1a. This eliminates the need to make the laser light 5 go back and forth multiple times around the focal point, thereby shortening the time required for the weakening step b. This in turn improves the production efficiency of the semiconductor element S.

[0037] In the weakening step b, the temperature of the base substrate 1 may be maintained within a predetermined temperature range by heating the base substrate 1. This causes the Ga metal precipitated by the irradiation of the laser light 5 to be in a molten state, making it less likely to adhere to the semiconductor layer 3. This makes it possible to maintain the quality of the semiconductor layer 3. The predetermined temperature range may be, for example, from near room temperature (approximately 15°C to 35°C) to 300°C.

[0038] In the weakening step b, the atmosphere, pressure, etc. in the laser processing device may be adjusted to suppress oxidation of the base substrate 1, which becomes hot due to irradiation with the laser light 5, and oxidation of the Ga metal precipitated by irradiation with the laser light 5. This reduces damage to the base substrate 1 caused by oxidation. As a result, the base substrate 1 can be reused without polishing to remove the damaged portion, or after only a small amount of polishing. This improves the production efficiency of the semiconductor element S and reduces the manufacturing cost of the semiconductor element S. In addition, the adhesion of the oxidized Ga metal to the semiconductor layer 3 can be suppressed, thereby reducing the risk of the quality of the semiconductor layer 3 being reduced. As a result, it becomes possible to manufacture a high-quality semiconductor element S.

[0039] In the weakening step b, the focus of the laser light 5 may be adjusted to the end 21 of the connection portion 2 on the base substrate 1 side. This makes it possible to suppress undesired thermal denaturation of the semiconductor layer 3 caused by the irradiation of the laser light 5. As a result, polishing for removing the thermally denatured portion of the semiconductor layer 3 can be omitted, or the amount of the semiconductor layer 3 that is polished can be reduced. This in turn makes it possible to improve the production efficiency of the semiconductor element S.

[0040] In the weakening step b, the focus of the laser light 5 may be adjusted to the end 22 of the connection portion 2 on the semiconductor layer 3 side. This makes it possible to suppress undesired thermal denaturation of the base substrate 1 due to irradiation with the laser light 5. As a result, polishing for removing the thermally denatured portion of the base substrate 1 can be omitted, or the amount of the base substrate 1 that needs to be polished can be reduced. This in turn makes it possible to improve the production efficiency of the semiconductor element S and reduce the manufacturing cost of the semiconductor element S.

[0041] In the weakening step b, the focus of the laser light 5 may be adjusted to an intermediate portion 23 located between the end of the connection portion 2 on the undersubstrate 1 side and the end 22 on the semiconductor layer 3 side. This makes it possible to suppress undesired thermal denaturation of the semiconductor layer 3 and the undersubstrate 1. As a result, it becomes possible to manufacture a high-quality semiconductor element S, improve the production efficiency of the semiconductor element S, and reduce the manufacturing cost of the semiconductor element S.

[0042] In the case where the connection portion 2 is not completely cut in the weakening step b, the separation step c may include a preparation step c1, a joining step c2, and a peeling step c3.

[0043] The preparation step c1 is a step of preparing a support substrate 10 having an opposing surface 10a to face the first surface 1a of the base substrate 1. The support substrate 10 has a bonding layer 10b made of solder using a material such as AuSn on the opposing surface 10a.

[0044] The bonding step c2 is a step of bonding a support substrate 10 to the upper surfaces of the multiple semiconductor layers 3. In the bonding step c2, first, the support substrate 10 is disposed on the multiple semiconductor layers 3 formed on the base substrate 1 in the formation step a. The support substrate 10 is disposed so that the opposing surface 10a faces the first surface 1a of the base substrate 1. Next, the support substrate 10 is heated while being pressed against the base substrate 1, and the support substrate 10 is bonded to the upper surfaces of the multiple semiconductor layers 3.

[0045] The peeling step c3 is a step of peeling the plurality of semiconductor layers 3 from the base substrate 1. In the peeling step c3, the base substrate 1 and the support substrate 10 are relatively separated from each other. As a result, tensile stress is generated in the connection parts 2 weakened by the irradiation of the laser light 5, and the connection parts 2 are broken, so that the plurality of semiconductor layers 3 can be peeled off from the base substrate 1. By weakening the connection parts 2, the plurality of semiconductor layers 3 can be peeled off from the base substrate 1 without being damaged. The peeling step c3 may include a step of forming a cleavage plane in the semiconductor layer 3, and a step of forming electrodes, wiring conductors, and the like on the semiconductor layer 3.

[0046] The preparation step c1 and the bonding step c2 may be performed between the formation step a and the weakening step b. In this case, the decomposition product gas or the evaporated gas generated by the irradiation of the laser light 5 flows through the space between the semiconductor layer 3 and the base substrate 1 along the first surface 1a toward the outer edge of the base substrate 1 and is released to the outside. The support substrate 10 may be formed with a gas flow path (not shown) for promoting the release of the decomposition product gas or the evaporated gas to the outside. The gas flow path may be, for example, a through hole penetrating the support substrate 10 in the thickness direction. The gas flow path may be, for example, a groove portion formed in the opposing surface 10a of the support substrate 10.

[0047] The method for manufacturing a semiconductor device according to the present disclosure includes a forming step of forming a plurality of semiconductor layers by epitaxial growth on a first surface of a base substrate such that adjacent semiconductor layers in a direction along the first surface are at least partially separated from each other in a direction along the first surface; a weakening step of irradiating a connection portion between each of the plurality of semiconductor layers and the first surface with laser light to weaken the connection portion; and a separating step of separating the plurality of semiconductor layers from the base substrate.

[0048] To produce quality semiconductor devices, there is room for improvement in the method of separating the semiconductor layer from the substrate.

[0049] According to the method for manufacturing a semiconductor device of the present disclosure, damage to the base substrate and the semiconductor layer when the semiconductor layer is separated from the base substrate can be reduced, which makes it possible to manufacture high-quality semiconductor devices and improves the production efficiency of semiconductor devices.

[0050] [Embodiment 2] Other embodiments according to the present disclosure will now be described with reference to the schematic drawings.

[0051] The method for manufacturing a semiconductor device according to the present embodiment includes an element formation step S1, a light irradiation step S2 (also referred to as a weakening step), and a separation step S3, as shown in Fig. 5. Also, as shown in Figs. 6A, 6B, and 6C, the element formation step S1 is a step of forming a semiconductor element 33 connected by a connection portion 2 on an underlying substrate 1 by an ELO method. The light irradiation step S2 is a step of bringing the connection portion 2 into contact with an etching solution 4 and irradiating light such as laser light 5 to at least a part of the connection portion 2 to melt or weaken the connection portion 2. The separation step S3 is a step of separating the semiconductor element 33, whose connection portion 2 has been weakened by the light irradiation step S2, from the underlying substrate 1.

[0052] The element formation step S1 and the light irradiation step S2 do not have to be performed in this order, and for example, the element formation step S1 and the light irradiation step S2 may be performed in parallel. This can shorten the process time. Examples of the semiconductor element 33 include, but are not limited to, a light emitting diode (LED), a semiconductor laser (LD), and a photodiode (PD).

[0053] The base substrate 1 has a first surface 1a, which is one flat main surface that serves as the starting point for semiconductor crystal growth, and a second surface 1b, which is the other flat main surface on the reverse side. At least the surface of the first surface 1a is a nitride semiconductor. The base substrate 1 used in the embodiment is, for example, a GaN substrate cut from a single crystal ingot of gallium nitride (GaN) so that the first surface 1a, which is the growth surface, is in a predetermined plane direction. The GaN substrate may be either an n-type substrate or a p-type substrate in which an impurity such as Si is doped into the semiconductor. The impurity density of the GaN substrate is, for example, 1×10 19 cm -3 The following can be used:

[0054] In addition to a GaN substrate, the base substrate 1 may be a sapphire substrate, a SiC substrate, or another substrate other than GaN, on which a GaN layer is formed. The surface of the base substrate 1 is not limited to a GaN layer, and any substrate made of a GaN-based semiconductor may be used. The "nitride semiconductor" referred to here is not limited to Al x Ga y In z N (0≦x≦1, 0≦y≦1, 0≦z≦1, 1).

[0055] A mask 6 is formed on the above-mentioned base substrate 1. The mask 6 is formed, for example, by stacking silicon oxide (e.g., SiO2, etc.) that is the material of the mask 6 on the base substrate 1 to a thickness of about 100 nm on the first surface 1a by a PCVD (Plasma Chemical Vapor Deposition) method or the like. Next, the SiO2 layer is patterned by, for example, photolithography and wet etching with buffered hydrofluoric acid (BHF) to form the mask 6 shown in FIG. 6A.

[0056] The mask 6 is in a stripe shape with multiple strips 6a arranged in parallel at a predetermined interval. The width of the opening 7, also called a mask window, between two adjacent strips 6a is, for example, about 2 μm to 20 μm. The width of the strips 6a is, for example, about 50 μm to 200 μm.

[0057] 7 is a plan view showing the pattern shape of the mask. The mask material for forming the mask 6 may be SiO2 or any other material that does not allow a semiconductor layer to grow from the mask material by vapor phase growth. The mask material may be, for example, ZrO X , TiO X Or AlO XFor example, an oxide such as Ti or a transition metal such as W or Cr can be used. The mask layer can be laminated by a method suitable for the mask material, such as vapor deposition, sputtering, or coating and curing. As a specific example, a SiO2 layer having a thickness of about 100 to 500 nm is formed as the mask 6. The SiO2 layer is formed by first laminating silicon oxide (SiO2), which is the material of the mask 6, on the first surface 1a to a thickness of about 100 to 500 nm by a method such as PCVD (Plasma Chemical Vapor Deposition).

[0058] The mask pattern of the mask 6 may be a band or stripe pattern as shown by reference symbol 7a in Fig. 7, or a lattice pattern as shown by reference symbol 7b in which a plurality of bands are arranged so as to intersect vertically and horizontally, or a so-called repeat pattern as shown by reference symbol 7c in which openings 7 separated at a fixed interval (repeat pitch) are repeated multiple times.

[0059] The edge region of the first surface 1a of the base substrate 1 near the end face (side surface) 1c of the base substrate 1 may also be covered with the above-mentioned mask 6, taking into consideration the ease of peeling and separating the semiconductor layer 3 described below. This makes it possible to easily peel off the semiconductor layer located at the end of the base substrate 1 and near the edge.

[0060] 6B, a semiconductor element layer 8, which is a semiconductor crystal growth layer, is grown by vapor phase growth from the first surface 1a exposed from the opening 7. In this embodiment, the semiconductor element layer 8 is a nitride semiconductor layer, but other materials may be used.

[0061] The crystal growth method can be vapor phase epitaxy (VPE) by chloride transport method using chloride as group III raw material, or metal organic chemical vapor deposition (MOCVD) using organic metal as group III raw material. By changing the ratio of the source gas of group III element and the ratio of the source gas of impurity during the growth process, the semiconductor element layer 8 can be formed as a multilayer film that functions as a semiconductor element 33 such as an LED or LD.

[0062] When the grown crystal exceeds the opening 7 of the mask 6, the crystal also grows laterally along the upper surface of the mask 6. The crystal growth ends before the semiconductor crystal grown from the first surface 1a overlaps with adjacent semiconductor crystals. In this manner, a semiconductor element layer 8 is obtained in which a nitride semiconductor is grown by the ELO method. The width of the semiconductor element layer 8 is, for example, about 50 μm to 200 μm, and the height is about 10 μm to 50 μm.

[0063] After forming the adhesive layer 9, which is, for example, a metal layer, the base substrate 1, the mask 6 formed on the base substrate 1, the semiconductor element layer 8, and the adhesive layer 9 are immersed in BHF for about 10 minutes, and the mask 6 is removed. As a result, a semiconductor element 33 is formed on the base substrate 1, as shown in FIG. 6C. The semiconductor element 33 and the base substrate 1 are connected to the base substrate 1 via the columnar connection parts 2, which are parts of the semiconductor element layer 8 grown in the opening parts 7 of the mask 6. The adhesive layer 9 can be used as an electrode for the semiconductor element 33.

[0064] However, depending on the configuration of the semiconductor element 33, the adhesive layer 9 does not necessarily have to be used as an electrode. The semiconductor element layer 8 has an upper surface 8a and a lower surface 8b located on the opposite side. The mask 6 may be removed before or after the semiconductor element 33 is connected to the support substrate 10, which will be described later, but it is preferable to corrode and dissolve at least a part of the adhesive layer 9 with BHF. The adhesive layer 9 may bond the upper surface of the semiconductor element 33 to the support substrate 10. Alternatively, the adhesive layer 9 may be a metal layer that also serves as an electrode for the semiconductor element 33 after being subjected to corrosion prevention.

[0065] Next, as shown in FIG. 6C, in the light irradiation process, the connection portion 2 is brought into contact with an etching solution 4, and light (in this example, laser light 5) containing a wavelength that causes dissolution by photochemical reaction at or around the connection portion 2 is irradiated to melt or weaken the connection portion 2.

[0066] Here, for example, light emitted from an LED or a halogen lamp may be used instead of the laser light 5. However, in order to obtain wavelength selectivity and a high reaction rate of the photochemical reaction, it is preferable to use the laser light 5 capable of high-intensity irradiation to a minute region.

[0067] Laser light 5 may be irradiated onto the semiconductor element 33 side of connecting portion 2 or an area including a part of the semiconductor element 33 side. In this case, when the semiconductor element 33 side of connecting portion 2 is separated from base substrate 1, separation is possible without leaving a protruding structure or the like on the semiconductor element 33 side, and process constraints when mounting semiconductor element 33 after this separation can be reduced.

[0068] Laser light 5 may be irradiated to the base substrate 1 side of connecting portion 2 or to a region including a part of the base substrate 1 side. By limiting the irradiation region of laser light 5 in this manner, the influence of thermal shock on semiconductor element 33 can be reduced, and high-precision alignment for controlling the focal position of laser light 5 is not required.

[0069] Laser light 5 can also be irradiated to an intermediate portion located between the end of connection portion 2 on the base substrate 1 side and the end on the semiconductor element 33 side. In this way, it is possible to minimize the area to be etched away, and it is possible to reduce the output of laser light 5 and shorten the etching time, thereby improving productivity.

[0070] Furthermore, the focus of the laser light 5 may be adjusted to the above-mentioned position, and the laser light 5 may be scanned in any direction within the substrate surface of the base substrate 1. In this case as well, instead of the laser light 5, other light sources as described above may be used.

[0071] The technique of irradiating the laser light 5 to the connection part 2 while it is in contact with an etching solution, which is an electrolyte, is also called photoelectrochemical etching (PEC) etching. In PEC etching, when a semiconductor (GaN) is irradiated with laser light in an etching solution, an "oxidation reaction" as shown in the following formula (1) and an "oxide film dissolution reaction" as shown in formula (2) occur. + " represents a hole.

[0072] <Oxidation reaction> 2GaN+6OH - +6h + → Ga2O3+3H2O+N2…(1)

[0073] <Dissolution reaction> Ga2O3+6OH - → 2GaO3 3- +3H2O …(2)

[0074] When laser light 5 is irradiated onto connection portion 2 in etching solution 4 due to the above-mentioned oxidation reaction and oxide film dissolution reaction, an electric field is generated from inside connection portion 2 toward its surface, causing connection portion 2 to dissolve in acid or alkali from the surface or become weakened.

[0075] This type of PEC etching is a light-induced etching that can only etch layers that contain photogenerated carriers, so low damage can be ensured by controlling the etching speed due to the oxidation reaction that occurs on the semiconductor surface with the amount of passing charge.

[0076] The photocarriers (holes) generated in the GaN layer flow into the etching solution and are used in the etching reaction as described above. Therefore, when the GaN layer is thinned by etching, the number of carriers decreases, and the current supply path in the semiconductor is depleted, completely blocking the reaction current path, which causes the etching reaction to self-stop. This self-stopping process increases the process margin and reduces yield loss due to process variations within a substrate and between lots.

[0077] 8A, 8B, and 8C, supporting substrate 10 is connected to semiconductor element 33, whose connecting portion 2 has been irradiated with laser light 5, using a substrate bonding device (not shown). When connecting supporting substrate 10 to semiconductor element 33, base substrate 1 and supporting substrate 10 are attached to the substrate bonding device so that first surface 1a of base substrate 1 and opposing surface 10a of supporting substrate 10 are parallel to each other.

[0078] Next, the opposing surface 10a of the support substrate 10 is brought into contact with the upper surface of the semiconductor element 33 (the upper surface of the adhesive layer 9). The support substrate 10 is pressurized to bring the adhesive layer 9 into close contact with the support substrate 10, and then heated to 300° C. to perform, for example, AuSn bonding. As a result, the support substrate 10 is bonded to the semiconductor element 33, as shown in FIG. 8A. This bonding is not limited to AuSn bonding, and various bonding methods using other materials are possible.

[0079] As shown in FIG. 8B, the connection portion 2 is weakened by irradiating it with a laser beam as described above. After the substrate bonding device is cooled, the base substrate 1 is removed from the substrate bonding device, and the support substrate 10 is moved in a direction away from the base substrate 1. As a result, a large tensile stress is generated in the connection portion 2 that has been weakened by the irradiation of the laser beam 5, and the connection portion 2 is broken as shown in FIG. 8C. At this time, since the connection portion 2 is in a weakened state, the base substrate 1 can be easily separated. The separation can be performed by an appropriate method. It is considered that the connection portion 2 remains on the base substrate 1 side, the semiconductor element 33 side, or both, depending on the location where it has been weakened. For this reason, after separation, the remaining pieces of the connection portion 2 remaining on the semiconductor element 33 are removed by polishing or the like.

[0080] In this way, the connection 2 between the semiconductor element 33 and the base substrate 1 is melted or weakened, which reduces the risk of cracks and crystal defects occurring during the separation process, allows the diameter of the base substrate 1 to be increased, and improves the yield of the separation process. In addition, in the separation process, a rough surface region having multiple crystal planes may be formed on at least one of the semiconductor element 33 and the base substrate 1. This makes it possible to make it difficult for cracks to occur or for the cracks to progress when the semiconductor element 33 is separated from the base substrate 1.

[0081] 9A to 9C are diagrams showing the etched shape of the connection part. When the connection part 2 is irradiated with the laser light 5 from the side, an electric field is generated in the direction of the arrow E from the base substrate 1 toward the semiconductor element 33, and the first surface 1a of the base substrate 1 becomes a Ga electrode surface, and the opposing surface 3a of the semiconductor element 33 facing the base substrate 1 becomes an N electrode surface, which is polarized. As a result, the oxidation of the first surface 1a, which is a Ga electrode surface, is promoted more than the oxidation of the opposing surface 3a, which is an N electrode surface, and etching proceeds faster. Therefore, as shown in FIG. 9A, the connection part 2 has a small width b1 on the base substrate 1 side and a large width b2 on the semiconductor element 33 side, and is etched into an inverted trapezoidal cross section.

[0082] Electron density is 3×10 17 cm -3 In this case, for example, the inventors have confirmed that when a GaN test piece is immersed in a KOH etching solution of pH 13 and irradiated with laser light from a HeCd laser with a wavelength λ=325 nm, an etching rate of 525 nm / min can be obtained.

[0083] In this embodiment, the semiconductor element layer 8 is formed of a material with a band structure that generates an energy barrier, for example, n-GaN / i-GaN / n-GaN. Then, selective regions are irradiated with laser light to generate photoexcitation, current flow, polarization due to electric field distortion, etc. This allows the connection portion 2 or a part of it to be selectively etched with an etchant such as KOH or TMAH that can promote a chemical etching reaction of the charge localized portion.

[0084] In this embodiment, the connection portion 2 is made to have a void structure by the VAS (Void-Assisted Separation) method, formation of a rough initial nucleus, porosity by anodization, In droplet method, etc. This increases the surface area and reduces the rigidity compared to an ELO structure without voids. At the same time, selective weakening is possible by increasing the etching rate. For example, as shown in FIG. 9B, the connection portion 2 can be etched to have a trapezoidal cross section with a small width b2 on the semiconductor element 33 side and a large width b1 on the base substrate 1 side.

[0085] By controlling the vacancy rate (vacancy density) on the semiconductor element 33 side and the base substrate 1 side of the connection portion 2, the etching rate can be controlled, and the widths b1 and b2 can also be controlled. This makes it possible to change the etching rate of the connection portion 2 so that width b1 is greater than width b2. In particular, vacancy at the interface between the connection portion 2 and the base substrate 1 (initial growth layer of the ELO structure) can be easily achieved by epitaxial growth conditions, the VAS method, etc.

[0086] Also, as shown in FIG. 9C, the width b3 of the intermediate portion between the end of the connection portion 2 on the undersubstrate 1 side and the end of the semiconductor element 33 side, more specifically the width b3 of the central portion, can be made smaller than the widths b1 and b2 of both ends of the connection portion 2, thereby realizing high operability of the weakened portion. To change the etching rate of the connection portion 2 to make the width b1 and width b2 > width b3, for example, it can be achieved by controlling the difference in electron concentration between the connection portion 2, the semiconductor element 33 side sandwiching the connection portion 2, and the undersubstrate 1 side. Alternatively, a layer with a different band gap may be inserted by heteroepitaxial growth, and the etching rate can also be controlled by inserting a stress layer that generates distortion at the interface of the connection portion 2 on the semiconductor element 33 side or the undersubstrate 1 side. Alternatively, the etching rate can be controlled by providing the above-mentioned multilayer structure inside the connection portion 2.

[0087] As described above, according to the method for manufacturing a semiconductor device of this embodiment, in addition to weakening the connection parts, a support substrate is used, which reduces the risk of cracks and crystal defects caused by the separation process, and allows the base substrate to have a larger diameter and improves the yield of the separation process.

[0088] The manufacturing method of a semiconductor element disclosed herein includes an element formation step of forming a semiconductor element located on an underlying substrate via a connection portion, a light irradiation step of irradiating the connection portion with light while in contact with an etching solution to melt or weaken the connection portion, and a separation step of separating the semiconductor element from the underlying substrate.

[0089] In the conventional technology described in Patent Document 1, if cracks and crystal defects occur in both the semiconductor element and the underlying substrate, it is considered that this will cause a decrease in the characteristics of the semiconductor element and the manufacturing yield. Therefore, there is a need for a method of manufacturing a semiconductor element that can reduce the occurrence of cracks and crystal defects in both the semiconductor element and the underlying substrate and is less likely to cause a decrease in the characteristics of the semiconductor element and the manufacturing yield.

[0090] According to the method for manufacturing a semiconductor device of the present disclosure, the occurrence of cracks and crystal defects due to the separation process can be reduced, and the diameter of the base substrate can be increased, thereby improving the yield of the separation process and improving productivity.

[0091] [Embodiment 3] 10 and 11 are cross-sectional views showing a method for manufacturing a semiconductor device according to embodiment 3. As shown in Fig. 10 and 11, the method for manufacturing a semiconductor device according to embodiment 3 includes the steps of forming a semiconductor substrate HK having an underlying substrate UK and a layer-like first semiconductor portion SL1 bonded to the underlying substrate UK, and isolating the first semiconductor portion SL1 from the underlying substrate UK. The first semiconductor portion SL1 includes a nitride semiconductor. The first semiconductor portion SL1 may be a first semiconductor layer.

[0092] The first semiconductor portion SL1 has a protruding portion TS that protrudes toward the underlying substrate UK, and the protruding portion TS includes a nitride semiconductor. The protruding portion TS is located in the center of the first semiconductor portion SL1 in a plan view and has an elongated shape. The protruding portion TS is bonded to the underlying substrate UK, and a hollow portion TK is formed in the semiconductor substrate HK, located between the underlying substrate UK and the first semiconductor portion SL1. The hollow portion TK contacts a side surface SF of the protruding portion TS and is connected to the outside of the semiconductor substrate HK, and can serve as a flow path for gas and liquid.

[0093] Specific examples of nitride semiconductors include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). The Z direction is the normal direction of the (0001) plane, which is the c-plane of the nitride semiconductor of the protruding portion TS. The X direction is the normal direction of the (11-20) plane, which is the a-plane of the nitride semiconductor of the protruding portion TS, and the Y direction is the normal direction of the (1-100) plane, which is the m-plane of the nitride semiconductor of the protruding portion TS.

[0094] 10, before the first semiconductor portion SL1 is separated from the base substrate UK, the protrusion portion TS is irradiated with laser light (laser ablation). On the other hand, in Fig. 11, before the first semiconductor portion SL1 is separated, the etching liquid EH is injected into the hollow portion TK, and the protrusion portion TS is irradiated with laser light (photoexcitation).

[0095] In the third embodiment, as shown in FIGS. 10 and 11, a first semiconductor portion SL1 is formed by an ELO (Epitaxial Lateral Overgrowth) method on a mask ML that is located on an underlying substrate UK and includes mask portions M1 and M2 and openings K1 and K2, and then the mask portions M1 and M2 are etched away to form a hollow portion TK. The mask ML may be a mask layer. The protruding portion TS is formed in the opening K1. The protruding portion TS may have a shape whose longitudinal direction is the <1-100> direction (Y direction) of the nitride semiconductor contained therein.

[0096] The first semiconductor portion SL1 includes a low dislocation portion WG that does not overlap with the convex portion TS in a plan view and has a threading dislocation density of 1 / 5 or less of the convex portion TS. The semiconductor substrate HK includes a second semiconductor portion SL2, and the first and second semiconductor portions SL1 and SL2 are arranged in the <11-20> direction (X direction) of the nitride semiconductor. The second semiconductor portion SL2 may be a second semiconductor layer. The semiconductor substrate HK has a device portion DL formed on the first semiconductor portion SL1. Although not shown, the device portion DL has, for example, a p-type semiconductor portion, an n-type semiconductor portion, an active portion including a light emitting region, and an electrode portion. The p-type semiconductor portion, the n-type semiconductor portion, the active portion, and the electrode portion are each formed in a layered shape, and are stacked to form the device portion DL. That is, the device portion DL may be a device layer. The light emitting region can be formed so as to overlap with the low dislocation portion WG in a plan view.

[0097] 10 and 11, the semiconductor substrate HK may include a support substrate SK facing an underlying substrate UK, and the first semiconductor portion SL1 may be located between the underlying substrate UK and the support substrate SK. An electrode portion of the device portion DL may be bonded to the support substrate SK.

[0098] FIG. 12 is a cross-sectional view showing an example of the configuration of the base substrate. As shown in FIG. 12, the nitride semiconductor included in the protruding portion TS may be a GaN-based semiconductor, and the base substrate UK may have a heterogeneous substrate MK having a lattice constant different from that of the GaN-based semiconductor of the protruding portion TS, and a seed portion SD formed on the heterogeneous substrate MK and including a nitride semiconductor. In this case, the base substrate UK may be composed of a main substrate MK which is a silicon substrate and a seed portion SD (for example, an AlN portion), or may be composed of a main substrate MK which is a silicon carbide substrate and a seed portion SD (for example, a GaN-based semiconductor portion). The base substrate UK may be composed of a main substrate MK which is a silicon substrate, a buffer portion BF (for example, including at least one of an AlN portion and a SiC portion) on the main substrate, and a seed portion SD (for example, a GaN-based semiconductor portion) on the buffer portion. Note that the configuration is not limited to these, and the base substrate UK may be a bulk-type GaN substrate or a bulk-type SiC substrate (hexagonal crystal system). The seed portion SD may be a seed layer, and the buffer portion BF may be a buffer layer.

[0099] Fig. 13 is a plan view showing a configuration example of a semiconductor substrate. As shown in Fig. 13, in the semiconductor substrate HK, the first semiconductor portion SL1 and the device portion DL may be divided into a plurality of semiconductor element portions HB. The semiconductor element portions HB function as, for example, LEDs (light emitting diodes) or semiconductor lasers.

[0100] In Fig. 10, after the semiconductor substrate HK is formed, laser ablation is caused in the protruding portion TS including the nitride semiconductor by irradiation with laser light LZ, thereby weakening or cutting across the protruding portion TS (cutting parallel to the c-plane). Since the width (size in the X direction) of the protruding portion TS is smaller than the width of the first semiconductor portion SL1, the process (weakening or cutting) of separating the first semiconductor portion SL1 from the base substrate UK is easy. Gas (decomposition products) generated by the laser ablation is released to the outside of the semiconductor substrate HK through the hollow portion TK. For example, nanosecond pulsed laser light can be used as the laser light.

[0101] In Fig. 11, after the semiconductor substrate HK is formed, the protrusions TS are irradiated with laser light LZ while the etching solution EH is in contact with the side surfaces of the protrusions TS, thereby performing anisotropic etching that progresses from the side surfaces of the protrusions TS to the inside. Specifically, the nitride semiconductor (e.g., GaN-based semiconductor) of the protrusions TS is converted into an oxide (e.g., Ga2O3) using holes generated by photoexcitation and anions (e.g., hydroxide ions) of the etching solution EH, and this oxide is ionized and dissolved in the etching solution EH to weaken or cut across (cut parallel to the c-plane) the protrusions TS. Since the width of the protrusions TS is smaller than the width of the first semiconductor portion SL1, the process (weakening or cutting) of separating the first semiconductor portion SL1 from the base substrate UK is easy. Irradiation with the laser light LZ generates electron-hole pairs in the convex portion TS, the holes are used to oxidize the nitride semiconductor, and the electrons are consumed in a reaction in the etching solution EH (an electrode may be provided in the etching solution EH, but this is not limiting). By performing anisotropic wet etching as shown in Figure 11, the convex portion TS can be etched while suppressing the progression of etching in the Z direction (damage to the low dislocation portion WG).

[0102] In FIG. 11, the convex portion TS may include a target portion TL where etching proceeds preferentially. The target portion TL may be a target layer. The nitride semiconductor (e.g., GaN-based semiconductor) included in the target portion TL may have a smaller band gap than the nitride semiconductor included in the adjacent portions above and below. In this case, the laser light LZ may be UV light having energy larger than the band gap of the nitride semiconductor included in the target portion TL. For example, a HeCd laser with a wavelength of 325 nm may be used as such a UV laser.

[0103] The target portion TL may contain indium and gallium (for example, an InGaN layer). The target portion TL may have a higher porosity and a lower rigidity than the adjacent portions above and below. The target portion TL does not have to be provided in the center of the protruding portion TS, and may be provided to include the base portion of the protruding portion TS or the tip portion (the portion that is bonded to the base substrate UK).

[0104] In the third embodiment, the step of separating the first semiconductor portion SL1 from the base substrate UK may be a step performed after weakening the convex portion TS, or may be a step of cutting across the convex portion TS. The laser light LZ may be irradiated from the base substrate UK side or from the support substrate SK side, but the latter is selected when the base substrate UK has light-shielding properties (for example, when it includes a silicon substrate).

[0105] In the third embodiment, a step of forming a semiconductor substrate HK having an underlying substrate UK and a first semiconductor portion (semiconductor layer) SL1 bonded to the underlying substrate UK, and a step of separating the first semiconductor portion (semiconductor layer) SL1 from the underlying substrate UK can be performed. Here, the first semiconductor portion (semiconductor layer) SL1 has a protruding portion TS protruding toward the underlying substrate UK, the protruding portion TS includes a nitride semiconductor, the protruding portion TS is bonded to the underlying substrate UK, and the semiconductor substrate HK has a hollow portion TK located between the underlying substrate UK and the first semiconductor portion (semiconductor layer) SL1, and the hollow portion TK is in contact with a side surface of the protruding portion TS and communicates with the outside of the semiconductor substrate HK. Then, before separating the first semiconductor portion (semiconductor layer) SL1, at least one of irradiation of the laser light to the protruding portion TS and injection of an etching solution into the hollow portion TK can be performed.

[0106] [Additional notes] The above provides a detailed explanation of the manufacturing method for a semiconductor element according to the present disclosure. However, the present disclosure is not limited to the above-described embodiments, and various modifications, improvements, etc. are possible without departing from the gist of the present disclosure. For example, in the first embodiment, an example in which a GaN substrate is used as the base substrate has been described, but as shown in the second and third embodiments, a base substrate having a material different from the semiconductor material contained in the semiconductor layer 3 may be used. In this case, for example, the base substrate may be formed of sapphire (Al2O3), silicon carbide (SiC), silicon (Si), etc. In this case, a buffer portion and a seed portion may be disposed on the base substrate. Furthermore, for example, in the above example, the laser is irradiated after removing the mask, but the mask may be removed after the laser irradiation and before peeling off the semiconductor layer 3. [Explanation of symbols]

[0107] 1. Base substrate 1a One main surface (first surface) 1b Other main surface (second surface) 1c Side (3rd surface), end surface 2 Connection 21,22 End 23 Middle Section 3 Semiconductor layer 4. Etching solution 5. Laser light 6. Deposition suppression mask (mask) 6a Belt 7 Openings 8. Semiconductor device layer 8a Top 8b Bottom side 9 Adhesive layer 10 Support substrate 10a Opposite surface 10b Bonding layer 33 Semiconductor elements 61 Belt 62 Opening G Gap (emission path) S Semiconductor element a Formation process a1 Mask formation process a2 Semiconductor layer formation process a3 Mask removal process b Weakening process c Separation process c1 Preparation process C2 Bonding Process C3 Peeling Process S1 Element Formation Process S2 Light Irradiation Process S3 Separation Process

Claims

1. preparing a semiconductor substrate comprising an undersubstrate, and a first semiconductor portion and a second semiconductor portion each including a nitride semiconductor, the first semiconductor portion and the second semiconductor portion each including a downward protruding portion connected to the undersubstrate and a low-dislocation portion that is wider than the protruding portion and has a low dislocation density; irradiating the convex portion with light; weakening or cutting the convex portion irradiated with the light, the protrusion has a longitudinal direction aligned with the <1-100> direction of the nitride semiconductor; the first semiconductor portion and the second semiconductor portion are spaced apart from each other in a <11-20> direction of the nitride semiconductor; a first semiconductor portion and a second semiconductor portion each having a cross-sectional shape in which corners of a lower surface along a c-plane of the nitride semiconductor are rounded when viewed in a cross section in a <1-100> direction of the nitride semiconductor.

2. A method for manufacturing a semiconductor element as described in claim 1, wherein each of the first semiconductor portion and the second semiconductor portion has a corner of the lower surface that is inverted tapered when viewed in a cross section of the nitride semiconductor in the <1-100> direction.

3. A method for manufacturing a semiconductor element as described in claim 1 or 2, wherein the light is incident from the top surface of the first semiconductor part and reaches the convex portion.

4. The method for manufacturing a semiconductor element according to claim 1, wherein the convex portion is cut in a <11-20> direction of the nitride semiconductor.

5. A method for manufacturing a semiconductor element described in any one of claims 1 to 4, wherein the focus of the light is adjusted to the upper end of the downward convex portion.

6. A method for manufacturing a semiconductor element described in any one of claims 1 to 4, wherein the focus of the light is adjusted to the lower end of the downward convex portion.

7. A method for manufacturing a semiconductor element described in any one of claims 1 to 4, wherein the focus of the light is adjusted to a portion between the upper and lower ends of the downward convex portion.

8. The semiconductor substrate includes a mask portion between the base substrate and the low-dislocation portion, 8. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a hollow portion between the base substrate and the low dislocation portion by removing the mask portion.

9. 9. The method for manufacturing a semiconductor element according to claim 1, wherein the semiconductor substrate has a device portion located on the first semiconductor portion.

10. The method for manufacturing a semiconductor element according to claim 9 , wherein in the semiconductor substrate, the first semiconductor portion and the device portion are divided into a plurality of semiconductor element portions.

11. A method for manufacturing a semiconductor element according to any one of claims 1 to 10, comprising a step of isolating the first semiconductor portion from the base substrate.

12. A preparation step of preparing a support substrate; The method for manufacturing a semiconductor element according to claim 9 or 10, further comprising a bonding step of bonding the device portion to the support substrate by heating at least one of the support substrate and the base substrate while keeping the support substrate and the base substrate in contact with each other.

13. the nitride semiconductor is a GaN-based semiconductor, 13. The method for manufacturing a semiconductor device according to claim 1, wherein the base substrate has a heterogeneous substrate having a lattice constant different from that of the GaN-based semiconductor, and a seed portion formed on the heterogeneous substrate and including a nitride semiconductor.

14. The light is a laser beam, and laser ablation is caused on the convex portion by irradiation of the laser beam, The method for manufacturing a semiconductor device according to claim 8 , wherein gas generated by laser ablation is discharged to the outside of the semiconductor substrate through the hollow portion.

15. The light is laser light, the protruding portion includes a target portion where etching proceeds preferentially, The method for manufacturing a semiconductor element according to any one of claims 1 to 13, wherein anisotropic etching proceeding from the side surface of the convex portion to the inside is performed by irradiating the convex portion with laser light while bringing an etching solution into contact with the side surface of the convex portion.

16. The method for manufacturing a semiconductor device according to claim 15 , wherein the nitride semiconductor contained in the target portion has a smaller band gap than the nitride semiconductors contained in the adjacent portions above and below.

17. 17. The method for manufacturing a semiconductor element according to claim 15, wherein the laser light is UV light having energy larger than a band gap of a nitride semiconductor contained in the target portion.

18. The method for manufacturing a semiconductor device according to claim 16 or 17, wherein the target portion contains indium and gallium.

19. The method of claim 15 , wherein the target portion has a higher porosity than adjacent portions above and below.

20. A method for manufacturing a semiconductor element according to any one of claims 14 to 19, wherein the laser light is scanned in any direction along the substrate surface of the base substrate.

21. A semiconductor device comprising: a first semiconductor portion including a nitride semiconductor; and a support substrate located above the first semiconductor portion and holding the first semiconductor portion; the first semiconductor portion includes a downward convex portion whose longitudinal direction is in the <1-100> direction of the nitride semiconductor, and a low-dislocation portion which is wider than the convex portion and has a low dislocation density; A semiconductor device, wherein the first semiconductor portion has a cross-sectional shape in which corners of a lower surface along a c-plane of the nitride semiconductor are rounded when viewed in a cross section in a <1-100> direction of the nitride semiconductor.

22. A semiconductor device as described in claim 21, wherein a lower end of the convex portion is weakened compared to the low-dislocation portion.

23. A second semiconductor portion including the nitride semiconductor, The semiconductor device according to claim 21 or 22, wherein the first semiconductor portion and the second semiconductor portion are spaced apart from each other in a <11-20> direction of the nitride semiconductor.

24. A semiconductor device according to claim 21, wherein the convex portion has a shape that tapers downward when viewed in a cross section perpendicular to the <1-100> direction.

25. A semiconductor device according to claim 21, wherein the convex portion has a shape that tapers upward when viewed in a cross section perpendicular to the <1-100> direction.

26. A semiconductor device described in any one of claims 21 to 23, wherein the convex portion has a constricted shape having a portion between an upper end and a lower end that is narrower than the upper end and the lower end when viewed in a cross section perpendicular to the <1-100> direction.

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