Semiconductor modules and semiconductor packages

Abstract

To provide a semiconductor module for which warping that occurs prior to separation into individual pieces can be easily suppressed. A semiconductor module 1 is formed by integrally molding a plurality of chips. The module comprises: a reference panel 10, which includes a plurality of reference chips 12 arranged in a row and a reference molded section 14 that fills at least spaces between the plurality of reference chips 12; and a layered panel 20 which comprises layered chips 22 layered respectively onto the reference chips 12, and a layered molded section 23 that fills at least spaces between the plurality of layered chips 22, the layered panel being layered onto one side of the reference panel 10. Each of the layered chips 22 is disposed so that a partial region thereof overlaps with a partial region of the respective reference chip 12 in a layering direction and is disposed so as to overlap with the reference molded section 14. The reference chips 12 are disposed so as to overlap with the layered molded section 23.

Description

[Technical field]

[0001] The present invention relates to a semiconductor module and a semiconductor package. [Background technology]

[0002] Volatile memories (RAMs) such as DRAMs (Dynamic Random Access Memory) have been known as storage devices. DRAMs are required to have larger capacities to withstand the increasing performance of arithmetic units (hereinafter referred to as logic chips) and the increasing amount of data. To address this, efforts have been made to increase capacity by miniaturizing memories (memory cell arrays, memory chips) and adding cells in a planar manner. However, this type of capacity increase is reaching its limit due to factors such as vulnerability to noise caused by miniaturization and increased chip area.

[0003] In response to this, technology has been developed recently to stack multiple planar memories to create a three-dimensional (3D) memory with a large capacity. In addition, efforts are being made to increase the speed of data communication between chips (logic chips and memory chips) in response to the increase in data volume (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Publication No. 2016 / 0300813 [Patent Document 2] China Patent Publication No. 103887279 Summary of the Invention [Problem to be solved by the invention]

[0005] In the package of Patent Document 1, dies are mounted on the front and back sides of the RDL. In Patent Document 1, a first molding compound seals the die on the front side of the RDL. Also, in Patent Document 1, a second molding compound seals the die on the other side to the back side of the RDL. In Patent Document 1, the thicknesses of the two dies, the first molding compound, and the second molding compound are controlled to suppress warpage of the package. However, if the shrinkage stress of the first molding compound and the second molding compound accumulates, warpage may occur in the entire wafer before singulation into packages.

[0006] Moreover, in the package of Patent Document 2, each of the two stacked packages includes a chip and a metal layer disposed near the side of the chip. Moreover, in Patent Document 2, the chip and metal layer are molded using a first mold body and a second mold body disposed near the side of the chip. In Patent Document 2, warping of the entire wafer is suppressed by providing a metal layer. However, providing a metal layer may increase the number of manufacturing steps. Furthermore, providing a metal layer may also increase the manufacturing cost.

[0007] The present invention has been made in consideration of the above-mentioned problems, and has an object to provide a semiconductor module and a semiconductor package that can easily suppress warping before being divided into individual pieces. [Means for solving the problem]

[0008] The present invention relates to a semiconductor module in which a plurality of chips are integrally molded, comprising: a reference panel having a plurality of reference chips arranged in parallel and a reference mold portion filling the space sandwiched between at least a plurality of the reference chips; and a stacked panel having stacked chips stacked on each of the reference chips and a stacked mold portion filling the space sandwiched between at least a plurality of the stacked chips, stacked on one side of the reference panel, wherein the stacked chips are arranged so that some areas of the stacked chips overlap with the reference chip in the stacking direction, and the stacked chips are arranged so that they overlap with the reference mold portion, and the reference chip is arranged so that they overlap with the stacked mold portion.

[0009] The stacked chips are preferably stacked in one-to-one correspondence with the reference chips in the stacking direction.

[0010] Furthermore, it is preferable that the reference chip is positioned toward one end of one diagonal in a specific area of ​​a rectangle in a planar view that includes the reference chip and the stacked chip in a direction intersecting the stacking direction, and the stacked chip is positioned toward the other end of the one diagonal.

[0011] It is also preferable that a plurality of the laminated panels are provided, and that the laminated chips are arranged in the stacking direction so as to overlap with some areas of adjacent laminated chips, and so as to overlap with the laminated molded portions of the adjacent laminated chips.

[0012] It is also preferable that the stacked chips are stacked in a one-to-one correspondence with other stacked chips in the stacking direction.

[0013] It is also preferable that the other stacked chip is disposed toward one end side of the other diagonal, and the further stacked chip is disposed toward the other end side of the other diagonal.

[0014] It is also preferable that the laminated chips are different types of chips for each laminated panel.

[0015] At least one of the stacked chips is preferably a bumpless stacked chip.

[0016] It is also preferred that the laminated panel is connected to another laminated panel or a reference panel using microbumps.

[0017] It is also preferable that the reference chip is a chip of a different type from the stacked chips.

[0018] The present invention also relates to a semiconductor package obtained by singulating the reference chip and the stacked chip, which are arranged in a stacked manner, into a set of the above-mentioned semiconductor module. Effect of the Invention

[0019] According to the present invention, it is possible to provide a semiconductor module and a semiconductor package that can easily suppress warping before being separated into individual pieces. [Brief description of the drawings]

[0020] [Figure 1] 1 is a plan view showing a semiconductor module according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a partially enlarged view of FIG. [Diagram 3] 3 is a cross-sectional view taken along line AA in FIG. 2. [Figure 4] 1 is a plan view showing a semiconductor package obtained by dividing the semiconductor module according to the first embodiment; [Diagram 5] 5 is a cross-sectional view of FIG. 4 taken along line B-B. [Figure 6] FIG. 6 is a plan view showing a semiconductor module according to a second embodiment of the present invention. [Figure 7] FIG. 7 is a partially enlarged view of FIG. [Figure 8] 8 is a cross-sectional view taken along CC in FIG. 7 . [Figure 9] 11 is a cross-sectional view of a semiconductor package obtained by dividing the semiconductor module according to the second embodiment. FIG. [Figure 10] 13 is a plan view showing a semiconductor package obtained by dividing a semiconductor module according to a third embodiment of the present invention. FIG. [Figure 11] FIG. 11 is a cross-sectional view of another semiconductor package according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] A semiconductor module 1 and a semiconductor package 100 according to each embodiment of the present invention will be described below with reference to FIGS. First, an overview of the semiconductor module 1 and the semiconductor package 100 according to each embodiment will be described.

[0022] The semiconductor module 1 according to each embodiment is configured by stacking a plurality of semiconductor panels, each having a plurality of chips arranged side by side, in a stacking direction. The semiconductor module 1 and the semiconductor panel may be in the form of a circular wafer as shown in FIG. 1 or a rectangular plate (not shown). The semiconductor panel has a structure in which a molding material is filled at least between a plurality of chips arranged side by side. Here, a difference in shrinkage stress occurs between the molding material and the chips due to a difference in thermal expansion coefficient. Therefore, shrinkage stress accumulates at the overlapping position of the molding material. The accumulation of shrinkage stress may cause warping of the semiconductor module 1. In each of the following embodiments, the accumulation of shrinkage stress is suppressed by shifting the positions of the overlapping chips in a direction intersecting the stacking direction.

[0023] [First embodiment] Next, a semiconductor module 1 and a semiconductor package 100 according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3, the semiconductor module 1 is formed by integrally molding a plurality of chips. The semiconductor module 1 includes a base panel 10, a laminated panel 20, and bumps 30 for external connection.

[0024] The reference panel 10 is, for example, a semiconductor panel formed in a circular shape in a plan view. The reference panel 10 has, for example, a structure in which a plurality of chips are arranged side by side and a molding material is filled at least between the chips. As shown in FIG. 3, the reference panel 10 includes a reference re-distribution layer (RDL) layer 11, a reference chip 12, pillars 13, and a reference mold part 14.

[0025] The reference redistribution layer 11 is, for example, circular in plan view. The reference redistribution layer 11 is, for example, a layer that enables electrical connection in the thickness direction (stacking direction). As shown in FIG. 3, the reference redistribution layer 11 forms a surface that is exposed on one plane of the reference panel 10.

[0026] The reference chip 12 is a different type of chip from the stacked chips described below. The reference chip 12 is, for example, a logic chip. As shown in Figs. 1 and 2, a plurality of reference chips 12 are provided and arranged side by side. In this embodiment, the reference chips 12 are rectangular in plan view and arranged in a lattice pattern. The plurality of reference chips 12 are arranged on one surface of the reference redistribution layer 11 and are electrically connected to the reference redistribution layer 11.

[0027] The pillars 13 are, for example, Cu. The pillars 13 extend from one surface of the standard redistribution layer 11. The pillars 13 are, for example, configured to have the same or approximately the same height as the height of the logic chip in the stacking direction. A plurality of pillars 13 are provided, for example, as shown in FIGS. 3 and 4.

[0028] The reference mold part 14 is filled in at least a space sandwiched between the multiple reference chips 12. The reference mold part 14 is, for example, a thermosetting epoxy resin. The reference mold part 14 is formed to have an outer shape that matches the circular shape of the reference redistribution layer 11 in a plan view, as shown in, for example, FIGS.

[0029] The laminated panel 20 is, for example, a semiconductor panel formed in a circular shape in a plan view with the same diameter as the reference panel 10. The laminated panel 20 has, for example, a structure in which a plurality of chips are arranged side by side with a molding material filled at least between the chips. As shown in FIG. 3, the laminated panel 20 includes a laminated rewiring layer 21, a laminated chip 22, and a laminated molded part 23. As shown in FIG. 3, the laminated panel 20 is laminated on one surface side of the reference panel 10. Specifically, the laminated panel 20 is laminated on the surface of the reference panel 10 opposite to the surface on which the reference rewiring layer 11 is exposed.

[0030] The laminated redistribution layer 21 is configured, for example, in a circular shape when viewed from above. The laminated redistribution layer 21 is, for example, a layer that enables electrical connection in the thickness direction (stacking direction). The laminated redistribution layer 21 forms a surface exposed on one plane of the laminated panel 20. In this embodiment, the laminated redistribution layer 21 may be arranged in contact with the reference chip 12 and the reference mold part 14 exposed on the other surface of the reference panel 10. In addition, the laminated redistribution layer 21 is arranged in electrical connection to the pillars 13.

[0031] The stacked chips 22 are, for example, RAMs. As shown in Fig. 1 and Fig. 2, a plurality of stacked chips 22 are provided and arranged side by side. In this embodiment, the stacked chips 22 are rectangular in plan view and arranged in a lattice pattern. The multiple stacked chips 22 are arranged on one surface of the stacked redistribution layer 21 and are electrically connected to the stacked redistribution layer 21.

[0032] The laminated mold part 23 is filled in at least the space between the plurality of laminated chips 22. The laminated mold part 23 is, for example, a thermosetting epoxy resin or the like. The laminated mold part 23 is formed to have an outer shape that matches the circular shape of the laminated rewiring layer 21 in a plan view, as shown in, for example, FIGS.

[0033] According to the above-mentioned reference chip 12, stacked chip 22, reference mold section 14, and stacked mold section 23, as shown in FIG. 1 to FIG. 5, the stacked chip 22 is arranged so as to overlap with the reference chip 12 in some regions in the stacking direction. The reference chip 12 is arranged so as to overlap with the stacked mold section 23. Also, the stacked chip 22 is stacked in one-to-one correspondence with the reference chip 12 in the stacking direction. Here, the reference chip 12 is arranged near one end of one diagonal in a predetermined region of a rectangle in a plan view including the reference chip 12 and the stacked chip 22 in a direction intersecting the stacking direction. Also, the stacked chip 22 is arranged near the other end of one diagonal. That is, the reference chip 12 and the stacked chip 22 are arranged offset in a direction away from each other (toward the corners) in one diagonal direction of the rectangular region as shown in FIG. 1, FIG. 2, and FIG. 4. That is, reference chip 12 is arranged so as to overlap across stacked mold part 23 and stacked chip 22 in a direction intersecting the stacking direction. Also, stacked chip 22 is arranged so as to overlap across reference mold part 14 and reference chip 12 in a direction intersecting the stacking direction. In this way, reference chip 12 and stacked chip 22 are arranged so as to reduce the overlapping area between reference mold part 14 and stacked mold part 23 in the stacking direction.

[0034] The semiconductor package 100 is obtained by dividing a set of the reference chip 12 and the stacked chip 22. Specifically, the semiconductor package 100 can be obtained by dividing the semiconductor module 1 into individual pieces for each predetermined rectangular area including one each of the reference chip 12 and the stacked chip 22, as shown in FIG.

[0035] The external connection bumps 30 are, for example, solder bumps. The external connection bumps 30 are arranged to establish electrical connection with the outside of the semiconductor module 1 (semiconductor package 100). The external connection bumps 30 are arranged on the exposed surface of the standard redistribution layer 11.

[0036] Next, the semiconductor module 1 of this embodiment and the operation of the semiconductor module 1 will be described. When heat is applied when the reference panel 10 and the laminated panel 20 are laminated, the reference mold part 14 and the laminated mold part 23 shrink. As shown in Fig. 3, in the lamination direction, the laminated chip 22, which has a small shrinkage stress, is overlapped on the reference mold part 14, which has a large shrinkage stress. Also, the reference chip 12, which has a small shrinkage stress, is overlapped on the laminated mold part 23, which has a large shrinkage stress. This makes it possible to suppress the concentration of shrinkage stress compared to when the reference mold part 14 and the laminated mold part 23 overlap. Therefore, warping of the semiconductor module 1 is reduced compared to when the reference mold part 14 and the laminated mold part 23, both of which have a large shrinkage stress, are arranged overlapping each other.

[0037] The semiconductor module 1 and the semiconductor package 100 according to the first embodiment described above provide the following advantages. (1) A semiconductor module 1 in which a plurality of chips are integrally molded, comprising: a reference panel 10 having a plurality of reference chips 12 arranged in parallel and a reference mold section 14 filling a space between at least the plurality of reference chips 12; and a laminated panel 20 having stacked chips 22 stacked on each of the reference chips 12 and a stacked mold section 23 filling a space between at least the plurality of stacked chips 22, stacked on one side of the reference panel 10, in which the stacked chips 22 are arranged so as to overlap with the reference chips 12 in some regions in the stacking direction, and are also arranged so as to overlap with the reference mold section 14, and the reference chips 12 are arranged so as to overlap with the stacked mold section 23. This makes it possible to distribute the shrinkage stress acting on the semiconductor module 1, and therefore makes it possible to easily suppress warping of the semiconductor module 1 before it is singulated.

[0038] (2) The stacked chips 22 are stacked in one-to-one correspondence with the reference chips 12 in the stacking direction. This makes it easier to separate the chips because no chip is disposed across multiple chips in a direction intersecting the stacking direction.

[0039] (3) In a predetermined area of ​​a rectangle in plan view including the reference chip 12 and the stacked chip 22 in a direction intersecting the stacking direction, the reference chip 12 is disposed close to one end of one diagonal, and the stacked chip 22 is disposed close to the other end of the one diagonal. This allows the chip and the molded part to be overlapped over a wider area, so that the shrinkage stress can be more dispersed and warping before singulation can be easily suppressed.

[0040] [Second embodiment] Next, a semiconductor module 1 and a semiconductor package 100 according to a second embodiment of the present invention will be described with reference to Figures 6 to 9. In the second embodiment, the same components are denoted by the same reference numerals, and descriptions thereof will be simplified or omitted. 6 to 9, the semiconductor module 1 according to the second embodiment differs from the first embodiment in that a plurality of stacked panels 20 are provided. The semiconductor module 1 according to the second embodiment also differs from the first embodiment in that a stacked chip 22 is arranged to overlap with another adjacent stacked chip 22 in a portion of the stacking direction, and is arranged to overlap with a stacked mold portion 23 of the other adjacent stacked chip 22. The semiconductor module 1 according to the second embodiment also differs from the first embodiment in that the stacked panel 20 and the other stacked panels 20 have pillars 26 similar to the reference panel 10.

[0041] 6 to 9, the stacked chips 22 are stacked in one-to-one correspondence with the other stacked chips 24 in the stacking direction. The stacked chips 22 are further stacked in one-to-one correspondence with the other stacked chips 25. That is, the stacked chips 22 are arranged in one-to-one correspondence with the reference chip 12, the other stacked chips 24, and the further stacked chips 25.

[0042] Here, the other stacked chip 24 and the further stacked chip 25 are arranged on the other diagonal line with respect to one diagonal line of the first embodiment, as shown in Figs. 6 and 7. Specifically, the other stacked chip 24 is arranged toward one end side of the other diagonal line. Moreover, the further stacked chip 25 is arranged toward the other end side of the other diagonal line. That is, the reference chip 12, the stacked chip 22, the other stacked chip 24, and the further stacked chip 25 are arranged in the four quadrants of a predetermined area and in the vicinity of the corners of a rectangular area. As a result, as shown in Figs. 8 and 9, the semiconductor module 1 reduces the overlapping area of ​​the reference mold part 14 and the stacked mold part 23 in the stacking direction. Therefore, warping of the semiconductor module 1 is suppressed.

[0043] The semiconductor module 1 and the semiconductor package 100 according to the second embodiment described above provide the following advantages. (4) A plurality of laminated panels 20 are provided, and each laminated chip 22 is arranged to overlap with another adjacent laminated chip 24 in a portion of the laminated chip 22 in the laminated direction, and is also arranged to overlap with the laminated molded portion 23 of the other adjacent laminated chip 24. This makes it possible to reduce the overlapping area of ​​the molded portions in the laminated direction, and thus makes it possible to easily suppress warping of the semiconductor module 1.

[0044] (5) The stacked chips 22 are stacked in a one-to-one correspondence with other stacked chips 24 in the stacking direction. This allows the semiconductor wafer 1 to be easily divided into individual chips.

[0045] (6) Another stacked chip 24 is disposed toward one end of the other diagonal, and yet another stacked chip 25 is disposed toward the other end of the other diagonal. This makes it possible to further reduce the overlapping area of ​​the molded parts in the stacking direction of the semiconductor module 1, thereby suppressing warping of the semiconductor module 1.

[0046] [Third embodiment] Next, a semiconductor module 1 and a semiconductor package 100 according to a third embodiment of the present invention will be described with reference to Figures 10 and 11. In the third embodiment, the same components are denoted by the same reference numerals, and descriptions thereof will be simplified or omitted. The semiconductor module 1 and semiconductor package 100 according to the third embodiment differ from the first and second embodiments in that the reference chip 12 and the stacked chip 22 are connected using microbumps 40, silicon through electrodes 41, and a back surface redistribution layer 27 formed on the surface of the reference chip 12 opposite to the reference redistribution layer 11. That is, as shown in Fig. 11, the semiconductor module 1 and semiconductor package 100 according to the third embodiment differ from the first and second embodiments in that the reference panel 10 and the stacked panel 20 are connected using microbumps 40, silicon through electrodes 41, and a back surface redistribution layer 27 electrically connected to the silicon through electrodes 41. Furthermore, the semiconductor module 1 and semiconductor package 100 of the third embodiment differ from the first and second embodiments in that, as shown in FIG. 10, when the microbumps 40 are in a position that does not overlap with the reference chip 12, the stacked chip 22, or another stacked chip 24 to which they are connected, the stacked redistribution layer 21 (not shown) is arranged on one side of the reference chip 12 (the side opposite to the side connected to the reference redistribution layer 11), one side of the stacked chip 22 (the side on the stacked chip 22 of the stacked panel 20 to be stacked), and one side of the other stacked chip 24 (the side on the stacked chip 24 of the stacked panel 20 to be stacked).

[0047] The semiconductor module 1 and the semiconductor package 100 according to the third embodiment described above provide the following advantages. (7) The laminated panel 20 is connected to another laminated panel 20 or the reference panel 10 using the microbumps 40 and the silicon through electrodes 41 and the backside rewiring layer 27 electrically connected to the silicon through electrodes 41. The laminated panel 20 is also connected to another laminated panel 20 or the reference panel 10 using the microbumps 40 and the silicon through electrodes 41 and the stacked rewiring layer 21 electrically connected to the silicon through electrodes 41. This makes it possible to reduce the overlapping area of ​​the reference mold part 14 and the stacked mold part 23 in the stacking direction even when the reference chip 12 and the stacked chip 22 are connected using the microbumps 40. Therefore, warping of the semiconductor wafer 1 can be suppressed.

[0048] Although the preferred embodiments of the semiconductor module and semiconductor package of the present invention have been described above, the present invention is not limited to the above-described embodiments and can be modified as appropriate.

[0049] For example, in the above-described embodiments, the stacked chips 22 may be different types of chips for each stacked panel 20. In addition, in the third embodiment, at least one of the stacked chips 22 may be a bumpless stacked chip.

[0050] In the above embodiment, the reference chip 12 may be the same type of chip as the stacked chips 22. That is, the reference chip 12 may be a RAM.

[0051] In the third embodiment, pillars (not shown) may be used as in the first and second embodiments. This allows the areas of the reference mold part 14 and the stacked mold part 23 to be reduced, making it possible to easily reduce warpage of the semiconductor wafer 1. [Explanation of symbols]

[0052] 1 Semiconductor module 10 Reference Panel 11 Reference redistribution layer 12 Reference Chip 13,26 Pillar 14 Reference mold part 20 Laminated Panel 21 Laminated redistribution layer 22,24,25 Stacked chip 23 Laminated mold section 27 Backside redistribution layer 40 Microbump 41 Silicon through-hole via 100 Semiconductor Packages

Claims

1. A semiconductor module in which a plurality of chips are integrally molded, a reference panel having a plurality of reference chips arranged side by side and a reference mold portion that fills at least a space between the plurality of reference chips; a laminated panel including laminated chips laminated on the respective reference chips and a laminated mold portion filled in a space between at least a plurality of the laminated chips, the laminated panel being laminated on one surface side of the reference panel; Equipped with The stacked chip is disposed so as to overlap with the reference chip in a stacking direction in a partial area thereof, and is disposed so as to overlap with the reference mold part, The reference chip is disposed so as to overlap the laminate mold part, the reference chip is disposed toward one end of one diagonal in a predetermined region of a rectangle in a plan view that includes the reference chip and the stacked chips in a direction intersecting a stacking direction; The stacked chip is disposed toward the other end of the one diagonal of the semiconductor module.

2. The semiconductor module according to claim 1 , wherein the stacked chips are stacked in a one-to-one correspondence with the reference chip in a stacking direction.

3. The laminated panel is provided in plurality, The semiconductor module according to claim 1 or 2, wherein the stacked chip is arranged so as to overlap with another adjacent stacked chip in a portion of the stacking direction, and is arranged so as to overlap with the stacked molded portion of the other adjacent stacked chip.

4. The semiconductor module according to claim 3 , wherein the stacked chips are stacked in a one-to-one correspondence with other stacked chips in the stacking direction.

5. The other stacked chip is disposed toward one end of the other diagonal line, 5. The semiconductor module according to claim 3, wherein the other stacked chip is disposed toward the other end of the other diagonal.

6. The semiconductor module according to claim 1 , wherein the laminated chips are different types of chips for each laminated panel.

7. 6. The semiconductor module according to claim 1, wherein at least one of the stacked chips is a bumpless stacked chip.

8. The semiconductor module according to claim 1 , wherein the laminated panel is connected to another laminated panel or a reference panel by using microbumps.

9. 9. The semiconductor module according to claim 1, wherein the reference chip is a chip of a different type from the stacked chips.

10. 10. A semiconductor package obtained by singulating the reference chip and the stacked chip, which are arranged in a stacked manner, as a set, of the semiconductor module according to claim 1.

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