Semiconductor Device

Abstract

To suppress performance degradation of a semiconductor device.SOLUTION: A semiconductor device has a semiconductor chip CPL having a non-overlapping region where the source pad SPL for the main transistor and the clip CLL do not overlap. In this case, the sense transistor 100 is located within the region between the first portion PU1 of the clip CLL and the first short side SS1 of the source pad SPL for the main transistor in plan view in the non-overlapping region.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device that is a component of an inverter, for example. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2018-121035 (Patent Document 1) describes a technology related to a packaging structure of a semiconductor device that is a component of an inverter. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-121035 A Summary of the Invention [Problem to be solved by the invention]

[0004] For example, there is a semiconductor device that seals a semiconductor chip on which a power transistor is formed, in which leads and electrodes called pads formed on the surface of the semiconductor chip are connected by a plate-shaped member called a "clip."

[0005] The plate-like member and the pad are connected via a conductive member, typically silver paste or solder. Here, peeling may occur in the conductive member due to the manufacturing process of the semiconductor device. The present inventor has newly discovered that after a reliability test of the semiconductor device, the peeling area may vary, and this variation in the peeling area may adversely affect the performance of the semiconductor device. Therefore, based on the new knowledge discovered by the present inventor, there is a need for a device that can reduce the adverse effect on the performance of the semiconductor device even if the peeling area varies. [Means for solving the problem]

[0006] In one embodiment, the semiconductor device includes a semiconductor chip having a non-overlapping region where a first electrode and a plate-like member do not overlap, and the sense transistor is located in a first region of the non-overlapping region between a first portion of the plate-like member and a first short side of the first electrode in a plan view. Effect of the Invention

[0007] According to one embodiment, it is possible to suppress a decrease in performance of a semiconductor device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a 12-phase brushless DC motor control system. [Diagram 2] FIG. 2 is a diagram showing a circuit configuration of an inverter circuit. [Diagram 3] FIG. 1 is a diagram showing a mounting configuration of a semiconductor device that realizes an inverter circuit. [Figure 4] FIG. 13 is a cross-sectional view illustrating a molding process for forming a sealing body, which is a view for explaining room for improvement newly found by the present inventors. [Diagram 5] FIG. 13 shows the clip in a "reverse tilt" state. [Figure 6] 1A and 1B are diagrams illustrating room for improvement in the related art. [Figure 7] FIG. 2 is a diagram showing a schematic diagram of "a location that is less susceptible to potential changes due to an increase or decrease in the amount of peeled off silver paste." [Figure 8] FIG. 1 is a diagram showing an embodiment that embodies the basic concept. [Figure 9] FIG. 9 is a cross-sectional view taken along line AA in FIG. 8. [Figure 10] FIG. 13 is a diagram showing a first modified example. [Figure 11] FIG. 11 is a diagram showing a second modified example. [Figure 12] FIG. 13 is a diagram showing a third modified example. [Figure 13] FIG. 13 is a diagram showing a fourth modified example. [Figure 14]1 is a flowchart illustrating an assembly process of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0010] <12-phase brushless DC motor control system> In recent years, in anticipation of functional safety for the practical application of autonomous driving in automobiles, the conventional three-phase brushless DC motors have been designed and developed to be six-phase or twelve-phase brushless DC motors. Brushless DC motors are not self-commuting, and are generally recognized to be complex to control. Therefore, a six-phase brushless DC motor control system that controls a six-phase brushless DC motor uses two sets of the conventional three phases (U phase, V phase, W phase), while a 12-phase brushless DC motor control system that controls a 12-phase brushless DC motor uses four sets of the conventional three phases (U phase, V phase, W phase), so that even if a malfunction occurs in one set, the malfunction does not immediately become apparent.

[0011] An inverter circuit is used as a circuit to control each phase, and the AC power supplied from this inverter circuit is supplied to the coils of each phase of the brushless DC motor. For this reason, a brushless DC motor control system that controls a 6-phase brushless DC motor or a 12-phase brushless DC motor uses 6 or 12 inverter circuits.

[0012] FIG. 1 is a diagram illustrating a schematic configuration of a 12-phase brushless DC motor control system.

[0013] The motor MOT shown in FIG. 1 is a 12-phase brushless DC motor and has 12 coils CL. Each coil CL is connected to an inverter circuit INV. That is, an inverter circuit INV is provided for each of the 12 coils of the motor MOT. Therefore, the 12-phase brushless DC motor control system shown in FIG. 1 has a total of 12 inverter circuits INV. Each inverter circuit INV is connected to a control circuit CT provided in an MCU (Micro Controller Unit), and each inverter circuit is controlled by this control circuit CT. Then, each inverter circuit INV controlled by the control circuit CT supplies AC power to the coils CL connected to the respective inverter circuits INV, thereby driving the motor MOT.

[0014] <Inverter circuit configuration> Next, a circuit configuration of the inverter circuit INV, which is a component of the above-mentioned 12-phase brushless DC motor control system, will be described.

[0015] FIG. 2 is a diagram showing a circuit configuration of the inverter circuit INV.

[0016] 2, the inverter circuit INV has a high-side switching circuit 10, a low-side switching circuit 20, and a control circuit 30.

[0017] The high-side switching circuit 10 includes a main transistor 11 which is a power transistor, and a sense transistor 12 .

[0018] On the other hand, the low-side switching circuit 20 includes a main transistor 21 made of a power transistor, and a sense transistor 22 .

[0019] In the high-side switching circuit 10 and the low-side switching circuit 20 configured in this manner, the main transistor 11 included in the high-side switching circuit 10 and the main transistor 21 included in the low-side switching circuit 20 are connected in series between a power supply potential VIN and a ground potential GND.

[0020] 2, the connection node between the main transistor 11 and the main transistor 21 is "OUT", and this connection node is connected to the coil CL shown in FIG.

[0021] Next, the control circuit 30 includes, for example, a pre-driver that applies a gate voltage to the gate electrode of the main transistor 11 and the gate electrode of the sense transistor 12, and a pre-driver that applies a gate voltage to the gate electrode of the main transistor 21 and the gate electrode of the sense transistor 22. Furthermore, the control circuit 30 has a sense circuit 31 electrically connected to the sense transistor 22 included in the low-side switching circuit 20.

[0022] 2, the inverter circuit INV has a sense circuit 31 electrically connected to the sense transistor 22 included in the low-side switching circuit 20, but for example, the sense transistor 12 included in the high-side switching circuit 10 is not used, and there is no sense circuit electrically connected to the sense transistor 12 included in the high-side switching circuit 10. However, the inverter circuit INV is not limited to this, and may be configured to have, for example, a sense circuit 31 electrically connected to the sense transistor 22 included in the low-side switching circuit 20 and a sense circuit electrically connected to the sense transistor 12 included in the high-side switching circuit 10. Furthermore, there may be no sense circuit 31 electrically connected to the sense transistor 22 included in the low-side switching circuit 20, but a sense circuit electrically connected to the sense transistor 12 included in the high-side switching circuit 10.

[0023] 2, an input node that inputs a control signal from the control circuit CT shown in FIG. 1 to the control circuit 30 is "IN", and an output node that outputs an output signal from the sense circuit 31 of the control circuit 30 is "OUT2". This output node is electrically connected to the control circuit CT shown in FIG. 1. In this manner, the inverter circuit INV is configured.

[0024] The control circuit 30 is configured to control the on / off of the main transistor 11 included in the high-side switching circuit 10 and to control the on / off of the main transistor 21 included in the low-side switching circuit 20, based on a control signal from the control circuit CT shown in Fig. 1. That is, the control circuit 30 controls the on / off of the main transistor 11 by switching the gate voltage applied to the gate electrode of the main transistor 11, and controls the on / off of the main transistor 21 by switching the gate voltage applied to the gate electrode of the main transistor 21.

[0025] In this manner, by controlling the main transistor 11 on / off and the main transistor 21 on / off, AC power is supplied from the connection node ("OUT") between the main transistor 11 and the main transistor 21 to the coil CL shown in FIG.

[0026] Here, the sense transistor 22 included in the low-side switching circuit 20 is provided to detect the current value of the current flowing through the main transistor 21 .

[0027] For example, the main transistor 21 and the sense transistor 22 form a current mirror circuit such that the current value of the current flowing through the main transistor 21:the current value of the current flowing through the sense transistor 22=12500:1 (sense ratio).

[0028] The sense transistor 22 is electrically connected to the sense circuit 31, and the current flowing through the sense transistor 22 is converted into a voltage by the sense circuit 31, and then output from the output node "OUT2" to the control circuit CT shown in Fig. 1. At this time, the control circuit CT shown in Fig. 1 measures the current value of the current flowing through the main transistor 21 based on the voltage signal input from "OUT2" and the "sense ratio".

[0029] The inverter circuit INV is configured as described above.

[0030] <Package structure> Next, the mounting configuration of the inverter circuit INV will be described.

[0031] FIG. 3 is a diagram showing a mounting configuration of a semiconductor device PKG that realizes an inverter circuit.

[0032] 3, the semiconductor device PKG has a sealing body MR having a rectangular planar shape. The sealing body MR has a side S1 which is a long side, a side S2 which faces the side S1, a side S3 which is a short side intersecting the sides S1 and S2, and a side S4 which faces the side S3. The leads LD protrude from the long sides S1 and S2.

[0033] 3, the outline of the sealing body MR is indicated by a dashed line, and components sealed inside the sealing body MR are illustrated. The internal configuration of the sealing body MR will be described below.

[0034] The semiconductor device PKG has a die pad DPC which is a chip mounting portion, a die pad DPL which is a chip mounting portion, and a die pad DPH which is a chip mounting portion. Specifically, the die pad DPL, the die pad DPC, and the die pad DPH are arranged in this order in the x direction. In other words, the die pad DPL is arranged on the left side, the die pad DPC is arranged in the center, and the die pad DPH is arranged on the right side.

[0035] A semiconductor chip CPC is mounted on the die pad DPC. A control circuit 30 shown in FIG. 2 is formed on this semiconductor chip CPC. A plurality of pads including, for example, a plurality of pads PDC1 and a plurality of pads PDC2 are formed on the surface of the semiconductor chip CPC. In this manner, the semiconductor chip CPC mounted on the die pad DPC is disposed in the center of the semiconductor device PKG.

[0036] Next, the semiconductor chip CPL is mounted on the die pad DPL. The low-side switching circuit 20 shown in FIG. 2 is formed on this semiconductor chip CPL. That is, the main transistor 21 and the sense transistor 22 constituting the low-side switching circuit 20 are formed on the semiconductor chip CPL. The main transistor 21 and the sense transistor 22 are composed of vertical trench power transistors that pass a current in the thickness direction of the semiconductor chip CPL. Then, a plurality of pads PDL are formed on the surface of the semiconductor chip CPL together with a source pad SPL for the main transistor. The plurality of pads PDL include a source pad for the sense transistor and a gate pad common to the main transistor 21 and the sense transistor 22.

[0037] As shown in Fig. 3, a clip CLL, which is a plate-like member made of copper, is disposed on the main transistor source pad SPL. As shown in Fig. 3, the clip CLL is electrically connected to the leads LDL. Meanwhile, each of the pads PDL is electrically connected to each of the pads PDC2 formed on the surface of the semiconductor chip CPC by a bonding wire W.

[0038] Next, the semiconductor chip CPH is mounted on the die pad DPH. The high-side switching circuit 10 shown in FIG. 2 is formed on this semiconductor chip CPH. That is, the main transistor 11 and the sense transistor 12 constituting the high-side switching circuit 10 are formed on the semiconductor chip CPH. The main transistor 11 and the sense transistor 12 are composed of vertical trench power transistors that pass a current in the thickness direction of the semiconductor chip CPH. On the surface of the semiconductor chip CPH, a plurality of pads PDH are formed together with a source pad SPH for the main transistor. The plurality of pads PDH include a source pad for the sense transistor and a gate pad common to the main transistor 11 and the sense transistor 12.

[0039] As shown in Fig. 3, a clip CLH, which is a plate-shaped member made of copper, is disposed on the main transistor source pad SPH. As shown in Fig. 3, the clip CLH is electrically connected to the leads LDH. Meanwhile, each of the pads PDH is electrically connected to each of the pads PDC1 formed on the surface of the semiconductor chip CPC by a bonding wire W.

[0040] In this embodiment, the planar shape of the semiconductor device PKG is substantially rectangular (specifically, a rectangle with each corner chamfered) as shown in Fig. 3. In this embodiment, the planar shape of each semiconductor chip is also rectangular as shown in Fig. 3. In this embodiment, the semiconductor chip CPC, the semiconductor chip CPL, and the semiconductor chip CPH are arranged so that the short side of each semiconductor chip is aligned with the long side of the semiconductor device PKG as shown in Fig. 3. This reduces the size of each semiconductor chip and the size of the semiconductor device PKG.

[0041] In this embodiment, the semiconductor chip CPL in which the low-side switching circuit 20 is formed and the semiconductor chip CPH in which the high-side switching circuit 10 is formed are the same type of semiconductor chip.

[0042] In this manner, a semiconductor device PKG is implemented and configured, which is composed of a SiP (System in Package) in which the semiconductor chip CPC, on which the circuit that constitutes the inverter circuit INV is formed, the semiconductor chip CPL, and the semiconductor chip CPH are implemented in a single package structure.

[0043] <Consideration of improvements> In the following, the clip CLL will be taken up as an example of the plate-like member, and room for improvement that exists in the semiconductor device PKG will be described.

[0044] In the above-mentioned semiconductor device PKG, in order to improve the heat dissipation efficiency, a configuration is sometimes adopted in which the back surface of the die pad DPL (die pad DPC, die pad DPH) is exposed from the lower surface of the sealing body MR. In the semiconductor device PKG having such a configuration, the present inventors have newly found that there is room for improvement as described below.

[0045] FIG. 4 is a cross-sectional view illustrating a molding process for forming a sealing body MR, which is a diagram for explaining room for improvement newly found by the present inventor. In FIG. 4, the leads 60A and 60B present in the lead frame are sandwiched between a lower mold 70A and an upper mold 70B. Then, in the cavity CAV, the die pad DPL, the semiconductor chip CPL mounted on the die pad DPL via the silver paste 50A, and the clip CLL mounted on the main transistor source pad SPL formed on the semiconductor chip CPL via the silver paste 50B are arranged. In addition, this clip CLL is connected to the lead 60A via the silver paste 50C. That is, the clip CLL has a function of electrically connecting the main transistor source pad SPL and the lead 60A.

[0046] Here, in the molding process shown in Fig. 4, a sealing body is formed by injecting resin into the cavity CAV. At this time, if a gap exists between the lower mold 70A and the die pad DPL in Fig. 4, the resin also flows into this gap. For this reason, in order to prevent a gap into which the resin flows from being formed between the lower mold 70A and the die pad DPL, for example, as shown in Fig. 4, the molding process is performed while applying a force pushing the die pad DPL from the lower mold 70A toward the cavity CAV.

[0047] In this case, the leads 60A and 60B are sandwiched and fixed between the lower mold 70A and the upper mold 70B. Meanwhile, the die pad DPL is pressed into the cavity CAV by the above-mentioned pressing force. As a result, the "offset X" showing the height difference between the lead 60A (60B) and the die pad DPL shown in FIG. 4 changes in a decreasing direction. Then, a force is applied to the clip CLL connected to both the lead 60A and the semiconductor chip CPL in the direction shown by the arrow in FIG. 4.

[0048] This causes deformation of the clip CLL, for example, as shown in Fig. 5. Specifically, the clip CLL, which connects to both the main transistor source pad SPL and the lead 60A formed on the semiconductor chip CPL, is generally disposed parallel to the semiconductor chip CPL, but the above-mentioned pressing force applied to the die pad DPL causes deformation in which the tip portion of the clip CLL becomes higher than the base portion of the clip CLL.

[0049] In this specification, the shape in which the tip portion of the clip CLL is higher than the base portion of the clip CLL as shown in FIG. 5 is referred to as "reverse inclination."

[0050] In this way, in the molding process for manufacturing the semiconductor device PKG in which the back surface of the die pad DPL is exposed from the lower surface of the sealing body MR, a pressing force is applied from the lower mold 70A to the cavity CAV side of the die pad DPL so that a gap into which the resin flows is not formed between the lower mold 70A and the die pad DPL. As a result, for example, as shown in FIG. 5, the shape of the clip CLL becomes "reverse inclined."

[0051] When the shape of the clip CLL becomes "reverse inclined," the portion of the silver paste 50B that contacts the base portion 80 of the clip CLL becomes thinner than the other portions of the silver paste 50B. This causes structural stress applied to the semiconductor device, resulting in, for example, peeled portion 90 in the silver paste 50B shown in FIG.

[0052] In this regard, the silver paste 50B has a function of electrically connecting the main transistor source pad SPL and the clip CLL formed on the semiconductor chip CPL, and serves as a current path through which a current flows. For this reason, if peeling occurs in the silver paste 50B that serves as the current path, the peeled portion 90 becomes a high impedance area, and the on-resistance of the semiconductor device increases. Furthermore, in the case of a semiconductor device equipped with a sense transistor, this causes a fluctuation in the sense ratio. In other words, peeling of the silver paste 50B adversely affects the performance of the semiconductor device.

[0053] In this manner, the clip CLL has been taken up as a plate-like member to explain the room for improvement present in the semiconductor device PKG. This is because, for example, the inverter circuit INV shown in FIG. 2 has a sense circuit 31 electrically connected to the sense transistor 22 included in the low-side switching circuit 20, and the main transistor 21 and the sense transistor 22 constituting the low-side switching circuit 20 are formed on the semiconductor chip CPL, and the plate-like member connected to this semiconductor chip CPL via the silver paste 50B is the clip CLL. Therefore, for example, when the inverter circuit INV is configured to have a sense circuit 31 electrically connected to the sense transistor 22 included in the low-side switching circuit 20 and a sense circuit electrically connected to the sense transistor 12 included in the high-side switching circuit 10, the main transistor 11 and the sense transistor 12 constituting the high-side switching circuit 10 are formed on the semiconductor chip CPH, and as a result, there is room for improvement similar to that of the clip CLL described above for the clip CLH, which is a plate-like member connected to this semiconductor chip CPH via the silver paste.

[0054] Furthermore, for example, if the inverter circuit INV is configured so that there is no sense circuit 31 electrically connected to the sense transistor 22 included in the low-side switching circuit 20, but has a sense circuit electrically connected to the sense transistor 12 included in the high-side switching circuit 10, there is room for the above-mentioned improvement in the clip CLH, which is a plate-shaped member connected to the semiconductor chip CPH via silver paste.

[0055] <New Findings Discovered by the Inventor> As described above, when peeling occurs in the silver paste 50B that serves as the current path, in the case of a semiconductor device equipped with a sense transistor, this causes a fluctuation in the sense ratio. Furthermore, the present inventor has newly discovered that, although the occurrence of peeling itself is a problem, the fluctuation in the sense ratio is particularly significantly affected by the fluctuation in the peeled area.

[0056] This point will be explained below.

[0057] For example, in the manufacturing process of a semiconductor device, a reliability test called HTSL (High Temperature Storage Life) may be performed after the semiconductor device is manufactured. This "HTSL" is a test to evaluate the influence of storing the semiconductor device at high temperature for a long time. In "HTSL", since the semiconductor device is kept at a high temperature, it is considered that peeling of the silver paste 50B caused by the cause shown in FIG. 4 and FIG. 5 will progress. However, the present inventor has newly found that the peeled part of the silver paste 50B not only expands due to "HTSL", but also shrinks by re-adhesion. That is, according to the study of the present inventor, the peeled area of ​​the silver paste 50B increases or decreases due to "HTSL". And when the peeled area of ​​the silver paste 50B increases or decreases, the potential distribution on the surface of the main transistor source pad SPL changes. As a result, the current flowing through the sense transistor changes, and the sense ratio fluctuates.

[0058] From the above, the present inventor has discovered a new finding that by performing a reliability test called "HTSL", the peeled area of ​​silver paste 50B increases or decreases, and this increase or decrease in the peeled area causes a change in the potential distribution on the surface of the main transistor source pad SPL, which in turn causes a change in the current (sense current) flowing through the sense transistor, thereby causing a change in the sense ratio.The present inventor has also discovered that in the arrangement position of the sense transistor in the related art, the change in potential caused by the increase or decrease in the peeled area is large, which causes a large change in the sense ratio, and this finding will be described below.

[0059] The term "related art" as used herein refers to art that is not publicly known, but has problems that the inventors have found, and is a technology that serves as a premise for the present invention.

[0060] 6(a) and 6(b) are diagrams illustrating room for improvement that exists in the related art.

[0061] As shown in FIG. 6(a), the sense transistor 100 is disposed near the center of the semiconductor chip CPL in the long side direction. As a result, in the related technology, the sense transistor 100 is disposed in a region close to the peeled portion 90. Then, as shown in FIG. 6(b), when the peeled portion 90 increases, the sense transistor 100 comes close to the peeled portion 90, and the sense transistor 100 is greatly affected by the potential change caused by the peeled portion 90. That is, in the related technology, since the sense transistor 100 is formed in a region close to the growing peeled portion 90, the current flowing through the sense transistor 100 fluctuates under the influence of the potential change caused by the peeled portion 90. Furthermore, the peeled portion 90 that has once grown may shrink due to re-adhesion, and in this case, a potential change also occurs, and the current flowing through the sense transistor 100 fluctuates under the influence of the potential change.

[0062] That is, in the related technology, the sense transistor 100 is disposed in a region close to the peeled portion 90, so that the current flowing through the sense transistor 100 is easily affected by the potential change caused by the increase or decrease of the peeled portion 90. In other words, in the related technology, the sense transistor 100 is disposed in a location that is easily affected by the potential change caused by the increase or decrease of the peeled portion 90. For this reason, in the related technology, the potential change caused by the increase or decrease of the peeled portion 90 is large, and this causes the sense ratio to vary greatly. This means that the sense ratio deviates from a preset value, and this means that the detection accuracy of the current (main current) flowing through the main transistor is reduced. Thus, in the related technology, the sense transistor 100 is disposed in a location where the potential change caused by the increase or decrease of the peeled portion 90 is large, so there is room for improvement in terms of suppressing the variation in the sense ratio.

[0063] In view of this, the present embodiment is devised to overcome the room for improvement that exists in the related art. The technical concept of the present embodiment that devised this devise will be described below.

[0064] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is to form the sense transistor in a place that is not easily affected by potential changes caused by an increase or decrease in the peeled portion of the silver paste. According to this basic idea, even if an increase or decrease in the peeled portion of the silver paste that bonds the source pad for the main transistor and the clip occurs by performing a reliability test called "HTSL", the sense transistor is not easily affected by potential changes caused by the increase or decrease in the peeled portion. As a result, according to the basic idea, the fluctuation of the sense ratio can be suppressed, and therefore the detection accuracy of the current (main current) flowing through the main transistor can be improved. In other words, according to the basic idea, the performance degradation of the semiconductor device, such as the decrease in the detection accuracy of the main current caused by the fluctuation of the sense ratio, can be suppressed.

[0065] Hereinafter, an embodiment that embodies the above-mentioned basic concept will be described.

[0066] <Embodiment> The basic idea is to form a sense transistor in a location that is less susceptible to potential changes due to an increase or decrease in the peeled-off portion of the silver paste, and in realizing this basic idea, it is important to find a "location that is less susceptible to potential changes due to an increase or decrease in the peeled-off portion of the silver paste."

[0067] In regard to this point, the present inventors have found the following locations as "locations that are less susceptible to potential changes due to an increase or decrease in the amount of peeled off silver paste," and will now explain this point.

[0068] Fig. 7 is a schematic diagram showing a "location that is less susceptible to potential changes caused by an increase or decrease in the amount of peeled silver paste". In Fig. 7, region RA is located away from peeled silver paste portion 90, and is a "location that is less susceptible to potential changes caused by an increase or decrease in the amount of peeled silver paste". For this reason, in this embodiment, a sense transistor is placed in region RA.

[0069] This will be explained in detail below.

[0070] 3, the semiconductor device PKG includes a die pad DPL, a semiconductor chip CPL mounted on the die pad DPL, leads LD arranged apart from the die pad DPL, and a clip CLL that electrically connects the semiconductor chip CPL and the leads LD. The clip CLL is an example of a plate-like member and is made of, for example, copper.

[0071] 2, the semiconductor chip CPL is formed with a main transistor 21 and a sense transistor 22 that constitute a low-side switching circuit 20. The main transistor 21 and the sense transistor 22 are formed of vertical trench power transistors that pass a current in the thickness direction of the semiconductor chip CPL.

[0072] As shown in FIG. 8, a main transistor source pad SPL electrically connected to the power transistor (main transistor 21 in FIG. 2) and a sense pad 200 electrically connected to the sense transistor 100 (sense transistor 22 in FIG. 2) are formed on the surface of the semiconductor chip CPL.

[0073] 8, the main transistor source pad SPL has a first short side SS1, a second short side SS2 opposite to the first short side SS1, a first long side LS1 intersecting with the first short side SS1, and a second long side LS2 opposite to the first long side LS1 in a plan view. The semiconductor chip CPL has an overlapping region where the main transistor source pad SPL and the clip CLL overlap, and a non-overlapping region where the main transistor source pad SPL and the clip CLL do not overlap in a plan view. At this time, the clip CLL extends in the y direction (first direction) in which the first long side LS1 and the second long side LS2 extend, intersects with the second short side SS2 in a plan view, and is electrically connected to the main transistor source pad SPL via silver paste. The non-overlapping region where the main transistor source pad SPL and the clip CLL do not overlap includes the region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL in a planar view, where the sense transistor 100 is arranged.

[0074] That is, the non-overlapping region is located between the first portion PU1 of the clip CLL (plate-shaped member) and the first short side SS1 of the main transistor source pad SPL (first electrode) in a plan view, and includes a first region in which the sense transistor 100 is disposed. In other words, the sense transistor 100 is located within the first region of the non-overlapping region between the first portion of the clip CLL (plate-shaped member) and the first short side SS1 of the main transistor source pad SPL (first electrode) in a plan view.

[0075] 8, a pad 300 electrically connected to the main transistor source pad SPL is formed on the surface of the semiconductor chip CPL. At this time, the main transistor source pad SPL and the pad 300 are connected via a first wiring WL1 connecting the first long side LS1 and the second long side LS2 of the main transistor source pad SPL and a second wiring WL2 connecting the first wiring WL1 and the pad 300.

[0076] 8, the sense transistor 100 and the sense pad 200 are connected by a third wiring WL3. In this case, the third wiring WL3 has a first portion P1 parallel to the first short side SS1 and a second portion P2 parallel to the first long side LS1.

[0077] Here, in the semiconductor chip CPC (control chip) shown in FIG. 3, the main current flowing through the main transistor is measured based on the sense current flowing through the sense transistor 100. In detail, the source voltage of the sense transistor 100 is input to the semiconductor chip CPC from the sense pad 200 electrically connected to the sense transistor 100, and the source voltage of the main transistor is input from the pad 300 electrically connected to the main transistor source pad SPL. Then, in the semiconductor chip CPC, after correcting the difference between the input source voltage of the sense transistor 100 and the source voltage of the main transistor to be zero, in other words, after correcting the difference between the source voltage of the sense transistor 100 and the source voltage of the main transistor to be equal, the sense current input from the sense pad 200 is converted into a voltage signal. In this way, the current value of the main current flowing through the main transistor is measured based on the voltage signal and a preset "sense ratio". In this regard, for example, if there is no increase or decrease in the peeled portion, the sense current value of the sense transistor 100 will be a desired value, and the measurement accuracy of the main current measured from the preset "sense ratio" is good. On the other hand, if an increase or decrease in the peeled portion occurs, the sense current value of the sense transistor 100 changes from the desired value, and the measurement accuracy of the main current measured based on the preset "sense ratio" decreases. Therefore, it is important to find a "place that is less susceptible to potential changes caused by an increase or decrease in the peeled portion of the silver paste," and in this embodiment, for example, as shown in Figure 8, the sense transistor 100 is disposed in a region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL in a plan view.

[0078] Next, FIG. 9 is a cross-sectional view taken along line AA in FIG.

[0079] As shown in FIG. 9, the main transistor and the sense transistor are composed of vertical trench power transistors that pass a current in the thickness direction of the semiconductor chip.

[0080] The main transistor is electrically connected to a main transistor source pad SPL, which is connected to a clip CLL via a silver paste 50B. On the other hand, the sense transistor is electrically connected to a sense pad 200.

[0081] <<Features of the embodiment>> Next, features of this embodiment will be described.

[0082] The feature of this embodiment is that, for example, as shown in FIG. 8, the sense transistor 100 is disposed in a region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL in a plan view. As a result, according to this embodiment, even if the peeled portion of the silver paste bonding the main transistor source pad SPL and the clip CLL increases or decreases by performing a reliability test called "HTSL", the sense transistor 100 is less susceptible to potential changes caused by the increase or decrease in the peeled portion. This is because, according to the new knowledge found by the present inventor, the region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL is a place away from the peeled portion of the silver paste, and is "a place that is less susceptible to potential changes caused by the increase or decrease in the peeled portion of the silver paste". That is, in this embodiment, the basic idea of ​​forming the sense transistor 100 in a place that is not easily affected by potential changes due to an increase or decrease in the peeled portion of the silver paste is embodied by a configuration in which the sense transistor 100 is disposed in a region between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL in a plan view based on the above-mentioned new findings. As a result, according to the configuration of this embodiment that embodies the basic idea, the fluctuation of the sense ratio can be suppressed, and therefore the detection accuracy of the current flowing through the main transistor can be improved. In other words, according to the configuration of this embodiment, it is possible to suppress the performance degradation of the semiconductor device, such as the decrease in the detection accuracy of the main current caused by the fluctuation of the sense ratio.

[0083] <Variation 1> FIG. 10 is a diagram showing the first modified example.

[0084] As shown in FIG. 10, in this variant example 1, the main transistor source pad SPL and the pad 300 are connected via a first wiring WL1 that connects a first corner where the first long side LS1 and the first short side SS1 intersect and a second corner where the second long side LS2 and the first short side SS1 intersect, and a second wiring WL2 that connects the first wiring WL1 and the pad 300.

[0085] Furthermore, in this first modification, the sense transistor 100 and the sense pad 200 are connected by a third wiring WL3, and the third wiring WL3 has a first portion P1 parallel to the first short side SS1 and a second portion P2 parallel to the first long side LS1.

[0086] In this modified example 1 configured as above, the sense transistor 100 is also disposed in a region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL in a plan view. For this reason, in this modified example 1, even if the peeled portion of the silver paste bonding the main transistor source pad SPL and the clip CLL increases or decreases by carrying out a reliability test called "HTSL", the sense transistor 100 is less susceptible to the effect of the potential change caused by the increase or decrease in the peeled portion. As a result, in this modified example 1, the fluctuation of the sense ratio can be suppressed.

[0087] <Variation 2> FIG. 11 is a diagram showing the second modified example.

[0088] 11, in the present modified example 2, the main transistor source pad SPL and the pad 300 are connected via a first wiring WL1 that connects the first long side LS1 and the second long side LS2 of the main transistor source pad SPL, and a second wiring WL2 that connects the first wiring WL1 and the pad 300. The sense transistor 100 and the sense pad 200 are connected by a third wiring WL3, and the third wiring WL3 has, in a plan view, a first portion P1 that is parallel to the first short side SS1 and intersects with the second long side LS2, a second portion P2 that is parallel to the second long side LS2, a third portion P3 that is parallel to the first short side SS1, and a fourth portion P4 that is parallel to the first long side LS1.

[0089] In this modified example 2 configured as above, the sense transistor 100 is also disposed in a region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL in a plan view. For this reason, in this modified example 2 as well, even if the peeled portion of the silver paste bonding the main transistor source pad SPL and the clip CLL increases or decreases by carrying out a reliability test called "HTSL", the sense transistor 100 is less susceptible to the effect of the potential change caused by the increase or decrease in the peeled portion. As a result, in this modified example 2 as well, the fluctuation of the sense ratio can be suppressed.

[0090] <Variation 3> FIG. 12 is a diagram showing the third modified example.

[0091] 12, in the third modification, the main transistor source pad SPL and the pad 300 are connected via a first wiring WL1 that connects the first long side LS1 and the second long side LS2 of the main transistor source pad SPL, and a second wiring WL2 that connects the first wiring WL1 and the pad 300. The sense transistor 100 and the sense pad 200 are connected by a third wiring WL3, and the third wiring WL3 has a first portion P1 that is parallel to the first long side LS1 and intersects with the first short side SS1 in a plan view, a second portion P2 that is parallel to the first short side SS1, and a third portion P3 that is parallel to the first long side LS1.

[0092] In this third modification configured as above, the sense transistor 100 is also disposed in a region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL in a plan view. For this reason, even if the peeled portion of the silver paste bonding the main transistor source pad SPL and the clip CLL increases or decreases by carrying out a reliability test called "HTSL", the sense transistor 100 is less susceptible to the effect of the potential change caused by the increase or decrease in the peeled portion. As a result, the third modification can also suppress the fluctuation of the sense ratio.

[0093] <Variation 4> In the embodiment, for example, as shown in FIG. 8, the basic idea of ​​forming the sense transistor 100 in a place that is not easily affected by potential changes due to an increase or decrease in the peeled portion of the silver paste is embodied by a configuration in which the sense transistor 100 is disposed in a region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL in a plan view. However, the basic idea described above is not limited to the configuration in which the sense transistor 100 is disposed in a region sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL, and can be embodied by, for example, the configuration shown in FIG. 13. This is because, according to the study by the present inventor, it has become clear that the growth of the peeled portion of the silver paste is not likely to progress not only to the tip of the clip CLL but also to the base portion. In other words, the base portion of the clip CLL is also a place that is not easily affected by potential changes due to an increase or decrease in the peeled portion of the silver paste, and by disposing the sense transistor 100 in this place, the fluctuation of the sense ratio can be suppressed.

[0094] Specifically, FIG. 13 is a diagram showing the fourth modified example.

[0095] As shown in FIG. 13, the semiconductor chip CPL has an overlapping region where the main transistor source pad SPL and the clip CLL overlap, and a non-overlapping region where the main transistor source pad SPL and the clip CLL do not overlap in a plan view.

[0096] The clip CLL has a first portion PU1 in contact with the silver paste 50B, a second portion PU2 in contact with the silver paste 50C, and a third portion PU3 located between the first portion PU1 and the second portion PU2. Here, the overlapping region is a region that overlaps with the third portion PU3 of the clip CLL in a plan view and includes a region in which the sense transistor 100 is disposed. That is, in the present modification 4, the sense transistor 100 is formed in a region of the semiconductor chip CPL that overlaps with the third portion P3 of the clip CLL in a plan view.

[0097] That is, the overlapping region overlaps with the third portion of the clip CLL (plate-shaped member) in a plan view and includes a first region in which the sense transistor 100 is disposed. In other words, the sense transistor 100 is located in the first region of the overlapping region that overlaps with the third portion of the clip CLL (plate-shaped member) in a plan view.

[0098] Even in the fourth modification thus configured, for example, by carrying out a reliability test called "HTSL", even if the peeled portion of the silver paste bonding the main transistor source pad SPL and the clip CLL increases or decreases, the sense transistor 100 becomes less susceptible to the effect of potential changes caused by the increase or decrease in the peeled portion. As a result, even in the fourth modification, the fluctuation of the sense ratio can be suppressed.

[0099] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device according to the embodiment will be described.

[0100] <<Semiconductor chip manufacturing process>> First, a semiconductor wafer having a plurality of chip regions is prepared. Then, by using a normal semiconductor manufacturing technique, a power transistor including a main transistor and a sense transistor is formed in each chip region. At this time, the main transistor and the sense transistor are formed so as to realize, for example, the layout shown in FIG. 8. Then, a source pad for the main transistor is formed on the surface of each chip region of the semiconductor wafer. This source pad for the main transistor is made of, for example, aluminum.

[0101] Next, if necessary, a plating film such as a nickel film, a palladium film, or a gold film is formed on the exposed surface of the main transistor source pad by using an electroless plating method or the like. Then, a back grinding process is performed on the semiconductor wafer, and the semiconductor wafer is diced. As a result, the multiple chip regions of the semiconductor wafer are individualized and divided into multiple semiconductor chips. In this way, the semiconductor chip of this embodiment is manufactured.

[0102] <<Semiconductor device assembly process>> Next, the assembly process of the semiconductor device will be described.

[0103] FIG. 14 is a flow chart illustrating the assembly process of a semiconductor device.

[0104] First, a lead frame having a die pad and leads spaced apart from the die pad is prepared. Then, a semiconductor chip manufactured in the above-mentioned semiconductor chip manufacturing process is mounted on the die pad. Specifically, after applying silver paste onto the die pad, the semiconductor chip is mounted on the die pad via the silver paste (S101).

[0105] Next, silver paste is applied onto the main transistor source pad formed on the surface of the semiconductor chip and onto the leads (S102). After that, a clip is placed so as to connect the main transistor source pad and the leads. At this time, the clip is connected to the main transistor source pad via the silver paste, and is also connected to the leads via the silver paste. As a result, the main transistor source pad and the leads are electrically connected by the clip (S103). Then, a curing process (heat treatment at about 150°C to 300°C) is performed to harden the silver paste (S104).

[0106] Next, for example, the leads and other pads formed on the surface of the semiconductor chip are connected with gold or conductor wires. That is, wire bonding is performed with gold or copper wires between the leads and other pads formed on the surface of the semiconductor chip (S105).

[0107] Thereafter, a resin sealing (molding) is performed to form a sealing body (S106). Then, a plating layer is formed as necessary on the outer lead portions of the leads exposed from the sealing body. Next, outside the sealing body, the leads are cut at predetermined positions to separate the sealing body from the frame of the lead frame. Next, the outer lead portions of the leads protruding from the sealing body are bent. In this manner, a semiconductor device can be manufactured.

[0108] Thereafter, a reliability test called "HTSL" is performed on the manufactured semiconductor device (S107). At this time, the peeled portion of the silver paste that bonds the main transistor source pad and the clip may increase or decrease. In this regard, in this embodiment, the sense transistor is formed in a place that is not easily affected by the potential change caused by the increase or decrease of the peeled portion of the silver paste (for example, the area sandwiched between the tip of the clip CLL and the first short side SS1 of the main transistor source pad SPL). As a result, according to the semiconductor device in this embodiment, the fluctuation of the sense ratio can be suppressed, and therefore the detection accuracy of the current flowing through the main transistor can be improved. In other words, according to this embodiment, the performance degradation of the semiconductor device, such as the decrease in the detection accuracy of the main current caused by the fluctuation of the sense ratio, can be suppressed. In other words, according to this embodiment, the manufacturing yield of the semiconductor device can be improved.

[0109] Thereafter, of the manufactured semiconductor devices, those that pass the above-mentioned reliability test are shipped. In this manner, the method for manufacturing a semiconductor device according to the present embodiment is carried out.

[0110] <Variation 5> In the above embodiment, a configuration in which the surface of the die pad DPL (die pad DPC, die pad DPH) is exposed from the bottom surface of the sealing body MR has been described as an example, but the basic idea of ​​the above embodiment is not limited to this and can also be applied, for example, to a configuration in which the surface of the die pad DPL (die pad DPC, die pad DPH) is exposed from the top surface of the sealing body MR.

[0111] In the configuration of this variant example 5, the resin sealing process (molding process) can be performed in a configuration in which the exposed surface of the die pad DPL is brought into contact with the lower mold, or in a configuration in which the exposed surface of the die pad DPL is brought into contact with the lower mold.

[0112] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0113] For example, in the above embodiment, an example has been described in which the main transistor source pad SPL has a rectangular shape in a plan view as shown in FIG. 8. However, the basic idea of ​​the above embodiment is not limited to this, and can be widely applied to cases in which the planar shape of the main transistor source pad SPL has a substantially rectangular shape (irregular shape) having at least a first short side, a second short side opposite the first short side, a first long side intersecting the first short side, and a second long side opposite the first long side, as shown in FIG. 6(a) and FIG. 6(b).

[0114] In the above embodiment, the power transistor formed on the semiconductor chip is assumed to be a power MOSFET. However, the technical ideas in the above embodiment are not limited to this, and can be widely applied to a semiconductor device using, for example, an IGBT (Insulated Gate Bipolar Transistor) as a power transistor.

[0115] In this case, the "main transistor source pad" should be read as the "main transistor emitter pad." In the claims, the term "first electrode" is used to encompass both the "main transistor source pad" and the "main transistor emitter pad." In other words, the "first electrode" in the claims is used with the intention of encompassing both the "main transistor source pad" and the "main transistor emitter pad."

[0116] In addition, although the embodiment has been described using silver paste as an example, the technical idea of ​​the embodiment is not limited to this, and can be widely applied to, for example, semiconductor devices using solder. In addition, the claims use the terms "first conductive member" and "second conductive member" as terms that encompass "silver paste" and "solder". In other words, the terms "first conductive member" and "second conductive member" in the claims are used with the intention of encompassing "silver paste" and "solder". [Explanation of symbols]

[0117] 10 High-side switching circuit 11 Main transistor 12 Sense transistor 20 Low-side switching circuit 21 Main transistor 22 Sense transistor 30 Control circuit 31 Sense circuit 50A Silver Paste 50B Silver Paste 50C Silver Paste 60A Lead 60B Lead 70A lower mold 70B upper mold 80 Base part 90 Peeling part 100 Sense transistor 200 Sense Pad 300 pads CAV Cavity CL coil CLH Clip CLL Clip CPC Semiconductor Chip CPH Semiconductor Chip CPL Semiconductor Chip CT control circuit DPC Die Pad DPL Die Pad DPH Die Pad GND Ground potential INV Inverter circuit MR sealed body MOT motor LD Lead LDL Lead LDH Lead LS1 First long side LS2 Second long side P1 Part 1 P2 2nd part P3 3rd part PAS protective film PDC1 Pad PDC2 Pad PDH Pad PDL Pad PKG Semiconductor device PU1 1st part PU2 2nd part PU3 3rd part RA area SPH Main transistor source pad SPL Source pad for main transistor SS1 1st short side SS2 2nd short side VIN power supply potential W Bonding Wire WL1 First wiring WL2 Second wiring WL3 3rd wiring

Claims

1. A die pad; A semiconductor chip mounted on the die pad; a lead spaced apart from the die pad; a plate-like member that electrically connects the semiconductor chip and the leads to each other; having The semiconductor chip comprises: A power transistor; a sense transistor for detecting a current flowing through the power transistor; Including, The surface of the semiconductor chip is provided with a first electrode electrically connected to the power transistor; a second electrode electrically connected to the sense transistor; is formed, The first electrode, in a plan view, A first short side; a second short side opposite to the first short side; a first long side intersecting the first short side; a second long side opposite to the first long side; having The semiconductor chip, in a plan view, an overlapping region where the first electrode and the plate-like member overlap each other; a non-overlapping region where the first electrode and the plate-like member do not overlap with each other; having the plate-like member extends in a first direction in which the first long side extends so as to intersect with the second short side in a plan view, is electrically connected to the first electrode via a first conductive member, and is electrically connected to the lead via a second conductive member; The plate-like member is a first portion in contact with the first conductive member; a second portion in contact with the second conductive member; a third portion located between the first portion and the second portion; having The first portion of the plate-like member, in a plan view, a third short side adjacent to the first short side of the first electrode; a third long side of the first electrode adjacent to the first long side and intersecting with the third short side; a fourth long side adjacent to the second long side of the first electrode and facing the third long side; having A semiconductor device, wherein the sense transistor is located within a first region of the non-overlapping region between the third short side of the first portion of the plate-like member and the first short side of the first electrode in a planar view.

2. 2. The semiconductor device according to claim 1, A semiconductor device further comprising a third electrode formed on the surface of the semiconductor chip and electrically connected to the first electrode.

3. 3. The semiconductor device according to claim 2, The first electrode and the third electrode are a first wiring that connects the first long side and the second long side of the first electrode; a second wiring that connects the first wiring and the third electrode; The semiconductor device is connected via a

4. 4. The semiconductor device according to claim 3, the sense transistor and the second electrode are connected by a third wiring, The third wiring is a first portion parallel to the first short side; a second portion parallel to the first long side; The semiconductor device has

5. 3. The semiconductor device according to claim 2, The first electrode and the third electrode are a first wiring that connects a first corner where the first long side and the first short side intersect with each other and a second corner where the second long side and the first short side intersect with each other; a second wiring that connects the first wiring and the third electrode; The semiconductor device is connected via a

6. 6. The semiconductor device according to claim 5, the sense transistor and the second electrode are connected by a third wiring, The third wiring is a first portion parallel to the first short side; a second portion parallel to the first long side; The semiconductor device has

7. 3. The semiconductor device according to claim 2, The first electrode and the third electrode are a first wiring that connects the first long side and the second long side of the first electrode; a second wiring that connects the first wiring and the third electrode; Connected via the sense transistor and the second electrode are connected by a third wiring, The third wiring, in a plan view, a first portion that is parallel to the first short side and intersects with the second long side; a second portion parallel to the second long side; a third portion parallel to the first short side; a fourth portion parallel to the first long side; The semiconductor device has

8. 3. The semiconductor device according to claim 2, The first electrode and the third electrode are a first wiring that connects the first long side and the second long side of the first electrode; a second wiring that connects the first wiring and the third electrode; Connected via the sense transistor and the second electrode are connected by a third wiring, The third wiring, in a plan view, a first portion that is parallel to the first long side and intersects with the first short side; a second portion parallel to the first short side; a third portion parallel to the first long side; The semiconductor device has

9. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the first conductive member contains silver.

10. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the plate-like member is a clip made of copper.

Images