Semiconductor Device

Abstract

The semiconductor device (1) comprises a semiconductor layer (40) divided into three regions, a first region (A1), a second region (A2), and a third region (A3), which do not overlap each other in a plan view, a first vertical MOS transistor (10) formed in the first region (A1), a second vertical MOS transistor (20) formed in the second region (A2), and a third vertical MOS transistor (30) formed in the third region (A3), and the first vertical The first gate wiring (118) of the MOS transistor (10) and the third gate wiring (138) of the third vertical MOS transistor (30) are electrically connected in series via a first diode (113) in this order as the forward direction, and the second gate wiring (128) and the third gate wiring (138) of the second vertical MOS transistor (20) are electrically connected in series via a second diode (123) in this order as the forward direction.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a chip size package type semiconductor device. [Background technology]

[0002] Vertical MOS transistors are sometimes used in electrical circuits that combine two systems with different current specifications into one system. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7253674 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for miniaturization of circuits using vertical MOS transistors. [Means for solving the problem]

[0005] In order to solve the above problems, a semiconductor device according to one embodiment of the present disclosure is a chip-size package type semiconductor device capable of face-down mounting, the semiconductor device having a semiconductor substrate on a back surface side, the semiconductor layer being divided into three regions, a first region, a second region, and a third region, which do not overlap each other in a plan view of the semiconductor device and are not disposed in a distributed manner, a first vertical MOS transistor entirely formed in the first region of the semiconductor layer, a second vertical MOS transistor entirely formed in the second region of the semiconductor layer, a third vertical MOS transistor entirely formed in the third region of the semiconductor layer, and a metal layer formed in contact with the back surface side of the semiconductor layer, the semiconductor substrate being a common drain region of the first vertical MOS transistor, the second vertical MOS transistor, and the third vertical MOS transistor, and the first vertical MOS transistor is disposed at a position included in the first region in the plan view. a first source pad and a first gate pad of a first vertical MOS transistor and a first gate wiring connected to the first gate pad, a second source pad, a second gate pad of a second vertical MOS transistor and a second gate wiring connected to the second gate pad are formed at a position included in the second region in the plan view, a third source pad and a third gate wiring of a third vertical MOS transistor are formed at a position included in the third region in the plan view, the first gate wiring and the third gate wiring are electrically connected in series via a first diode whose forward direction is from the first gate wiring to the third gate wiring, and the second gate wiring and the third gate wiring are electrically connected in series via a second diode whose forward direction is from the second gate wiring to the third gate wiring. Effect of the Invention

[0006] By using the above-mentioned triple-configuration vertical MOS transistor in a circuit that merges two conduction paths with different current specifications into one, it is possible to reduce the area required by the circuit compared to conventional circuits.

[0007] Therefore, according to the semiconductor device having the above configuration, it is possible to realize miniaturization of circuits using vertical MOS transistors. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of a structure of a semiconductor device according to an embodiment. [Figure 2A] FIG. 2A is a schematic plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 2B] FIG. 2B is a schematic plan view showing an example of the structure of the semiconductor device according to the embodiment. [Figure 3A] FIG. 3A is a schematic plan view showing an example of a part of the structure of the semiconductor device according to the embodiment. [Figure 3B] FIG. 3B is a schematic cross-sectional view showing an example of a part of the structure of the semiconductor device according to the embodiment. [Figure 3C] FIG. 3C is a schematic cross-sectional view showing an example of a part of the structure of the semiconductor device according to the embodiment. [Figure 4A] FIG. 4A is a schematic plan view showing an example of a part of the structure of the semiconductor device according to the embodiment. [Figure 4B] FIG. 4B is a schematic cross-sectional view showing an example of a part of the structure of the semiconductor device according to the embodiment. [Figure 4C] FIG. 4C is a schematic cross-sectional view showing an example of a part of the structure of the semiconductor device according to the embodiment. [Figure 5A] FIG. 5A is a schematic plan view of a general unit configuration of a first transistor according to an embodiment. [Figure 5B] FIG. 5B is a schematic perspective view of a general unit configuration of a first transistor according to the embodiment. [Figure 6] FIG. 6 is a circuit diagram showing an example of use of the semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a circuit diagram showing an example of use of a semiconductor device according to a comparative example. [Figure 8A] FIG. 8A is a schematic plan view showing an example of the structure of a transistor according to a comparative example. [Figure 8B] FIG. 8B is a schematic plan view illustrating an example of the structure of a transistor according to a comparative example. [Figure 9A] FIG. 9A is a schematic plan view showing an example of the structure of a transistor according to a comparative example. [Figure 9B] FIG. 9B is a schematic plan view illustrating an example of the structure of a transistor according to a comparative example. [Figure 10A] FIG. 10A is a schematic plan view showing a modified example of the structure of the semiconductor device according to the embodiment. [Figure 10B] FIG. 10B is a schematic plan view showing a modified example of the structure of the semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a graph plotting the relationship between the area of ​​a transistor in a plan view and the ESD resistance. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments described below each show a specific example of the present disclosure. The numerical values, shapes, materials, components, arrangement positions of the components, connection forms, and the like shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0010] In this disclosure, "A and B are electrically connected" includes cases where A and B are directly connected via wiring, where A and B are directly connected without wiring, and where A and B are indirectly connected via a resistance component (resistance element, resistance wiring).

[0011] (Embodiment) [1. Structure of semiconductor device] The structure of the semiconductor device according to the embodiment will be described below. The semiconductor device according to the embodiment is a chip size package (CSP) type semiconductor device that has a dual configuration in which two vertical MOS (Metal Oxide Semiconductor) transistors are formed on a semiconductor substrate and can be mounted face-down. The two vertical MOS transistors are power transistors, so-called trench MOS type field effect transistors.

[0012] Fig. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor device 1 according to an embodiment. Figs. 2A and 2B are schematic plan views showing an example of the structure of a semiconductor device 1 according to an embodiment. The size and shape of the semiconductor device 1 in Figs. 2A and 2B are examples. The size, shape and arrangement of the pads and electrodes are also examples.

[0013] 2B shows the state immediately after the portion 13 of the first source electrode 11, the first gate electrode 19, the first gate wiring 118, the portion 23 of the second source electrode 21, the second gate electrode 29, the second gate wiring 128, the portion 33 of the third source electrode 31, and the third gate wiring 138 are formed on the front surface side of the semiconductor layer 40. Pads that should not be visible at this point are shown with dotted lines. Each component will be described later.

[0014] FIG. 1 is a cross section of the semiconductor device 1 taken along line II in FIG. 2A.

[0015] 1, the semiconductor device 1 has a semiconductor substrate 42, a metal layer 41, and a low-concentration impurity layer 43 formed on the semiconductor substrate 42. In the present disclosure, the semiconductor substrate 42 and the low-concentration impurity layer 43 are collectively referred to as a semiconductor layer 40.

[0016] The semiconductor substrate 42 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing an impurity of a first concentration. The semiconductor layer 40 has a low-concentration impurity layer 43 of the first conductivity type that is formed in contact with the semiconductor substrate 42 and contains an impurity of a second concentration lower than the first concentration. The low-concentration impurity layer 43 is formed on the semiconductor substrate 42 by, for example, epitaxial growth.

[0017] As shown in Figures 1 and 2A, the semiconductor device 1 has a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") entirely formed in a first region A1 of the semiconductor layer 40, a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") entirely formed in a second region A2 of the semiconductor layer 40, and a third vertical MOS transistor 30 (hereinafter also referred to as "transistor 30") entirely formed in a third region A3 of the semiconductor layer 40.

[0018] The transistor 10 entirely formed within the first region A1 means that, in a planar view, all of the elements constituting the transistor 10 are included within the first region A1 and are not included in any region other than the first region A1. Similarly, the transistor 20 entirely formed within the second region A2 means that, in a planar view, all of the elements constituting the transistor 20 are included within the second region A2 and are not included in any region other than the second region A2. Similarly, the transistor 30 entirely formed within the third region A3 means that, in a planar view, all of the elements constituting the transistor 30 are included within the third region A3 and are not included in any region other than the third region A3.

[0019] As shown in FIG. 2A, the surface side of the semiconductor layer 40 is divided into a first region A1, a second region A2, and a third region A3, which do not overlap each other and are not distributed in a plan view. Here, the first region A1, the second region A2, and the third region A3 are not distributed in a plan view, meaning that the first region A1, the second region A2, and the third region A3 are not associated with any outlying areas. In FIG. 2A, a virtual boundary line 90 that divides the first region A1, the second region A2, and the third region A3 is shown by a dotted line. For ease of understanding, the dotted line indicating the boundary line 90 is shown extending to the outside of the semiconductor layer 40, but the actual boundary line 90 ends at the outer periphery of the semiconductor layer 40 in a plan view (for convenience, the ends of the boundary line 90 are shown as P1, P2, P3, and P4, respectively, in FIG. 2A and FIG. 2B). The boundary line 90 will be described later.

[0020] 2A, the dashed lines indicating the first region A1, the second region A2, and the third region A3 are not strictly aligned with the outer periphery and boundary line 90 of the semiconductor layer 40 for ease of understanding, but are shown with some space between them, but the outer periphery of the first region A1, the outer periphery of the second region A2, and the outer periphery of the third region A3 substantially coincide with the outer periphery and boundary line 90 of the semiconductor layer 40. In the semiconductor device 1 according to the embodiment, there is no region that is not the first region A1, the second region A2, or the third region A3 in plan view.

[0021] The metal layer 41 is formed in contact with the back surface side of the semiconductor layer 40, and may be made of silver (Ag) or copper (Cu), as a non-limiting example. Note that the metal layer 41 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material.

[0022] 1, a first body region 18 of a second conductivity type different from the first conductivity type is formed in a first region A1 of the low-concentration impurity layer 43. A first source region 14 of the first conductivity type is formed in the first body region 18.

[0023] In the first region A1, a plurality of first gate trenches 17 are formed, each extending from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a depth reaching a part of the low-concentration impurity layer 43, and a first gate conductor 15 is formed on the first gate insulating film 16 inside the first gate trench 17. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40. The first gate conductor 15 is electrically connected to the first gate electrode 19 via a first gate wiring 118 (see FIG. 2B).

[0024] The first source electrode 11 is composed of a portion 12 and a portion 13 , and the portion 12 is connected via the portion 13 to a first source region 14 and a first body region 18 .

[0025] The portion 12 of the first source electrode 11 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, by way of non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 12 may be plated with gold or the like.

[0026] Portion 13 of first source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0027] The first gate electrode 19 may be formed simultaneously with the first source electrode 11 and may be formed of the same composition and / or material as the first source electrode 11 .

[0028] As shown in FIG. 2B, the first gate wiring 118 is disposed so as to surround the portion 13 of the first source electrode 11 and the first gate electrode 19 in a plan view. The first gate wiring 118 is connected in series with the first gate electrode 19 via the first gate resistor element 117. FIG. 3B shows a schematic cross-sectional view including the first gate resistor element 117. FIG. 3B is a cut surface of the semiconductor device 1 taken along II-II in FIG. 3A, and FIG. 3A is a schematic plan view showing an enlarged view of an area A11 surrounded by a dashed line in FIG. 2B.

[0029] As shown in FIG. 2B, a first Zener diode 115 is provided between a portion 13 of the first source electrode 11 and the first gate electrode 19 in a plan view. FIG. 3C shows a schematic cross-sectional view including the first Zener diode 115. FIG. 3C is a cut surface of the semiconductor device 1 taken along III-III in FIG. 3A. The first gate electrode 19 and the portion 13 of the first source electrode 11 are electrically connected via the first Zener diode 115.

[0030] Both the gate resistor element and the Zener diode are installed in the hope of providing a protective function that prevents the transistor from being destroyed when an excessive voltage is applied to the gate electrode. In other words, they are elements installed to enhance ESD (Electro Static Discharge) resistance. Both the first gate resistor element 117 and the first Zener diode 115 may be formed by, for example, injecting impurities into polysilicon. By controlling the type, amount, and position of the impurity, respectively, it is possible to control the resistivity of the first gate resistor element 117 and the position, number, and electrical direction of the PN junction in the first Zener diode 115.

[0031] The first Zener diode 115 may be formed such that a portion having a first conductivity type as a result of the implantation of a first conductivity type impurity and a portion having a second conductivity type as a result of the implantation of a second conductivity type impurity are alternately formed as shown in Fig. 3C. In the example shown in Fig. 3C, two PN junctions are formed in both directions between the first gate electrode 19 and the portion 13 of the first source electrode 11 by the first Zener diode 115.

[0032] In a plan view, a first EQR (EQui potential ring) 116 electrically connected to the semiconductor substrate 42 may be provided on the outer periphery of the first region A1. The first EQR 116 is provided in the hope of preventing leakage current from flowing between the outside and the first body region 18 of the transistor 10. As a non-limiting example, the first EQR 116 may be made of a metal material including any one or more of aluminum, copper, gold, and silver.

[0033] It should be noted that the semiconductor device 1 according to the embodiment does not necessarily need to include a gate resistor element, a Zener diode, and an EQR.

[0034] A second body region 28 of the second conductivity type is formed in the second region A2 of the low concentration impurity layer 43. A second source region 24 of the first conductivity type is formed in the second body region 28.

[0035] Further, in the second region A2, a plurality of second gate trenches 27 are formed, each extending from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a depth reaching a part of the low-concentration impurity layer 43, and a second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40. The second gate conductor 25 is electrically connected to the second gate electrode 29 via the second gate wiring 128 (see FIG. 2B).

[0036] The second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23.

[0037] The portion 22 of the second source electrode 21 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, as a non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 22 may be plated with gold or the like.

[0038] Portion 23 of second source electrode 21 is a layer that connects portion 22 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0039] The second gate electrode 29 may be formed simultaneously with the second source electrode 21 and may be formed of the same composition and / or material as the second source electrode 21.

[0040] 2B, the second gate wiring 128 is disposed so as to surround the portion 23 of the second source electrode 21 and the second gate electrode 29 in a plan view. The second gate wiring 128 is connected in series to the second gate electrode 29 via the second gate resistor element 127.

[0041] 2B, in a plan view, a second Zener diode 125 is provided between a portion 23 of the second source electrode 21 and the second gate electrode 29. The second gate electrode 29 and the portion 23 of the second source electrode 21 are electrically connected via the second Zener diode 125.

[0042] Both the second gate resistor 127 and the second Zener diode 125 may be formed by, for example, doping polysilicon with impurities. By controlling the type, amount, and position of the impurities, it is possible to control the resistivity of the second gate resistor 127 and the positions, number, and electrical direction of the PN junctions in the second Zener diode 125.

[0043] The second Zener diode 125 may be of a similar structure to the first Zener diode 115, for example, as shown in FIG. 3C.

[0044] In a plan view, a second EQR 126 electrically connected to the semiconductor substrate 42 may be provided on the outer periphery of the second region A2. The second EQR 126 is provided in the hope of preventing leakage current from flowing between the outside and the second body region 28 of the transistor 20. As a non-limiting example, the second EQR 126 may be made of a metal material including any one or more of aluminum, copper, gold, and silver.

[0045] A third body region 38 of the second conductivity type is formed in the third region A3 of the low-concentration impurity layer 43. A third source region 34 of the first conductivity type is formed in the third body region 38. A plurality of third gate trenches 37 are formed in the third region A3, each of which is formed to a depth from the upper surface of the semiconductor layer 40 through the third source region 34 and the third body region 38 to a portion of the low-concentration impurity layer 43, and a third gate conductor 35 is formed on the third gate insulating film 36 inside the third gate trench 37. The third gate conductor 35 is a buried gate electrode buried inside the semiconductor layer 40. The third gate conductor 35 is electrically connected to a third gate wiring 138 (see FIG. 2B).

[0046] The third source electrode 31 is composed of a portion 32 and a portion 33 , and the portion 32 is connected via the portion 33 to a third source region 34 and a third body region 38 .

[0047] The portion 32 of the third source electrode 31 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, as a non-limiting example, any one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 32 may be plated with gold or the like.

[0048] Portion 33 of third source electrode 31 is a layer that connects portion 32 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0049] In a plan view, a third EQR 136 electrically connected to the semiconductor substrate 42 may be provided on the outer periphery of the third region A3. The third EQR 136 is provided in the hope of preventing leakage current from flowing between the outside and the third body region 38 of the transistor 30. The third EQR 136 may be made of a metal material including at least one of aluminum, copper, gold, and silver, as a non-limiting example.

[0050] 2B, the third gate wiring 138 is disposed so as to surround the portion 33 of the third source electrode 31 in plan view, but in the present disclosure, no gate electrode or gate pad connected to the third gate wiring 138 is present in a position included in the third region A3. Note that no gate resistor or Zener diode, which may be disposed in the first region A1 or the second region A2, is formed.

[0051] The third gate wiring 138 is connected in series to the first gate wiring 118 via the first diode 113. The first diode 113 is formed such that the direction from the first gate wiring 118 to the third gate wiring 138 is the forward direction. FIG. 4B shows a schematic cross-sectional view including the first diode 113. FIG. 4B is a cut surface of the semiconductor device 1 taken along IV-IV in FIG. 4A, and FIG. 4A is a schematic plan view showing an enlarged view of a region A12 surrounded by a dashed line in FIG. 2B.

[0052] The third gate wiring 138 is connected in series to the first gate wiring 118 via the first resistance element 114. Therefore, the first diode 113 and the first resistance element 114 are connected in parallel between the first gate wiring 118 and the third gate wiring 138. Fig. 4C shows a schematic cross-sectional view including the first resistance element 114. Fig. 4C is a cut surface of the semiconductor device 1 cut along VV in Fig. 4A.

[0053] Both the first resistor element 114 and the first diode 113 may be formed by, for example, doping polysilicon with impurities. By controlling the type, amount, and position of the impurities, respectively, it is possible to control the resistivity of the first resistor element 114 and the positions, number, and electrical direction of the PN junctions in the first diode 113.

[0054] The first diode 113 may be formed with one portion having the first conductivity type by implanting a first conductivity type impurity and one portion having the second conductivity type by implanting a second conductivity type impurity, as shown in Fig. 4B for example. In the example shown in Fig. 4B, only one PN junction is formed, the forward direction of which is electrically in the direction from the first gate wiring 118 to the third gate wiring 138.

[0055] The third gate wiring 138 is connected in series to the second gate wiring 128 via the second diode 123. The second diode 123 is formed such that the direction from the second gate wiring 128 to the third gate wiring 138 is the forward direction. In addition, the third gate wiring 138 is connected in series to the second gate wiring 128 via the second resistance element 124. Therefore, the second diode 123 and the second resistance element 124 are connected in parallel between the second gate wiring 128 and the third gate wiring 138.

[0056] Both the second resistor element 124 and the second diode 123 may be formed by, for example, doping polysilicon with impurities. By controlling the type, amount, and position of the impurities, respectively, it is possible to control the resistivity of the second resistor element 124 and the positions, number, and electrical direction of the PN junctions in the second diode 123.

[0057] The second diode 123 has a structure similar to that of the first diode 113 shown in FIG. 4B, for example, and has only one PN junction formed therein whose forward direction is electrically in the direction from the second gate wiring 128 to the third gate wiring 138.

[0058] 1, the first body region 18 and the first source region 14 are covered with an interlayer insulating layer 44 having an opening, and a portion 13 of the first source electrode 11 is provided, which is connected to the first source region 14 through the opening in the interlayer insulating layer 44. The interlayer insulating layer 44 and the portion 13 of the first source electrode 11 are covered with a passivation layer 45 having an opening, and a portion 12 is provided, which is connected to the portion 13 of the first source electrode 11 through the opening in the passivation layer 45.

[0059] Similarly, the second body region 28 and the second source region 24 are covered with an interlayer insulating layer 44 having an opening, and a portion 23 of the second source electrode 21 is provided, which is connected to the second source region 24 through the opening in the interlayer insulating layer 44. The interlayer insulating layer 44 and the portion 23 of the second source electrode 21 are covered with a passivation layer 45 having an opening, and a portion 22 is provided, which is connected to the portion 23 of the second source electrode 21 through the opening in the passivation layer 45.

[0060] Similarly, the third body region 38 and the third source region 34 are covered with an interlayer insulating layer 44 having an opening, and a portion 33 of the third source electrode 31 is provided which is connected to the third source region 34 through the opening in the interlayer insulating layer 44. The interlayer insulating layer 44 and the portion 33 of the third source electrode 31 are covered with a passivation layer 45 having an opening, and a portion 32 is provided which is connected to the portion 33 of the third source electrode 31 through the opening in the passivation layer 45.

[0061] 2B, the first source pad 111, the second source pad 121, and the third source pad 131 respectively refer to regions where the first source electrode 11, the second source electrode 21, and the third source electrode 31 are partially exposed on the surface of the semiconductor device 1, i.e., terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 respectively refer to regions where the first gate electrode 19 and the second gate electrode 29 are partially exposed on the surface of the semiconductor device 1, i.e., terminal portions.

[0062] The numbers of the first source pads 111, the second source pads 121, and the third source pads 131 are not necessarily limited to the numbers exemplified in Fig. 2A. The shapes of the first source pads 111, the second source pads 121, and the third source pads 131 are not necessarily limited to the elliptical shapes exemplified in Fig. 2A, and may be, for example, rectangular or circular. The arrangements of the first source pads 111, the second source pads 121, and the third source pads 131 are not necessarily limited to the arrangements exemplified in Fig. 2A.

[0063] The number of first gate pads 119 and second gate pads 129 is not necessarily limited to the number illustrated in Fig. 2A, and may be a plurality of numbers equal to or greater than 2. Furthermore, the shapes of first gate pads 119 and second gate pads 129 are not necessarily limited to the circular shapes illustrated in Fig. 2A, and may be, for example, rectangular or elliptical.

[0064] Due to the above-described configurations of transistor 10, transistor 20, and transistor 30, the semiconductor substrate 42 and the area of ​​the low-concentration impurity layer 43 immediately above the semiconductor substrate 42 form a common drain region that is shared by the first drain region of transistor 10, the second drain region of transistor 20, and the third drain region of transistor 30.

[0065] Metal layer 41 is a common drain electrode in which the first drain electrode of transistor 10, the second drain electrode of transistor 20, and the third drain electrode of transistor 30 are commonized.

[0066] In this disclosure, the center of a shape in a plan view is defined as follows: for a circular shape such as the first gate pad 119 in FIG. 2A, it is its center; for a rectangular shape such as the first region A1, it is the intersection of its diagonals; and for an oval shape such as the first source pad 111, it is the intersection of the axis of line symmetry extending in the longitudinal direction and the axis of line symmetry extending in the width direction.

[0067] 2A, the first region A1 and the second region A2 are disposed with the third region A3 in between. In the present disclosure, the first region A1 and the second region A2 sandwiching the third region A3 means that the first region A1 and the third region A3 are adjacent to each other without any other region therebetween, and the second region A2 and the third region A3 are adjacent to each other without any other region therebetween. Therefore, in a plan view of the semiconductor layer 40, the third region A3 is adjacent to both the first region A1 and the second region A2.

[0068] That a region is adjacent to another region in a plan view has the same meaning as that the regions are facing each other, and that the outer circumferences of the regions coincide with each other at the boundary line 90 between them. Hereinafter, the length of the boundary line 90 may be referred to as the facing length.

[0069] As shown in FIG. 2B, the boundary line 90 between the first region A1 and the third region A3 may be regarded as a virtual line that traces the center position of the interval between the portion 13 of the first source electrode 11 and the portion 33 of the third source electrode 31. The boundary line 90 has a finite width, but may be regarded as the interval itself. Even in the case of the interval, it can be recognized as a line by the naked eye or by appearance at low magnification. In the example shown in FIG. 2A and FIG. 2B, the boundary line 90 between the first region A1 and the third region A3 is a dotted line from P1 to P2.

[0070] In addition, when the first EQR 116 is installed on the outer periphery of the first area A1 and the third EQR 136 is installed on the outer periphery of the third area A3 in a plan view, the first EQR 116 and the third EQR 136 may be integrated into one in a place where the outer periphery of the first area A1 coincides with the outer periphery of the third area A3. In this case, the location where the integrated EQR is installed may be regarded as the boundary line 90 between the first area A1 and the third area A3 in a plan view.

[0071] 2B, in the semiconductor device 1 according to the embodiment, the first diode 113 is disposed across the boundary line 90 between the first region A1 and the third region A3 in a plan view. That is, one of the ends of the first diode 113 is in the first region A1, and the other is in the third region A3 in a plan view.

[0072] 2B, in the semiconductor device 1 according to the embodiment, the first resistor element 114 is disposed across the boundary line 90 between the first region A1 and the third region A3 in a plan view. That is, in a plan view, one of the ends of the first resistor element 114 is disposed in the first region A1, and the other is disposed in the third region A3.

[0073] The boundary line 90 between the second region A2 and the third region A3 may be regarded as a virtual line that traces the center position of the interval between the portion 23 of the second source electrode 21 and the portion 33 of the third source electrode 31. It may also be regarded as the interval itself, although it has a finite width. In the example shown in Figures 2A and 2B, the boundary line 90 between the second region A2 and the third region A3 is a dotted line that runs from P3 to P4 via P5.

[0074] In addition, when the second EQR 126 is installed on the outer periphery of the second area A2 and the third EQR 136 is installed on the outer periphery of the third area A3 in a plan view, the second EQR 126 and the third EQR 136 may be integrated into one in a place where the outer periphery of the second area A2 coincides with the outer periphery of the third area A3. In this case, the location where the integrated EQR is installed may be regarded as the boundary line 90 between the second area A2 and the third area A3 in a plan view.

[0075] 2B, in the semiconductor device 1 according to the embodiment, the second diode 123 is disposed across the boundary line 90 between the second region A2 and the third region A3 in a plan view. That is, one of the ends of the second diode 123 is in the second region A2, and the other is in the third region A3 in a plan view.

[0076] 2B, in the semiconductor device 1 according to the embodiment, the second resistor element 124 is disposed across the boundary line 90 between the second region A2 and the third region A3 in a plan view. That is, one of the ends of the second resistor element 124 is disposed in the first region A1, and the other is disposed in the third region A3 in a plan view.

[0077] Although not shown in Figures 2A and 2B, the first region A1 and the second region A2 may be adjacent to each other (see the modified example shown in Figures 10A and 10B). The boundary line between the first region A1 and the second region A2 may be considered as a virtual line that traces the center position of the gap between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Although the width of the boundary line is finite, it may be considered as the gap itself.

[0078] In addition, when the first EQR 116 is installed on the outer periphery of the first region A1 and the second EQR 126 is installed on the outer periphery of the second region A2 in a plan view, the first EQR 116 and the second EQR 126 may be integrated into one in a place where the outer periphery of the first region A1 coincides with the outer periphery of the second region A2. In this case, the location where the integrated EQR is installed may be regarded as the boundary between the first region A1 and the second region A2 in a plan view.

[0079] In the semiconductor device 1 according to the embodiment, as shown in Figures 2A and 2B, the area a1 of the first region A1 in a plan view is larger than the area a3 of the third region A3 in a plan view (a1>a3). Furthermore, the area a3 of the third region A3 in a plan view is larger than the area a2 of the second region A2 in a plan view (a3>a2). Therefore, the first region A1, the second region A2, and the third region A3 have a relationship of a1>a3>a2 in terms of areas in a plan view.

[0080] 2B, the area in plan view of portion 13 of first source electrode 11 formed in first region A1 is approximately equal to the area in plan view of portion 33 of third source electrode 31 formed in third region A3. As described above, the area a1 in plan view of first region A1 is larger than the area a3 in plan view of third region A3 (a1>a3), but since first gate electrode 19 is formed in first region A1, the area in plan view of portion 13 of first source electrode 11 is reduced by that amount.

[0081] 5A and 5B are a plan view and a perspective view, respectively, of a transistor 10, a transistor 20, and a transistor 30, which are repeatedly formed in the X direction and the Y direction of the semiconductor device 1 according to the embodiment. For ease of understanding, the semiconductor substrate 42 and the metal layer 41, the passivation layer 45, the first source electrode 11, the second source electrode 21, the third source electrode 31, and the interlayer insulating layer 44 are not shown in FIG. 5A and FIG. 5B.

[0082] The Y direction is parallel to the surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. The X direction is parallel to the surface of the semiconductor layer 40 and perpendicular to the Y direction. The Z direction is perpendicular to both the X direction and the Y direction and is the height direction of the semiconductor device.

[0083] As shown in Figures 5A and 5B, the transistor 10 includes a first connection portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connection portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and is of the same second conductivity type as the first body region 18. The first source region 14 and the first connection portion 18a are alternately and periodically arranged in the Y direction. The same is true for the transistor 20 and the transistor 30.

[0084] In the semiconductor device 1 according to the present disclosure, the first conductivity type is defined as N type and the second conductivity type is defined as P type, with the first source region 14, the second source region 24, the third source region 34, the semiconductor substrate 42, and the low concentration impurity layer 43 being N-type semiconductors, and the first body region 18, the first connection portion 18a, the second body region 28, the second connection portion 28a, the third body region 38, and the third connection portion 38a being P-type semiconductors.

[0085] [2. Operation of Semiconductor Device] In the semiconductor device 1 according to the embodiment, it is assumed that a current flows from either the first source pad 111 in the first region A1 or the second source pad 121 in the second region A2 as an inlet, through the common drain region and the back surface drain electrode 41, and from the third source pad 131 in the third region A3 as an outlet. That is, the embodiment does not assume driving that conducts through a path from the first source pad 111 to the second source pad 121 or the reverse path.

[0086] In the semiconductor device 1, a conduction path through which a current flows from the first source pad 111 in the first region A1 as an inlet to the third source pad 131 in the third region A3 as an outlet is called a first conduction path. A conduction path through which a current flows from the second source pad 121 in the second region A2 as an inlet to the third source pad 131 in the third region A3 as an outlet is called a second conduction path.

[0087] In the first conduction path, a current flows as follows. First, in the semiconductor device 1, a high voltage is applied to the first source electrode 11 and a low voltage is applied to the third source electrode 31, and a voltage of sufficient magnitude that is equal to or greater than a threshold voltage is applied (ON control) to the first gate electrode 19 (first gate conductor 15) with the first source electrode 11 as a reference. Then, a conduction channel is formed in the first body region 18 near the first gate insulating film 16.

[0088] Furthermore, the voltage applied to the first gate electrode 19 is transmitted to the third gate conductor 35 via the first gate wiring 118, the first diode 113, and the third gate wiring 138. If this voltage is equal to or higher than the threshold (ON control), a conductive channel is formed in the third body region 38 near the third gate insulating film 36. At this time, a current flows through a path of the first source electrode 11-the first source region 14-the conductive channel formed in the first body region 18-the low-concentration impurity layer 43-the semiconductor substrate 42-the metal layer 41-the semiconductor substrate 42-the low-concentration impurity layer 43-the conductive channel formed in the third body region 38-the third source region 34-the third source electrode 31, and the semiconductor device 1 becomes conductive.

[0089] The above path is the first conduction path. The semiconductor device 1 according to the embodiment has a structure in which, when the transistor 10 is controlled to be ON, the transistor 30 is also automatically controlled to be ON.

[0090] It should be noted that when the first conduction path is made conductive, the PN junction at the contact surface between the second body region 28 and the low-concentration impurity layer 43 in the transistor 20 functions as a body diode. This prevents conduction from the first source pad 111 to the second source pad 121. When the first conduction path is used in the semiconductor device 1, it is desirable not to apply a voltage equal to or higher than the threshold voltage to the second gate electrode 29 (second gate conductor 25) of the transistor 20 (OFF control).

[0091] It should be noted that there is a certain voltage drop across the first diode 113. The voltage applied to the first gate electrode 19 to make the first conductive path conductive needs to be adjusted to be greater than the threshold voltage of the transistor 30 by the voltage drop across the first diode 113.

[0092] Incidentally, the second gate wiring 128 is also connected to the third gate wiring 138 via the second diode 123, but the second diode 123 is formed so that the electrical direction from the third gate wiring 138 to the second gate wiring 128 is the reverse direction. For this reason, the voltage applied to the first gate electrode 19 is not transmitted to the second gate wiring 128 (the second gate conductor 25).

[0093] The second gate wiring 128 is also connected to the third gate wiring 138 via the second resistance element 124, but the resistance value of the second resistance element 124 is adjusted to a value that sufficiently reduces the voltage from the third gate wiring 138. Therefore, the voltage applied to the first gate electrode 19 is not transmitted to the second gate wiring 128 (second gate conductor 25) at least at a value equal to or greater than the threshold value.

[0094] In the second conduction path, a current flows as follows. First, in the semiconductor device 1, a high voltage is applied to the second source electrode 21 and a low voltage is applied to the third source electrode 31, and a sufficiently large voltage that is equal to or greater than the threshold voltage is applied (ON control) to the second gate electrode 29 (second gate conductor 25) with the second source electrode 21 as a reference. Then, a conduction channel is formed in the second body region 28 near the second gate insulating film 26.

[0095] Furthermore, the voltage applied to the second gate electrode 29 is transmitted to the third gate conductor 35 via the second gate wiring 128, the second diode 123, and the third gate wiring 138. If this voltage is equal to or higher than the threshold (ON control), a conductive channel is formed in the third body region 38 near the third gate insulating film 36. At this time, a current flows through the path of the second source electrode 21-the second source region 24-the conductive channel formed in the second body region 28-the low-concentration impurity layer 43-the semiconductor substrate 42-the metal layer 41-the semiconductor substrate 42-the low-concentration impurity layer 43-the conductive channel formed in the third body region 38-the third source region 34-the third source electrode 31, and the semiconductor device 1 becomes conductive.

[0096] The above path is the second conduction path. The semiconductor device 1 according to the embodiment has a structure in which, when the transistor 20 is controlled to be ON, the transistor 30 is also automatically controlled to be ON.

[0097] It should be noted that when the second conduction path is made conductive, the PN junction at the contact surface between the first body region 18 and the low-concentration impurity layer 43 in the transistor 10 functions as a body diode. This prevents conduction from the second source pad 121 to the first source pad 111. When the second conduction path is used in the semiconductor device 1, it is preferable not to apply a voltage equal to or higher than the threshold voltage to the first gate electrode 19 (first gate conductor 15) of the transistor 10 (OFF control).

[0098] It should be noted that there is a certain voltage drop across the second diode 123. The voltage applied to the second gate electrode 29 to make the second conductive path conductive needs to be adjusted to be greater than the threshold voltage of the transistor 30 by the voltage drop across the second diode 123.

[0099] Incidentally, the first gate wiring 118 is also connected to the third gate wiring 138 via the first diode 113, but the first diode 113 is formed so that the electrical direction from the third gate wiring 138 to the first gate wiring 118 is the reverse direction. For this reason, the voltage applied to the second gate electrode 29 is not transmitted to the first gate wiring 118 (first gate conductor 15).

[0100] The first gate wiring 118 is also connected to the third gate wiring 138 via the first resistance element 114, but the resistance value of the first resistance element 114 is adjusted to a value that sufficiently reduces the voltage from the third gate wiring 138. Therefore, the voltage applied to the second gate electrode 29 is not transmitted to the first gate wiring 118 (first gate conductor 15) at least at a value equal to or greater than the threshold value.

[0101] As described above, it is desirable that the first diode 113 has a structure with only one PN junction so that unnecessary drops occur as little as possible before the voltage applied to the first gate pad 119 is transmitted to the third gate wiring 138. Also, the first resistance element 114 is required to have a resistance value large enough so that the voltage applied to the first gate pad 119 drops to a voltage equal to or lower than the threshold voltage before it is transmitted to the second gate wiring 128.

[0102] Similarly, the second diode 123 is desirably structured to have only one PN junction so as to minimize unnecessary drops in voltage applied to the second gate pad 129 before it is transmitted to the third gate wiring 138. The second resistance element 124 is required to have a resistance value large enough so that the voltage applied to the second gate pad 129 drops to a voltage equal to or lower than the threshold voltage before it is transmitted to the first gate wiring 118.

[0103] In both the first and second conductive paths, most of the current flowing horizontally inside the semiconductor device 1 passes through the metal layer 41, which has a low resistivity, but some of it may flow through the semiconductor substrate 42.

[0104] [3. Examples of semiconductor device usage] 6 is a circuit diagram showing a part of a power supply circuit that supplies current to a load 6 from a first power supply 51 and a second power supply 52, each of which is detachable, via a semiconductor device 1 according to an embodiment. Here, the potential of the load 6 is taken as a reference, and the potential of the first power supply 51 is assumed to be higher than the potential of the second power supply 52.

[0105] The semiconductor device 1 of the embodiment is installed so as to merge two power systems, a first power supply 51 having a high potential and a second power supply 52 having a lower potential, and combine them into one system toward a downstream load 6 having a low potential.

[0106] The maximum value of the current flowing due to the power supply from the first power supply 51, which has a high potential, is I1 [A], and the maximum value of the current flowing due to the power supply from the second power supply 52, which has a lower potential than the first power supply 51, is I2 [A]. I1 and I2 may be considered to be the maximum current values ​​specified in the first conduction path and the second conduction path, respectively, described in the product data sheet of the semiconductor device 1 according to the embodiment.

[0107] There is a relationship of I1>I2 due to the relationship of the potentials of the first power supply 51 and the second power supply 52. ​​The first power supply 51 side, through which a relatively large current I1 flows, is connected to the first source pad 111 of the transistor 10, which has a large area in a plan view in the semiconductor device 1, and the second power supply 52 side, through which a relatively small current I2 flows, is connected to the second source pad 121 of the transistor 20, which has a small area in a plan view in the semiconductor device 1.

[0108] A switching element 8 (for example, a single-type vertical MOS transistor) is connected between the semiconductor device 1 and the second power supply 52. ​​A control IC 4 is connected to the switching element 8 and the semiconductor device 1, and the control IC 4 controls ON / OFF of the switching element 8, the transistor 10, and the transistor 20 individually.

[0109] First, a state in which only the first power supply 51 is connected and the second power supply 52 is not connected (a state in which the second power supply 52 is not present in FIG. 6) will be described. At this time, the control IC 4 controls the transistor 10 to be ON and the transistor 20 to be OFF. Since the transistor 10 is controlled to be ON, the transistor 30 is also controlled to be ON automatically. Then, power is supplied from the first power supply 51 to the load 6 via the first conduction path in the semiconductor device 1.

[0110] The first conduction path is a conduction path inside the semiconductor device 1, and as described above, is a conduction path through which a current flows from the first source pad 111 of the transistor 10 as an inlet to the third source pad 131 of the transistor 30 as an outlet. When the first conduction path is conductive, the transistor 20 is controlled to be OFF. Since the transistor 20 is controlled to be OFF, the current flowing due to the power supply from the first power supply 51 can be prevented from flowing toward the second power supply 52.

[0111] Next, a state in which only the second power supply 52 is connected and the first power supply 51 is not connected (a state in which the first power supply 51 is not present in FIG. 6) will be described. At this time, the control IC 4 controls the transistor 20 to be ON and the transistor 10 to be OFF. Since the transistor 20 is controlled to be ON, the transistor 30 is also controlled to be ON automatically. Then, power is supplied from the second power supply 52 to the load 6 via the second conduction path in the semiconductor device 1.

[0112] The second conduction path is a conduction path inside the semiconductor device 1, and as described above, is a conduction path through which a current flows from the second source pad 121 of the transistor 20 as an inlet to the third source pad 131 of the transistor 30 as an outlet. When the second conduction path is conductive, the transistor 10 is controlled to be OFF. Because the transistor 10 is controlled to be OFF, the current flowing due to the power supply from the second power supply 52 can be prevented from flowing toward the first power supply 51.

[0113] When the first power supply 51 and the second power supply 52 are connected simultaneously (the state of FIG. 6), the control IC 4 first controls the switching element 8 to be OFF, creating a state in which only the first power supply 51 supplies power. This is because the first power supply 51 has a higher potential and is dominant in power supply. Furthermore, the transistor 10 is controlled to be ON and the transistor 20 is controlled to be OFF, so that the transistor 30 is also controlled to be ON, and power is supplied from the first power supply 51 to the load 6 via the first conduction path.

[0114] [4. Effects of semiconductor device] Fig. 7 shows a comparative example in which the semiconductor device 1 according to the embodiment is not used in the power supply circuit shown in Fig. 6. The effects of using the semiconductor device 1 according to the embodiment will be described below in comparison with the comparative example.

[0115] In the comparative example shown in Fig. 7, instead of the semiconductor device 1 according to the embodiment, for example, a single-structure vertical MOS transistor 10B (hereinafter referred to as transistor 10B) whose structure is shown in the schematic plan views of Fig. 8A and Fig. 8B, and a single-structure vertical MOS transistor 20B (hereinafter referred to as transistor 20B) whose structure is shown in the schematic plan views of Fig. 9A and Fig. 9B are used. Furthermore, a single-structure vertical MOS transistor 30B (hereinafter referred to as transistor 30B) whose structure is shown in the schematic plan views of Fig. 8A and Fig. 8B is connected immediately before the load 6.

[0116] In the transistors 10B, 20B, and 30B, components similar to those in the semiconductor device 1 according to the embodiment are indicated by adding the letter B to the reference numerals of the corresponding components.

[0117] The transistor 10B has, in plan view, two source pads 111B, one gate pad 119B, and one drain pad 151B. The drain pad 151B of the transistor 10B is connected to a surface drain electrode and serves as, for example, an outlet for a current flowing in from the source pad 111B of the transistor 10B.

[0118] The transistor 20B has, in plan view, two source pads 121B, one gate pad 129B, and one drain pad 152B. The drain pad 152B of the transistor 20B is connected to the surface drain electrode and serves as, for example, an outlet for a current flowing in from the source pad 121B of the transistor 20B.

[0119] The transistor 30B has, in plan view, two source pads 131B, one gate pad 139B, and one drain pad 153B. The drain pad 153B of the transistor 30B is connected to the surface drain electrode and serves as, for example, an inlet for a current flowing out to the source pad 131B of the transistor 30B.

[0120] 8B and 9B, in the same manner as shown in the schematic plan view (FIG. 2B) of the semiconductor device 1 according to the present embodiment, show the state immediately after the source electrode portion 13B (23B, 33B), the gate electrode 19B (29B, 39B), the gate wiring 118B (128B, 138B), and the surface drain electrode to which the drain pad 151B (152B, 153B) is connected are formed on the surface side of the semiconductor layer 40. For ease of understanding, pads that should not be visible at this point are shown by dotted lines in FIGS. 8B and 9B.

[0121] The area in a plan view of the portion 13B of the source electrode of the transistor 10B is the same as the area in a plan view of the portion 13 of the first source electrode 11 of the transistor 10 included in the semiconductor device 1 according to the embodiment. The area in a plan view of the portion 33B of the source electrode of the transistor 30B is the same as the area in a plan view of the portion 33 of the third source electrode 31 of the transistor 30 included in the semiconductor device 1 according to the embodiment. Therefore, the conduction resistance of the path from the first power supply 51 through the transistor 10B and the transistor 30B to the load 6 in FIG. 7 may be considered to be equivalent to the conduction resistance of the first conduction path of the semiconductor device 1 according to the embodiment in FIG.

[0122] In addition, the area in a plan view of portion 23B of the source electrode of transistor 20B is the same as the area in a plan view of portion 23 of second source electrode 21 of transistor 20 included in semiconductor device 1 according to the embodiment. Therefore, the conduction resistance of the path from second power supply 52 through transistor 20B and transistor 30B to load 6 in Fig. 7 may be considered to be equivalent to the conduction resistance of the second conduction path of semiconductor device 1 according to the embodiment in Fig. 6.

[0123] 7, when only the first power supply 51 is connected (the second power supply 52 does not exist in FIG. 7), the control IC 4 controls the transistor 20B to be OFF, preventing the current flowing due to the power supply from the first power supply 51 from flowing toward the second power supply 52. ​​Furthermore, a voltage equal to or higher than a threshold value is applied to the gate pad 119B of the transistor 10B, thereby controlling it to be ON, and further, a voltage equal to or higher than a threshold value is applied to the gate pad 139B of the transistor 30B, thereby controlling it to be ON.

[0124] Therefore, the current flowing due to the power supply from the first power supply 51 flows in from the source pad 111B of the transistor 10B, flows out from the drain pad 151B, and then flows in from the drain pad 153B of the transistor 30B and flows out from the source pad 131B. As shown in Figures 8A and 8B, the area of ​​the transistor 10B in a plan view (the area of ​​the source electrode portion 13B) is relatively large because the current flowing due to the power supply from the first power supply 51 is relatively large.

[0125] 7, when only the second power supply 52 is connected (the first power supply 51 is not present in FIG. 7), the control IC 4 controls the transistor 10B to be OFF, thereby preventing the current flowing due to the power supply from the second power supply 52 from flowing toward the first power supply 51. Furthermore, a voltage equal to or higher than a threshold value is applied to the gate pad 129B of the transistor 20B, thereby controlling it to be ON, and further, a voltage equal to or higher than a threshold value is applied to the gate pad 139B of the transistor 30B, thereby controlling it to be ON.

[0126] Therefore, the current flowing due to the power supply from the second power supply 52 flows in from the source pad 121B of the transistor 20B, flows out from the drain pad 152B, and then flows in from the drain pad 153B of the transistor 30B and flows out from the source pad 131B. As shown in Figures 9A and 9B, the area of ​​the transistor 20B in a plan view (the area of ​​the portion 23B of the source electrode) is relatively small because the current flowing due to the power supply from the second power supply 52 is relatively small.

[0127] As described above, in the power supply circuit according to the comparative example shown in Fig. 7, the transistors 10B and 30B perform the same functions as the transistors 10 and 30 provided in the semiconductor device 1 according to the embodiment in the power supply circuit of Fig. 6. Similarly, in the power supply circuit according to the comparative example shown in Fig. 7, the transistors 20B and 30B perform the same functions as the transistors 20 and 30 provided in the semiconductor device 1 according to the embodiment in the power supply circuit of Fig. 6.

[0128] 7, it is necessary to ensure the areas of transistors 10B, 20B, and 30B, and to provide a certain margin between each of them. In addition, transistors 10B, 20B, and 30B each have a drain pad (151B, 152B, 153B) in plan view, and therefore have a structure that requires a certain area.

[0129] 6, the transistor 10B, the transistor 20B, and the transistor 30B according to the comparative example can be integrated into one by using the semiconductor device 1 according to the embodiment. This makes it possible to eliminate the need for a certain installation margin that must be provided between the transistor 10B, the transistor 20B, and the transistor 30B, which was necessary in the circuit board on which the power supply circuit according to the comparative example is mounted.

[0130] In addition, in the semiconductor device 1 according to the embodiment, the drain pads (151B, 152B, 153B) of the transistors 10B, 20B, and 30B in the comparative example can be eliminated. Moreover, in the semiconductor device 1 according to the embodiment, the third transistor 30 does not have a gate pad, so that the gate pad 139B formed in the transistor 30B (FIG. 8B) in the comparative example shown in FIG. 7 can be eliminated.

[0131] As described above, by using the semiconductor device 1 according to the embodiment, the area required for a circuit board can be significantly reduced. In the circuit board having the power supply circuit shown in Fig. 6 mounted thereon, the board itself can be made smaller than in the comparative example, and other components can be mounted in the resulting surplus area.

[0132] Therefore, the semiconductor layer 1 according to the embodiment is a chip-size package type semiconductor device 1 capable of face-down mounting, and has a semiconductor substrate 42 on the back side thereof, and includes a semiconductor layer 40 divided into three regions, a first region A1, a second region A2, and a third region A3, which do not overlap each other in a plan view of the semiconductor device 1 and are not disposed in a dispersed manner, a first vertical MOS transistor 10 entirely formed in the first region A1 of the semiconductor layer 40, a second vertical MOS transistor 20 entirely formed in the second region A2 of the semiconductor layer 40, a third vertical MOS transistor 30 entirely formed in the third region A3 of the semiconductor layer 40, and a metal layer 41 formed in contact with the back side of the semiconductor layer 40, and the semiconductor substrate 42 is a common drain region of the first vertical MOS transistor 10, the second vertical MOS transistor 20, and the third vertical MOS transistor 30, and a first source of the first vertical MOS transistor 10 is disposed at a position included in the first region A1 in a plan view. A second source pad 121 of the second vertical MOS transistor 20, a second gate pad 129 of the second vertical MOS transistor 20, and a second gate wiring 128 of the second vertical MOS transistor 20 connected to the second gate pad 129 are formed at a position included in the second region A2 in a plan view, and a third source pad 131 of the third vertical MOS transistor 30 and a second gate wiring 128 of the third vertical MOS transistor 30 are formed at a position included in the third region A3 in a plan view. and a third gate wiring 138 are formed, the first gate wiring 118 and the third gate wiring 138 are electrically connected in series via a first diode 113 whose forward direction is from the first gate wiring 118 to the third gate wiring 138, and the second gate wiring 128 and the third gate wiring 138 are electrically connected in series via a second diode 123 whose forward direction is from the second gate wiring 128 to the third gate wiring 138.

[0133] The semiconductor device 1 according to the embodiment has a structure in which, by providing the first diode 113, when the transistor 10 is turned on, the transistor 30 is also turned on automatically, and the first conduction path is conductive. At this time, as viewed from the third gate wiring 138, the second diode 123 is formed electrically in the reverse direction, so that the transistor 20 is not turned on.

[0134] Similarly, by providing the second diode 123, when the transistor 20 is turned on, the transistor 30 is automatically turned on, and the second conduction path is conductive. At this time, as viewed from the third gate wiring 138, the first diode 113 is formed electrically in the reverse direction, so that the transistor 10 is not turned on.

[0135] The first diode 113 has one end connected to the first gate wiring 118 and the other end connected to the third gate wiring 138. Similarly, the second diode 123 has one end connected to the second gate wiring 128 and the other end connected to the third gate wiring 138.

[0136] Therefore, in the semiconductor device 1 of the embodiment, in a planar view, the first diode 113 is formed such that one end of the first diode 113 is in the first region A1 and the other end of the first diode 113 is in the third region A3, and in a planar view, the second diode 123 is formed such that one end of the second diode 123 is in the second region A2 and the other end of the second diode 123 is in the third region A3.

[0137] When the first diode 113 and the second diode 123 are formed as described above, there is also an effect of preventing an unnecessary reduction in the conduction area of ​​the first conduction path or the second conduction path.

[0138] 2B, the first diode 113 is typically installed across a boundary line 90 (dotted line from P1 to P2) between the first region A1 and the third region A3 in a plan view. When the first EQR 116 is installed in the first region A1 and the third EQR 136 is installed in the third region A3, the boundary line 90 between the first region A1 and the third region A3 is where the first EQR 116 and the third EQR 136 are shared in a plan view, but in order to install the first diode 113, it may be necessary to divide a part of the shared EQR.

[0139] Therefore, in the semiconductor device 1 according to the embodiment, in a plan view, the first EQR 116 is formed on at least a part of the periphery of the first region A1, in a plan view, the third EQR 136 is formed on at least a part of the periphery of the third region A3, in a plan view, the first EQR 116 and the third EQR 136 are commonized in a portion where the first region A1 and the third region A3 face each other, and in a plan view, the first diode 113 may be disposed in a portion where the first EQR and the third EQR are not common. That is, in a plan view, the first diode 113 may be disposed at a location where the common EQR is interrupted, which is a boundary line 90 between the first region A1 and the third region A3.

[0140] 6, there are cases where no voltage is applied to either the first gate pad 119 or the second gate pad 129. At this time, depending on the immediately preceding usage state of the semiconductor device 1, a potential may remain in the first gate wiring 118 and the third gate wiring 138, or in the second gate wiring 128 and the third gate wiring 138.

[0141] When the first gate wiring 118 and the third gate wiring 138 are connected via the first resistance element 114, even if the resistance value of the first resistance element 114 is high, a path is formed to release the residual potentials of the first gate wiring 118 and the third gate wiring 138 to the first gate pad 119, which is advantageous. Similarly, when the second gate wiring 128 and the third gate wiring 138 are connected via the second resistance element 124, even if the resistance value of the second resistance element 124 is high, a path is formed to release the residual potentials of the second gate wiring 128 and the third gate wiring 138 to the second gate pad 129, which is advantageous.

[0142] Therefore, in the semiconductor device 1 of the embodiment, the first gate wiring 118 and the third gate wiring 138 may be connected in series via the first resistance element 114, the first diode 113 and the first resistance element 114 may be connected in parallel between the first gate wiring 118 and the third gate wiring 138, the second gate wiring 128 and the third gate wiring 138 may be connected in series via the second resistance element 124, and the second diode 123 and the second resistance element 124 may be connected in parallel between the second gate wiring 128 and the third gate wiring 138.

[0143] The first resistance element 114 has one end connected to the first gate wiring 118 and the other end connected to the third gate wiring 138. Similarly, the second resistance element 124 has one end connected to the second gate wiring 128 and the other end connected to the third gate wiring 138.

[0144] Therefore, in the semiconductor device 1 of the embodiment, it is desirable that, in a planar view, the first resistance element 114 is formed so that one end of the first resistance element 114 is in the first region A1 and the other end of the first resistance element 114 is in the third region A3, and that, in a planar view, the second resistance element 124 is formed so that one end of the second resistance element 124 is in the second region A2 and the other end of the second resistance element 124 is in the third region A3.

[0145] When the first resistor element 114 and the second resistor element 124 are formed as described above, it is possible to obtain the effect of preventing an unnecessary reduction in the conduction area of ​​the first conduction path or the second conduction path.

[0146] In the semiconductor device 1 according to the embodiment, the first conductive path has the first source pad 111 in the first region A1 as an inlet and the third source pad 131 in the third region A3 as an outlet. Therefore, if the first region A1 and the third region A3 are adjacent in a plan view, the first conductive path is conveniently shortened to reduce the conductive resistance. Similarly, the second conductive path has the second source pad 121 in the second region A2 as an inlet and the third source pad 131 in the third region A3 as an outlet. Therefore, if the second region A2 and the third region A3 are adjacent in a plan view, the second conductive path is conveniently shortened to reduce the conductive resistance.

[0147] Therefore, in a plan view, it is preferable that the first region A1 and the second region A2 are disposed with the third region A3 therebetween, and that the third region A3 is adjacent to the first region A1 and the second region A2.

[0148] In the semiconductor device 1 according to the embodiment, emphasis is placed on reducing the conduction resistance of the first conduction path. For this reason, as shown in Fig. 2A or 2B, it is preferable that the opposing length between the first region A1 and the third region A3 (the length of the dotted line from P1 to P2) is longer than the opposing length between the second region A2 and the third region A3 (the length of the dotted line from P3 through P5 to P4) in a plan view. By arranging the semiconductor device 1 in the above-mentioned plan view, the area where the current density is highest in the first conduction path can be expanded (the opposing length is increased), and therefore the conduction resistance can be reduced.

[0149] In the semiconductor device 1 according to the embodiment, in the first conductive path that conducts a relatively large current, it is desirable that the areas of the inlet and the outlet in a plan view are approximately the same because if either the inlet or the outlet is relatively small, it becomes a bottleneck and increases the conduction resistance.

[0150] Therefore, in the semiconductor device 1 according to the embodiment, the first source electrode of the first vertical MOS transistor 10 is formed in a position included in the first region A1 in a plan view, and the third source electrode of the third vertical MOS transistor 30 is formed in a position included in the third region A3 in a plan view, and it is desirable that the area of ​​the first source electrode is approximately equal to the area of ​​the third source electrode in a plan view. The first and third source electrodes here refer to the portions 13 and 33 of the first and third source electrodes 11 and 31, which are in direct contact with the semiconductor layer 40.

[0151] Furthermore, in the semiconductor device 1 of the embodiment, since no gate pad or gate electrode is present in the third region A3 in a planar view, even if the areas of the portion 13 of the first source electrode 11 and the portion 33 of the third source electrode 31 are the same in a planar view, the area a3 of the third region A3 can be reduced compared to the area a1 of the first region A1.

[0152] In addition, since the second conductive path has a small current specification, the area of ​​the conductive path can be reduced by taking this into consideration. In this case, it does not matter if the area of ​​the outlet (part 33 of the third source electrode 31) in a plan view is larger than the area of ​​the inlet (part 23 of the second source electrode 21).

[0153] Therefore, in the semiconductor device 1 according to the embodiment, it is desirable that the area a1 of the first region A1 is larger than the area a3 of the third region A3, and the area a3 of the third region A3 is larger than the area a2 of the second region A2 in a plan view. The difference between the area a1 of the first region A1 in a plan view and the area a3 of the third region A3 in a plan view is approximately the area of ​​one first gate pad 119.

[0154] 10A and 10B are schematic plan views showing modified examples of the structure of the semiconductor device 1 according to the embodiment. Fig. 10B is similar to Fig. 2B, and shows the state immediately after the portion 13 of the first source electrode 11, the first gate electrode 19, the first gate wiring 118, the portion 23 of the second source electrode 21, the second gate electrode 29, the second gate wiring 128, the portion 33 of the third source electrode 31, and the third gate wiring 138 are formed on the front surface side of the semiconductor layer 40. Pads that should not be visible at this point are shown by dotted lines.

[0155] 10A and 10B, compared to FIG. 2A and FIG. 2B, the third region A3 is not sandwiched between the first region A1 and the second region A2, but the first region A1 and the second region A2 are adjacent to each other in some places. Also, in a plan view, the first gate pad 119 is provided in the first region A1 at a position adjacent to the third region A3.

[0156] The first gate pad 119 is provided in a position adjacent to the third region A3 in the first region A1, meaning that the first source pad 111 is not even partially sandwiched between the first gate pad 119 and the third region A3 closest to the first gate pad 119 in the first region A1.

[0157] With this arrangement, it is possible to shorten the connection distance between the first gate pad 119 and the third gate wiring 138. Therefore, the voltage applied to the first gate pad 119 can be quickly transmitted to the third gate wiring 138, thereby improving the response speed of the semiconductor device 1. This effect is also achieved with the arrangement of the second gate pad 129 and the third region A3 in a plan view.

[0158] Therefore, in a plan view, the first gate pad 119 may be provided in a position adjacent to the third region A3, and the second gate pad 129 may be provided in a position adjacent to the third region A3.

[0159] 2B and 10B, when the first Zener diode 115 and / or the second Zener diode 125 are formed in the semiconductor device 1, it is desirable to simultaneously form the first diode 113 and / or the second diode 123. By forming them simultaneously, the manufacture of the semiconductor device 1 can be facilitated.

[0160] In the first place, the first Zener diode 115 and / or the second Zener diode 125 and the first diode 113 and / or the second diode 123 are both diodes, and can perform their respective functions simply by appropriately controlling the formation position and number of PN junctions or the direction of the electrical PN junctions. As shown in FIG. 2B, the first Zener diode 115 and / or the second Zener diode 125 and the first diode 113 and / or the second diode 123 are only different in their in-plane installation positions in the plan view of the semiconductor device 1. Therefore, they can be formed simultaneously simply by changing the in-plane implantation positions of the impurities accordingly.

[0161] In this case, when comparing the regions of the first diode 113 and the first Zener diode 115 that have the same conductivity type in a plan view, the concentrations of impurities of the same conductivity type are the same in each of them. The same impurity concentration means that the concentration profiles of the impurities roughly match when comparing one region with another in the depth direction.

[0162] Therefore, in a planar view, the first source electrode 11 (part 13) and the first gate electrode 19 of the first vertical MOS transistor 10 are formed at a position included in the first region A1, and in a planar view, the first Zener diode 115 is formed between the first source electrode 11 (part 13) and the first gate electrode 19, and impurities of the same conductivity type in the regions of the same conductivity type included in the first diode 113 and the first Zener diode 115 may have the same concentration.

[0163] Similarly, when the first gate resistor 117 and / or the second gate resistor 127 are formed in the semiconductor device 1, it is desirable to simultaneously form the first resistor 114 and / or the second resistor 124. By forming them simultaneously, the manufacture of the semiconductor device 1 can be facilitated.

[0164] Therefore, in a planar view, the first gate electrode 19 of the first vertical MOS transistor 10 is formed in the first region A1, and in a planar view, the first gate resistance element 117 is formed between the first gate electrode 19 and the first gate wiring 118, and impurities of the same conductivity type in the regions of the same conductivity type included in the first resistance element 114 and the first gate resistance element 117 may have the same concentration.

[0165] [5. Additional Considerations] 6 using the semiconductor device 1 according to the embodiment. In a transistor in an ON state, generally, when the area of ​​the transistor in a plan view is large, the total gate width increases, and therefore the conduction resistance decreases. In other words, the area of ​​the transistor in a plan view and the conduction resistance are generally inversely proportional to each other.

[0166] In the semiconductor device 1, the area a1 of the transistor 10 forming the first conduction path in a plan view is larger than the area a2 of the transistor 20 forming the second conduction path in a plan view. Therefore, the first conduction path has a lower conduction resistance and is suitable for passing a relatively large current.

[0167] The conduction resistance R1 [Ω] of the first conduction path may be determined taking into consideration the maximum value I1 [A] of the current flowing due to the power supply from the first power source 51. Similarly, the conduction resistance R2 [Ω] of the second conduction path may be determined taking into consideration the maximum value I2 [A] of the current flowing due to the power supply from the second power source 52. Therefore, in the semiconductor device 1 according to the embodiment, it is desirable to determine the areas of the transistors 10 and 20 so that the conduction resistances suitable for the first conduction path and the second conduction path are respectively realized.

[0168] However, if the area of ​​each transistor in plan view calculated as above is too small, the ESD resistance may decrease. This is because if the area of ​​a transistor in plan view is small, the excessive voltage or surge current applied to the gate electrode cannot be sufficiently dispersed in the cell (gate conductor) of the transistor.

[0169] If the ESD guaranteed value (electrostatic resistance guaranteed value) of the semiconductor device 1 is hereinafter represented as ESDt [V], the semiconductor device 1 according to the embodiment is required to realize resistance of ESDt or more with the transistor 20 having the smallest area. When used in a power supply circuit as shown in Fig. 6, the ESDt typically required for the semiconductor device 1 is about 1000 [V] to 2000 [V].

[0170] For the purpose of achieving a desired ESDt, it has been described that, in the case of the transistor 20, the second Zener diode 125 and / or the second gate resistor element 127 is provided. However, providing the second Zener diode 125 provides a path connecting the second gate pad 129 (second gate electrode 29) and the second source pad 121 (part 23 of the second source electrode 21), as shown in the part of the transistor 20 in Fig. 6, which has the side effect of causing a leakage current between the gate and the source.

[0171] FIG. 11 shows the area a [mm 2 ] and the maximum voltage value ESDt [V] that was confirmed to not destroy the transistor when applied to the gate pad. The horizontal axis is a, and the vertical axis is ESDt. Note that the area a of the transistor in a plan view refers to the area a1 of the first region A1 in a plan view and the area a2 of the second region A2 in a plan view in the example of the semiconductor device 1 according to the embodiment. In other words, it includes areas that do not contribute to conduction.

[0172] The data plotted with the circle markers was taken with a transistor that had neither a Zener diode nor a gate resistor. The data plotted with the triangle markers was taken with a transistor that had only a Zener diode and no gate resistor. The data plotted with the diamond markers was taken with a transistor that had both a Zener diode and a gate resistor.

[0173] Figure 11 shows that when no gate resistor is installed, the ESDt tends to increase as the transistor area a is increased. It also shows that ESDt can be improved by installing a Zener diode, even without increasing the transistor area a. When a gate resistor is installed in addition to the Zener diode, a nearly constant ESDt can be obtained, regardless of the transistor area.

[0174] When the ESD protection value of the semiconductor device 1 according to the embodiment is desired to be, for example, 2000 [V], it is sufficient that 2000 [V] can be guaranteed for the transistor 20 having the smallest area in plan view. 2 ], it is desirable to provide the second Zener diode 125 and the second gate resistor element 127. On the other hand, if it is desired to avoid an increase in leakage current between the gate and the source due to the provision of the second Zener diode 125, it is better not to provide the second Zener diode 125. If the required ESD guarantee value is 2000 [V], the area a2 of the transistor 20 in plan view is approximately 2.0 [mm 2 ] or more would be sufficient.

[0175] Therefore, according to the data of the circular markers in FIG. 11, the electrostatic tolerance guarantee value described in the product data sheet of the semiconductor device 1 is set to ESDt [V], and the area of ​​the second region A2 in a plan view is set to a2 [mm 2 ], then the relationship a2>(ESDt-93) / 990 must hold.

[0176] Furthermore, at this time, the portion 23 of the second source electrode 21 of the second vertical MOS transistor 20 and the second gate electrode 29 are formed at a position included in the second region A2 in a planar view, and there is no path electrically connecting the portion 23 of the second source electrode 21 and the second gate electrode 29, and the second gate electrode 29 and the second gate wiring 128 may be connected without going through a resistor.

[0177] By adopting the above-described structure, it is possible to prevent an increase in leakage current between the gate and source of the transistor 20, while at the same time making it possible to obtain a desired ESD protection value (ESDt [V]) for the semiconductor device 1.

[0178] At this time, sufficient ESDt should already be realized in the transistor 10 having a larger area in plan view in the semiconductor device 1. Therefore, the portion 13 of the first source electrode 11 and the first gate electrode 19 of the first vertical MOS transistor 10 are formed at a position included in the first region A1 in plan view, and there is no path electrically connecting the portion 13 of the first source electrode 11 and the first gate electrode 19, and the first gate electrode 19 and the first gate wiring 118 may be connected without an intervening resistor.

[0179] With such a structure, it is possible to prevent the leakage current between the gate and source of the transistor 10 from increasing unnecessarily.

[0180] Incidentally, even if the area a2 of the second region A2 in a planar view has a relationship of a2<(ESDt-93) / 990, the desired ESD guarantee value may be realized by providing the second Zener diode 125 or the second gate resistance element 127.

[0181] Therefore, the portion 13 of the first source electrode 11 and the first gate electrode 19 of the first vertical MOS transistor 10 are formed at a position included in the first region A1 in a planar view, there is no path electrically connecting the portion 13 of the first source electrode 11 and the first gate electrode 19, and the first gate electrode 19 and the first gate wiring 118 are connected without a resistor, the portion 23 of the second source electrode 21 and the second gate electrode 29 of the second vertical MOS transistor 20 are formed at a position included in the second region A2 in a planar view, the portion 23 of the second source electrode 21 and the second gate electrode 29 are connected via the second Zener diode 125, and the second gate electrode 29 and the second gate wiring 128 may be connected in series with the second gate resistor element 127 therebetween.

[0182] By using the above-described structure, it is possible to avoid an unnecessary increase in leakage current between the gate and source in the transistor 10, while obtaining a desired ESD guaranteed value (ESDt [V]) for the semiconductor device 1.

[0183] Although the semiconductor device according to one aspect of the disclosure has been described above based on the embodiment and the modified examples, the present disclosure is not limited to the embodiment. As long as it does not deviate from the gist of the present disclosure, various modifications conceived by a person skilled in the art to these embodiments and forms constructed by combining components in different embodiments and modified examples may also be included within the scope of one or more aspects of the present disclosure. [Industrial Applicability]

[0184] A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path. [Explanation of symbols]

[0185] 1 Semiconductor device 4. Control IC 6 Load 8 Switching elements 10 Transistor (first vertical MOS transistor) 10B, 20B, 30B transistors (single-structure vertical MOS transistors) 11 First source electrode 12, 13, 13B, 22, 23, 23B, 32, 33, 33B part 14 First Source Region 15 First gate conductor 16 First gate insulating film 17 First gate trench 18 First Body Region 18a First connection part 19 First gate electrode 19B, 29B, 39B Gate electrodes 20 Transistor (second vertical MOS transistor) 21 Second source electrode 24 Second Source Region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second Body Region 28a Second connection 29 Second gate electrode 30 Transistor (third vertical MOS transistor) 31 Third source electrode 34 Third Source Region 35 Third Gate Conductor 36 Third gate insulating film 37 Third Gate Trench 38 Third Body Region 38a Third Connection 40 Semiconductor layer 41 Metal layer (rear drain electrode) 42 Semiconductor Substrate 43 Low concentration impurity layer 44 Interlayer insulation layer 45 Passivation Layer 90 Border 111 First Source Pad 111B, 121B, 131B Source Pad 113 First Diode 114 First Resistance Element 115 First Zener Diode 116 First EQR 117 First gate resistor 118 First gate wiring 118B, 128B, 138B gate wiring 119 First Gate Pad 119B, 129B, 139B Gate Pads 121 Second Source Pad 123 Second Diode 124 Second Resistive Element 125 Second Zener Diode 126 Second EQR 127 Second gate resistor 128 Second gate wiring 129 Second Gate Pad 131 Third Source Pad 136 Third EQR 138 3rd gate wiring 151B, 152B, 153B drain pad A1 First Area A2 Second Area A3 The third area

Claims

1. A chip size package type semiconductor device capable of face-down mounting, A semiconductor layer having a semiconductor substrate on a back surface side, the semiconductor layer being divided into three regions, a first region, a second region, and a third region, which do not overlap each other in a plan view of the semiconductor device, and which are not distributed among each other; a first vertical MOS transistor formed entirely in the first region of the semiconductor layer; a second vertical MOS transistor formed entirely in the second region of the semiconductor layer; a third vertical MOS transistor formed entirely in the third region of the semiconductor layer; a metal layer formed in contact with a rear surface side of the semiconductor layer, the semiconductor substrate is a common drain region of the first vertical MOS transistor, the second vertical MOS transistor, and the third vertical MOS transistor; a first source pad and a first gate pad of the first vertical MOS transistor, and a first gate wiring connected to the first gate pad are formed at a position included in the first region in the plan view; a second source pad and a second gate pad of the second vertical MOS transistor, and a second gate wiring connected to the second gate pad are formed at a position included in the second region in the plan view; a third source pad and a third gate wiring of the third vertical MOS transistor are formed at a position included in the third region in the plan view; the first gate wiring and the third gate wiring are electrically connected in series via a first diode having a forward direction from the first gate wiring to the third gate wiring; The second gate wiring and the third gate wiring are electrically connected in series via a second diode having a forward direction from the second gate wiring to the third gate wiring. Semiconductor device.

2. the first diode is formed such that one end of the first diode is in the first region and the other end of the first diode is in the third region; The second diode is formed such that one end of the second diode is in the second region and the other end of the second diode is in the third region. The semiconductor device according to claim 1 .

3. the first gate wiring and the third gate wiring are further connected in series via a first resistance element; the first diode and the first resistance element are connected in parallel between the first gate wiring and the third gate wiring, the second gate wiring and the third gate wiring are further connected in series via a second resistance element, The second diode and the second resistor element are connected in parallel between the second gate wiring and the third gate wiring. The semiconductor device according to claim 1 .

4. the first resistor element is formed such that one end of the first resistor element is in the first region and the other end of the first resistor element is in the third region; The second resistive element is formed such that one end of the second resistive element is in the second region and the other end of the second resistive element is in the third region. The semiconductor device according to claim 3 .

5. In the plan view, the first region and the third region are adjacent to each other, and the second region and the third region are adjacent to each other. The semiconductor device according to claim 1 .

6. In the plan view, an area of ​​the first region is larger than an area of ​​the third region, The area of ​​the third region is greater than the area of ​​the second region. The semiconductor device according to claim 1 .

7. a first source electrode of the first vertical MOS transistor is formed at a position included in the first region in the plan view; a third source electrode of the third vertical MOS transistor is formed at a position included in the third region in the plan view; In the plan view, the area of ​​the first source electrode is equal to the area of ​​the third source electrode. The semiconductor device according to claim 6.

8. In the plan view, a first EQR (EQUI potential ring) is formed on at least a part of an outer periphery of the first region, In the plan view, a third EQR is formed on at least a part of an outer periphery of the third region, In the plan view, the first EQR and the third EQR are common to each other in a portion where the first region and the third region face each other, In the plan view, the first diode is disposed in a portion where the first EQR and the third EQR are not shared. The semiconductor device according to claim 1 .

9. the first gate pad is disposed in a position adjacent to the third region in the plan view; In the plan view, the second gate pad is disposed in a position adjacent to the third region. The semiconductor device according to claim 1 .

10. a first source electrode and a first gate electrode of the first vertical MOS transistor are formed at positions included in the first region in the plan view; a first Zener diode is formed between the first source electrode and the first gate electrode in the plan view; The first diode and the first Zener diode have the same concentration of impurities of the same conductivity type in the regions of the same conductivity type. The semiconductor device according to claim 1 .

11. a first source electrode and a first gate electrode of the first vertical MOS transistor are formed at positions included in the first region in the plan view; a first gate resistor element is formed between the first gate electrode and the first gate wiring in the plan view; The first resistance element and the first gate resistance element include regions of the same conductivity type, and the impurities of the same conductivity type are at the same concentration. The semiconductor device according to claim 3 .

12. A gate electrode and a gate pad connected to the third gate wiring are not formed in a position included in the third region in the plan view. The semiconductor device according to claim 1 .

13. The electrostatic discharge tolerance guaranteed value described in the product data sheet of the semiconductor device is ESDt [V], The area of ​​the second region in the plan view is a2 [mm ２ ], then The relationship a2>(ESDt-93) / 990 holds true The semiconductor device according to claim 6.

14. a second source electrode and a second gate electrode of the second vertical MOS transistor are formed at a position included in the second region in the plan view; There is no path electrically connecting the second source electrode and the second gate electrode, The second gate electrode and the second gate wiring are connected without a resistor. The semiconductor device according to claim 13.

15. a first source electrode and a first gate electrode of the first vertical MOS transistor are formed at positions included in the first region in the plan view; There is no path electrically connecting the first source electrode and the first gate electrode, The first gate electrode and the first gate wiring are connected without a resistor. The semiconductor device according to claim 14.

16. a first source electrode and a first gate electrode of the first vertical MOS transistor are formed at a position included in the first region in the plan view; There is no path electrically connecting the first source electrode and the first gate electrode, the first gate electrode and the first gate wiring are connected without a resistor; a second source electrode and a second gate electrode of the second vertical MOS transistor are formed at a position included in the second region in the plan view; the second source electrode and the second gate electrode are connected via a second Zener diode; The second gate electrode and the second gate wiring are connected in series with a second gate resistor element therebetween. The semiconductor device according to claim 6.

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