Table learning method with reduced learning rate applied to driving circuit and driving circuit using this method

Abstract

To provide a method applied to a controller in a driving circuit that includes a driving subcircuit configured to drive a load.SOLUTION: A method according to the present invention includes the steps of: performing a table learning operation on a table with at least a first rate during a learning period; and after the learning period, performing a table learning operation on the table at a second rate lower than the first rate. The table is stored in a memory in a controller. The table learning operation includes the steps of: receiving a first feedback signal from a load corresponding to a first cycle; obtaining a control code from the table according to the first feedback signal; generating a control signal according to the control code; receiving a second feedback signal from a load corresponding to a second cycle; and updating the control code and re-storing the updated control code in the table in the memory.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a method applied to a driving circuit, and more particularly to a method applied to a driving circuit that is low-power and can handle a variety of operating conditions. [Background technology]

[0002] Recently, piezoelectric-actuated speakers (piezo speakers) have appeared. Due to the capacitive nature of thin-film piezoelectric actuators, these piezoelectric speakers present a highly capacitive load to the amplifier. Conventional driving circuits such as class-AB, -D, -G, -H amplifiers are all evolved under the assumption that the load (a coil made of very thin wire) is mostly resistive and slightly inductive, and these amplifiers are not suitable / designed to drive highly capacitive loads such as piezoelectric speakers.

[0003] A driving circuit including a DC-DC converter with energy recycling capability has been developed to drive a capacitive piezoelectric speaker. The performance of the driving circuit including DC-DC depends on providing a pulse width modulated (PWM) signal (as a gate control signal) with a precise pulse width. Therefore, how to generate a PWM signal with a precise pulse width is an important goal in this field, especially when the circuit parameters are different from device to device and the circuit operating conditions such as battery voltage level vary. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 6,984,967 [Patent Document 2] U.S. Patent No. 7,391,190 [Patent Document 3] U.S. Patent No. 7,609,040 [Patent Document 4] U.S. Patent No. 7,923,980 [Patent Document 5] U.S. Patent No. 8,975,826 [Patent Document 6] U.S. Patent No. 8,976,543 [Patent Document 7] U.S. Patent No. 6,348,779 [Patent Document 8] U.S. Patent No. 6,215,286 [Patent Document 9] U.S. Patent No. 6,191,567 [Patent Document 10] U.S. Patent No. 6,166,527 [Patent Document 11] U.S. Patent No. 6,088,243 [Patent Document 12] U.S. Patent Application Publication No. 2022 / 0209647 [Patent Document 13] U.S. Patent Application Publication No. 2022 / 0021305 Summary of the Invention

[0005] Therefore, an object of the present invention is to provide a table learning method that can adaptively adjust a Pulse Width Control Code (PWCC) used to generate a Pulse Width Modulation (PWM) signal during operation of an energy reuse amplifier in order to solve the above problems.

[0006] One embodiment of the present invention discloses a method applied to a controller in a drive circuit, the drive circuit including a drive sub-circuit configured to drive a load, the method including: performing a table learn operation on a table at least at a first rate during a learning period; performing a table learn operation on the table at a second rate lower than the first rate after the learning period, the table being stored in a memory in the controller, the table learn operation including: receiving a first feedback signal from the load corresponding to a first cycle; obtaining a control code from the table according to the first feedback signal; generating a control signal according to the control code, the drive sub-circuit performing an operation on the load according to the control signal during a second cycle; receiving a second feedback signal from the load corresponding to the second cycle; updating the control code according to the first feedback signal and the second feedback signal, and storing the updated control code back in the table in the memory.

[0007] Another embodiment of the present invention discloses a drive circuit. The drive circuit includes a drive sub-circuit coupled to a load and a controller including a memory in which a table is stored. The controller is configured to control the drive sub-circuit to perform a table learn operation on the table at least at a first rate during a learning period; and perform a table learn operation on the table at a second rate lower than the first rate after the learning period. The table learn operation includes receiving a first feedback signal from the load corresponding to a first cycle; obtaining a control code from the table according to the first feedback signal; generating a control signal according to the control code, where the drive sub-circuit performs an operation on the load according to the control signal during a second cycle; receiving a second feedback signal from the load corresponding to the second cycle; and updating the control code according to the first feedback signal and the second feedback signal and storing the updated control code back in the table in the memory.

[0008] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a schematic diagram of a drive circuit according to one embodiment of the present invention. [Diagram 2] 1 is a schematic diagram of an exemplary implementation of a bidirectional circuit including a capacitive load in accordance with an embodiment of the present invention; [Diagram 3] FIG. 2 is a schematic diagram of a detailed implementation of a PWM controller. [Figure 4] 1 is a flow chart of a process according to one embodiment of the present invention. [Diagram 5] FIG. 2 illustrates an exemplary LUT for recording a PWCC according to one embodiment of the present invention. [Figure 6] 4 is a flow chart of a table learning process according to one embodiment of the present invention. [Figure 7] 4 is a flow chart of a detailed table learning process according to one embodiment of the present invention. [Figure 8] 13A-13C show simulation results of the output voltage waveforms generated by a bidirectional circuit before and after a table learning process. [Figure 9] 1 is a flow chart of a process according to one embodiment of the present invention. [Figure 10] 1 is a flow chart of a process according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] U.S. Patents 11,290,015, 11,133,784, and 11,336,182 disclose an energy recycling amplifier including a DC-DC converter for driving a capacitive load, particularly a piezoelectric capacitive speaker load. The DC-DC converter is typically controlled by a pulse width modulated (PWM) signal. U.S. Patent 11,271,480 discloses a method for pre-calculating pulse width information associated with a PWM signal and storing this information in an addressable table memory as a pulse width control code (PWCC).

[0011] The calculation of the control code may be affected by various factors including the variable characteristics of the piezoelectric speaker, the offset of the DC-DC converter, the variation of the battery voltage level, and the manufacturing mismatch of the associated drive circuit. For example, the inductance of the inductor used in the DC-DC converter usually has a tolerance error, which results in the charge / discharge operation of the DC-DC converter being inconsistent. The permittivity / capacitance of the piezoelectric speaker varies with the applied voltage. Furthermore, the permittivity curve with respect to the supply voltage of all piezoelectric speakers may not be exactly the same, and / or the circuit elements of the energy reuse amplifier and its drive circuit usually have a manufacturing mismatch. These errors and mismatches result in the voltage increments and decrements generated by the control code being inaccurate in the charge (discharge) operation. The inaccuracy of the charge (discharge) operation performed on the piezoelectric speaker may increase / introduce distortion and errors in the output signal, degrading the sound quality.

[0012] The present invention provides (at least) a table learning method, which can adaptively adjust the pulse width control code and can adapt to devices with various parameters. Before describing the table learning in detail, we first introduce the driving circuit that realizes the table learning algorithm.

[0013] In the present invention, the term "coupled to" may refer to a direct or indirect connection. "Component A is coupled to component B" may indicate that component A is directly connected to component B, or that component A is connected to component B via some component C.

[0014] 1 is a schematic diagram of a driver circuit 10 according to one embodiment of the present invention. The driver circuit 10 includes a pulse-width modulation (PWM) controller 110 and a bidirectional circuit 120. The bidirectional circuit 120 is coupled between a voltage source (also called a power source such as a battery) 11 and a capacitive load CL, and is configured to drive the capacitive load CL. In one embodiment, the capacitive load CL may include a piezoelectrically actuated speaker (hereinafter abbreviated as piezoelectric speaker) that generates sound when driven by the driver circuit 10. The bidirectional circuit 120 receives a power supply voltage V from the voltage source 11. DD and can supply a current to or drain a current from a capacitive load CL. TOG represents the voltage at the output terminal of the bidirectional circuit 120. In one embodiment, the drive circuit 10 may be an energy reuse amplifier and the bidirectional circuit 120 may be a DC-DC converter with energy reuse capabilities. Details of DC-DC converters utilized as drive circuits with energy reuse capabilities are taught in U.S. Patent Nos. 11,271,480 and 11,336,182 and will not be described here for the sake of brevity.

[0015] In one embodiment, the load CL here may be a capacitive speaker load, for example a piezoelectrically actuated speaker. The driving circuit 10 may receive an input signal IN generated according to an original audio signal within an audible range (for example, between 16.5 Hz and 22 KHz). The driving circuit drives the capacitive speaker load according to the input signal IN, such that the output of the capacitive speaker load is substantially proportional to the input signal IN. In the present application, the signal a being substantially proportional to the signal b means that ||a(t)-c·b(t)|| 2<=ε, where ||s(t)|| 2 may represent the energy of any signal s(t), a(t) and b(t) represent time-varying functions of signals a and b, respectively, c represents a constant that can be either positive or negative, and ε represents a small positive number, e.g., 10 -1 , 10 -2 , 10 -3 etc.

[0016] The bidirectional circuit 120 includes an inductor L1 and four switches T1-T4. The switch T1 is coupled between a first terminal of the inductor L1 and a voltage source 11. The switch T2 is coupled between a first terminal of the inductor L1 and a ground terminal. The switch T3 is coupled between a second terminal of the inductor L1 and a capacitive load CL. The switch T4 is coupled between the second terminal of the inductor L1 and a ground terminal. The bidirectional circuit 120 can be operated by receiving PWM signals SP1-SP4 from the PWM controller 110, and the switches T1-T4 are controlled by the PWM signals SP1-SP4, respectively.

[0017] The PWM controller 110 can control the bidirectional circuit 120 to operate in a charging phase or a discharging phase. In the charging operation, the bidirectional circuit 120 can supply a charging current to charge the capacitive load CL. The charging phase includes an InFlux phase (i.e., a flux increase phase) and a DeFlux phase (i.e., a flux decrease phase). In the InFlux phase of the charging operation, the switches T1 and T4 are turned on, the switches T2 and T3 are turned off, and the InFlux current flowing from the voltage source 11 through the inductor L1 can form a magnetic field using the magnetic energy stored in the inductor L1. In the DeFlux phase of the charging operation following the InFlux phase, the switches T2 and T3 are turned on, the switches T1 and T4 are turned off, and the magnetic energy stored in the inductor L1 is converted into electrical energy and output to the capacitive load CL via a current flowing toward the capacitive load CL.

[0018] In a discharge operation, the bidirectional circuit 120 can form / drain a discharge current from the capacitive load CL, and the energy carried by the discharge current can be transferred to the voltage source 11 and reused by / through the battery or capacitor of the voltage source 11. The discharge phase can also include an InFlux phase and a DeFlux phase. In the InFlux phase of the discharge operation, the switches T2 and T3 are turned on and the switches T1 and T4 are turned off, and the discharge current flowing from the capacitive load CL through the inductor L1 can form a magnetic flux using the magnetic energy stored in the inductor L1. In the DeFlux phase of the discharge operation following the InFlux phase, the switches T1 and T4 are turned on and the switches T2 and T3 are turned off, and the magnetic energy stored in the inductor L1 is converted into electrical energy, which is output to the voltage source 11 via a current flowing toward the voltage source 11, and reused in the voltage source 11.

[0019] It should be noted that the InFlux current path and the DeFlux current path in the above paragraph are for illustration purposes. Those skilled in the art can make modifications or changes based on the actual situation. For example, in the InFlux stage of the discharge operation, the switches T1 and T3 can be turned on simultaneously while the switches T2 and T4 are off, and the InFlux current can flow directly from the load CL to the voltage source, which is especially effective when the load voltage V TOG is the power supply voltage V DD In this case, the InFlux current flowing through inductor L1 and the corresponding power dissipated in inductor L1 are reduced.

[0020] The PWM controller 110 can receive a feedback signal FB from the capacitive load CL and also receive the input signal IN to determine the pulse width of the PWM signals SP1-SP4. In an audio application such as a high-fidelity amplifier where the capacitive load CL includes a piezoelectric speaker, the PWM controller 110 can output the PWM signals SP1-SP4 as gate control signals for the switches T1-T4 to control the charge / discharge operation of the bidirectional circuit 120 to minimize the difference between the feedback signal FB and the input signal IN. Thus, based on the difference between the feedback signal FB and the input signal IN, the PWM controller 110 can determine whether to charge or discharge the capacitive load CL, and can also determine the amount of charge transferred during the charge / discharge provided by the bidirectional circuit 120 in each operation cycle of the bidirectional circuit 120 so as to continuously minimize the difference between the feedback signal FB and the input signal IN. Within the period of the operation cycle, the charge or discharge operation is accomplished at least once by the bidirectional circuit 120. The detailed implementation and operation of bidirectional circuit 120 is disclosed in US Pat. No. 11,336,182 and is therefore omitted here for the sake of brevity.

[0021] 2 is a schematic diagram of an exemplary implementation of a bidirectional circuit 120 including a capacitive load CL, in accordance with one embodiment of the present invention. In this embodiment, the piezoelectric speaker is PZT The bidirectional circuit 120 is actuated by a thin film actuator (e.g., a material abbreviated as Lead Zirconate Titanate, PZT) represented by the formula: The bidirectional circuit 120 has a single-ended output, while the piezoelectric speaker PZT has a first terminal (e.g., a top electrode) and a second terminal (e.g., a bottom electrode). In the embodiment shown in FIG. 2, the bidirectional circuit 120 is coupled to the PZT actuator of the piezoelectric speaker via a Single-Ended-to-Differential converter 200 and a bias voltage generator 202.

[0022] The single-ended-to-differential converter 200 converts the voltage V TOG Based on the characteristics of the DC-DC converter, the bidirectional circuit 120 outputs the differential voltages VoP and VoN. TOG is unipolar and can be considered positive (power supply voltage V DD In other words, when the voltage V TOG may rise during the charge phase and fall during the discharge phase.

[0023] The Single-Ended-to-Differential converter 200 provides a switching / toggle mechanism to extend the voltage swing range to drive a piezoelectric speaker, denoted as PZT. In particular, the Single-Ended-to-Differential converter 200 includes two switches SW1 and SW2. The switch SW1 is configured to selectively couple a first terminal of the piezoelectric speaker PZT to an output terminal or node ND of the bidirectional circuit 120. The switch SW2 is configured to selectively couple a second terminal of the piezoelectric speaker PZT to an output terminal or node ND of the bidirectional circuit 120.

[0024] In the first period TT1, the switch SW1 is connected to the node P1, and the switch SW2 is connected to the node P2. Thus, the terminal V TOP is coupled to the output terminal of the bidirectional circuit 120, and the terminal V BOT is coupled to node ND. In this situation, the differential voltage VoP minus VoN is the voltage V TOG In the second period TT2, the switch SW1 is connected to the node N1, and the switch SW2 is connected to the node N2. Thus, the terminal V TOP is connected to node ND, and the terminal V of the piezoelectric speaker PZT BOT is coupled to the output terminal of the bidirectional circuit 120. In this situation, the differential voltage V TOP -VBOT =VoP-VoN is the -V TOG is equal to

[0025] In other words, the switches SW1 and SW2 may be controlled by a first control signal, such that the switches SW1 and SW2 are simultaneously switched to nodes P1 and P2, respectively, and / or the switches SW1 and SW2 are simultaneously switched to nodes N1 and N2, respectively.

[0026] Most currently available thin-film PZT materials only support unipolar operation. To utilize such unipolar thin-film PZT as an actuator for a piezoelectric speaker, a bias voltage generator 202 is optionally coupled between the Single-Ended-to-Differential converter 200 and the piezoelectric speaker to generate a bias voltage V BIAS where V BIAS Since ≒ max(VoN-VoP) (max indicates the maximum function), V TOP =VoP+V BIAS =>VoN=V BOT is guaranteed and the unipolar requirement is met.

[0027] In one embodiment, the piezoelectric speaker is driven by a driving voltage V PZT When the PZT actuator is driven by the driving voltage V PZT is the voltage V at the first terminal (top electrode) of the piezoelectric speaker PZT. TOP and the voltage V at the second terminal (bottom electrode) of the PZT actuator of the piezoelectric speaker. BOT This refers to the difference between the driving voltage V PZT The membrane is deformed by the applied voltage, generating a displacement, which in turn displaces / compresses the air and produces sound. The position of the membrane of a piezoelectric speaker changes depending on the applied V PZT When the membrane is horizontally oriented, the driving voltage V PZT As the driving voltage V PZTAs the driving voltage V decreases, the membrane gradually bends downward. In other words, the vertical displacement of the membrane decreases with increasing driving voltage V PZT and the membrane can be controlled by a driving voltage V PZT can be controlled to be in an intermediate position by varying

[0028] In an exemplary embodiment, the voltage V output by the bidirectional circuit 120 TOG can swing between 0V and +15V, so that the differential voltage VoP-VoN can swing between +15V and -15V (i.e., between 0V and +15V in the first period TT1 and between 0V and -15V in the second period TT2 as shown and described in FIG. 2). In this situation, the bias voltage V BIAS can be designed to be equal to 15V, resulting in a drive voltage V for the piezoelectric speaker PZT. PZT can swing between 0V and 30V, which allows the piezoelectric speaker PZT to be driven by a unipolar driving voltage V PZT It is guaranteed that the driving voltage V PZT and the voltages VoP and VoN output by the Single-Ended-to-Differential converter 200 can be expressed as follows: V PZT =V TOP -V BOT =(VoP+V BIAS )-VoN

[0029] 2, the single-ended-to-differential converter 200 may further include a voltage shift circuit 204. The voltage shift circuit 204 is connected to a ground terminal or a shifted voltage V MV In normal operation, switch SW3 may be coupled to a ground terminal. However, when the voltage V TOG When the voltage V is close to ground, it becomes difficult for the discharge current to flow through / to the inductor L1, and therefore the efficiency / effectiveness of the bidirectional circuit 120 decreases. TOGWhen V is close to ground, the switch SW3 switches MV is switched to receive the voltage V TOG to / to a higher level. This increases the flux increasing capability of the inductor L1, promoting InFlux operation and allowing discharging to be performed more efficiently / effectively. In one embodiment, the shift voltage V MV V DD , may be equal to the source voltage supplied to the bidirectional circuit 120, i.e., V MV =V DD However, the shift voltage V MV may have other suitable values, DD Not limited to.

[0030] In other words, the voltage shift circuit 204 or the switch SW3 may be controlled by a second control signal, which is generated according to the input signal IN or the feedback signal FB. The voltage shift circuit 204 or the switch SW3 may shift the shift voltage V when the magnitude of the input signal IN or the feedback signal FB is less than a certain threshold. MV can be selectively applied to node ND.

[0031] 1 in conjunction with FIG. 2, the PWM controller 110 receives a feedback signal FB from a capacitive load CL, such as a piezoelectric speaker PZT. The feedback signal FB is a signal that represents a driving voltage V PZT should be appropriately reflected / represented, so that the PWM controller 110 can determine whether to charge or discharge the piezoelectric speaker PZT based on the relationship between the feedback signal FB and the input signal IN. In one embodiment, the feedback signal FB can be expressed as: FB=ADC{VoP-VoN}

[0032] In other words, the PWM controller 110 may receive the feedback signal FB after the differential voltage VoP-VoN is converted into digital form via an analog-to-digital converter, as shown by the ADC in FIG. 2.

[0033] As described above, the PWM controller 110 can output the PWM signals SP1-SP4 to control the bidirectional circuit 120, and the pulse widths of the PWM signals SP1-SP4 are determined based on the input signal IN and the feedback signal FB. In one embodiment, the PWM controller 110 can retrieve and / or update the pulse width control codes (PWCCs) used to generate the PWM signals SP1-SP4. The PWCCs may be pre-calculated or adjusted / re-calculated or adjusted according to the relationship between the input signal IN and the feedback signal FB, and these updated PWCCs may be stored in a PWCC look-up table in memory for future reference.

[0034] Specifically, based on the relationship between the input signal IN and the feedback signal FB, PZT Charge to C PZT The amount of charge discharged from and the corresponding control code, i.e., PWCC, required by the bidirectional circuit 120 to control the PWM pulse width may be adjusted or recalculated to perform such charge / discharge operation, and the corresponding entry in the PWCC lookup table may be updated accordingly. During the subsequent operation cycle, the PWM controller 110 may fetch such adjusted or recalculated PWCC from the PWCC lookup table according to the received input signal IN and feedback signal FB, and use this retrieved PWCC to control the pulse width of the PWM signals SP1-SP4.

[0035] 3 is a schematic diagram of one embodiment of the PWM controller 110. The PWM controller 110 includes a control circuit 302, a memory 304, a digital-to-analog converter (DAC) 306, a sawtooth signal generator (or waveform generator) 308, and a comparator 310. In this embodiment, the PWCCs are stored as one or more look-up tables (LUTs) in the memory 304. For example, the memory 304 may include a charge table / LUT 304_1 and a discharge table / LUT 304_2. The charge LUT 304_1 is configured to store the PWCCs used to generate the PWM signals SP1-SP4 for the charge operation. The discharge LUT 304_2 is configured to store the PWCCs used to generate the PWM signals SP1-SP4 for the discharge operation.

[0036] The control circuit 302 determines whether the bidirectional circuit 120 should operate in a charging operation or a discharging operation according to the input signal IN and the feedback signal FB. For example, if Δ=IN-FB, when Δ>Δmin, the charging operation is started and V PZT increases, and when Δ<-Δmin, the discharge operation starts and V PZT where Δmin is a threshold, typically a small positive value, determined by the system designer according to performance requirements. This allows the control circuit 302 to use IN, FB to determine whether to look up (obtain) PWCC from LUT304_1 or LUT304_2. Furthermore, the V obtained at the end of a cycle of the charge / discharge operation is PZT By checking |Δ|>Δmin against a target value, for example by checking whether |Δ|>Δmin, the control circuit 302 can perform the additional step of updating the PWCC stored in the LUT by the table learning process described in this invention.

[0037] The PWM controller 110 of FIG. 1 controls the generation of the PWM signals SP1-SP4 by looking up (retrieving) the PWCC from the appropriate LUT stored in the memory 304 of FIG. 3, which shows in detail how the PWM signals corresponding to the PWCCs are generated by the controller 320. The PWCCs stored in the memory 304 are in the form of a digital code. In addition to the pulse width (time) of each pulse, this digital code of the PWCC may contain data such as the number of PWM pulses to generate. In general, the PWCCs may refer to any information related to the generation and use of PWM pulses and are not limited by the embodiments disclosed in this invention. These PWCCs may be used to generate different input (digital) values ​​to the DAC 306 to generate different output (analog) voltage levels V A and controls the pulse width of SP1 to SP4. Voltage level V A is a sawtooth signal S generated by the sawtooth signal generator 308. saw (or a sawtooth signal with flat tops), comparator 310 determines whether the pulse width (time) is V A That is, the pulse width of the generated PWM signal such as SP1 to SP4 is determined by the output voltage level V of the DAC 306 generated according to the input value derived from the corresponding PWCC. A is determined by.

[0038] In one embodiment, the DAC 306 converts its digital input value to its analog output voltage level V A|Δ|, which means that the relationship between the pulse width (time) of the PWM signal and the digital pulse width information contained in the PWCC digital code is monotonic. In one embodiment, a larger PWCC digital code is used to generate a pulse with a longer / wider (time-wise) pulse width, and a smaller / narrower PWCC digital code is used to generate a pulse with a shorter (time-wise) pulse width. That is, the larger the PWCC, the longer / wider the pulse width. In this embodiment, the larger the difference between the input signal IN and the feedback signal FB (i.e., the larger |Δ|), the greater the C during the charge / discharge operation. PZT The more charge that needs to be added to or removed from C during a charge / discharge operation, the longer / wider the pulse width of the PWM signal must be, and the larger PWCC must be. Conversely, the smaller the difference between the input signal IN and the feedback signal FB (i.e., the smaller |Δ|), the more charge that must be added to or removed from C during a charge / discharge operation. PZT The amount of charge that needs to be added to or removed from PWM signal 1 becomes smaller, the pulse width of the PWM signal becomes shorter / narrower, and PWCC becomes smaller.

[0039] In another embodiment, the value of PWCC may be inversely proportional to the length / width of the PWM pulse to be generated. That is, a large PWCC is used to generate a short / narrow pulse and a small PWCC is used to generate a long / wide pulse. In such a situation, the larger the difference between the input signal IN and the feedback signal FB, the smaller the PWCC will be. Conversely, the smaller the difference between the input signal IN and the feedback signal FB, the larger the PWCC will be. This operation is also feasible if the relationship between the pulse width and the PWCC value is monotonic.

[0040] The detailed implementation and operation of the DAC 306 and associated PWM controller 110 are disclosed in US application Ser. No. 17 / 380,027 and are therefore omitted here for the sake of brevity.

[0041] It should be noted that the calculation of PWCC can be complex and thus expensive to perform in real time by the PWM controller 110. For example, V PZT To produce a change in PZT and its terminal V TOP and V BOT must be added or removed through the two terminals of the piezoelectric actuator, denoted as V PZT When the capacitance C changes PZT Therefore, the value of the applied voltage V shown in Figure 2 changes. PZT Over a continuous swing of capacitance C PZT also changes continuously, so that V PZT to produce a constant unit change in C PZT The amount of charge added to or removed from V PZT Another example is the V DD is the battery voltage, denoted as V DD affects the InFlux PWM pulse width during charging operation and the DeFlux PWM pulse width during discharging operation. V DD If V is supplied from a battery, DD V gradually decreases with operation. DD As a result of this change, the pulse widths of the above two types of PWM also drift with operation.

[0042] In any of the above situations, it may be desirable to use the LUT to adaptively update the information contained within the PWCC with results from a current cycle of charge / discharge operation, so that future operating cycles of the bidirectional circuit 120 can be based on the latest state of the dynamically changing operating conditions of the amplifier 10. Such adaptive updating of the PWCC stored in the LUT not only accounts for variations such as changes in the battery supply voltage, but also accounts for inaccurately calculated factory default PWCCs due to reasons such as part-to-part tolerances (e.g., inductor tolerances are typically ±10%, there is parameter drift due to operating temperature or humidity, etc.).

[0043] To achieve the above objective, i.e., by adaptively updating the PWCC in the LUT, V PZT To improve the accuracy of or minimize |Δ|, the present invention provides a method of table learning, in which the PWM controller 110 monitors the feedback signal FB to calculate the capacitance of the capacitive load CL (e.g., the C PZT ) reaches its intended value, which can determine whether to adjust / update the PWCC and store the updated PWCC value in memory 304.

[0044] 4 is a flow chart of a process 40 according to one embodiment of the present invention. The process 40 may be implemented in a PWM controller for controlling a bidirectional circuit to drive a capacitive load, the PWM controller being intended to control the bidirectional circuit to perform a charge or discharge operation on the capacitive load, thereby providing a feedback signal (which may be represented by a feedback signal FB) to the capacitive load C. PZT The voltage between the two terminals of approaches the input signal IN. As shown in FIG.

[0045] Step 402: Receive a first feedback signal FB1 from a load, and receive an input signal IN.

[0046] Step 404: Obtain the PWCC according to the first feedback signal FB1 and the input signal IN.

[0047] Step 406: Generate a plurality of PWM signals SP1 to SP4 according to the PWCC.

[0048] Step 408: The multiple PWM signals SP1 to SP4 are output to the bidirectional circuit 120.

[0049] Step 410: After the multiple PWM signals SP1 to SP4 are output, a second feedback signal FB2 is received from the load.

[0050] Step 412: Determine whether to adjust the PWCC according to the first feedback signal FB1 and the second feedback signal FB2.

[0051] In step 402, the PWM controller 110 receives a feedback signal FB1 that reflects the load voltage of the capacitive load at the end of the previous operating cycle (also called the first cycle), and receives an input signal IN corresponding to the current operating cycle.

[0052] According to the feedback signal FB1 corresponding to the previous operating cycle and the input signal IN corresponding to the current operating cycle, the PWM controller 110 can determine whether to perform a charging or discharging operation during the current operating cycle (also called the second cycle) according to the difference between the input signal IN and the feedback signal FB1, and further determine to perform a memory read operation from either the charging table 304_1 or the discharging table 304_2.

[0053] The details of determining whether the PWM controller 110 performs a charging or discharging operation are not limited. In one embodiment, when the input signal IN is greater than the feedback signal FB1 (for example, IN - FB1 > ε1, ε1 > 0), the PWM controller determines that the bidirectional circuit 120 performs a charging operation, and when the input signal IN is less than the feedback signal FB1 (for example, IN - FB1 < -ε2, ε2 > 0), the PWM controller can determine that the bidirectional circuit 120 performs a discharging operation. ε1 and ε2 may be the same or different. In addition to determining to perform a charging or discharging operation, in one embodiment, when -ε2 < IN - FB1 < ε1, the PWM controller can determine not to perform either charging or discharging during the current operating cycle, that is, when -ε2 < IN - FB1 < ε1, the mode of the cycle can be "idle".

[0054] Then, in step 404, the PWM controller 110 can obtain the PWCC according to the feedback signal FB1 and the input signal IN. The PWM controller fetches the PWCC from either the charging table 304_1 or the discharging table 304_2 stored in the memory 304 based on which operation to perform.

[0055] The LUT of the present invention, i.e., charge table 304_1 or discharge table 304_2, may be in the form of or include a two-dimensional (2D) array. Figure 5 illustrates a portion of an exemplary LUT according to one embodiment of the present invention. For simplicity, only the first seven columns and rows 29-36 of the LUT are shown in Figure 5.

[0056] The PWCC stored in a particular column is for generating a PWM signal to control the bidirectional circuit 120 to generate a specific intended voltage change to the capacitive load CL under different operating points. Assuming that the LUT shown in FIG. 5 represents a charging table, the PWCC stored in the nth column generates a PWM signal to perform a charging operation and applies n×ΔV to the capacitive load. U where ΔV U can be a unit of voltage change such as 0.73 mV. In other words, the PWCC in the first column performs a charging operation and applies 1×ΔV to the load CL. U The PWM signal for achieving an increment of 2×ΔV is generated for the load CL in the second row. U Similarly, assuming that the LUT shown in FIG. 5 represents a discharge table, the PWCC stored in the nth column performs a discharge operation and increases the n×ΔV of the load CL, and so on. U ΔV U The determination of is described in more detail below.

[0057] The PWCCs stored in the same column can be viewed as a collection of different PWM pulse widths to accommodate different operating points, which are the voltages applied across inductor L1 during InFlux operation (to convert electrical energy into magnetic energy in inductor L1) and during DeFlux operation (to convert the magnetic energy in inductor L1 back into electrical energy), a particular V PZT C at voltage levels PZT The value of V during the current cycle DD , V TOG , V MV The voltage level of the load CL may be determined by factors / variations such that the pulse widths of the PWM signals S1-S4 need to be optimized for each operating point in order to control the operation of the bidirectional circuit 120 to consistently generate the same intended voltage change across the load CL.

[0058] In essence, the LUT may be in the form of a 2D array, as shown in Figure 5. One dimension of the LUT (e.g., a column of the LUT) contains PWCCs that vary according to various factors of different operating points to achieve a consistent voltage change across the load CL under the different operating points. The other dimension of the LUT (e.g., a particular row of the LUT) contains PWCCs that generate different magnitudes of voltage change across the load CL under a particular operating point, where the magnitude of the voltage change is n x ΔV. U The unit size can be an integer multiple of .

[0059] Capacitance C PZT is the applied voltage V PZT Since it changes with the applied voltage V PZT Since V can be represented by a feedback signal or approximated by an input signal, the PWCCs stored in one column of the LUT (to be understood as a first sub-array along the first dimension of the 2D array in the claims) can be used to calculate the load voltage V at different levels. PZTor corresponding to different levels of the input signal IN. Similarly, the PWCCs stored in one row of the LUT (understood as a second sub-array along the second dimension of the claimed 2D array) correspond to a particular level of the input signal IN or a particular level of the load voltage or feedback signal FB.

[0060] For this embodiment, each entry of the LUT can be fetched by referencing a 2D address (n1, n2) with indexes n1 and n2. Index n1 can indicate the current level of the input signal IN (or the feedback signal FB / FB1). Index n2 can indicate the voltage change expected to be reached in the current / next operating cycle, which corresponds to the difference value between the input signal IN and the feedback signal FB.

[0061] The expected / intended voltage change / difference can be quantized as an integer multiple of ΔV, meaning that ΔV can be considered as the step size of the charge or discharge operation (where ΔV and ΔV U are used interchangeably herein). That is, in one embodiment, the intended voltage difference across the capacitive load caused by a charge or discharge operation is an integer multiple of the step size ΔV. The value of ΔV may be determined in any suitable manner. In one embodiment, the load voltage V PZT In the scenario where V is represented as an N-bit digital signal, ΔV can be calculated as follows:

number

[0062] Here, V pp represents the peak-to-peak voltage of the capacitive load or the voltage range of the load voltage. In an exemplary embodiment, the peak-to-peak voltage V pp is equal to 30V, and V PZT If expressed as an 8-bit system, the delta voltage ΔV may be equal to:

number

[0063] In one embodiment, the index n2 may be obtained by first calculating the difference between the input signal IN and the feedback signal FB1, and then obtaining / extracting a useful integer as the index n2 according to the previously calculated difference.

[0064] In one embodiment, the difference between the input signal IN and the feedback signal FB1 can be mathematically expressed as: Diff k =abs(IN k )-abs(FB k-1 ) (Formula 2) Here, Diff k is the difference value corresponding to the operating cycle k, abs() is the absolute value acquisition operation that outputs the absolute value or magnitude, and the indexes k and k-1 are time cycle indexes that refer to the current operating cycle and the previous operating cycle, respectively. Here, FB k-1 represents FB1 corresponding to the previous operating cycle described above. In Equation 2, the presence of the absolute value operation is due to the capacitive load CL / C PZT How much charge is stored in the load voltage V PZT The purpose of the present invention is to properly evaluate the IN (regardless of the polarity of IN) so that a proper decision can be made as to whether to perform a charge or discharge operation. k and F.B. k-1 We can see the effect of the polarity of IN k and F.B. k-1 The effect of the polarity of the input signal IN / IN is added via toggle switches SW1 and SW2 of the Single-Ended-to-Differential converter 200 shown in FIG. k and feedback signal FB1 / FB k-1 Since both are digital, the difference Diff / Diff k is also digital.

[0065] Difference value Diff kAfter calculating n, in one embodiment, an index n2 may be further calculated, which may be mathematically expressed as:

number

[0066] In FIG. 3a, B_diff is the difference value Diff / Diff, assuming that the difference value Diff is a digital signal of B_diff-bit. k Additionally, the step size in the second dimension of the LUT, denoted as ΔV or STP2, is ΔV=V pp / 2 B2 =STP2, where B2 is related to the charge / discharge resolution provided by the LUT. In other words, the index n2 is the difference value Diff / Diff k In an exemplary embodiment, the difference value Diff / Diff k is a 24-bit signal (B_diff=24), and the LUT calculates ΔV as ΔV=STP2=V pp / 2 12 By adopting the above-mentioned method, a 12-bit resolution (B2=12) can be achieved. Thus, the index n2 can be calculated by taking the most significant 12 bits of abs(Diff) (12=B_diff-B2). Here, the notations ΔV and STP2 are used interchangeably, and the notations N and B2 are also used interchangeably.

[0067] In another embodiment, another equation for index n2 can be expressed as follows:

number

[0068] 5 shows an excerpt of a LUT that records PWCCs corresponding to several values ​​of indexes n1 and n2, where index n1 is a row index and index n2 is a column index. According to the difference value between the input signal IN and the feedback signal FB, the PWM controller 110 can determine the index n2 and determine the number of delta voltages ΔV to be achieved in this operation cycle, for example, 1×ΔV, 2×ΔV, 7×ΔV, to obtain a PWCC from a selected column.

[0069] In addition, Diff / Diff k Note that the detailed arithmetic operation for obtaining / extracting a useful integer as index n2 according to n2 and Diff is not limited. k can be expressed by Formula 3a and Formula 3b, the requirements of the present invention are met and it is within the scope of the present invention.

[0070] Meanwhile, the index n1 can indicate the current level of the input signal IN or the feedback signal FB. Thus, according to the received input signal IN or feedback signal FB, the PWM controller 110 can determine the index n1 and fetch the PWCC from the selected row. As mentioned above, the feedback signal FB can be used to determine the voltage V of the piezoelectric speaker PZT. PZT may be generated from the differential voltage VoP-VoN of the Single-Ended-to-Differential converter 200, which corresponds to: In a preferred embodiment, the input signal IN is applied to determine the index n1, which can improve the stability of the energy reuse system. Note that the feedback signal FB can eventually approach the input signal IN. Thus, applying the input signal IN to determine the index n1 can also achieve the same result.

[0071] In one embodiment, the index n1 can be expressed as:

number

[0072] Value 2 (B1-1) Note that +1 is optionally included in the calculation of index n1. In an embodiment where the input signal IN is already biased to always be positive, the value 2 (B1-1) The +1 is not necessary, and the index n1 can be expressed as follows:

number

[0073] Another expression for index n1 can be expressed as follows:

number

[0074] Similarly, the detailed arithmetic operation of obtaining / extracting a useful integer as index n1 according to the input signal IN is not limited. As long as the relationship between n1 and IN can be expressed by either Equation 4a or Equation 4b, the requirements of the present invention are met and it is within the scope of the present invention.

[0075] Based on the indexes n1 and n2 obtained according to the feedback signal FB1 and the input signal IN, the PWM controller can fetch the PWCC accordingly.

[0076] In steps 406 and 408, the PWM controller generates the PWM signals SP1 to SP4 according to the fetched PWCC, and outputs the generated PWM signals SP1 to SP4 to the bidirectional circuit 120.

[0077] Next, the bidirectional circuit 120 performs a charging operation or a discharging operation in accordance with the PWM signals SP1 to SP4 generated in step 408.

[0078] In step 410, after the charging or discharging operation by the PWM signals SP1-SP4 is completed (or at the end of the current operating cycle), the PWM controller 110 can further receive a feedback signal FB2, which corresponds to the current operating cycle.

[0079] In one embodiment, the feedback signal FB1 / FB k-1 is the load voltage V at the end of the previous operating cycle (e.g., operating cycle k-1). PZT (V BIAS During the current operation cycle, the bidirectional circuit performs a charge or discharge operation based on the PWCC obtained according to the feedback signal FB1, and the load voltage V PZT At the end of the current operating cycle (say, operating cycle k), the load voltage V PZT is the feedback signal FB2 / FB k As (V BIAS can be observed regardless of

[0080] For details of steps 402-410, reference may be further made to US Pat. No. 11,271,480, and will not be described here for the sake of brevity.

[0081] In step 412, the PWM controller 110 can determine whether or how to adjust the PWCC according to the feedback signals FB1 and FB2. After receiving the feedback signal FB2, the controller 110 can further determine the actual voltage difference. If the actual voltage difference is not equal to or significantly deviates from the intended voltage difference, it may be necessary to adjust the PWCC according to the feedback signals FB1 and FB2. Once the PWCC is updated, the updated PWCC is written back (i.e., saved) to the address (n1, n2) of the LUT in the memory from which the original PWCC was fetched in step 404.

[0082] 6 is a flow chart of a table learning process 60 according to one embodiment of the present invention. The table learning process 60 may be implemented in a PWM controller such as 110 and may be considered as a detail of step 412. As shown in FIG. 6, the table learning process 60 includes the following steps:

[0083] Step 600: Intended voltage difference dV intend Get the.

[0084] Step 602: Actual voltage difference dV actual Calculate.

[0085] Step 604: Intended voltage difference dV intend and the actual voltage difference dV actual Calculate the mismatch MM between

[0086] Step 606: Determine whether or how to adjust the PWCC according to the mismatch MM.

[0087] Step 608: Increase the PWCC.

[0088] Step 610: Decrease the PWCC.

[0089] In step 600, the PWM controller 110 obtains the intended voltage difference dV intend The intended voltage difference dV intend is the load voltage V expected to be generated by a charge or discharge operation using the PWCC during the current operating cycle. PZT is the intended voltage change relative to

[0090] In one embodiment, the intended voltage difference dV intend When performing a charge operation, it can be obtained as n2 × ΔV, and when performing a discharge operation, it can be obtained as (-1) × n2 × ΔV. The intended voltage difference dV intend can be regarded as the target voltage change expected to be achieved via charging or discharging operation during the current operating cycle according to the PWCC obtained in step 404.

[0091] After receiving the feedback signal FB2 of the current operating cycle, in step 602, the PWM controller 110 calculates an actual voltage difference dV as the difference between the feedback signal FB2 of the current operating cycle and the feedback signal FB1 of the previous operating cycle. actual , for example dV actual =FB2-FB1. Actual voltage difference dV actual is the load voltage V that is actually generated by the charging or discharging operation using the PWCC during the current operating cycle. PZT Reflects the actual voltage change relative to

[0092] Intended voltage difference dV intend and the actual voltage difference dV actualBy comparing the intended voltage difference dV, it can be determined whether or how accurate the PWCC is. In step 604, the PWM controller 110 compares the intended voltage difference dV intend and the actual voltage difference dV actual In one embodiment, the PWM controller may calculate the mismatch MM as follows: MM=dV actual -dV intend Here, in this embodiment, the mismatch MM is the actual voltage difference dV actual to the intended voltage difference dV intend is equal to minus .

[0093] In step 606, the PWM controller 110 thereby determines whether or how to adjust the PWCC according to the mismatch MM. If the mismatch MM indicates that the charging or discharging operation performed by the bidirectional circuit is insufficient, the PWM controller may increase the PWCC (step 608) and store the increased PWCC back in the memory 304. On the other hand, if the mismatch MM indicates that the charging or discharging operation performed by the bidirectional circuit is excessive, the PWM controller 110 may decrease the PWCC (step 610) and store the decreased PWCC back in the memory 304. Otherwise, if the mismatch MM indicates that the charging or discharging operation performed by the bidirectional circuit is neither insufficient nor excessive, the PWM controller may decide not to adjust / update the PWCC.

[0094] The details of determining whether the charge or discharge operation is insufficient or excessive according to the mismatch MM in step 606 are not limited. For example, dV intend >0 and dV actualAssuming that a charging operation is being performed with MM<0 or MM<-TH2 (when TH2>0), the PWM controller 110 can determine that the charging operation is insufficient when MM>0 or MM>TH1 (when TH1>0), and can determine that the charging operation is excessive when MM>0 or MM>TH1 (when TH1>0). intend and dV actual can be interpreted as the intended voltage increment and the actual voltage increment under the charging operation / environment, respectively (the voltage increment represents the amount of voltage increment).

[0095] On the other hand, dV intend <0 and dV actual Assuming that a discharge operation is being performed, meaning MM>0 or MM>TH3 (if TH3>0), the PWM controller 110 can determine that the discharge operation is insufficient, and that the charge operation is excessive if MM<0 or MM<-TH4 (if TH4>0). intend / dV actual Since it becomes negative, the voltage decrement (voltage decrement represents the amount of voltage decrement / drop) during discharge operation is (-1) × dV intend and (-1) × dV actual Thus, (-1) × dV intend and (-1) × dV actual can be interpreted as the intended and actual voltage decrements under a discharging operation / environment, respectively.

[0096] It should be noted that the threshold values ​​for determining whether the charging (discharging) operation is insufficient or excessive, for example TH1 to TH4, can be selected according to the actual situation and are not limited to specific values.

[0097] The table learning operation accompanying the above driving operation can be regarded as a feedback control mechanism, and can be further detailed as a detailed table learning process 70, as shown in Fig. 7 (subscript k in Fig. 7 represents the motion cycle index). The detailed table learning process 70 includes the following steps:

[0098] Step 700: Input signal IN k and feedback signal FB k-1 Receive.

[0099] Step 702: The LUT indices n1 and n2 are obtained.

[0100] Step 704: Input signal IN k and feedback signal FB k-1 Difference value Diff k If the difference value Diff is greater than 0, the process proceeds to step 710. If the difference value Diff is less than 0, the process proceeds to step 720.

[0101] Step 710: Fetch the PWCC from the charging table 304_1 according to the address (n1, n2).

[0102] Step 711: Obtain a PWM signal according to the PWCC.

[0103] Step 712: Execute a charging operation and generate a feedback signal FB k Receive.

[0104] Step 713: Actual voltage difference dV actual and the intended voltage difference dV intend Get the.

[0105] Step 714: Actual voltage difference dV actual and the intended voltage difference dV intend Calculate the mismatch MM between

[0106] Step 715: Compare the mismatch MM with the thresholds TH1 and -TH2. If the mismatch MM is less than the threshold -TH2, then proceed to step 716. If the mismatch MM is greater than the threshold TH1, then proceed to step 717.

[0107] Step 716: PWCC is increased by one.

[0108] Step 717: PWCC is decreased by one.

[0109] Step 720: Fetch the PWCC from the discharge table 304_2 according to the address (n1, n2).

[0110] Step 721: Obtain a PWM signal according to the PWCC.

[0111] Step 722: Execute the discharge operation and output the feedback signal FB k Receive.

[0112] Step 723: Actual voltage difference dV actual and the intended voltage difference dV intend Get the.

[0113] Step 724: Actual voltage difference dV actual and the intended voltage difference dV intend Calculate the mismatch MM between

[0114] Step 725: Compare the mismatch MM with thresholds TH3 and -TH4. If the mismatch MM is greater than the threshold TH3, then proceed to step 726. If the mismatch MM is less than the threshold -TH4, then proceed to step 727.

[0115] Step 726: PWCC is increased by one.

[0116] Step 727: PWCC is decreased by one.

[0117] Step 750: Enter the next operating cycle and return to step 700.

[0118] According to the detailed table learning process 70, the PWM controller 110 can determine whether to charge or discharge according to whether the difference value Diff is a positive value or a negative value, and fetch the PWCC in the charge table 304_1 or the discharge table 304_2 accordingly. In the table learning operation, the PWCC can be increased or decreased according to the comparison with the threshold value under the charge or discharge operation. For example, in the charging phase, the actual voltage difference dV actual and the intended voltage difference dV intend can be a positive value. Thus, a larger mismatch MM indicates overcharging, and a smaller mismatch MM indicates undercharging. The mismatch MM is compared to thresholds TH1 and -TH2. Thus, if the mismatch MM is less than the threshold -TH2, which can be a negative value or 0, it is determined that the charging is insufficient and the PWCC needs to be increased by 1. If the mismatch MM is greater than the threshold TH1, which can be a positive value or 0, it is determined that the charging is excessive and the PWCC needs to be decreased by 1. The values ​​of TH1 and TH2 can be the same or different.

[0119] On the other hand, during the discharge phase, the actual voltage difference dV actual and the intended voltage difference dV intend can be a negative value. Thus, a larger mismatch MM indicates insufficient discharge, and a smaller mismatch MM indicates excessive discharge. The mismatch MM is compared with thresholds TH3 and -TH4. Thus, if the mismatch MM is greater than the threshold TH3, which can be a positive value or 0, it is determined that the discharge is insufficient and the PWCC needs to be increased by 1. If the mismatch MM is less than the threshold -TH4, which can be a negative value or 0, it is determined that the discharge is excessive and the PWCC needs to be decreased by 1. The values ​​of TH3 and TH4 can be the same or different.

[0120] In other words, step 716 represents the PWCC being increased if the actual voltage increment is less than the intended voltage increment. Step 717 represents the PWCC being decreased if the actual voltage increment is greater than the intended voltage increment. Step 726 represents the PWCC being increased if the actual voltage decrement is less than the intended voltage decrement. Step 727 represents the PWCC being decreased if the actual voltage decrement is greater than the intended voltage decrement.

[0121] Also, in this embodiment, the PWCC is increased or decreased by 1 every operating cycle, but is not limited thereto. In another embodiment, the PWCC may be adjusted (increased or decreased) in any suitable manner, such as by a level determined based on the value of the mismatch MM. For example, the PWCC may be adjusted by more than 1 when the mismatch MM is much larger or much smaller than the corresponding threshold. As long as the PWCC is fetched from memory, updated, and written back to memory, the requirements of the present invention are met and it is within the scope of the present invention.

[0122] Additionally, the PWCC update operations illustrated in the detailed table learning process 70 may occur every operating cycle. Those skilled in the art should appreciate that the present invention is not so limited. For example, in one embodiment, the table learning operations may occur at any fixed or variable frequency, such as, for example, once every 3 or 5 operating cycles. In another embodiment, the table learning function may be enabled for a particular period of time and then disabled, and the enablement time may be predetermined.

[0123] It should also be noted that some steps of the detailed table learning process 70 are interchangeable. For example, the operation of determining the indexes n1 and n2 in step 702 and the operation of calculating the difference value Diff in step 704 may be swapped. That is, the difference value Diff may be calculated before determining the LUT indexes n1 and n2, or these two steps may be performed simultaneously. This does not affect the effect achieved by the detailed table learning process 70.

[0124] In another respect, PWCCs arranged as a 2D array as in Figure 5 show a functional example. Those skilled in the art can make modifications and variations accordingly. For example, PWCCs originally arranged as a 2D array can be stacked (or even rearranged) as a long 1D array and stored in a LUT in memory, and this is also intended to be within the scope of the present invention.

[0125] FIG. 8 shows the simulation results of the output voltage waveforms generated by the bidirectional circuit 120 before and after the table learning operation, showing the differential voltages VoP, VoN, and their subtraction VoP-VoN. In the simulation shown in FIG. 8, the input signal IN is a single-tone signal with a sine waveform. As shown on the left side of FIG. 8, before performing the table learning operation (or without table learning), the waveform is very distorted, rough and irregular, which may cause the audio signal to contain significant distortion. In contrast, after performing the table learning operation, the waveform becomes a smooth sine wave signal, as shown on the right side of FIG. 8. This means that the sound quality is significantly improved by applying the table learning operation.

[0126] Furthermore, the DAC in the PWM controller (using the circuit topology disclosed in U.S. Pat. No. 11,271,480) has some imperfections that actually destroy the monotonicity of the DAC. The table learning operation may be able to eliminate these imperfections as well.

[0127] The table learning method provided in the present invention can be implemented in any suitable manner. In the above embodiment, the table learning operation is implemented in the PWM controller 110 of the drive circuit 10, more specifically in the control circuit 302 of the PWM controller 110, which may be realized as an integrated circuit (IC). The table learning operation may therefore be implemented as an application specific integrated circuit (ASIC) included in the control circuit 302. In such a situation, the calculations for realizing the table learning may be implemented using comparators, adders, and / or subtractors of the IC. Alternatively or additionally, the table learning method may include a software algorithm implemented in a processing circuit such as a microprocessor, a microcontroller unit, etc., where the control circuit 302 of the PWM controller 110 may be considered as a component of the processing circuit.

[0128] In addition, in the above embodiment, the control circuit 302 may be a circuit that performs a table learning operation. In one embodiment, the control circuit 302 may be a digital circuit, and the input signal IN and the feedback signal FB processed by the control circuit 302 are digital signals.

[0129] U.S. Patent Application Nos. 18 / 048,852 and 18 / 177,765 disclosed a table learning algorithm that can adapt the PWCC, Pulse Width Control Code, to various observable and unobservable operating conditions. The operating conditions can be battery voltage (which can weaken over time), parameter variations / drift of electrical components (capacitance, inductance, resistance, etc.). It has been shown that the table learning algorithm implemented in an audio amplifier reduces THD (total harmonic distortion) and significantly improves sound quality.

[0130] As described above, the table learning operation involving memory writing and ADC reading can be executed for each operation cycle. The operation cycle in this specification may sometimes be referred to as an ADC cycle, which is the reciprocal of the ADC rate / frequency. The ADC cycle / rate / frequency is further described in detail in U.S. Patent Application No. 18 / 051,015, which is incorporated herein by reference. In the following description, or in the context of reducing the table learning frequency, the table learning operation may refer to one iteration that includes at least one ADC reading and one memory writing before steps 700 to 750 of process 70.

[0131] However, after the table has stabilized, it is not necessary to update the table / PWCC so frequently. This is because the drift of the battery voltage and circuit parameters changes slowly compared to the ADC frequency.

[0132] In this application, for the table to be stable / converged means that it is not necessary to update the table entries for a certain period. For example, when the mismatch MM is within the range of -TH2 < MM < TH1 or within the range of -TH4 < MM < TH3, it is not necessary to update the table entries. Furthermore, for the table to be stable also means that the table entries remain within a narrow range over a long period. For example, in the table learning operation, PWCC = PWCC + 1 is executed, then PWCC = PWCC - 1 is executed, then PWCC = PWCC + 1 is executed, then PWCC = PWCC - 1 is executed, and so on. In this case, the table can also be considered stable / converged.

[0133] In this regard, the power consumption can be reduced by decreasing the table learning frequency, which means that instead of performing L table / PWCC updates within L ADC cycles, only m table / PWCC updates are performed within L ADC cycles, where m < L. The m table / PWCC updates may be evenly or unevenly distributed over the L ADC cycles according to the actual requirements. By doing so, at least (L - m) memory write operations within the L ADC cycles are saved. Furthermore, in the case of a system where the (DC-DC) operation does not depend on the ADC results, (L - m) ADCs are further avoided.

[0134] For example, the learn-1-skip-k method may be adopted, which means that after performing one table learning operation in one operation cycle, the table learning operation can be skipped in the next / consecutive k operation cycles. Here (in the context of the following description or reducing the table learning frequency), k refers to the number of the next / consecutive skipped operation cycles after the table learning operation cycle in which the table learning operation is performed.

[0135] In one embodiment, the number k of skipped operation cycles may be a certain value or may be constant over a certain period. For example, k = 0 during the learning period (e.g., 5 minutes), and k = K after the learning period, where K is a constant such as 15, 60, etc., but not limited thereto. The learning period may refer to the time interval during which the table learning operation is frequently performed, e.g., performed for each operation cycle or at the rate of the ADC rate. The learning period may refer to the time interval during which the table has not converged to a stable state.

[0136] In one embodiment, the number k of operation cycles to be skipped may be adaptively determined, preferably after the table is stabilized. For example, k may be increased if the table error decreases, and / or k may be decreased if the table error increases. A list of predetermined k, for example, {7, 17, 35, 60}, may be prepared in advance. A larger or smaller k may be selected from the list if the table error decreases or increases, but is not limited thereto. The table error refers to an indication of whether to update (a part of the entries) of the table. For example, if the table error is large enough, (a part of the entries) of the table shall be updated. As an example, in the context of the driving circuit 10 (the bidirectional circuit 120 or the driving circuit constituting the bidirectional circuit 120 may be referred to as a class X amplifier), the table error may be |dV intend -dV actual or its statistics, where dV intend / dV actual is the voltage difference intended / actually achieved by the PWCC. In one embodiment, k may be a (pseudo)random number, preferably after the table has stabilized.

[0137] In one embodiment, k may be, but is not limited to, a (pseudo)random number or a (pseudo)random number selected from a list containing (pseudo)random numbers, e.g., {12, 19, 35, 68}, to resolve potential noise associated with the frequency of table learning events.

[0138] This is not limited to the use of a learn-1-skip-k scheme. For example, the system can operate in scenarios where learning periods are interspersed with non-learning or (table learning) skip periods. lrn The lengths of the learning periods, denoted as L skip The length of the non-learning or skip period, denoted as , may be determined / adapted, for example, according to a table error. The length of the skip period may increase / decrease in response to a decrease / increase in the table error.

[0139] Scenarios of skipping duty are simulated as 6%, 50%, and 75%, and the skipping duty is (L skip / (L skip +L lrn )), where L skip / L lrn indicates the skipping / learning period. The results show that the THD and idle noise performance (in rms) for skipping duty as 6%, 50%, and 75% are almost the same. This means that skipping more table learning operations has little detriment to the (THD and idle noise) performance.

[0140] Another experiment / simulation shows that V PZT The spectrum of the driver output is compared. The first case is during extensive learning (table learning operation every ADC cycle) after the table has stabilized. The second case is when no learning has been done at all (i.e. no table updates or memory writes) after the table has stabilized. PZT The data is collected for a certain period of time, e.g., 0.3 seconds (equivalent to 256,000 samples) after the table is stabilized, and the results show that in the first case, when the input signal level is -25 dBFS (FS stands for full scale), a SNDR (signal-to-noise ratio) of 69.56 dB can be achieved, while in the second case, when the input signal level is -25 dBFS, a SNDR of 69.44 dB can be achieved. This is because the k / L skip This means that the can be expanded / extended.

[0141] The operation of reducing the table learning frequency can be summarized as a process 90. The process 90 can be executed by a controller. As shown in FIG. 9, the process 90 includes the following steps:

[0142] Step 902: During a learning period, perform a table learning operation on the table at least at a first rate.

[0143] Step 904: After the learning period, perform a table learning operation on the table at a second rate lower than the first rate.

[0144] In one embodiment, the table in the process 90 can refer to, but is not limited to, the charge table 304_1 or the discharge table 304_2. In one embodiment, the first rate can refer to / correspond to, but is not limited to, the ADC rate. In one embodiment, the learning period can refer to, but is not limited to, the period during which the table is not stable / converged and the table learning operation is performed extensively (e.g., at least at the first rate). The first rate can be considered as the minimum rate at which the table learning operation is performed (during the learning period). In one embodiment, the controller can determine whether the table is stable and determine the learning period according to the result of whether the table is stable or not. In one embodiment, the controller performing the process 90 can be, but is not limited to, a PWM controller.

[0145] If the table learning operation is performed less frequently after the table has stabilized / converged (to reduce power consumption), the requirements of the present invention are met and this is within the scope of the present invention.

[0146] The table learning operation of step 902 may include the following steps (shown as process A0 in FIG. 10).

[0147] Step A02: Receive a first feedback signal from a load corresponding to a first cycle.

[0148] Step A04: Obtain a control code from a table according to the first feedback signal.

[0149] Step A06: Generate a control signal according to the control code, and the driving sub-circuit performs an operation on the load according to the control signal during the second cycle.

[0150] Step A08: Receive a second feedback signal from the load corresponding to a second cycle.

[0151] Step A10: Update the control code according to the first feedback signal and the second feedback signal, and store the updated control code back in the table in the memory.

[0152] In one embodiment of process A0, the control code may refer to / correspond to, but is not limited to, a PWCC. In one embodiment of step A06, the control signal may refer to, but is not limited to, a PWM signal. In one embodiment of step A06, the driving sub-circuit may be referred to, but is not limited to, a bidirectional circuit. In one embodiment of step A06, the operation may be referred to, but is not limited to, a charging operation or a discharging operation.

[0153] It should be noted that processes 90 and A0 may also be applied to the feedback control scheme disclosed in US Patent No. 18 / 177,765, and are within the scope of the present invention.

[0154] In summary, to save power consumption, especially the power consumed in the memory write operations of table learning, the table learning speed can be reduced.

[0155] Those skilled in the art will readily recognize that numerous modifications and variations of the apparatus and method may be made while retaining the teachings of this invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. 16. A method for application to a controller in a drive circuit, the drive circuit including a drive sub-circuit configured to perform an operation on a load, the method comprising: performing a table learn operation on the table at least at a first rate during a learning period; after the learning period, performing the table learning operation on the table at a second rate that is lower than the first rate; The table is stored in a memory in the controller; The step of performing the table learning operation includes: receiving a first feedback signal from the load corresponding to a first operating cycle; obtaining a control code from the table according to the first feedback signal; generating a control signal in accordance with the control code, the drive subcircuit performing an operation on the load in accordance with the control signal during a second operating cycle; receiving a second feedback signal from the load corresponding to the second operating cycle; updating the control code according to the first feedback signal and the second feedback signal, and storing the updated control code back in a table in the memory. method.

2. The step of performing the table learning operation at the second rate lower than the first rate includes: performing the table learning operation in a third operation cycle; skipping the table learn operation for a number of skipped operating cycles following the third operating cycle.

3. The method of claim 2 , wherein the number of the plurality of skipped operating cycles is constant over a period of time.

4. The method of claim 2 , wherein the number of the plurality of skipped operating cycles is randomly generated or selected from a list comprising random numbers.

5. increasing the number of skipped operating cycles when the table error decreases; or decreasing the number of the plurality of skipped operating cycles when the table error increases; The method of claim 2 , wherein the table error is determined according to the first feedback signal and the second feedback signal.

6. The method of claim 5 , wherein the number of said plurality of skipped operating cycles is selected from a predetermined list.

7. 2. The method of claim 1, wherein the first feedback signal is captured by an analog-to-digital converter coupled to the load, the analog-to-digital converter operating at an analog-to-digital conversion rate.

8. The method of claim 7 , wherein the first rate is an analog-to-digital conversion rate.

9. the control signal is a pulse width modulated (PWM) signal; The method of claim 1 , wherein the control code is a pulse width control code (PWCC) that determines a pulse width of the PWM signal.

10. the operation is a charging operation or a discharging operation, The method of claim 1 , wherein the load is a capacitive load.

11. The method of claim 1 , further comprising the step of determining whether the table is stable.

12. A drive circuit, the drive circuit comprising: a drive subcircuit coupled to a load; a controller including a memory in which the table is stored; The controller controls the drive subcircuit; performing table learning operations on the table at at least a first rate during a learning period; and performing the table learning operation on the table at a second rate after the learning period, the second rate being lower than the first rate; The performing of the table learning operation includes: receiving a first feedback signal from the load corresponding to a first operating cycle; obtaining a control code from the table according to the first feedback signal; generating control signals in accordance with the control code, the drive subcircuit performing operations on the load in accordance with the control signals during a second operating cycle; receiving a second feedback signal from the load corresponding to the second operating cycle; and updating the control code according to the first feedback signal and the second feedback signal, and storing the updated control code back in a table in the memory. Drive circuit.

13. The controller: performing the table learning operation in a third operation cycle; and 13. The drive circuit of claim 12, configured to perform: skipping the table learning operation for a number of skipped operating cycles following the third operating cycle.

14. 14. The drive circuit of claim 13, wherein the number of the plurality of skipped operating cycles is constant over a period of time.

15. The drive circuit of claim 13 , wherein the number of the plurality of skipped operating cycles is randomly generated or selected from a list comprising random numbers.

16. The controller: increasing the number of skipped operating cycles when the table error decreases; or decreasing the number of the plurality of skipped operating cycles when the table error increases; The drive circuit of claim 13 , wherein the table error is determined according to the first feedback signal and the second feedback signal.

17. The drive circuit of claim 16, wherein the number of the plurality of skipped operating cycles is selected from a predetermined list.

18. an analog-to-digital converter coupled to the load; the first feedback signal is captured by the analog-to-digital converter; 13. The drive circuit of claim 12, wherein the analog to digital converter operates at an analog to digital conversion rate.

19. 20. The drive circuit of claim 18, wherein the first rate is an analog-to-digital conversion rate.

20. the control signal is a pulse width modulated (PWM) signal; The drive circuit of claim 12, wherein the control code is a pulse width control code (PWCC) that determines a pulse width of the PWM signal.

21. the controller is a PWM controller; The PWM controller includes: a digital-to-analog converter (DAC) configured to convert the pulse width control code (PWCC) into an analog voltage; a waveform generator configured to generate a sawtooth or sawtooth-like signal; a comparator configured to compare the sawtooth signal or the sawtooth-like signal with the analog voltage and generate a comparison result as a PWM signal having a pulse width corresponding to the PWCC.

22. The drive subcircuit comprises: An inductor; a first switch coupled between a voltage source and a first terminal of the inductor; a second switch coupled to the first terminal of the inductor; a third switch coupled between the load and the second terminal of the inductor; a fourth switch coupled to the second terminal of the inductor; the operation is a charging operation or a discharging operation, During the charging operation, the drive subcircuit generates a first current flowing toward the load; The drive circuit of claim 12 , wherein during the discharge operation, the drive subcircuit forms a second current flowing from the load.

23. The driver circuit receives an input signal; The drive circuit of claim 12 , wherein the controller controls the drive sub-circuit such that an output of the load is substantially proportional to the input signal.

24. The driving circuit receives an input signal generated according to an original audio signal within an audible range; The driver circuit of claim 12 , wherein the load is a speaker load.

25. The drive circuit of claim 12 , wherein the controller is configured to perform the step of determining whether the table is stable.

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