Semiconductor Test Equipment

Abstract

To solve the problem in adjusting the temperature of a power semiconductor element to be tested and adjusting the position of terminal connection of the power semiconductor element.SOLUTION: A power semiconductor element is fixed by being held between heating / cooling plates of a device fixing and connecting device 610. To the heating / cooling plates, a circulation water pipe 135 is attached. To the circulation water pipe 135, circulation water for making the power semiconductor element have a predetermined temperature is supplied. A terminal of the power semiconductor element is connected to a connection structure 218, and test current is supplied through the connection structure 218. At one end of the connection structure 218, a terminal connection part to be connected to the connection terminal of the power semiconductor element is disposed. In the connection structure 218, a heat pipe is disposed. At a lower part of the connection structure 218, a cooling fan 229 is disposed.SELECTED DRAWING: Figure 69

Description

[Technical field]

[0001] The present invention relates to a semiconductor testing apparatus for performing power cycle tests on semiconductor elements such as SiC, IGBT, MOS-FET, GaN, and bipolar transistors, and a method for testing the semiconductor elements.

[0002] Provided is a semiconductor testing device and a semiconductor element testing method that can efficiently reproduce stress similar to a failure mode in the usage environment of a semiconductor element and can evaluate a power semiconductor element or the like with high reliability. [Background technology]

[0003] Power semiconductors are semiconductors that can handle high voltages and large currents. For example, HEVs / EVs, which are "advanced technologies" that combine inverters incorporating the latest power semiconductors with motors, are currently becoming more and more popular. In the future, this combination is expected to become the "core" and contribute to the electrification of various types of transportation equipment, including railways, ships, aircraft, and satellites.

[0004] Power semiconductors come in a wide variety of sizes and types, as they are used for everything from small amounts of power supply for CPUs and memory to large amounts of power supply to drive motors.

[0005] In order to further improve energy conversion efficiency, there is also progress in the development of new materials for wide-gap power semiconductors, such as SiC (silicon carbide) and GaN (gallium nitride).

[0006] Power semiconductors can handle a lot of power, so they generate a lot of heat and need to be cooled efficiently. Therefore, many items must be considered when it comes to mounting reliability.

[0007] The lifespan of a power semiconductor element includes a lifespan caused by thermal fatigue caused by heat generation in the power semiconductor element itself, a lifespan caused by thermal fatigue caused by temperature changes in the external environment of the power semiconductor element, and a lifespan caused by voltage fatigue caused by the voltage applied to the gate insulating film of the power semiconductor element.

[0008] Generally, life tests for power semiconductor elements are performed by repeatedly turning current on and off to the semiconductor element. For example, tests are performed by setting voltages and currents to the emitter terminal (source terminal) and collector terminal (drain terminal) of the transistor of the semiconductor element, and applying periodic on-off signals (operation / non-operation signals) to the gate terminal.

[0009] The current applied to the semiconductor element during testing is large, at several hundred amperes, and requires low-resistance wiring to avoid heat generation and voltage drop. Because the test current is large, the connection between the semiconductor element and the wiring must be made with low resistance.

[0010] Many of the semiconductor elements to be tested are connected in multiple stages, and when the semiconductor elements are transistors, the voltage between the channels varies greatly depending on the test conditions, etc. If the test signal applied to the semiconductor element is not appropriate, the semiconductor element may be destroyed by the test signal.

[0011] There are many types of semiconductor device tests, and it is necessary to change the wiring connections to correspond to the type of test. Changing the wiring connections takes a lot of time and can lead to poor connections and connection errors. The packages of power semiconductor elements are also becoming smaller, and as the packages become smaller, the areas of the connection parts of the terminals of the packages are also becoming smaller. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Patent Publication No. 2014-138488 Summary of the Invention [Problem to be solved by the invention]

[0013] In conventional semiconductor testing equipment, a test of a power semiconductor element (such as a transistor) is carried out by turning on and off the transistor 117 and passing a constant current Id through the channel of the transistor.

[0014] There are a wide variety of test items that can be performed using semiconductor device test equipment (power cycle test equipment), and it is necessary to change the setting conditions or test conditions to correspond to the test items.

[0015] A wide variety of reliability tests must be carried out on power semiconductors, but conventional semiconductor element testing equipment has the problem that it is not possible to carry out these tests efficiently.

[0016] There are a wide variety of test items that can be performed by a semiconductor test device (power cycle test device), and it is necessary to change the connection (wire connection) with the transistor 117 in accordance with the test items.

[0017] The constant current Id is often several hundred amperes or more, and it is necessary to use thick wires for the connection wiring 211 and power supply wiring 212 that pass the current. In addition, a large current Id flows through the semiconductor electrode terminal. If there is contact resistance between the connection electrode terminal of the semiconductor element and the connection wiring, the contact portion will generate heat, which may destroy the semiconductor element.

[0018] In recent years, power semiconductor elements have also been getting smaller in package size. As the packages of power semiconductor elements get smaller, the size of the connection electrodes of the power semiconductor elements has also become smaller.

[0019] When the connection terminals of the power semiconductor element become smaller, it becomes difficult to connect them to the connection wiring of the connection board. In addition, the connection resistance also increases. Because a large current flows through the power semiconductor element, if the connection resistance increases, the connection part will heat up and the power semiconductor element will burn out.

[0020] In a test device for power semiconductor elements, it is not possible to fix the elements by soldering, etc. In a test device for power semiconductor elements, it is necessary to make the power semiconductor elements to be tested detachable.

[0021] Changing the wiring connections of thick wires to accommodate test items takes a long time, and since it requires a working space for changing the wiring connections, there is a problem that the test equipment becomes large. [Means for solving the problem]

[0022] The semiconductor device testing apparatus of the present invention comprises a current switching section that energizes one device while the other device is in a power-off state, a plurality of power supply devices, a plurality of temperature measuring devices, and a noise control device. In the semiconductor device of the present invention, the cycle and time for turning on (operating) the semiconductor device can be set arbitrarily.

[0023] By changing or controlling any one of the cycle tc, on time ton, and off time toff of the power semiconductor element, the time and interval during which a predetermined current flows through the power semiconductor element is controlled.

[0024] When a current is applied to a power semiconductor element for an on-time ton1, the temperature of the power semiconductor element gradually rises. Temperature information of the power semiconductor element is acquired in real time and converted into temperature. When the power semiconductor element reaches the target temperature Ta, the time for turning on the power semiconductor element is changed to ton2, and the on-time of the power semiconductor element is controlled so that the temperature of the power semiconductor element remains at a constant value Ta.

[0025] The power semiconductor element 117 has electrode terminals 226 formed or disposed on a flat surface of the back surface and signal terminals 227 formed or disposed on a side surface. Alternatively, the electrode terminals 226 and the signal terminals 227 are formed or disposed on the flat surface of the back surface of the power semiconductor element 117. On the connection board 514, an electrode pattern 505 that connects to the electrode terminal 226 is formed, and an electrode pattern 506 that connects to the signal terminal 227 is formed. The power semiconductor element 117 is inserted into the sample hole 512 of the sample placement plate 511 with the electrode terminal 226 facing upward, and positioned.

[0026] Anisotropic conductive rubber 504 is disposed between signal terminal 227 and connection board 514. When connection board 514 is pressed, signal terminal 227 and electrode pattern 506 are electrically connected.

[0027] As described above, anisotropic conductive rubber 504 is sandwiched between electrode terminal 226 and signal terminal 227 of semiconductor element 117 and electrode pattern 506 and signal terminal 227 of connection board 514. Electrode pattern 506 and signal terminal 227 are electrically connected by anisotropic conductive rubber 504. Heat-resistant resist 523 is formed between electrode pattern 505 and electrode pattern 506. The electrode patterns are connected to connection portion 507, and a test current is applied to connection portion 507 to test semiconductor element 117. Effect of the Invention

[0028] The semiconductor element testing apparatus and semiconductor testing method of the present invention can display the device state in real time, accurately measure the temperature of the semiconductor device, and can stop the test before the semiconductor device is completely destroyed, and can measure the thermal resistance in real time and automatically measure the K-factor. In the semiconductor device testing apparatus of the present invention, the signal terminal 227 and the electrode pattern 506 are electrically connected by the anisotropic conductive rubber 504 when pressed.

[0029] The power semiconductor element 117 to be tested can be removed by removing the anisotropic conductive rubber 504. In addition, by matching the shape of the wiring pattern of the connection board 514 with that of the power semiconductor element 117 to be tested and by taking into consideration the wiring connection pattern, a wide variety of tests can be performed. [Brief description of the drawings]

[0030] [Figure 1]1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. [Diagram 2] 1A and 1B are a plan view and a cross-sectional view of a semiconductor element. [Diagram 3] 3A and 3B are an equivalent circuit diagram and an explanatory diagram of a connection board in the semiconductor testing device of the present invention; [Figure 4] 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. [Diagram 5] 1A and 1B are a plan view and a cross-sectional view of a semiconductor element. [Figure 6] 3A and 3B are an equivalent circuit diagram and an explanatory diagram of a connection board in the semiconductor testing device of the present invention; [Figure 7] 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. [Figure 8] 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. [Figure 9] FIG. 2 is an explanatory diagram of a sample placement plate in the semiconductor testing device of the present invention. [Figure 10] 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; [Figure 11] 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; [Figure 12] 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; [Figure 13] 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; [Figure 14] 4 is an explanatory diagram of a pressing plate in the semiconductor testing device of the present invention. [Figure 15] 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing apparatus according to the present invention; [Figure 16] 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing apparatus according to the present invention; [Figure 17] 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing apparatus according to the present invention; [Figure 18] 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing apparatus according to the present invention; [Figure 19] 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element. [Figure 20]FIG. 2 is an explanatory diagram of a sample placement plate in the semiconductor testing device of the present invention. [Figure 21] 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing apparatus according to the present invention; [Figure 22] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Diagram 23] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Figure 24] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Diagram 25] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Figure 26] 1 is an explanatory diagram of a mounting method of a semiconductor element in a semiconductor testing apparatus according to the present invention; [Figure 27] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Figure 28] 1A and 1B are an equivalent circuit diagram and a block diagram of a semiconductor testing device according to the present invention; [Figure 29] FIG. 1 is a configuration diagram of a semiconductor testing device according to the present invention. [Diagram 30] FIG. 1 is a configuration diagram of a semiconductor testing device according to the present invention. [Diagram 31] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Diagram 32] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Diagram 33] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Diagram 34] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Diagram 35] FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. [Diagram 36] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Figure 37] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Figure 38] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Figure 39] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Diagram 40] FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. [Diagram 41] FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. [Diagram 42] FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. [Diagram 43] FIG. 2 is an explanatory diagram of a heat pipe in the semiconductor testing device of the present invention. [Diagram 44] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Diagram 45] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Figure 46] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Figure 47] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Figure 48] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Figure 49] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Figure 50] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Figure 51] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Figure 52] 1 is an explanatory diagram of a method for testing a semiconductor element according to the present invention; [Figure 53] FIG. 2 is an explanatory diagram of a sample placement plate in the semiconductor testing device of the present invention. [Figure 54] 1 is an explanatory diagram of a connection board in a semiconductor testing device according to the present invention; [Figure 55] FIG. 2 is an explanatory diagram of a semiconductor element. [Figure 56] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Figure 57] FIG. 1 is an explanatory diagram of a semiconductor testing device according to the present invention. [Figure 58] FIG. 1 is an explanatory diagram of a semiconductor device testing device according to the present invention. [Figure 59] FIG. 1 is an explanatory diagram of a semiconductor device testing device according to the present invention. [Figure 60] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 61]1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 62] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 63] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 64] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 65] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 66] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 67] 1 is an explanatory diagram of a semiconductor device testing method according to the present invention; [Figure 68] 1 is a structural diagram of a semiconductor device testing device according to the present invention; [Figure 69] 1 is a structural diagram of a semiconductor device testing device according to the present invention; [Figure 70] 1 is a structural diagram of a semiconductor device testing device according to the present invention; [Figure 71] 1 is a structural diagram of a semiconductor device testing device according to the present invention; [Figure 72] 1 is a structural diagram of a semiconductor device testing device according to the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a power semiconductor testing apparatus for a power cycle test or the like and a method for testing a power semiconductor element according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0032] In the embodiments described in the specification, an IGBT is taken as an example of a power semiconductor device. The present invention is not limited to an IGBT, and can be applied to various power semiconductor devices such as SiC, MOSFET, JFET, and transistor.

[0033] The present invention is not limited to being applied to transistors, but can also be applied to two-terminal elements such as diodes, etc. Also, the present invention can be applied to other power semiconductor elements such as thyristors and triacs. The present invention is not limited to power semiconductor elements, but it goes without saying that the present invention can also be applied to low-power semiconductor elements and semiconductor elements for small-signal control.

[0034] The present invention applies a current or voltage to an element or component to perform testing. Therefore, the test objects are not limited to power semiconductor elements. It goes without saying that the present invention can also be applied to power resistors, thermistors, posistors, ZNR, phototransistors, photodiodes, Schottky diodes, high-speed diodes, speakers, motors, mechanical relays, and the like.

[0035] In each drawing for explaining the embodiment of the invention, elements having the same function are given the same reference numerals, and the description thereof may be omitted. In addition, the embodiments described in this specification can be combined with each other.

[0036] 1A and 1B are an explanatory diagram and an equivalent circuit diagram of a semiconductor element 117 to be tested. Fig. 1(a) is an explanatory diagram that shows a schematic diagram of a state in which the semiconductor element 117 to be tested is seen from the back side as an example. Fig. 1(b) is an equivalent circuit diagram of the semiconductor element.

[0037] 1(a), an SOP (Small Outline Package) is shown as an example of the shape of a semiconductor element, etc. Electrode terminals 226a and 226b are formed on the back surface of the SOP. In the SOP, signal terminals 227 are formed or arranged on the back surface (the surface on which the electrode terminals 226 are formed) and side surfaces of the package.

[0038] A transistor is illustrated as the semiconductor element 117. The transistor 117 has a P terminal (collector terminal of the transistor 117) to which a large current is applied, and an N terminal (emitter terminal of the transistor 117) to which a large current is applied.

[0039] A plating film 524 (not shown) is formed on the electrode terminal 226. The plating film 524 will be described as a Ni-P film, but a thin film may also be formed of Ni or Ni-B. The plating film 524 (not shown) may be made of any material as long as it can be bonded closely to the electrode pattern. Examples of the material include, other than nickel (Ni), tin, silver, gold, copper, lead, zinc, and alloys thereof.

[0040] The thickness of the plating film 524 (not shown) is preferably 1 μm or more and 20 μm or less. In particular, the thickness is preferably 2 μm or more and 6 μm or less. It is preferable to form a gold plating film 525 (not shown) on the plating film 524.

[0041] The plating film 524 formed on the electrode terminal 226 is made thicker than the plating film 524 formed on the terminal 227. Alternatively, the plating film 524 is formed on the electrode terminal 226, and the plating film 524 is not formed on the terminal 227. Alternatively, the plating film 524 formed on the signal terminal 227 is made thinner than the plating film 524 formed on the electrode terminal 226.

[0042] The total thickness of the plating film 524 (not shown) and the gold plating film 525 (not shown) is preferably 1 μm to 10 μm, and more preferably 2 μm to 6 μm.

[0043] It is preferable to form gold plating 525 (not shown) on the plating film 524. When the plating film 524 is not formed on the electrode terminals 226 or the signal terminals 227, it is preferable to form the gold plating film 525 on the electrode terminals 226 or the signal terminals 227.

[0044] The gold plating film 525 (not shown) has a thickness of 0.01 μm or more. The gold plating film 525 (not shown) has the function of preventing or suppressing oxidation or contamination of the surface of the plating film 524.

[0045] Fig. 2 is a cross-sectional view of the semiconductor element 117 in Fig. 1. Fig. 2(b) is a cross-sectional view taken along line AA' in Fig. 2(a). Fig. 2(c) is a cross-sectional view taken along line BB' in Fig. 2(a). Electrode terminals 226 are arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side of the package of the semiconductor element 117.

[0046] FIG. 3 is an explanatory diagram showing a connection state between the electrode terminals 226 of the semiconductor element 117 and the connection portion 507, and a connection state between the signal terminals 227 and the connection pins 502 of the connector 202. As shown in FIG.

[0047] Electrode terminal 226a and connection portion 507a are electrically connected by connection wiring 503. Electrode terminal 226b and connection portion 507b are electrically connected by connection wiring 503. Eight connection pins 502 are arranged within connector 202.

[0048] The connection pin 502a and the signal terminal 227d of the semiconductor element 117 are electrically connected by a signal wiring. The connection pin 502b and the signal terminal 227c of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502c and the signal terminal 227b of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502d and the signal terminal 227a of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502e and the signal terminal 227h of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502f and the signal terminal 227f of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502g and the signal terminal 227g of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502h and the signal terminal 227e of the semiconductor element 117 are electrically connected by a signal wiring 508.

[0049] 4A and 4B are an explanatory diagram and an equivalent circuit diagram of the semiconductor element 117 to be tested. Fig. 4A is an explanatory diagram that shows a schematic diagram of the semiconductor element 117 as viewed from the back side. Fig. 4B is an equivalent circuit diagram of the semiconductor element.

[0050] 4(a), a QFN (Quad Flat No leaded package) is shown as an example of the shape of a semiconductor element, etc. Electrode terminals 226a and 226b are formed on the back surface of the QFN. In the QFN, a signal terminal 227 is formed or placed on the back surface of the package (the surface on which the electrode terminal 226 is formed).

[0051] A transistor is illustrated as the semiconductor element 117. The transistor 117 has a P terminal (collector terminal of the transistor 117) to which a large current is applied, and an N terminal (emitter terminal of the transistor 117) to which a large current is applied.

[0052] A plating film 524 (not shown) is formed on the electrode terminal 226. The plating film 524 will be described as a Ni-P film, but a thin film may also be formed of Ni or Ni-B. The plating film 524 (not shown) may be made of any material as long as it can be bonded closely to the electrode pattern. Examples of the material include, other than nickel (Ni), tin, silver, gold, copper, lead, zinc, and alloys thereof.

[0053] The thickness of the plating film 524 (not shown) is preferably 1 μm or more and 20 μm or less. In particular, the thickness is preferably 2 μm or more and 6 μm or less. It is preferable to form a gold plating film 525 (not shown) on the plating film 524.

[0054] The plating film 524 formed on the electrode terminal 226 is made thicker than the plating film 524 formed on the signal terminal 227. Alternatively, the plating film 524 is formed on the electrode terminal 226, and the plating film 524 is not formed on the signal terminal 227. Alternatively, the plating film 524 formed on the signal terminal 227 is made thinner than the plating film 524 formed on the electrode terminal 226.

[0055] The total thickness of plating film 524 (not shown) and gold plating film 525 (not shown) is preferably 1 μm to 10 μm, and more preferably 2 μm to 6 μm.

[0056] In either the SOP or QFN package shape, it is also preferable to make the electrode terminals 226 higher (thicker) than the signal terminals 227. For example, the electrode terminals 226 may be made higher than the signal terminals 227 by about 10 μm to 0.5 mm.

[0057] 1 etc., it is preferable to form gold plating 525 (not shown) on plating film 524. When plating film 524 is not formed on electrode terminal 226 or signal terminal 227, it is preferable to form gold plating film 525 on electrode terminal 226 or signal terminal 227.

[0058] 1, the thickness of the gold plating film 525 (not shown) is set to 0.01 μm or more. The gold plating film 525 (not shown) has the function of preventing or suppressing oxidation or contamination of the surface of the plating film 524.

[0059] Fig. 5 is a cross-sectional view of the semiconductor element 117 in Fig. 4. Fig. 4(b) is a cross-sectional view taken along line AA' in Fig. 4(a). Fig. 4(c) is a cross-sectional view taken along line BB' in Fig. 4(a). Electrode terminals 226 are arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side of the package of the semiconductor element 117.

[0060] In the example of Fig. 4, two transistors 117 (transistor 117m, transistor 117s) are disposed or formed in a QFN as shown in Fig. 4(b). As shown in Fig. 4(a), an electrode terminal 226a of the P terminal of transistor 117s, an electrode terminal 226a of the P terminal of transistor 117s, an electrode terminal 226c of the O terminal of transistor 117m, and an electrode terminal 226b of the N terminal of transistor 117m are formed or disposed on the back surface of the QFN.

[0061] The transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em, while the transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es.

[0062] In the example of Fig. 4, a diode Ds for measuring temperature is formed in the semiconductor element (transistor) 117s. The diode Ds is formed in the same process as the transistor 117. The diode Ds is used to measure temperature information Tj of the transistor 117s. The diode Ds is connected to an anode terminal as and a cathode terminal ks. The anode terminal as is a signal terminal 227a, and the cathode terminal km is a signal terminal 227b.

[0063] A diode Dm for measuring temperature is formed in the semiconductor element (transistor) 117m. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure temperature information Tj of the transistor 117m. The diode Dm is connected to an anode terminal am and a cathode terminal km. The anode terminal am is a signal terminal 227e, and the cathode terminal km is a signal terminal 227g.

[0064] The transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em. A signal Vgs for turning on and off the transistor 117 is applied to the gate terminal gm. A constant current Icm is applied to the anode terminal am and the cathode terminal km from the constant current circuit 118 to the diode Dm.

[0065] The transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es. The gate terminal gs is shorted to the emitter terminal es, and a test of the semiconductor element is performed in a diode-connected state.

[0066] Fig. 5 is a cross-sectional view of the semiconductor element 117 in Fig. 4. Fig. 5(b) is a cross-sectional view taken along line AA' in Fig. 4(a). Fig. 5(c) is a cross-sectional view taken along line BB' in Fig. 4(a). Electrode terminals 226 are arranged on the surface of the package of the semiconductor element 117, and signal line terminals are arranged on the side of the package of the semiconductor element 117.

[0067] FIG. 6 is an explanatory diagram showing a connection state between the electrode terminals 226 of the semiconductor element 117 and the connection portion 507, and a connection state between the signal terminals 227 and the connection pins 502 of the connector 202. As shown in FIG.

[0068] The electrode terminal 226a and the connection portion 507a are electrically connected by a connection wiring 503. The electrode terminal 226b and the connection portion 507b are electrically connected by a connection wiring 503. The electrode terminal 226c and the connection portion 507c are electrically connected by a connection wiring 503.

[0069] Eight connection pins 502 are arranged in the connector 202, and the connection pin 502a and the signal terminal 227d of the semiconductor element 117 are electrically connected by a signal wiring. The connection pin 502b and the signal terminal 227c of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502c and the signal terminal 227b of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502d and the signal terminal 227a of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502e and the signal terminal 227h of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502f and the signal terminal 227f of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502g and the signal terminal 227g of the semiconductor element 117 are electrically connected by a signal wiring 508. The connection pin 502 h and the signal terminal 227 e of the semiconductor element 117 are electrically connected by a signal wiring 508 .

[0070] In the embodiment of the present invention, the shape of the semiconductor element is exemplified by SOP and QFN, but is not limited thereto. Any shape may be used as long as the electrode terminal 226 and the signal terminal 227 can be connected to the electrode pattern 505 and the electrode pattern 506 of the connection board 514 using a substantially flat connecting portion such as the anisotropic conductive rubber 504. For example, it goes without saying that the shape may be BGA (Ball Grid Array), COG (Chip On Glass), flip chip bonding IC, pin grid array, etc.

[0071] The anisotropic conductive rubber 504 may be replaced with an anisotropic conductive paste, an anisotropic conductive adhesive, a conductive paste, an anisotropic conductive film, a conductive bonding material, etc. It goes without saying that the above items are also applicable to the other embodiments.

[0072] The P terminal is connected to electrode terminal 226a. The N terminal is connected to electrode terminal 226b. The electrode terminal 226 is formed in a flat shape on the back surface of the SOP or QFN. A nickel (Ni) plating film is formed on the surface of the electrode terminal 226 as required. The electrode terminal 226 is electrically connected to the electrode pattern 505 of the connection board 514 via the anisotropic conductive rubber 504 .

[0073] 1, a diode Dm for measuring temperature is formed in the semiconductor element (transistor) 117. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure temperature information Tj of the transistor 117.

[0074] The diode Dm is connected to an anode terminal am and a cathode terminal km, the anode terminal am being a signal terminal 227e, and the cathode terminal km being a signal terminal 227g.

[0075] In addition, the collector terminal cm of the transistor 117 is connected to a signal terminal 227d, and the emitter terminal em of the transistor 117 is connected to a signal terminal 227h. The gate terminal gm of the transistor 117 is connected to a signal terminal 227f. The signal terminal 227 is formed or disposed on the side of the SOP. In addition, the back surface of the SOP is configured to be electrically connected to the electrode pattern 506 of the connection board 514.

[0076] Eight signal terminals 227 are arranged on the side of the SOP in the example of Fig. 1, and on the back surface of the QFN in the example of Fig. 4. The signal terminals 227 are electrically connected to the electrode pattern 506 of the connection board 514 via the anisotropic conductive rubber 504. The signal terminals 227, the electrode terminals 226, and the electrode patterns 505 and 506 of the connection board 514 are simultaneously electrically connected by one piece of anisotropic conductive rubber 504. Alternatively, only the signal terminals 227 and the electrode pattern 506 are electrically connected via the anisotropic conductive rubber 504.

[0077] An example of the anisotropic conductive rubber 504 is a low-load compression type in which gold-plated metal wires are arranged at a narrow pitch on silicone rubber. The wire diameter of the metal wire is 0.02 mm or more and 0.04 mm or less. The thickness is 0.2 mm or more and 2 mm or less. The metal wire may be made of gold or a gold alloy. The gold-plated metal wire is preferably of a non-magnetic type, which allows the semiconductor element 117 to be tested and evaluated at high frequencies.

[0078] The metal wires arranged in a sheet of silicone rubber or the like are, for example, arranged parallel to the thickness direction (perpendicular to the plane of the sheet). In particular, it is preferable to arrange the metal wires at an angle of 10° (DEG.) to 35° (DEG.) with respect to an axis perpendicular to the plane of the metal wire sheet.

[0079] By tilting the metal wire with respect to the vertical axis, the sheet has good flexibility in the thickness direction. Also, the metal wire is inserted obliquely between the electrode pattern 505 and the electrode terminal 226, and between the electrode pattern 506 and the signal terminal 227, resulting in good electrical contact (electrical connection). High-precision contact can be achieved with a low contact load. In addition, the maintenance cycle can be improved, allowing for repeated use over a long period of time.

[0080] In addition to silicone rubber, butyl rubber, ethylene propylene rubber, ethylene vinyl acetate copolymer material, epichlorohydrin rubber, acrylic rubber, etc. can also be used.

[0081] The anisotropic conductive rubber 504 is not limited to anisotropic conductive rubber. For example, it can be replaced with an anisotropic conductive film (ACF), an anisotropic conductive adhesive, etc. In this specification, for ease of explanation, 504 will be explained as anisotropic conductive rubber 504.

[0082] An anisotropic conductive film is a conductive film made by mixing fine metal particles with a thermosetting resin or a thermoplastic resin and molding it into a film shape. In this semiconductor device, it is preferable to make the semiconductor element 117 to be tested detachable, so it is preferable to use an ACF made of a thermoplastic resin.

[0083] The conductive particles are mainly structured as spheres with a diameter of 3 to 5 μm, with a nickel layer, a gold plating layer, and an insulating layer on the outside. ACF is sandwiched between the electrode part and the electrode part of the part, and then thermocompressed with a heater or the like.

[0084] Anisotropic conductive adhesives can electrically connect and fix opposing electrodes together. They can also be used for materials that cannot be joined by soldering or that cannot withstand the high temperatures of soldering. Anisotropic conductive adhesives consist of an adhesive (binder) to fix the electrodes together, and conductive particles that are uniformly dispersed in the binder.

[0085] As a binder component, it must be a material that has not only adhesive strength but also insulation to prevent electrical conduction between adjacent electrodes and has each reliability. If these basic properties are satisfied, any resin, such as synthetic rubber, thermoplastic resin, or thermosetting resin, can be used as a binder depending on the specifications.

[0086] Examples of conductive materials include metals (nickel or a composite of nickel coated with gold), metal-plated plastic or resin cores, or materials with an insulating coating on top that breaks down when exposed to heat or pressure. The shape is selected to be close to spherical, and the particle size is selected from a few μm to several tens of μm depending on the specifications, particularly the distance between the electrodes.

[0087] A collector terminal cm, a gate terminal gm, and an emitter terminal em are arranged in the transistor 117. A signal Vgs for turning on and off the transistor 117 is applied to the gate terminal gm. A constant current Icm is applied from a constant current circuit 118 to a diode Dm through an anode terminal am and a cathode terminal km.

[0088] Fig. 7 is an explanatory diagram and an equivalent circuit diagram of a semiconductor element 117 to be tested in another example. Fig. 7(a) is an explanatory diagram that shows a schematic diagram of the semiconductor element 117 as viewed from the back side. Fig. 7(b) is an equivalent circuit diagram of the semiconductor element. Fig. 7 shows an example of an SOP package. A transistor is illustrated as the semiconductor element 117. Note that, although this is also true for other examples, the semiconductor element 117 is not limited to a transistor.

[0089] For example, a wide variety of devices can be applied, such as the semiconductor element in Figure 55, power resistors, posistors, thermistors, etc. It goes without saying that multiple elements, such as resistor elements and transistors, formed in one SOP or QFN can also be applied.

[0090] 7(b), the transistor 117 has a P terminal (collector terminal of the transistor 117) to which a large current is applied, and an N terminal (emitter terminal of the transistor 117) to which a large current is applied. A diode Dm is formed or disposed between the emitter terminal em of the transistor Qm and the collector terminal cm of the transistor Qm. The cathode terminal of the diode Dm is connected to the collector terminal cm of the transistor Qm, and the anode terminal of the diode Dm is connected to the emitter terminal em of the transistor Qm.

[0091] 7(a), electrode terminals 226a and 226b are formed on the back surface of the SOP. The P terminal is connected to electrode terminal 226a. The N terminal is connected to electrode terminal 226b. Electrode terminal 226 is formed in a flat shape on the back surface of the SOP. A nickel (Ni) plating film is formed on the surface of electrode terminal 226 as necessary. Furthermore, gold plating is formed on the surface of electrode terminal 226 to prevent oxidation. The electrode terminal 226 is electrically connected to the electrode pattern 505 of the connection board 514 via the anisotropic conductive rubber 504 .

[0092] 7, a diode Dm for measuring temperature is formed in the semiconductor element (transistor) 117. The diode Dm is formed in the same process as the transistor 117. The diode Dm is used to measure temperature information Tj of the transistor 117.

[0093] The diode Dm may be a parasitic diode of a transistor. It goes without saying that obtaining temperature information Tj and the like using the parasitic diode Dm can also be applied to other embodiments of the present invention.

[0094] The collector terminal cm of the transistor 117 is connected to a signal terminal 227d, and the emitter terminal em of the transistor 117 is connected to a signal terminal 227h. The gate terminal gm of the transistor 117 is connected to a signal terminal 227f. The signal terminal 227 is formed or disposed on a side surface of the QFN. The signal terminal 227 is configured so as to be electrically connected to an electrode pattern 506 of a connection board 514 on the rear surface of the QFN.

[0095] 7, like the other examples, eight signal terminals 227 are arranged on the side and back of the SOP so as to be connected to electrode pattern 506. Signal terminals 227 are electrically connected to electrode pattern 506 of connection board 514 via anisotropic conductive rubber 504. Signal terminals 227, electrode terminals 226, and electrode patterns 505 and 506 of connection board 514 are simultaneously electrically connected by one sheet of anisotropic conductive rubber 504 or the like.

[0096] Incidentally, the signal terminal 227, the electrode terminal 226, and the electrode pattern 505 and the electrode pattern 506 of the connection substrate 514 are not limited to being electrically connected simultaneously by one piece of anisotropic conductive rubber 504 etc. It goes without saying that the anisotropic conductive rubber 504 etc. connecting the signal terminal 227 and the electrode pattern 506 of the connection substrate 514 and the anisotropic conductive rubber 504 etc. connecting the electrode terminal 226 and the electrode pattern 505 of the connection substrate 514 may be anisotropic conductive rubber 504 separate from each other. The above points also apply to other embodiments of the present invention.

[0097] A collector terminal cm, a gate terminal gm, and an emitter terminal em are arranged in the transistor 117. A signal Vgs for turning on and off the transistor 117 is applied to the gate terminal gm. The emitter terminal em and the collector terminal cm are configured so that a constant current Icm can be passed from an external constant current circuit 118 to the diode Dm.

[0098] Fig. 8 is an explanatory diagram and an equivalent circuit diagram of a semiconductor element 117 to be tested in another example. The example in Fig. 8 is configured by arranging or forming two semiconductor elements 117 of Fig. 7(b) in one QFN. As described above, it goes without saying that two or more semiconductor elements 117 may be arranged or formed in a package such as a QFN. A plurality of semiconductor elements 117 are arranged in the QFN, and signal terminals 227 and electrode terminals 226 are formed or arranged on the QFN or the like in accordance with the number of semiconductor elements 117 . Fig. 8(a) is an explanatory diagram showing a schematic diagram of the semiconductor element 117 as viewed from the back side, and Fig. 8(b) is an equivalent circuit diagram of the semiconductor element.

[0099] In the example of FIG. 8, as shown in FIG. 8(b), two transistors 117 (transistor 117m and transistor 117s) described in FIG. 7(b) are disposed or formed within a QFN.

[0100] As shown in FIG. 8(a), an electrode terminal 226a of the P terminal of transistor 117s, an electrode terminal 226a of the P terminal of transistor 117s, an electrode terminal 226c of the O terminal of transistor 117m, and an electrode terminal 226b of the N terminal of transistor 117m are formed or arranged on the rear surface of the QFN.

[0101] The diode Ds is connected between the emitter terminal es and the collector terminal cs of the transistor 117s, and the diode Dm is connected between the emitter terminal em and the collector terminal cm of the transistor 117m.

[0102] The transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em, while the transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es.

[0103] 8, a diode Ds for measuring temperature is formed in the semiconductor element (transistor) 117s, and a diode Dm for measuring temperature is formed in the semiconductor element (transistor) 117m.

[0104] The diodes Ds and Dm are formed in the same process as the transistor 117. The diode Ds is used to measure temperature information Tj of the transistor 117s. The diode Dm is used to measure temperature information Tj of the transistor 117m. The present invention obtains the temperature information Tj of the transistor 117 (transistor 117m or transistor 117s) using one of the diodes D (diode Dm or diode Ds) that tests the transistors 117s and 117m.

[0105] The transistor 117m has a collector terminal cm, a gate terminal gm, and an emitter terminal em. A signal Vgs is applied to the gate terminal gm to turn on and off the transistor 117. The transistor 117s has a collector terminal cs, a gate terminal gs, and an emitter terminal es.

[0106] When testing transistor 117m, the gate terminal gs is shorted to the emitter terminal es, transistor 117s is in a diode-connected state, and the transistor 117m is tested. When testing transistor 117s, the gate terminal gm is shorted to the emitter terminal em, transistor 117m is in a diode-connected state, and the transistor 117s is tested. It goes without saying that both transistors 117m and 117s may be in a transistor operating state, and both transistors (transistor 117m, transistor 117s) may be tested simultaneously. The above points are similar to those in other embodiments of the present invention. FIG. 9 is a plan view and an explanatory diagram of a sample placement plate 511 in the semiconductor testing device of the present invention.

[0107] The semiconductor element 117 to be tested and the like are placed in the sample holes 512 of the sample placement plate 511. In this specification, the semiconductor element 117 will be described mainly by taking as an example an SOP-shaped package and a QFN-shaped package.

[0108] The thickness of the sample placement plate 511 is thinner than the thickness of the semiconductor element 117 to be tested. The sample placement plate is made of an insulating material.

[0109] 9, fixing holes 510 are formed at the four corners of a sample placement plate 511. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the sample placement plate 511. The positioning holes 509 are through holes.

[0110] Fig. 10 is a plan view and an explanatory diagram of a connection substrate 514. As shown in Fig. 10(a), fixing holes 510 are formed in the four corners of the connection substrate 514. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the sample placement plate 511. The positioning holes 509 are through holes.

[0111] Examples of the material of the heat-resistant substrate of the connection substrate 514 include glass epoxy material, ceramic material, phenolic resin material, insulated aluminum material, polyimide film, and PET material.

[0112] On the connection board 514, an electrode pattern 505 corresponding to the electrode terminals 226 of the semiconductor element 117 to be tested, and an electrode pattern 506 corresponding to the signal terminals 227 of the semiconductor element 117 are formed. A connector 202 is mounted on the connection board 514 , and a control signal is applied to the terminal of the semiconductor element 117 via a connection pin 502 of the connector 202 .

[0113] Connection portion 507 is formed or disposed on connection board 514. The basic material of connection portion 507 is thick copper, and the surface is plated with nickel (Ni). In addition to copper for connection portion 507, silver, copper alloy, silver alloy, and gold alloy can also be used.

[0114] Fig. 10(b) is a cross-sectional view of connection board 514 taken along line CC' in Fig. 10(a). Electrode patterns 505 and 506, signal wiring 508 (not shown), and connection wiring 503 (not shown) are formed on heat-resistant board 526. Heat-resistant resist 523 is formed between electrode patterns 505 and 506. A two-component alkaline development type solder resist is exemplified, such as the heat-resistant / heat-dissipating resist HRS-2-6 series by Yamashita Material Co., Ltd. Copper is exemplified as the material of the electrode patterns 505 and 506. A plating film 524 is formed on the surfaces of the electrode patterns 505 and 506. The plating film 524 is exemplified by a thin film (Ni-P film) formed by Ni-P plating, and a gold plating film 525 is formed on the surface of the Ni-P film.

[0115] Although the plating film 524 will be described as a Ni-P film, a thin film may also be formed from Ni or Ni-B. The plating film 524 may be made of any material as long as it can be bonded closely to the electrode pattern. In addition to nickel (Ni), examples of the material include tin, silver, gold, copper, lead, zinc, and alloys of these. The thickness of the plating film 524 is preferably 1 μm or more and 10 μm or less, and more preferably 2 μm or more and 6 μm or less. The thickness of gold plating film 525 is set to 0.01 μm or more. Gold plating film 525 has the function of preventing or suppressing oxidation or contamination of the surface of plating film 524.

[0116] The total thickness of plating film 524 and gold plating film 525 is preferably 1 μm to 10 μm, and more preferably 2 μm to 6 μm.

[0117] Moreover, it is preferable that the thickness of the plating film 524 plus the thickness of the gold plating film 525 be 1 μm or more and 10 μm or less from the plane of the heat-resistant resist 523 to form the convex portion. In particular, it is preferable that the thickness of the convex portion be 2 μm or more and 6 μm or less.

[0118] By forming plating film 524 etc. on electrode pattern 505 and electrode pattern 506, electrode pattern 505 etc. are formed to have a convex structure protruding from heat-resistant resist 523 film. Therefore, anisotropic conductive rubber 504 is deformed by convex electrode pattern 505 etc. The deformation of anisotropic conductive rubber 504 provides good electrical connection between electrode terminal 226 and electrode pattern 505, and between signal terminal 227 and electrode pattern 506.

[0119] A large current of several hundred amperes (A) or more flows through electrode pattern 505, so the electrode area is formed large. Electrode pattern 506 is often used as a terminal to which a control signal for transistor 117 is applied. Therefore, a large current rarely flows through electrode pattern 506, so the area of ​​electrode pattern 506 is relatively small.

[0120] A large current can be applied by sharing a plurality of electrode patterns 506 (electrically connecting a plurality of electrode patterns 506). In this case, a plurality of signal terminals 227 for applying the same signal are formed or arranged.

[0121] 10(b), plating 524 of the same thickness is formed or disposed on electrode pattern 505 and electrode pattern 506. In addition, a gold plating film 525 is formed on plating film 524.

[0122] 10(c), plating 524 having a thickness thicker than that on electrode pattern 506 is formed or disposed on electrode pattern 505. That is, plating film 524b is formed thicker than plating film 524a. In addition, gold plating film 525 having the same thickness is formed on plating film 524.

[0123] 10(c), anisotropic conductive rubber 504 is sandwiched between signal terminal 227 and electrode pattern 506 for electrical connection. Electrode terminal 226 and electrode pattern 505 are electrically connected by being directly in close contact with each other.

[0124] 10 shows an example in which the thickness of the plating film 524 is made different, and the electrode pattern 505 is configured to be more convex than the electrode pattern 506. It goes without saying that in addition to making the thickness of the plating film 525 different, the thicknesses of the electrode patterns 505 and 506 may be changed to make the electrode pattern 505 more convex than the electrode pattern 506. Fig. 10 shows an embodiment in which the thickness of the connection substrate 514 is uniform (flat, even). Fig. 57 shows an embodiment in which the thickness of the connection substrate 514 is varied. Fig. 57(b) is a cross-sectional view taken along line CC' in Fig. 57(a). In Fig. 57, a mounting recess 239 is formed in a connection board 514.

[0125] As an example, the placement recess 239 is formed by removing the heat-resistant resist 523 of the connection board 514. Alternatively, when the heat-resistant resist 523 is formed, the placement recess 239 is formed by a molding die.

[0126] An electrode pattern 506 is formed in the placement recess 239. In addition, the thickness of the electrode pattern 506 is formed to be thinner than the thickness of the electrode pattern 505, as shown in FIG.

[0127] A plating film 524 is formed on the electrode patterns 505 and 506, and gold plating 525 is formed on the plating film 524. In Fig. 57(b), plating film 525b and plating film 525a are illustrated as having the same film thickness, but it goes without saying that plating film 525b and plating film 525a may have different film thicknesses as shown in Fig. 10. Other points are the same as or similar to other embodiments of the present invention, so a description thereof will be omitted.

[0128] FIG. 57(c) is an explanatory diagram showing a state in which a semiconductor element 117 such as an SOP 117 or a QFN 117 is attached to the electrode pattern 505 and the electrode pattern 506 in FIGS. 57(a) and 57(b).

[0129] Anisotropic conductive rubber 504a is inserted or placed in placement recess 239. Anisotropic conductive rubber 504a is sandwiched between signal terminal 227 and electrode pattern 506. Electrode terminal 226 and electrode pattern 505 are directly electrically connected.

[0130] 11, when the anisotropic conductive rubber 504a is pressed, the signal terminal 227 and the electrode pattern 506 are electrically connected by the conductive wire 230. In Fig. 13, a placement recess 239 is formed on the periphery of the anisotropic conductive rubber 504a.

[0131] In the embodiment of FIG. 57, since the arrangement recess 239 is formed, even if the anisotropic conductive rubber 504a has a thickness, the anisotropic conductive rubber 504a is stored within the arrangement recess 239, and the electrode pattern 505 and the electrode terminal 226 are in close contact with each other, thereby achieving a closer and better electrical connection.

[0132] FIG. 11(a) is an explanatory diagram when the electrode terminals 226 of the SOP and QFN and the electrode pattern 505, and the signal terminals 227 of the SOP and QFN and the electrode pattern 506 are aligned via the anisotropic conductive rubber 504. FIG.

[0133] In the embodiment of FIG. 11, one anisotropic conductive rubber 504 can electrically connect the electrode terminal 226 and the electrode pattern 505, and the signal terminal 226 and the electrode pattern 506 at the same time.

[0134] Alternatively, the first anisotropic conductive rubber 504 may be configured to electrically connect the electrode terminal 226 and the electrode pattern 505, and the second anisotropic conductive rubber 504 may be configured to electrically connect the signal terminal 226 and the electrode pattern 506.

[0135] The formation area of ​​the electrode pattern 505a is larger than the formation area of ​​the electrode terminal 226a. The formation area of ​​the electrode pattern 505b is larger than the formation area of ​​the electrode terminal 226b. The formation area of ​​the electrode pattern 505c is larger than the formation area of ​​the electrode terminal 226c.

[0136] As described above, by making the electrode area of ​​electrode pattern 505 larger than the formation area of ​​electrode terminal 226, alignment becomes easier and connection with anisotropic conductive rubber 504 also becomes easier.

[0137] The formation area of ​​electrode pattern 506a is larger than the formation area of ​​signal terminal 227a. The formation area of ​​electrode pattern 506b is larger than the formation area of ​​signal terminal 227b. The formation area of ​​electrode pattern 506c is larger than the formation area of ​​signal terminal 227c. The formation area of ​​electrode pattern 506d is larger than the formation area of ​​signal terminal 227d. The formation area of ​​electrode pattern 506e is larger than the formation area of ​​signal terminal 227e. The formation area of ​​electrode pattern 506f is larger than the formation area of ​​signal terminal 227f. The formation area of ​​electrode pattern 506g is larger than the formation area of ​​signal terminal 227g. The formation area of ​​electrode pattern 506h is larger than the formation area of ​​signal terminal 227h.

[0138] As described above, by making the electrode area of ​​the electrode pattern 506 larger than the formation area of ​​the signal terminal 227, alignment becomes easier and connection with the anisotropic conductive rubber 504 also becomes easier.

[0139] An SOP or QFN as a semiconductor element 117 to be tested is placed in a sample hole 512 in a sample placement plate 511 with the electrode terminals 226 and signal terminals 227 facing upward. An anisotropic conductive rubber 504 is placed on the electrode terminals 226 and signal terminals 227. A connection board 514 is placed on the anisotropic conductive rubber 504.

[0140] It is preferable to use anisotropic conductive rubber 504 with a Shore hardness of not less than 30 and not more than 100. If the Shore hardness is less than 30, it will deform when pressed, and if the Shore hardness is more than 100, it will not deform when pressed, resulting in poor electrical connection.

[0141] The connection board 514 and the sample placement plate 511 are positioned by positioning posts 518 inserted into positioning holes 509 , so that the electrode terminals 226 and the electrode patterns 505 , and the signal terminals 227 and the electrode patterns 506 are aligned.

[0142] By pressing downward from the connection board 514 side, the anisotropic conductive rubber 504 is deformed, and the electrode terminal 226 and the electrode pattern 505 , and the signal terminal 227 and the electrode pattern 506 are electrically connected via the anisotropic conductive rubber 504 . 11(b) and 11(c) show schematic diagrams of the direction of the conductive wires 230. FIG.

[0143] Anisotropic conductive rubber 504 is made of silicone rubber and gold-plated metal wires arranged at a narrow pitch as conductive wires 230. The wire diameter of the metal wires is 0.02 mm or more and 0.04 mm or less, and the thickness of the silicone rubber is 0.2 mm or more and 2 mm or less. The silicone rubber is pressed to a thickness of 10 μm or less.

[0144] The arrangement pitch of the conductive wires 230 is, for example, 0.05 mm or more and 0.4 mm or less. The metal wires arranged on a sheet of silicone rubber or the like are preferably arranged so that the metal wires are tilted at an angle of 10° (DEG.) to 35° (DEG.) with respect to an axis perpendicular to the plane of the metal wire sheet.

[0145] 11(b) is a schematic diagram showing a state in which the conductive wires 230 are arranged in the vertical direction relative to the paper surface. FIG. 11(c) is an explanatory diagram showing a schematic diagram of the arrangement direction of the conductive wires 230 in the cross section of the anisotropic conductive rubber 504.

[0146] By tilting the metal wire with respect to the vertical axis, the sheet has good flexibility in the thickness direction. The gold-plated metal wire is preferably of the non-magnetic type. This allows the semiconductor element 117 to be tested and evaluated at high frequencies.

[0147] As shown in FIG. 11(b), the signal terminal 227 has a rectangular shape, and the anisotropic conductive rubber 504 is arranged so that the longitudinal direction of the conductive wire 230 approximately coincides with the longitudinal direction of the rectangular shape.

[0148] When pressed, the conductive wires 230 in the anisotropic conductive rubber 504 penetrate between the electrode pattern 506 and the signal terminal 227, and between the electrode pattern 505 and the electrode terminal 226, thereby achieving good electrical connection.

[0149] Fig. 12 is a plan view and an explanatory diagram of a connection board 514 in the case where there are three electrode terminals 226 (electrode terminal 226a, electrode terminal 226b, electrode terminal 226c) shown in Fig. 5. Three connection parts 507 (connection part 507a, connection part 507b, connection part 507c) are also formed or arranged. Other configurations or structures are the same or similar to those described in Fig. 10, so description thereof will be omitted.

[0150] FIG. 13(a) is an explanatory diagram of the state in which the electrode terminals 226 of the SOP·QFN and the electrode pattern 505, and the signal terminal 227 of the SOP·QFN and the electrode pattern 506 are aligned via anisotropic conductive rubber 504 when there are three electrode terminals 226 (electrode terminal 226a, electrode terminal 226b, electrode terminal 226c) as shown in FIG. 5 etc. FIG. 13(b) shows a schematic diagram of the conductive wires 230 arranged in the vertical direction relative to the paper surface. 13(b), the anisotropic conductive rubber 504a is disposed on the signal terminal 227. The anisotropic conductive rubber 504 is not disposed on the electrode pattern 505. The anisotropic conductive rubber 504 has a rectangular shape, and one anisotropic conductive rubber 504 covers (is layered on) a plurality of signal terminals 227 . The conductive wires 230 in the anisotropic conductive rubber 504 are arranged and oriented in the longitudinal direction of the rectangular shape of the anisotropic conductive rubber 504 .

[0151] 13(b) expands and contracts when pressed, etc., and because it has a rectangular shape, it is particularly likely to expand and contract in the longitudinal direction. Therefore, the conductive wire 230 is likely to move in the longitudinal direction (orientation direction) of the conductive wire 230. The movement of the conductive wire 230 allows the signal terminal 227 and the electrode pattern 506 to be well electrically connected.

[0152] 13(b), when the anisotropic conductive rubber 504 has a rectangular shape, the conductive wire 230 is disposed, oriented, or formed in the longitudinal direction of the anisotropic conductive rubber 504. When the signal terminal 227 and the electrode pattern 506 have a rectangular shape, the conductive wire 230 is disposed, oriented, or formed in the longitudinal direction of the signal terminal 227 and the electrode pattern 506.

[0153] Although the conductive wire 230 is arranged, oriented, or formed in the longitudinal direction of the signal terminal 227 and the electrode pattern 506, the direction of the formation of the conductive wire 230 may be within ±45° (DEG.) with respect to the longitudinal direction. Preferably, the direction of the formation of the conductive wire 230 is within ±20° (DEG.) with respect to the longitudinal direction.

[0154] Other configurations or structures are the same as or similar to those described in Fig. 11, and therefore will not be described here. It goes without saying that the above can also be applied to other embodiments in this specification, such as the embodiment in Fig. 57.

[0155] 14 is a plan view and an explanatory diagram of the pressing plate 515. The pressing plate has a good flatness and a structure or configuration that can be insulated from at least the conductive part of the connection board. Examples of the material of the pressing plate include copper, stainless steel, aluminum, and brass. Other examples include ceramics and phenol resin.

[0156] Pressing plate 515 is disposed on connection board 514. Pressing from above with pressing plate 515 presses connection board 514 evenly. The pressure presses anisotropic conductive rubber 504 disposed in close contact with electrode patterns 505 and 506 of connection board 514. Anisotropic conductive rubber 504 electrically connects electrode pattern 505 and electrode terminal 226. Also, electrode pattern 506 and signal terminal 227 are electrically connected.

[0157] Fixing holes 510 are formed in the four corners of the pressing plate 515. The fixing holes 510 are through holes. Two positioning holes 509 are formed in the pressing plate 515. The positioning holes 509 are through holes. FIG. 15 is an explanatory diagram of a connection state in which SOP 117 or QFN 117 and connection board 514 are connected with anisotropic conductive rubber 504.

[0158] As shown in Fig. 15, it is placed on a positioning support plate 519. The positioning support plate 519 is formed of a material with good thermal conductivity. Examples of the material of the positioning support plate 519 include copper, stainless steel, aluminum, brass, and ceramics. Note that the surface plate 520 shown in Fig. 16 and other figures is also formed of a material with good thermal conductivity, similar to the positioning support plate 519. This is to transfer heat from the heating / cooling plate 134 well.

[0159] The SOP117 or QFN117 is closely attached to the positioning support plate 519. Furthermore, grease with good thermal conductivity is applied between the SOP117 or QFN117 and the positioning support plate 519, if necessary.

[0160] The SOP117 or QFN117 is placed by being fitted into the sample hole 512 of the sample placement plate 511. Also, a variable mechanism is configured and added to vary the size of the sample hole 512 in accordance with the size of the SOP117 or QFN117 so that various SOP117s or QFN117s can be clamped and fixed as necessary.

[0161] Anisotropic conductive rubber 504 is disposed on the electrode terminals 226 and the signal terminals 227 of the SOP 117 or QFN 117. When pressed, the anisotropic conductive rubber 504 generates electrical conduction in the vertical direction.

[0162] Electrode patterns 505 and 506 of connection board 514 are positioned on anisotropic conductive rubber 504. Heat-resistant resist 523 is formed or placed between electrode terminals 226 and signal terminals 227 and the like.

[0163] A plating film 524b is formed on the electrode patterns 505 and 506, and is convex by about several μm from the surface of the heat-resistant resist 523. If the electrode patterns 505 etc. themselves are convex from the flat portion of the heat-resistant resist 523 etc., there is no need to make them convex with the plating film 524 etc. It is preferable to make the signal terminals 227 and electrode terminals 226 of the SOP 117 or QFN 117 also convex with the plating film 524a.

[0164] As indicated by dotted lines in FIG. 15, anisotropic conductive rubber 504 is pressed more strongly by plating film 524, whereby electrode pattern 505 of connection board 514 is electrically connected to electrode terminal 226, and electrode pattern 506 is electrically connected to signal terminal 227.

[0165] In the embodiment of FIG. 15, the electrode terminal 226 and the signal terminal 227 use a common (single) piece of anisotropic conductive rubber 504 to realize electrical connection with the electrode pattern 505 or the electrode pattern 506 .

[0166] However, the present invention is not limited to this, and the electrode pattern 505 and the electrode terminal 226 may be electrically connected by the first anisotropic conductive rubber 504, and the electrode pattern 506 and the signal terminal 227 may be electrically connected by the second anisotropic conductive rubber 504. Even in the above case, the matters described in Figs. 11 and 13 are implemented. Fig. 56 is an explanatory diagram of a state in which the semiconductor element 117 is connected to a connection board 514. Basically, the state in Fig. 15 is applicable. In FIG. 56, anisotropic conductive rubber 504 a is disposed between electrode pattern 506 of connection board 514 and signal terminal 227 .

[0167] 56, plating film 524 is formed on electrode pattern 505 and electrode pattern 506, and gold plating 525 is formed on plating film 524. In FIG.

[0168] In FIG. 56, since plating film 524b is formed thick, even if anisotropic conductive rubber 504 is thick, electrode pattern 505 and electrode terminal 226 are tightly attached by pressing, and good electrical connection is achieved.

[0169] Anisotropic conductive rubber 504 is sandwiched between signal terminal 227 and electrode pattern 506. Electrode terminal 226 is directly electrically connected to electrode pattern 505. As described in Fig. 13, anisotropic conductive rubber 504 is pressed, and electrical connection is established between signal terminal 227 and electrode pattern 506 via conductive wire 230.

[0170] In the embodiment of FIG. 56, even if the anisotropic conductive rubber 504 has a thickness, the electrode pattern 505 and the electrode terminal 226 are in close contact with each other, and a closer and better electrical connection can be achieved. 56 can be applied to the configuration or structure of the arrangement recess 239 in FIG. 57.

[0171] 16 and 17 are explanatory diagrams for explaining a mounting portion of a semiconductor element 117 to be tested by the semiconductor testing device of the present invention. Fig. 16(a) is an explanatory diagram showing a schematic view of the mounting portion as seen from above. Fig. 16(b) is a cross-sectional view taken along line AA' in Fig. 16(a).

[0172] 17, a thick plating film 524 is formed on an electrode pattern 505. Anisotropic conductive rubber 504a is disposed between a signal terminal 227 and an electrode pattern 506. The electrode pattern 505 and the electrode terminal 226 are in close contact with each other and are electrically connected by pressing.

[0173] Two supports 518 (support 518a and support 518b) are attached to the positioning support plate 519. The support 518a is inserted into the positioning hole 509a of the sample placement plate 511, the positioning hole 509a of the connection board 514, and the positioning hole 509a of the pressing plate 515. The support 518b is inserted into the positioning hole 509b of the sample placement plate 511, the positioning hole 509b of the connection board 514, and the positioning hole 509b of the pressing plate 515.

[0174] The SOP 117 and QFN 117 are inserted into the sample holes 512. The electrode patterns of the connection board 514 and the electrode terminals 226 and signal terminals 227 of the QFN are positioned by inserting the support posts 518 into the positioning holes. Pressing is performed in the B direction from the pressing plate 515 side. FIG. 18 is an explanatory diagram for explaining a method of mounting a test semiconductor element 117 on the semiconductor testing apparatus of the present invention. As shown in FIG. 18( a ), a sample placement plate 511 has sample holes 512 , positioning holes 509 , and fixing holes 510 formed therein.

[0175] 18(b), a semiconductor element 117 is placed in a sample hole 512 of a sample placement plate 511. The QFN or SOP semiconductor element 117 is placed with the electrode terminals 226 facing upward. Anisotropic conductive rubber 504 is placed on the electrode terminals 226.

[0176] 18(c), a connection board 514 is disposed on the anisotropic conductive rubber 504. A current power supply device is disposed so as to be connectable to a connection portion 507 of the connection board 514.

[0177] 18(d), a pressing plate 515 is placed on the connection substrate 514. The sample placement plate 511, the connection substrate 514, and the pressing plate 515 are positioned by positioning posts 518 inserted into the positioning holes 509.

[0178] Next, as shown in FIG. 18(e), a fixing post (not shown) or the like is inserted into the fixing hole 510, and a pressing tool 516 is attached to the fixing post, and the anisotropic conductive rubber 504 is pressed.

[0179] In Fig. 9 and other figures, there is one sample hole 512 in the sample placement plate 511, but the present invention is not limited to this. Fig. 19 shows an embodiment in which two semiconductor elements 117 are connected and tested in this connected state. In the embodiment of Fig. 9(b), two semiconductor elements 117 of Fig. 1 are connected. The electrode terminal 226b of the semiconductor element 117s and the electrode terminal 226a of the semiconductor element 117m are connected by a connection wiring 503. The connection wiring 503 is formed on a connection board 514. Other configurations and the like are explained in other embodiments in the specification, so explanations will be omitted.

[0180] In the embodiment of Fig. 19, as shown in a sample placement plate 511 of Fig. 20, a sample hole 512a for a semiconductor element 117s and a sample hole 512b for a semiconductor element 117m are formed in a sample placement plate 511. The present invention makes it possible to test a plurality of semiconductor elements 117 by appropriately forming the number of sample holes 512 in the sample placement plate 511.

[0181] 27 is a configuration diagram of a power cycle test apparatus (semiconductor test apparatus) of the present invention. The power cycle test apparatus has a chiller (cooling / warming device) 136, a heating / cooling plate 134, and a circulating water pipe 135 that circulates water between the heating / cooling plate 134 and the chiller 136. A transistor 117 is mounted on the heating / cooling plate 134 as a semiconductor element to be tested. In practice, to accommodate a wide variety of shapes of the semiconductor elements 117, a surface plate 520 is attached on the heating / cooling plate 134, a positioning support plate 519 is attached on the surface plate 520, and the semiconductor element 117 is placed on the positioning support plate 519.

[0182] The device fixing / connecting apparatus 610 includes a heating / cooling plate 134 and a circulating water pipe 135 that circulates water between the heating / cooling plate 134 and a chiller 136. In addition, a transistor 117 is mounted on the heating / cooling plate 134 as a semiconductor element to be tested, and a sample connection circuit 203 (not shown) is configured or arranged therein. Heat from the heating / cooling plate 134 is transferred to the semiconductor element 117 via the surface plate 520 and the positioning support plate 519 .

[0183] The heat from the heating / cooling plate 134 sets the test conditions by changing the current Id, gate voltage Vgs, and voltage Vce so that the temperature information Tj of the transistor 117 to be tested becomes a predetermined value.

[0184] If the temperature information Tj changes, it is determined that the transistor 117 has deteriorated or the characteristics have changed, and the test of the transistor 117 is stopped or the control method is changed.

[0185] In the following description, the current Id is applied to or passed through the transistor 117, but the present invention is not limited to this. It goes without saying that Id may be a current that changes over a predetermined period or time. Also, Id is not limited to a current, and may be a voltage.

[0186] A change in the temperature information Tj is used to determine or evaluate a change in the characteristics of the transistor 117. Also, the change in characteristics, reliability, and lifespan of the transistor 117 are evaluated based on the time it takes for the voltage Vce to reach a predetermined voltage, the time it takes for the transistor 117 to break down, and the like.

[0187] In the semiconductor testing method of the present invention, the external conditions are changed according to the deterioration or characteristic change of transistor 117. For example, if transistor 117 generates heat, the water temperature is lowered. Lowering the water temperature reduces the current flowing through transistor 117, which prevents the deterioration and characteristic change of transistor 117 from progressing, and as a result, the lifespan of transistor 117 is extended. Therefore, the lifespan and reliability characteristics of transistor 117 for a given set of conditions can be quantitatively measured and determined.

[0188] The temperature of the transistor 117 is maintained at a specified or predetermined value by heating or cooling the circulating water of the chiller 136. The temperature of the transistor, etc. is periodically changed in response to the test conditions, and is cooled or heated to a constant value. Temperature information Tj of the test transistor is measured, and the chiller 136 is controlled to maintain the measured temperature information Tj at a constant value.

[0189] Chillers are designed to keep the temperature of equipment constant by circulating water or heat transfer medium while controlling its temperature. They are primarily used for cooling, but can also heat as well as cool. They are designed to control a variety of temperatures.

[0190] The control rack 131 includes a power supply device 132 that supplies a test current and a test voltage to the transistor 117, and a control circuit 133 that controls the transistor 117 or sets test conditions.

[0191] Temperature information Tj of the transistor 117 is input to the control circuit 133, and the control circuit 133 controls the chiller 136 based on the temperature information Tj. Alternatively, the control circuit 133 controls the chiller 136 so as to set the temperature information Tj to a predetermined value.

[0192] Although circulating water is described in this specification, it is not limited to water. Ethylene glycol, glycerin, freon, etc. may also be used, and forced air cooling may also be used. Chiller 136 controls the liquid in circulating water pipe 135 to a temperature range of, for example, -1°C to +100°C, and supplies it to heating / cooling plate 134 of the test unit. Heating / cooling plate 134 has a sufficiently large heat capacity.

[0193] In the above embodiment, the heating / cooling plate 134 is used, but the heating plate and the cooling plate may be separate bodies, and heating / cooling may be performed using a heat source / cold source other than the heating / cooling plate.

[0194] Figure 68 shows a voltage and current application jig (equipment) for a double-sided cooling sample (power semiconductor element). By using a double-sided cooling structure for the semiconductor device, it becomes possible to apply a large current.

[0195] 38 and 43 show heat pipes 223 arranged on the back surface of connection structure 218. The present invention is not limited to this, and as shown in Figures 68 and 69, heat pipes 223 may be arranged on the side surface of connection structure 218, and the side surface of connection structure 218 may be pressed from above with pressing member 608 to be fixed. The voltage and current application jig (device) suppresses heat generation in the contacts and wiring, and can reproduce test conditions according to the purpose.

[0196] 68, a test current and a control signal are supplied from a device fixing / connecting device 610. The test current is applied to a connection structure 218. A terminal connection part 609 for connecting with a connection terminal of a power semiconductor element is arranged at one end of the connection structure 218. A heat pipe 223 is arranged in the connection structure 218. A cooling fan 229 is arranged at the bottom or top of the connection structure 218. The air flow generated by the cooling fan 229 passes between the connection structure 218, the heat pipe 223, and the pressing member 608, and suppresses the temperature rise of the connection part with the device 117, the contact point, the connection structure 218, etc. The device fixing and connecting device 610 includes a connecting structure 218.

[0197] 27, 28 and 29, the device fixing and connecting device 610 contains the heating and cooling plate 134, the semiconductor element 117 to be tested, a device for fixing or holding the semiconductor element 117 having a pressing head 530 and the like, and a sample connection circuit 203. The cover of the device fixing and connecting device 610 is made of a structure capable of electrostatic shielding and electromagnetic shielding, and the cover is grounded.

[0198] The heat pipe 223 is in close contact with the connection structure 218. Thermally conductive grease or heat dissipating silicone oil compound may be applied between the surface of the connection structure 218 and the heat pipe 223.

[0199] The material of the connection structure 218 will be described as copper, but is not limited to copper. Examples of materials for the connection structure 218 include copper (linear expansion coefficient 16.8), brass (linear expansion coefficient 19), iron (linear expansion coefficient 12.1), and stainless steel (SUS304) (linear expansion coefficient 17.3).

[0200] Examples of materials for the heat pipe 223 include materials with a large linear expansion coefficient, such as aluminum (linear expansion coefficient 23), tin (linear expansion coefficient 26.9), and lead (linear expansion coefficient 29.1). Of these, it is preferable to use copper (linear expansion coefficient 16.8) as the material for the connection structure 218 and aluminum (linear expansion coefficient 23) as the material for the heat pipe. Alternatively, an alloy obtained by mixing aluminum with a second metal such as molybdenum may be used.

[0201] Figure 69 is a perspective view of the side of Figure 68 seen from the opposite direction. A circulating water pipe 135 that supplies or discharges circulating water is attached inside the device fixing / connecting device 610. The cooling fan 229 may be disposed on the top or side of the connecting structure 218. Alternatively, it may be disposed in two or more directions, such as above, below, left, or right.

[0202] A pressing member 608 is attached to the support column 534 and fixes and holds the connection structure 218. In addition, the pressing member 608 can be moved up and down the support column 534, and the pressing member 608 can be held with a predetermined pressure.

[0203] 70, 71, and 72 show devices used for high heat dissipation general-purpose devices (TO packages, etc.) for use in the semiconductor device testing device of the present invention. Used for TO-247 packages as power semiconductor devices. A current application circuit and an on-off pulse driver circuit for applying to the gate terminal of the transistor are mounted or formed on the connection board 514.

[0204] The connection board 514 can be custom designed to match the semiconductor device to be tested, and can accommodate a variety of device shapes. For example, it can accommodate the chip shapes or structures of various semiconductor elements 117 described in Figures 2, 5, 7, 58, etc.

[0205] 72, a heating / cooling plate 134b is placed under a positioning support plate 519a. A power semiconductor device 117 to be tested is placed on the positioning support plate 519a. A connection terminal of the power semiconductor device is electrically connected to an electrode of a connection board 514. A gate signal and a test current from the connection board 514 are applied to the power semiconductor device 117. The device stand 611 is a stand on which the semiconductor device element 117 is placed, and is made of a resin material that suppresses static electricity, and has flexibility and springiness.

[0206] Pressing posts 531 are arranged and pressed so that the connection terminals of power semiconductor device 117 and connection board 514 are in close contact with each other, thereby achieving good electrical connection between the connection terminals of the power semiconductor device and connection board 514. When semiconductor element 117 has the configuration shown in Fig. 2, Fig. 5, etc., connection board 514 may have the configuration shown in Fig. 10, Fig. 12, Fig. 54, Fig. 57, etc., and anisotropic conductive rubber 504 may be used to connect electrode pattern 506 and signal terminal 227.

[0207] The positioning support plate 519b is disposed on the upper surface of the power semiconductor device 117 to fix the position of the power semiconductor device. The heating / cooling plate 134a cools or heats the power semiconductor device 117 from the upper surface thereof.

[0208] 70 and 71 are diagrams showing the structure of a surface mount component jig used in the semiconductor element test apparatus of the present invention and an explanatory diagram showing the mounting of a device element 117. Surface mount devices such as QFN packages and SOP packages can also be used.

[0209] A surface plate 520 made of a metal material with good thermal conductivity is disposed on heating / cooling plate 134b. A positioning support plate 519 is disposed on surface plate 520. Semiconductor element 117 is disposed on connection board 514 and also on device stand 611. Connection terminals of semiconductor element 117 are pressed by insulating pressing plate 513, and the connection terminals of conductive element 117 and electrodes of connection board 514 are connected. The connection is made with the electrodes formed on the connection board 514. The positioning support plate 519 presses and fixes the connection board 514 so that the connection board 514 has a flatness. 22 is an explanatory diagram of the semiconductor testing device of the present invention. The heating and cooling plate 134 is placed on a base 522. The base 522 is exemplified by a vibration-proof surface plate.

[0210] 23 to 25 are explanatory diagrams of a method for testing a semiconductor element 117, mainly when the semiconductor element 117 is attached to an SOP 117 or a QFN 117, in the semiconductor testing device of the present invention. It goes without saying that the method can also be applied to a semiconductor chip such as that shown in FIG.

[0211] A surface plate 520 is attached to the base 522. The surface plate 520 is a plate to which the positioning support plate 519 is attached. By changing the surface plate 520, the positioning support plate 519 can be easily changed.

[0212] The positioning support plate 519 needs to be changed in accordance with the shape of the sample placement plate 511 and the positions of the positioning holes 509. Furthermore, the size and position of the sample holes 512 of the sample placement plate 511 are changed in accordance with the shapes of the SOP117 and QFN117.

[0213] As shown in FIG. 23, the positioning posts 518 of the positioning post plate 519 are inserted into the positioning holes 509 of the sample placement plate 511, and the sample placement plate 511 is fixed.

[0214] The thickness of the sample placement plate 511 is configured to be thinner than the thickness of the SOP 117 and the QFN 117. The SOP 117 and the QFN 117 are placed with the electrode terminals 226 of the sample holes 512 facing upward.

[0215] The positioning support plate 519 is made of a base material made of a metal material with good thermal conductivity. For example, copper, stainless steel, and aluminum are exemplified. The surface of the positioning support plate 519 is plated with nickel (Ni) or silver (Ag).

[0216] Anisotropic conductive rubber 504 (not shown) is disposed on the electrode terminals 226 of the SOP 117 and the QFN 117. The anisotropic conductive rubber 504 is rectangular, and its area is equal to or slightly larger than the area including the arrangement areas of the electrode terminals 226 and the signal terminals 227. The sample placement plate 511 is countersunk, and configured so that the anisotropic conductive rubber 504 fits exactly into the countersunk portion.

[0217] 24, a connection board 514 is placed on anisotropic conductive rubber 504. The connection board 514 is placed so that an electrode pattern 505 of the connection board 514 corresponds to an electrode terminal 226 of the SOP117 and QFN117, and an electrode pattern 506 of the connection board 514 corresponds to a signal terminal 227 of the SOP117 and QFN117.

[0218] Support 534 is attached to base 522. Arm stand 533 is attached to support 534. Arm 532 is attached to arm stand 533. Arm 532 is configured to be rotatable about a central axis. The length of arm 532 is set and configured so that pressing head 530 is positioned above anisotropic conductive rubber 504, as shown in FIG.

[0219] It goes without saying that the matters explained above can also be applied to the devices of the present invention shown in Figures 68 and 72. It goes without saying that the configurations, members, structures, and operations shown in Figures 25, 68, and 72 can be applied in whole or in part in combination with one another.

[0220] A pressing post 531 is attached to the pressing head 530, and an arm 532 and pressing post 531 are attached to the pressing head 530. The position of the pressing head 530 moves up and down by sliding the pressing post 531. By moving the position of the pressing head 530 up and down, the pressing force of the anisotropic conductive rubber 504 is adjusted or set.

[0221] Rubber 517 is attached to the pressing head 530. Any elastic material may be used for the rubber 517. By using an elastic material, the anisotropic conductive rubber 504 can be pressed uniformly over the entire surface.

[0222] Examples of elastic materials or elastic objects include sponge, seaweed, soft plastic, air packs, liquid packs, gel packs, rubber metal, metal or resin springs, and leaf springs.

[0223] For example, a pressure motor is used for pressing. Pressure motors are fluid machines that convert the pressure of a liquid into mechanical motion, and include prime movers and actuators that convert the pressure of a fluid into rotary motion. Pressure cylinders are used to convert the pressure of a fluid into linear motion.

[0224] A pump converts rotational energy into pressure energy. A pressure motor converts pressure energy into rotational energy, so its basic structure is similar to that of a pump. Unlike electric motors, it can operate stably even in high-temperature environments. Also, even if the power source stops, it can still operate by storing pressure in an accumulator or the like. A pressure sensor is provided to detect the pressure.

[0225] 25 shows that pressure is applied to anisotropic conductive rubber 504 by pressure head 530 from above connection board 514. However, connection board 514 is often made of a glass epoxy material or the like, and connection board 514 is thin and easily deformed when pressed.

[0226] 14 is placed on the connection board 514. The pressure plate 515 is made of a material and thickness that has good thermal conductivity, is smooth, and does not easily bend, such as a metal material. By applying pressure from above the pressure plate 515 using the pressure head 530, pressure can be applied uniformly to the anisotropic conductive rubber 504 at a constant pressure.

[0227] Fig. 21 is an explanatory diagram showing a state in which pressure is applied to anisotropic conductive rubber 504 using pressure head 530. Fig. 21 shows a case in which pressure is applied from above connection board 514 via rubber 517. The pressure is indicated by an arrow.

[0228] At least one of the electrode patterns (electrode pattern 505, electrode pattern 506) and plating film 524 is more convex than a flat portion constituted by heat-resistant resist 523 etc. Therefore, the convex portion presses anisotropic conductive rubber 504, and the electrode pattern 505 and electrode terminal 226, and the electrode pattern 506 and signal terminal 227 are electrically connected via the anisotropic conductive rubber 504.

[0229] Regarding the electrical connection state, a monitor terminal (not shown) for measuring the resistance between electrode pattern 505 and electrode terminal 226, and between electrode pattern 506 and signal terminal 227 is provided on connection board 514. Pressing is performed with pressure head 530, and the resistance value of the monitor terminal is monitored. When the resistance value falls below a predetermined resistance value, the connection is completed and the pressure of pressure head 530 is maintained.

[0230] 22 shows a pressing head 530 supported by a one-way arm 532 attached to an arm stand 533. In this case, the pressing head 530 may become tilted.

[0231] To address this issue, an arm 532 is provided between support posts 534a and 534b as shown in Fig. 26. In other words, support posts 534a, 534b, and arm 532 form a "gate" shape.

[0232] Arm 532 is supported by left and right support columns (support columns 534a, 534b). Therefore, pressing column 531 that moves pressing head 530 can be stably maintained. Anisotropic conductive rubber 504 can be uniformly pressed, so good electrical connection can be achieved.

[0233] Fig. 28 is a configuration diagram of a semiconductor testing device of the present invention (for example, a power cycle testing device for testing a power transistor). Fig. 44 is an equivalent circuit diagram or an explanatory diagram of the semiconductor testing device.

[0234] The current power supply device 121 outputs a large constant current Id for testing the transistor 117. The current power supply device 121 supplies power (current, voltage) in synchronization with a control signal from the control circuit board 111, and drives the load at a set constant current or constant voltage using the supplied power. The current power supply device 121 can set a maximum voltage value to be output. The current power supply device 121 steadily outputs at least one of a current and a voltage.

[0235] The switch circuit 122a (SWa) turns on (supply) and off (cut) the supply of the constant current output by the current power supply device 121. The switch circuit 122a is set or controlled to be on (output constant current) or off (cut off constant current) based on a signal from the control circuit board 111. Usually, the switch circuit 122a is turned on before the start of a test, and is constantly maintained in the on state during the test of the semiconductor device.

[0236] 28 illustrates one current power supply device 121. The number of current power supply devices 121 is not limited to one. For example, the semiconductor testing device of the present invention may have two or more current power supply devices 121. The more the number of current power supply devices 121 increases, the more diverse the current waveforms Id or voltage waveforms that can be generated.

[0237] In the embodiment of the present invention, the current power supply device 121 is described, but the current power supply device 121 is not limited to one that outputs a constant current. For example, a current power supply device that can set a maximum voltage is used as the current power supply device 121. An example is one in which the current power supply device 121 functions to output a predetermined constant current at a set maximum voltage under certain conditions. Another example is one in which the output terminal voltage is configured to be able to set a predetermined maximum voltage when a constant current is output. It goes without saying that in the semiconductor testing device of the present invention, the current power supply device 121 may be a power supply device that can output both voltage and current, rather than a device that outputs only a constant current.

[0238] 28 and other embodiments are described assuming that the current Id is generated by the current power supply device 121, but the current Id can also be realized by adjusting the applied voltage in accordance with the on-resistance state of the transistor 117. Therefore, it goes without saying that the semiconductor testing device of the present invention is not limited to the current power supply device 121 that outputs a current, and may be configured as a power supply device that outputs a voltage.

[0239] The current Id can also be realized by controlling the voltage value of the gate voltage of the transistor 117. In this specification, a predetermined current is applied to the transistor 117 by controlling the current power supply device 121. However, this is not limiting, and it goes without saying that the voltage of the gate terminal g of the transistor 117 and the voltage of the collector terminal c of the transistor 117 may be adjusted or controlled.

[0240] For ease of explanation, in the embodiment of the semiconductor device testing method of the present invention, it is assumed that the constant current Id is generated by the current power supply device 121. The constant current Id flowing through the transistor 117 is supplied by operating the current power supply device 121. The current power supply device 121 is controlled to be turned on / off by a signal from the control circuit board 111. The device control circuit board 209 is controlled in timing by the control circuit board 111.

[0241] An emitter terminal e of the transistor 117 is grounded (connected to a ground line). A gate terminal g of the transistor 117 is connected to the gate driver circuit 113.

[0242] A gate driver circuit 113, a variable resistance circuit 125, a constant current circuit 118, and an operational amplifier (buffer circuit) 116 are arranged or formed in the sample connection circuit 203. The sample connection circuit 203 is arranged separately from the device control circuit board 209 so that it can be arranged in the vicinity of the transistor 117 to be tested.

[0243] It is preferable to provide one sample connection circuit 203 for each transistor 117 to be tested, but this is not limited thereto, and one sample connection circuit 203 including multiple signal circuits may be provided for multiple transistors 117.

[0244] The sample connection circuit 203 is connected to the transistor 117 via a connection pin 206 of the connector 202. The gate driver circuit 113 and the gate terminal g of the transistor 117 are arranged so as to have a short distance of 30 mm or less between them. If the distance between the gate driver circuit 113 and the gate terminal g of the transistor 117 is long, noise or the like is superimposed on the gate terminal g, causing the transistor 117 to malfunction, directly leading to the destruction of the transistor 117.

[0245] 29, the device control circuit board 209 is placed in room B of the housing 210 of the semiconductor testing equipment. The housing 210 is a frame or device body in which the power supply device 132, the drive circuit, and the heating / cooling plate 134 of the semiconductor testing equipment are incorporated. The sample connection circuit 203 is placed in room C1 of the housing 210 of the semiconductor testing equipment in order to be located close to the transistor 117 to be tested. The sample connection circuit 203 is connected to a connector 208 placed on the side of the housing 210. Wiring connected to a connection pin 206 of the connector 208 is connected to the device control circuit board 209 in room B.

[0246] The housing 210 is not limited to a box-like one, but may be, for example, a room. The current power supply device 121 is placed in the room. The partition walls 214, 215, and 217 may be walls of the room.

[0247] 29, a semiconductor element 117 (transistor, etc.) to be tested is placed in chamber C1. The transistor 117, etc. are placed and fixed on a heating and cooling plate 134.

[0248] The device fixing / connecting apparatus 610 includes a heating / cooling plate 134 and a circulating water pipe 135 that circulates water between the heating / cooling plate 134 and a chiller 136. In addition, a transistor 117 is mounted on the heating / cooling plate 134 as a semiconductor element to be tested, and a sample connection circuit 203 (not shown) is configured or arranged therein.

[0249] 29, for ease of illustration and understanding, the SOP 117, QFN 117, etc. are shown as being arranged and fixed on the heating / cooling plate 134. In reality, as shown in Fig. 16(b), a surface plate 520 with good thermal conductivity and a positioning support plate 519 are arranged on the heating / cooling plate 134, and the SOP 117 and QFN 117 are arranged on the support plate 519. The above matters are the same in Figs. 27, 29, 30, 36, 38, 39, 43, etc.

[0250] 29, the connector 208 is provided on the side of the housing 210, and the connector 208 and a device control circuit board 209 arranged in room B are connected by signal wiring 235. Control signals or output signals of the gate driver circuit 113, the gate signal control circuit 112, the temperature measurement circuit 115, the variable resistance circuit 125, and the operational amplifier circuit 116 are input / output from / to the device control circuit board 209.

[0251] 36, the transistor 117 and the like are fixed by being sandwiched between the heating and cooling plates 134a and 134b. As described above, in the present invention, the housing 210 is divided into a plurality of regions including the C1 chamber. The C1 chamber is configured to be injected with dry air (dry gas, gas with a low dew point temperature). Air pressure is applied to the C1 chamber, and the air injected into the C1 chamber is discharged through the opening 216 and the like.

[0252] The connection structure 218 is inserted from the C2 chamber through the opening 216 of the partition wall 217. By inserting the connection structure 218, the connection portion 507 of the transistor 117 and the connection structure 218 are electrically connected, and a constant current (test current) Id can be applied to the transistor 117. The connection structure 218 is made of copper or a copper alloy and has a silver or nickel plated surface.

[0253] The partition wall 217 has a function of electrostatic shielding and holding the connection structure 218. It goes without saying that the partition wall 217 can be omitted if a separate electrostatic shielding functional component, a fixing or holding stand for the connection structure 218 is disposed or configured. Furthermore, it goes without saying that when the partition wall 217 is not provided, the connection portion 507 of the transistor 117 may be positioned and fixed to the connection structure 218 .

[0254] The partitions (partitions 214, 215, 217) have the function of separating the respective chambers (chamber C1, chamber C2, chamber A, chamber B) and the function of preventing outside air from flowing in. In particular, since condensation may occur in chamber C1 during testing in low temperature conditions, dry air with a dew point of -20°C or lower is flowed into chamber C1. The dry air that flows into chamber C1 is exhausted to the other chambers through opening 216. However, if the opening of opening 216 is large, a large amount of dry air is required. Therefore, it is preferable that opening 216 is sized so that fork plug 205 and connection structure 218 serving as connection members can be inserted just right.

[0255] 30, a fixing screw 221 is attached to the other end of the connection structure 218, and the connection wiring 211 is connected to the connection structure 218. A fork plug 205 shown in FIG. 31 etc. is attached to the other end of the connection wiring 211 as a connection member.

[0256] 30, 38, and 43 show a pressing member 608 for fixing the connection structure 218. The connection structure 218 is fixed by the pressing member 608, and a terminal connection portion 609 consisting of the connection fittings 232 and 233 is stably fitted with the connection portion 507 of the device 117 to be tested. When separating the device 117 and the connection structure 218, the pressing member 608 is first removed.

[0257] Fixing screw 221 of connection structure 218 is not limited to a screw, and may be anything that can electrically connect connection wiring 211 to connection structure 218. Needless to say, fixing screw 221 may be one that can make contact by pressing with a spring (not shown).

[0258] The sample connection circuit 203 is connected to a device control circuit board 209 by a connection pin 206 of a connector 208. The sample connection circuits 203 are individually arranged corresponding to each transistor 117 to be tested, and the sample connection circuits 203 are configured so as to be easily removable. The connectors 208 and 213 are not limited to connectors, and may be any connectors that can electrically connect and disconnect wiring.

[0259] 35 is an explanatory diagram of a connection structure 218 in a semiconductor testing device of the present invention. A heat pipe 223 is in close contact with a recess 234 on the surface of the connection structure 218. Thermally conductive grease or a heat dissipating silicone oil compound may be applied between the surface of the connection structure 218 and the heat pipe.

[0260] The recess 234 is formed in the heat pipe fitting 231. The heat pipe 223 is disposed so as to fit into the recess 234. By disposing the heat pipe 223 in the recess, the risk of the heat pipe 223 being damaged is reduced.

[0261] The heat pipe metal fitting 231 is made of a metal that has good electrical and thermal conductivity. Examples of the metal include copper and silver. Other non-metallic materials such as carbon can also be used.

[0262] It is preferable to use thermally conductive grease that contains boron nitride (boron). It is preferable to use heat dissipating silicone oil compound that uses silicone oil as a base oil and mixes powder with good thermal conductivity such as alumina. The heat pipe 223 is a sealed container in which a small amount of liquid (working liquid) is vacuum sealed, and the inner wall has a capillary structure (wick).

[0263] When part of the heat pipe is heated, the working fluid evaporates in the heated area (absorbing the latent heat of evaporation), and the vapor moves to the low-temperature area at high speed (sonic speed). The vapor condenses in the low-temperature area (releasing the latent heat of evaporation), and the condensed working fluid flows back to the heated area due to the capillary action of the wick. The above phase changes are repeated continuously without any external force, and heat is transferred instantly, allowing the heat generated at the terminals of the semiconductor element to be transferred quickly and efficiently.

[0264] The heat pipe 223 is composed of an array of multiple containers (copper pipes). The inside of the container is in a highly decompressed state, and contains a wick (capillary structure) and an appropriate amount of working fluid (pure water, etc.). As the working fluid, in addition to pure water, methanol (methyl alcohol), acetone, sodium, mercury, fluorocarbon refrigerants, and ammonia may be used. Wick materials include aluminum, copper, stainless steel, sintered alloy, wire mesh, foamed metal, and ceramics.

[0265] The connection structure 218 is not limited to metal. It goes without saying that it may be made of a nonmetallic material such as ceramic, graphite, or a composite material of graphite and copper or aluminum. In the case where a current is directly applied to the connection structure 218, the connection structure 218 is made of a metal material such as copper. The surface of the connection structure 218 is preferably plated with silver, nickel, or the like. Figure 35 is an explanatory diagram of the configuration of the connection structure 218. Figure 35(a) is a diagram that typically illustrates the back surface, and Figure 35(b) is a diagram that typically illustrates the side surface.

[0266] The connection structure 218 mainly comprises a heat pipe fitting 231, a connection fitting 232, and a connection fitting 233. The connection fitting 232 and the connection fitting 233 etc. constitute a terminal connection portion 609. The connection portion 507 of the semiconductor element is inserted into the terminal connection portion 609.

[0267] Contact parts 225a and 225b are disposed between the connecting fitting 232 and the connecting fitting 233. Platinum, gold, silver, tungsten, copper, nickel, or an alloy of a combination thereof is used as the contact part 225. It is also preferable to use a silver-oxide contact material (Ag+ZnO, Ag+SnO2, Ag+SnO2In2O3, Ag+, Ag+SnO2Sn2Bi2O7).

[0268] Connection fitting 233 is fixed to heat pipe fitting 231 with fixing screw 224a. Connection fitting 232 is fixed to connection fitting 233 with fixing screw 224b. Connection part 507 of the semiconductor element is fixed by tightening fixing screw 224b. Connection wiring 211 is fixed to the left end of heat pipe fitting 231 with fixing screw 221.

[0269] 36 is an explanatory diagram of a state in which the connection portion 507 is connected to the connection structure 218. The connection portion 507 is sandwiched between the contact portion 225a and the contact portion 225b. The connection fitting 232 is fixed to the connection portion 507 by the fixing screw 224b.

[0270] The transistor 117 is fixed to a heating / cooling plate 134a, and is further sandwiched between heating / cooling plates 134b. The transistor 117 is appropriately maintained at a test temperature by the heating / cooling plates 134. A heat pipe 223 is attached in the recess 234.

[0271] A test constant current Id is applied from the connection structure 218 to the connection portion 507. The constant current Id is large, at several hundred amperes (A). The connection portion 507 usually has a relatively small area, and there is contact resistance between the contact portion 225 and the connection portion 507. Therefore, when a large current flows through the connection portion 507, heat is generated at the contact portion 225.

[0272] The heat is conducted to the transistor 117 being tested, overheating the transistor 117. Overheating may cause the transistor 117 to deteriorate or the connection part 507 to burn out. Heat is also generated in the electrode terminals 226 of the SOP 117 and QFN 117, and the generated heat is conducted through the connection board 514. The conducted heat increases the temperature of the connection part 507. Therefore, the heat generated at the contact part 225 needs to be dissipated quickly.

[0273] Connection structure 218 of the present invention has heat pipe 223. Heat generated at contact portion 225 is transferred by heat pipe 223. Therefore, heat at contact portion 225 is quickly removed from contact portion 225. In addition, heat from connection portion 507 and connection board 514 is removed.

[0274] A partition wall 217 is disposed between the C1 chamber and the C2 chamber. As shown in FIG. 37, an opening 216 is formed in the partition wall 217. A connection structure 218a1 is inserted into the opening 216a1, and a connection structure 218b1 is inserted into the opening 216b1. A connection structure 218a2 is inserted into the opening 216a2, and a connection structure 218b2 is inserted into the opening 216b2. A connection structure 218an is inserted into the opening 216an, and a connection structure 218bn is inserted into the opening 216bn.

[0275] 37, the P terminal of the transistor 117Q1 to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218a1. Also, the N terminal of the transistor 117Q1 to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218b1.

[0276] Similarly, the P terminal of the transistor 117Q2 to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218a2. Moreover, the N terminal of the transistor 117Q2 to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218b2.

[0277] Similarly, the P terminal of the transistor 117Qn to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218an. Moreover, the N terminal of the transistor 117Qn to be tested is sandwiched and electrically connected between the connection fitting 232 and the connection fitting 233 of the connection structure 218bn.

[0278] An electrostatic shield plate or electrostatic shield net is arranged on the partition 217, which blocks noise from the power supply 132 and the drive circuit system of the chamber B, and the noise is not applied to the chamber C1. In addition, noise generated by turning on and off the transistor 117 is not applied to the drive circuit system of the chamber B.

[0279] 38 is an explanatory diagram illustrating a connection state between the transistor 117 and the connection structure 218. The transistor 117 is fixed to the heating / cooling plate 134a. In reality, a surface plate 520, a positioning support plate 519, etc. are disposed or formed on the heating / cooling plate 134a, but these are omitted for ease of understanding and drawing.

[0280] Fixation is performed by a spring (not shown). Heat conductive grease or heat dissipating silicone oil compound may be applied for adhesion. If necessary, as shown in FIG. 36, a heating / cooling plate 134b is also placed above the transistor 117 so that the transistor 117 can be set to a predetermined temperature condition. Note that this is not limited to a spring, and any structure or mechanism that allows fixing may be used.

[0281] A connector 202 is connected to the terminals (emitter terminal e, gate terminal g, collector terminal c) of the transistor 117. A signal wiring 222 is drawn out to the connector 202. A control signal Vgs to be applied to the gate terminal g of the transistor 117 and a constant current Ic from a constant current circuit 118 are applied to the signal wiring 222.

[0282] Connection structure 218a is inserted into opening 216a of partition wall 217 from the C2 chamber side. Connection structure 218b is similarly inserted into opening 216b of partition wall 217 from the C2 chamber side. When connection structure 218 is inserted, connection portion 507 is sandwiched between connection fitting 232 and connection fitting 233. In this state, connection portion 507 of transistor 117 and connection structure 218 are electrically connected by tightening fixing screw 224b.

[0283] The transistor 117 to be tested must be fixed in close contact with the heating / cooling plate 134 or the like. In addition, the anisotropic conductive rubber 504 positions the electrode pattern 505 and the electrode terminal 226 for electrical connection, so it is difficult to remove them easily.

[0284] In the attachment of the transistors 117, a plurality of transistors 117 to be tested first are fixed to the heating / cooling plate 134 or the like. Next, the transistor 117 to be tested first is selected and the connection structure 218 is attached to the connection portion 507.

[0285] The selected transistor 117 is electrically connected to the connection portion 507 by inserting the connection structure 218 from the C2 chamber side into the opening 216 in which the selected transistor 117 is located.

[0286] Electrical connection with the transistor 117 is easy since it is only necessary to select the position for inserting the connection structure 218. In addition, by changing the signal applied to the connection wiring 211 connected to the connection structure 218, the test conditions and test contents of the transistor 117 can be easily changed.

[0287] 36, the connection portion 507 is clamped by applying pressure between the contact portions 225a and 225b. A connection wiring 211 is connected to one end of the connection structure 218, and a constant current Id is applied from the connection wiring 211 to the transistor 117. A heat pipe 223 is disposed on the back surface side of the connection structure 218.

[0288] A current of several hundred amperes (A) flows through connection portion 507. Even if there is a slight resistance in contact portion 225, a current of several hundred amperes (A) generates a large amount of heat, overheating connection portion 507. If this occurs, transistor 117 will also be overheated, causing transistor 117 to deteriorate or break down.

[0289] In the present invention, heat generated at contact point 225 is transferred to connection wiring 211 of connection structure 218 by heat pipe 223. Therefore, contact point 225 does not overheat. A cooling fan 229 is disposed below connection structure 218 to dissipate heat from heat pipe 223. FIG. 38 is an explanatory diagram for explaining a method for cooling the connection structure 218 in the semiconductor testing device of the present invention.

[0290] 38, a cooling fan 229 for removing heat from the heat pipe 223 is disposed on the back surface of the connection structure 218. The rotation speed of the cooling fan 229 is controlled according to the overheating state of the connection portion 507 and the heat pipe 223. FIG. 39 is an explanatory diagram for explaining a method of connecting a semiconductor element 117 and a connection structure 218 in the semiconductor testing device of the present invention.

[0291] A partition 217 is provided between the C1 chamber and the C2 chamber. An opening 216 is formed in the partition 217 in correspondence with the positions of the transistors 117 to be tested, etc., as shown in Fig. 37. The opening 216 of the partition 217 and a fixing base (not shown) of the connection structure 218 allow the connection structure 218 to be positioned horizontally or stably and fixed.

[0292] 39(a), the transistor 117 to be tested is positioned and fixed in close contact with the heating and cooling plate 134a. Thermally conductive grease and silicone oil compound for heat dissipation are applied between the transistor 117 and the heating and cooling plate 134a.

[0293] A detachable connector 202 is connected to the terminals (emitter terminal e, gate terminal g, collector terminal c) of the transistor 117. A signal wiring 222 is connected to the connector 202, and the signal wiring 222 is connected to a sample connection circuit 203.

[0294] The signal wiring 222 between the sample connection circuit 203 and the connector 202 is formed to be as short as possible. If the signal wiring 222 is long, noise is superimposed on the signal wiring 222, causing the transistor 117 to malfunction. For example, if noise is superimposed on the gate terminal g of the transistor 117, the transistor 117 may turn on and break down. The signal wiring 222 should be twisted or a shielded wiring such as a coaxial cable should be used.

[0295] 39(b), the connection structure 218a is inserted into the opening 216a. By inserting the connection structure 218a into the opening 216a, the connection portion 507a of the transistor 117 is sandwiched between the connection fitting 232 and the connection fitting 233 at the tip of the connection structure 218a. After the connection structure 218a and the connection portion 507a are coupled, the fixing screw 224b1 is tightened, whereby a good electrical connection can be achieved between the contact portion 225 and the connection portion 507.

[0296] Similarly, connection structure 218b is inserted into opening 216b. By inserting connection structure 218b into opening 216b, connection portion 507b of transistor 117 is sandwiched between connection fitting 232 and connection fitting 233 at the tip of connection structure 218b. After connection structure 218b and connection portion 507b are coupled, fixing screw 224b2 is tightened, thereby achieving good electrical connection between contact portion 225 and connection portion 507.

[0297] 38, the heat pipe 223 is attached to the recess 234 of the heat pipe metal fitting 231 of the connection structure 218. However, the present invention is not limited to this.

[0298] For example, a connection structure 218 may be configured as shown in Fig. 40. In Fig. 40, Fig. 40(a) is a schematic diagram of the back surface (lower surface) of the connection structure 218, and Fig. 40(a) is a schematic diagram of the front surface (upper surface) of the connection structure 218.

[0299] 40, heat pipe 223a is disposed on concave surface 234a. Heat pipe 223a is formed or disposed up to connecting fitting 233. By forming or disposing heat pipe 223a up to connecting fitting 233, heat generated at connecting portion 507 can be transferred more efficiently.

[0300] 40(b), the heat pipe 223b is disposed on the concave surface 234b. By disposing the heat pipes 223 on both sides of the connection structure 218, the heat generated at the connection portion 507 can be transferred more efficiently.

[0301] In the embodiment of Fig. 38, the heat pipe 223 and the like are cooled by the cooling fan 229, but the present invention is not limited to this. For example, as shown in Fig. 41, the heat dissipation fins 228 may be formed or arranged so as to be in close contact with the heat pipe 223. The heat transferred inside the heat pipe 223 is efficiently transferred to the heat dissipation fins 228, and the heat transfer and heat dissipation effect of the heat pipe 223 is further improved.

[0302] 41 is not formed or placed in a location corresponding to opening 216. Connection structure 218 is inserted from C2 chamber to C1 chamber through opening 216. In order to maintain the airtightness of C1 chamber, opening 216 has a size equal to the cross-sectional area of ​​connection structure 218 plus α. Therefore, if heat dissipation fin 228 is formed or placed on connection structure 218, it cannot be inserted into opening 216. Therefore, heat dissipation fin 228 is not formed or placed on the side connected to connection portion 507 of transistor 117 with partition wall 217 as the reference.

[0303] 42, a circulating water pipe 135 may be formed or disposed in the connection structure 218 to cool the connection structure 218. The connection structure 218 is cooled by the refrigerant flowing in the circulating water pipe, and the heat in the heat pipe 223 is efficiently transferred to the connection structure 218. Therefore, the heat generated in the connection portion 507 is efficiently dissipated.

[0304] In the transistor 117 (SOP 117, QFN 117, semiconductor element 117) in Fig. 1, the electrode terminal 226a is connected to the connection portion 507a, and the electrode terminal 226b is connected to the connection portion 507b, as shown in Fig. 3. Therefore, the connection portion 507 has two terminals, the connection portion 507a (P) and the connection portion 507b (N).

[0305] As shown in Fig. 6, the connection portion 507 of the transistor 117 may have three terminals, that is, a connection portion 507a (P), a connection portion 507b (N), and a connection portion 507c. As shown in Fig. 6, the electrode terminal 226a is connected to the connection portion 507a, the electrode terminal 226b is connected to the connection portion 507b, and the electrode terminal 226c is connected to the connection portion 507c. The semiconductor testing apparatus and semiconductor device testing method of the present invention are capable of testing a wide variety of semiconductor devices 117.

[0306] The semiconductor element 117 in FIG. 6 is, as shown in FIG. 4, a transistor 117m and a transistor 117s arranged in one SOP or QFN package.

[0307] A collector terminal cs of the transistor 117s is connected to a connection portion 507a. An emitter terminal es of the transistor 117s and a collector terminal cm of the transistor 117m are connected to each other, with the midpoint being connected to a connection portion 507c. An emitter terminal em of the transistor 117m is connected to a connection portion 507b.

[0308] An emitter terminal em, a gate terminal gm, and a collector terminal cm are connected to the transistor 117m, while an emitter terminal es, a gate terminal gs, and a collector terminal cs are connected to the transistor 117s.

[0309] FIG. 43 is an explanatory diagram illustrating the connection state between a transistor 117 (semiconductor element 117) having three connection portions 507 (connection portion 507a (P), connection portion 507b (N), and connection portion 507c (O)) and a connection structure 218.

[0310] 43, a placement recess 239 is formed or configured in a connection board 514, and an anisotropic conductive rubber 504a is placed in the placement recess 239. The anisotropic conductive rubber 504a electrically connects the signal terminal 227 and the electrode pattern 506. A pressing plate 515 is placed on the connection board 514, and the pressing plate 515 is pressed by a pressing head 530 via rubber (elastic material) 517.

[0311] In FIG. 43, the connection between connection structure 218a and connection portion 507a, and the connection between connection structure 218b and connection portion 507b are similar to those described in FIG. 38 and FIG. 39, and therefore description thereof will be omitted.

[0312] 43, heat pipe 223a is formed or disposed in connection structure 218a, and heat pipe 223b is formed or disposed in connection structure 218b, whereas heat pipe 223 is not formed or disposed in connection structure 218c. Connection structure 218c is connected to connecting portion 507c.

[0313] A large current does not flow through the connection portion 507c(O) of the transistor 117. Therefore, the connection portion 507c does not overheat. There is no need to form a heat pipe 223 in the connection structure 218c. By forming the connection structure 218c thinner than the other connection structures 218 (connection structure 218a, connection structure 218b), the connection between the connection structure 218 and the connection portion 507 of the transistor 117 becomes easy. In addition, since the space for arranging the transistor 117 can be narrow, the number of transistors 117 that can be mounted on the heating / cooling plate 134 can be increased.

[0314] Needless to say, the heat pipe 223 may be formed or disposed in the connection structure 218c. Other details are the same as or similar to the embodiments of Figures 38 and 39, and therefore description thereof will be omitted.

[0315] Fig. 58 is a schematic diagram of a thermal cycle test (thermal shock test) in an embodiment of the semiconductor device testing apparatus of the present invention. In Fig. 58, wiring electrodes 607a, 607b, and 607c are formed on an insulating substrate 602. A semiconductor chip 601 is connected to wiring electrode 607a with solder 605.

[0316] A bonding terminal (not shown) of the semiconductor chip 601 and the wiring electrode 607b are electrically connected by an aluminum wire 606. A wiring electrode 607c is formed or arranged on the back surface of the insulating substrate 602 and is connected to the copper base 604 by solder 605.

[0317] The thermal cycle test (thermal shock test) shown in Figure 58 is a test to predict the lifespan of a product or system against relatively gentle temperature changes that occur when the product or system is started or stopped.

[0318] In a power module 117 (a power semiconductor element, a power semiconductor chip, a module in which a semiconductor element is mounted), the case temperature (Tc) changes relatively slowly and significantly when the module is started and stopped. If this stress is repeated and a crack in the die bond (a bonding material such as solder) reaches the bottom of the power semiconductor chip, it will cause an increase in thermal resistance, leading to thermal runaway and destroying the power module.

[0319] The semiconductor device testing apparatus of the present invention heats the power module 117 from outside, heats the power module itself by heat generation, or cools the power module from the outside. Heating or cooling is performed by using cooling water or hot water from a chiller.

[0320] In the semiconductor device testing apparatus and semiconductor device testing method of the present invention, the temperature of the power semiconductor device (transistor, etc.) 117 is periodically changed in response to the test conditions, and the device is cooled to a constant temperature and heated to a constant temperature. Temperature information Tj of the transistor being tested is also measured, and chiller 136 is controlled to maintain the measured temperature information Tj at a constant value.

[0321] The chiller 136 is configured to keep the temperature of equipment, etc. constant by circulating water or heat transfer medium while controlling its temperature. It is mainly used for cooling, but it can also heat as well as cool. It is configured to be able to control various temperatures.

[0322] The control rack 131 includes a power supply device 132 that supplies a test current and a test voltage to a power semiconductor element 117 (such as a transistor), and a control circuit that controls the transistor 117 or sets test conditions.

[0323] The control circuit 132 receives transistor temperature information Tj and controls the chiller based on the temperature information Tj, or controls the chiller 136 so as to set the temperature information Tj to a predetermined value.

[0324] Although circulating water is described in this specification, it is not limited to water. Ethylene glycol, glycerin, freon, etc. may also be used, and forced air cooling may also be used. The chiller 136 controls the liquid in the circulating water pipe 135 to a temperature range of, for example, -1°C to +100°C, and supplies it to the cooling / heating heat sink of the test unit. The cooling / heating heat sink 134 has a sufficiently large thermal capacity.

[0325] Relatively gentle expansion and contraction occurs due to heating or cooling of the power module 117. The semiconductor element testing device of the present invention can set the temperature and cycle of cooling or heating. A durability test of the semiconductor module can be performed by adjusting the temperature and cycle. The number of test cycles can be set arbitrarily between 100 and 100,000 cycles. In addition, the cooling time and heating time can be set arbitrarily.

[0326] 59 is a schematic diagram of a power cycle test in the semiconductor device testing apparatus of the present invention. Tests on life and reliability can be performed in an operation pattern in which junction temperature changes occur frequently.

[0327] In the power cycle test, heat rises and falls depending on the operating conditions of the power semiconductor element 117. The change in the case temperature (molding resin of the semiconductor chip, the case of the module having the semiconductor chip 601, etc.) is small, and this is a test for the life span in an operating pattern in which the junction temperature changes frequently.

[0328] Heat generated from the semiconductor chip 601 is transferred through the aluminum wire 606 as shown by the arrow A, and the heat generated from the semiconductor chip 601 is transferred in the direction of the insulating substrate 602 as shown by the arrow B.

[0329] A power cycle test is an essential test item for the power semiconductor device 117 and the power semiconductor module 117. In the structure of the power module 117, when the operation of the power semiconductor 117 causes a temperature change in the joint, a crack occurs on the joint surface due to stress caused by the difference in linear expansion coefficient between the aluminum wire 606 and the power semiconductor chip (such as a silicon chip) 601.

[0330] If the cracks grow, they will lead to failure due to peeling. In particular, for power semiconductors117 used in inverters, it is necessary to take this power cycle failure into consideration from the equipment design stage.

[0331] The semiconductor element testing device of the present invention can arbitrarily set the rapid heat generation (expansion) temperature, change time, and retention time, as well as the cooling (contraction) temperature, change time, and retention time that accompany the operation of the power semiconductor element 117. Therefore, it is possible to easily realize a durability test against stress due to differences in linear expansion coefficients, etc.

[0332] The number of test cycles can be set arbitrarily between 100 and 100,000. In addition, the cooling time, heating time, holding time, and temperature change time can be set arbitrarily. The method for testing a semiconductor device according to the present invention will be described below. Figures 44, 45 and 46 are explanatory diagrams of the method for testing a semiconductor device according to the present invention.

[0333] A constant current circuit 118 supplies a constant current Ic to the diode Di of the transistor 117. An operational amplifier circuit 116 buffers and outputs a terminal voltage Vi of the diode Di. The terminal voltage Vi is applied to a temperature measurement circuit 115, which determines temperature information Tj of the transistor 117 from the terminal voltage Vi and transfers it to the controller circuit board 11. The temperature information is output from a connector 213 of the device control circuit board 209 to the mother board 207 and sent to the control circuit board 111 (see FIG. 28, etc.).

[0334] The semiconductor device testing apparatus and the semiconductor device testing method of the present invention realize a noise control technique. The noise control technique implements an inrush current removal method and a surge voltage removal method. Fig. 61 is an explanatory diagram of the inrush current removal method. Fig. 62 is an explanatory diagram of the surge voltage removal method.

[0335] New devices such as SiC / GaN have low on-resistance and high-speed switching performance. Due to their characteristics, they react sensitively to switching noise (surge, etc.) even during power cycle testing. Therefore, since there is a risk of device destruction, it is important to control noise as a test device or test method.

[0336] The noise control method, inrush current elimination method, surge voltage elimination method, etc. specifically implement the test methods described in Figures 46, 48, 51, and 52, and the implementation circuits use the configurations or operations of Figures 28, 29, 44, 45, 49, 50, and 51. Due to improvements in the performance of semiconductor elements or in response to demands for higher functionality, the margin for designing circuits using power semiconductor elements is decreasing.

[0337] In particular, the low on-resistance and high switching speed of new devices such as IGBT, SiC, and GaN increase switching noise, which can cause device destruction due to noise (surge, etc.). In the semiconductor device testing apparatus of the present invention, techniques such as noise control have been established, making it possible to realize a testing state that is not affected by inrush currents and surge voltages.

[0338] In the inrush current removal method shown in FIG. 61, as shown in FIG. 44, FIG. 45, FIG. 49, FIG. 50, FIG. 51, etc., a switching circuit board 201 consisting of a MOS transistor or the like as a switching element is arranged or connected between the drain terminal and source terminal (between channels) of a power semiconductor element 117 (power transistor) to be tested.

[0339] When the switch circuit 124b of the switch circuit board 201a is turned on, the drain terminal and the source terminal of the transistor 117 are short-circuited. Due to the short-circuit, no voltage or current is applied between the channels of the transistor 117. Furthermore, when the switch circuit 124b is turned on, the output terminals of the current power supply device 121 that supplies a test current to the transistor 117 are short-circuited, causing the charge to be discharged.

[0340] When the switch circuit 124b is turned on, a current flows, discharging the charge of the current power supply device 121. Alternatively, the current output by the current power supply device 121 flows to the ground via the switch circuit 124b.

[0341] When an inrush current Is flows through the transistor under test, the transistor is destroyed by the inrush current Is or surge voltage Vs. To prevent the inrush current Is or surge voltage Vs from occurring, the switch circuit is controlled to turn on and off and the on / off sequence is controlled.

[0342] 61, in the conventional example, a current (drain current Id) flowing between the channels of a transistor occurs as an inrush current. In the present invention, by controlling the switch circuit 124, etc., no inrush current occurs.

[0343] Similarly, a surge voltage can be removed by controlling the switch circuit 124. As shown in Fig. 62, in the conventional example, a surge voltage occurs between the drain terminal and the source terminal of the transistor 117, but in the present invention, the surge voltage can be removed by controlling the switch circuit board 201. The semiconductor element testing apparatus (power cycle tester) and the semiconductor element testing method of the present invention are capable of measuring saturated thermal resistance.

[0344] The power cycle tester has multiple functions, allowing you to measure the saturation thermal resistance at any set current and / or voltage, as well as cycle time, number of cycles, and simultaneous measurement of multiple devices.

[0345] The thermal resistance of a semiconductor package is the amount of heat generated per 1W of power. With a power cycle tester, the thermal saturation resistance can be measured from the junction temperature (Tj) and ambient temperature (Ta) in a thermally saturated state at a specified power. The test flow is as follows: 1. Input the Ic (Id) current and Vce (Vds) voltage as the test conditions. 2. By starting the saturated thermal resistance test, the ambient temperature (temperature before power is applied) and the junction temperature are measured. 3. Calculate the thermal resistance from steps 1 and 2 above. The thermal resistance value in the thermally saturated state is displayed. Rth=Tj-Ta / Pd however, Rth: Saturation thermal resistance (℃ / W) Tj: Junction temperature (℃) Ta: Temperature before energization (℃)

[0346] The power cycle tester allows you to set the gate voltage according to the power control conditions. The gate voltage can be automatically varied to set the Vce voltage for the test conditions. The setting flow is as follows: 1.Applied current: Specify Ic (Id). 2. Specify the test power. 3. When the test starts, the gate voltage is automatically adjusted to suit the specified power. By using this gate voltage, testing can be easily performed at the collector-emitter voltage (Vce) and drain-source voltage (Vds) that match the test conditions.

[0347] Fig. 63 is a graph showing the measurement of the saturated thermal resistance transition of eight devices (Dev1 to Dev8). The power cycle tester of the present invention can simultaneously measure the saturated thermal resistance transition of many power devices and visualize it on a display or the like. It is also possible to print it out on a printer.

[0348] The semiconductor device testing apparatus and the semiconductor device testing method of the present invention can perform a short pulse power cycle test. Figure 64 shows an example of a measured waveform when measuring a power cycle test using a current pulse.

[0349] Fig. 64(a) shows a gate voltage waveform applied to the gate terminal g of the semiconductor element 117 to be tested. The gate voltage is generated in the device control circuit board 209 and applied to the semiconductor element 117 from the sample connection circuit 203. The gate on-time ta and cycle tc can be variably set by the device control circuit board 209. Also, while 0(V) is the off-voltage, it may be necessary to lower the off-voltage level depending on the type of semiconductor element 117. In the semiconductor testing apparatus of the present invention, in addition to the first off-voltage of 0(V), the magnitude of the second off-voltage Vt and the application time tn2 can be set.

[0350] Fig. 64(b) is a graph showing a current (voltage) waveform applied to the collector terminal c or drain (source) terminal of the semiconductor element 117 to be tested. The current (voltage) to be applied can be realized by controlling the switch circuit 124a of the switch circuit board 201b of Fig. 45 etc. The lengths and timings of the te time, td time, and tf time in Fig. 62(b) can be set and controlled by the operation timing of the switch circuit 124a.

[0351] The semiconductor testing equipment of the present invention can perform power cycle testing using current pulses of as short as 10 ms (milliseconds). Even when a 10 ms pulse current is applied, the surge absorption circuit absorbs the surge current / voltage that occurs when the current is turned on / off, preventing damage to the test device.

[0352] In addition, measurement data can be logged during 10 ms pulse testing. For example, accurate Tj measurement is possible for devices equipped with temperature sensing diodes even when a 10 ms pulse current is applied. This makes it possible to trace the process leading up to the breakdown of semiconductor elements.

[0353] The semiconductor device testing apparatus and semiconductor device testing method of the present invention can implement the test methods in accordance with the JEITA, IEC, and AQG324 guidelines shown in FIG. The semiconductor device testing apparatus and the semiconductor device testing method of the present invention are capable of carrying out a pulsed power cycle test. Conventional semiconductor device testing apparatus and methods for testing semiconductor devices can only perform tests that involve turning transistors on and off.

[0354] For example, as shown in Fig. 66(a), a power semiconductor element (transistor, etc.) is turned on to cause a predetermined current to flow. Then, as shown in Fig. 66(b), the temperature of the power semiconductor element gradually rises from t1 when current is applied. At t2, the current Ia becomes constant. At t3, the power semiconductor element is in the on state, so the temperature exceeds the target temperature Ta.

[0355] To lower the temperature, it is necessary to change the cooling water temperature, etc. It takes time to change the cooling water temperature, and the specified test state cannot be maintained for the period during which the cooling water temperature exceeds the target temperature. The present invention allows the transistor to be pulsed not only during the on and off times, but also during the on time of the transistor.

[0356] Fig. 67 is an explanatory diagram of the semiconductor device testing device and the semiconductor device testing method of the present invention. As shown in Fig. 67(a), by changing or controlling any of the cycle Tc, on-time ton, and off-time toff of the power semiconductor device, the time and interval during which a predetermined current flows through the power semiconductor device can be precisely controlled.

[0357] FIG. 67(a) shows an example in which the on-time ton1 and the off-time toff1 are set during the same cycle time tc, and then at time t4, the settings are changed to the on-time ton2 and the off-time toff2.

[0358] As shown in FIG. 67, the semiconductor testing device of the invention can acquire temperature information Tj in real time, compare it with a target temperature Ta, and perform testing of semiconductor elements. In Figures 64 and 67, ta, tc, and te are illustrated as being the same time, but it goes without saying that they may be changed with time.

[0359] By turning on the power semiconductor element 17 (transistor, etc.), a predetermined current flows. As shown in Fig. 67(b), the temperature of the power semiconductor element 117 gradually increases. If the power semiconductor element 117 is in the off state, the temperature of the power semiconductor element 117 decreases. When the temperature of the power semiconductor element 117 reaches the target temperature Ta, the power semiconductor element 117 is turned off, and when the temperature of the power semiconductor element 117 exceeds the target temperature Ta, the power semiconductor element 117 is turned off. The present invention can identify the location of a failure caused by pulse current passing. The semiconductor device testing apparatus of the present invention can also perform a pulse-type continuous current passing test.

[0360] In conventional continuous current tests, a direct current is applied, so if the sample generates a large amount of heat, it is not possible to apply the current up to the specified level. However, by changing the duty ratio of the pulse current method of the present invention, it is possible to test at a specified current density.

[0361] An on-voltage Vg that turns on the gate of the transistor 117 at a set frequency and for a set on-voltage time is output from the gate driver circuit 113. As an example, as shown in Fig. 46(a), the on-off cycle of the transistor 117 is tcycle, the on time is ton, and the off time is toff.

[0362] 46(a), the transistor 117 is controlled to be turned on and off. The gate driver circuit 113 is controlled by a gate signal control circuit 112. The current source 121 outputs a constant current Id, which is supplied to the transistor 117 .

[0363] The transistor 117 is turned on and off by the Vgs signal voltage output from the gate driver circuit 113, and a current Id flows between the channels of the transistor 117 while the transistor 117 is on.

[0364] The gate driver circuit 113 has an internal variable resistance circuit 125. The value of the variable resistance circuit 125 is configured so that it can be set to a predetermined value or in steps between 0 (Ω) and 500 (Ω). The value of the variable resistance circuit 125 may be set by a control signal from the control circuit board 111 while observing the waveform of the gate terminal g.

[0365] A resistor R (not shown) may be disposed between the gate terminal g and the emitter terminal e or the collector terminal c of the transistor 117. By adjusting the value of the resistor R, the inclination angles of the rising and falling voltage waveforms of the gate signal can be adjusted.

[0366] When the value of the variable resistance circuit 125 is large, the slope of the rising / falling waveform of the gate signal of the transistor 117 applied to the gate terminal of the transistor 117 becomes gentler.

[0367] On the other hand, when the resistance value of the variable resistance circuit 125 is small, the slope of the rising / falling waveform of the gate signal becomes steeper. By changing the resistance value of the variable resistance circuit 125 or setting it to a predetermined value, the on-time of the transistor 117 can be adjusted.

[0368] The gate driver circuit 113 can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) in the gate voltage applied to the gate terminal g of the transistor 117. By separately adjusting the rise time Tr and the fall time Td, the on time of the transistor 117 can be adjusted arbitrarily.

[0369] The resistance value of the variable resistance circuit 125 is set by the control circuit board 111. The setting is not limited to a constant value. The slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate driver circuit 113 may be changed. The resistance value at the rising edge and the resistance value at the falling edge of the gate signal may be changed. Also, the resistance value may be variably controlled in real time. By variably controlling the variable resistance circuit 125, the on-time of the transistor 117 is stabilized.

[0370] Reducing the resistance value at the rising edge of the gate signal makes the waveform of the on-voltage applied to the gate terminal of transistor 117 steeper, quickly turning on transistor 117. Reducing the resistance value at the rising edge of the gate signal makes the waveform of the on-voltage applied to the gate terminal of transistor 117 gentler, slowly turning on transistor 117.

[0371] Reducing the resistance value when the gate signal falls makes the waveform of the on-voltage applied to the gate terminal of transistor 117 steeper, quickly turning off transistor 117. Reducing the resistance value when the gate signal falls makes the waveform of the on-voltage applied to the gate terminal of transistor 117 gentler, and transistor 117 turns off more slowly.

[0372] As described above, it is possible to control, adjust, or set the value of the variable resistance circuit connected to the gate terminal of the transistor 117, or the rise time / fall time of the gate driver circuit 113. Therefore, as a function of the gate driver circuit 113, it is possible to change or modify the inrush current Is and surge voltage Vs generated in the transistor 117.

[0373] Needless to say, the operation of the transistor 117 can be controlled not only by controlling the on-voltage of the gate terminal of the transistor 117, but also by changing or setting the value of the constant current Id or voltage Vm supplied to the transistor 117 by the current power supply device 121.

[0374] The variable resistance circuit 125 of the gate driver circuit 113 is controlled by the control circuit board 111. The cycle time tcycle, on time ton, and off time toff of the gate signal output by the gate driver circuit 113 shown in FIG. 46 are controlled by a gate signal control circuit 112, and the gate signal is applied to the gate terminal of a transistor 117. In addition, the gate signal control circuit 112 is controlled by the control circuit board 111.

[0375] 44, 45, etc., the resistance value of the variable resistance circuit 125 of the gate driver circuit 113 is variable, but this is not limited to this. For example, it goes without saying that the variable resistance circuit 125 may be an external resistor, and the resistor may be connected to the gate terminal of the transistor 117 by a connector (not shown) or the like. The value of the resistor to be connected is set by observing the waveform of the gate terminal of the transistor 117 and the waveform of the channel current Id.

[0376] 44, 45, etc., a constant current circuit 118 is connected between a collector terminal c and an emitter terminal e of a transistor 117. The constant current circuit 118 passes a predetermined constant current Ic. The constant current Ic is for monitoring the temperature of the transistor 117.

[0377] In addition, since the present specification will be described taking an IGBT as an example, the terminals of the transistor 117 are a gate terminal g, a collector terminal c, and an emitter terminal e. In the case of a MOS transistor 117, the terminals of the transistor 117 are a gate terminal g, a drain terminal d, and a source terminal s.

[0378] A body diode or a channel diode Di is formed in the transistor 117. Note that the diode Di may be a diode of a separate semiconductor chip mounted on the semiconductor chip on which the transistor 117 is formed.

[0379] The diode Di may be a diode (parasitic diode) formed secondarily when the transistor 117 is formed. The parasitic diode is formed secondarily due to the layer structure of the transistor 117. The diode Di is formed near the channel portion of the transistor 117 due to its structure.

[0380] The diode Di may be any element that does not operate when the transistor 117 is operating. For example, it is not limited to a diode, and it goes without saying that a transistor connected as a diode may also be used.

[0381] In addition, the device is not limited to a semiconductor such as a diode, but may be a device such as a resistor. A constant current Ic is applied to a device such as a resistor to measure the terminal voltage of the resistor. This voltage is measured as voltage Vi.

[0382] As described above, the element for acquiring the temperature may be not only a semiconductor device, but also a resistor, etc. In other words, any device that can acquire a voltage value by passing a current or a current value by applying a voltage can be used.

[0383] The resistance value of diode Di changes due to heat generation by transistor 117. When a constant current Ic flows through diode Di, the voltage across the terminals of diode Di changes in proportion to the change in the resistance value of diode Di. By monitoring or measuring the voltage across the terminals, the temperature or temperature change of transistor 117 can be known. In order to monitor the temperature of the transistor 117 from the voltage of the diode Di, it is necessary to obtain the temperature coefficient in advance.

[0384] The temperature coefficient is measured by setting the transistor 117 at a predetermined temperature in a thermostatic chamber, passing a constant current Ic through the diode Di, and measuring the terminal voltage of the diode Di. The terminal voltage of the diode with respect to temperature can be obtained by varying the predetermined temperature and measuring the terminal voltage of the diode Di. Therefore, the temperature coefficient K of the transistor 117 can be obtained from the terminal voltage of the diode Di with respect to temperature.

[0385] The temperature coefficient K may differ for each production lot of the transistor 117, but generally it is a constant value for each production lot. Therefore, if the transistor 117 to be tested is sampled from each production lot and the temperature coefficient K is calculated, the temperature coefficient K can be used for the other transistors 117.

[0386] To obtain the temperature coefficient K with high accuracy, the temperature coefficient K of each transistor 117 is measured and tested individually, even for the same lot. Measurement of the temperature coefficient K is not limited to using a thermostatic bath. For example, the temperature coefficient K is obtained by changing the temperature of the water flowing through the heat sink on which the transistor 117 is mounted.

[0387] During testing, a test current Id is intermittently applied to the transistor 117. Immediately after the test current Id is turned off, or after a short, predetermined time has elapsed since the test current Id was turned off, a constant current Ic for temperature measurement is caused to flow from a constant current circuit 118.

[0388] In order to prevent the constant current Ic from heating the transistor 117 or to avoid any influence of the constant current Ic, the constant current Ic is set to a current value sufficiently smaller than the constant current Id passed through the channel of the transistor 117. The constant current Id is set to a current value that does not generate heat that would affect the temperature measurement.

[0389] Specifically, the constant current Ic is set to 1 / 1000 or less of the current Id passed through the transistor 117 during testing. Preferably, the current Ic passed through the transistor 117 is set to 1 / 100000 or more and 1 / 10000 or less of the current Id. The constant current Ic is set to 0.1 mA or more and 100 mA or less.

[0390] The channel current Id is changed, and the diode Di voltage (the voltage between the collector and emitter terminals of the transistor 117) is measured to obtain the temperature coefficient K. The obtained temperature coefficient K is stored in the temperature measurement circuit 115.

[0391] When measuring temperature, if the diode Di is formed on the same chip as the transistor 117, the saturation voltage Vn may change depending on the gate voltage Vgs. It is preferable that the gate voltage Vgs is zero (0) voltage or a negative voltage (minus voltage).

[0392] 27, based on the temperature information Tj, the control circuit board 111 controls the chiller 136. The chiller 136 adjusts the temperature of the circulating water (circulating solution), and adjusts the temperature of the heating / cooling plate .

[0393] In the above embodiment, the temperature coefficient K is calculated in advance, but the semiconductor testing method of the present invention is not limited to this. Temperature information Tj of the transistor 117 is calculated from the temperature coefficient and the diode terminal voltage, etc. The transistor 117 is disposed in close contact with the heating / cooling plate 134 , and the temperature of the heating / cooling plate 134 is configured to be approximately equal to that of the transistor 117 .

[0394] The control circuit board 111 controls the chiller 136 to set the temperature of the heating / cooling plate 134 to a predetermined temperature, applies a constant current Ic to the transistor 117, and measures the terminal voltage of the diode Di.

[0395] From the measurement results, the temperature coefficient K is obtained. The temperature of the heating / cooling plate 134 is set to a plurality of temperatures, the temperature coefficient K is obtained at each temperature, and the accuracy of the temperature coefficient value is improved from the results.

[0396] The temperature coefficient K is obtained by heating the transistor 117 to a predetermined temperature using the heating / cooling plate 134, passing a constant current Ic through the diode Di, and measuring the terminal voltage. The terminal voltage of the diode Di versus temperature can be obtained by varying the predetermined temperature and measuring the terminal voltage of the diode Di. Therefore, the temperature coefficient K of the transistor 117 can be obtained from the terminal voltage of the diode Di versus temperature.

[0397] When testing the transistor 117, the constant current Ic is caused to flow through the diode Di when the channel current Id is not flowing. In other words, when the transistor 117 is not turned on, the constant current Ic is caused to flow and the voltage across the diode Di is measured.

[0398] The operational amplifier circuit (buffer circuit) 116 outputs the terminal voltage Vi (terminal c-terminal e) of the diode Di. The operational amplifier circuit 116 is not limited to being composed of an operational amplifier element. Any circuit having high input impedance and low output impedance may be used. The temperature measurement circuit 115 obtains temperature information Tj of the transistor 117 being tested from the stored temperature coefficient K and voltage Vi.

[0399] The obtained temperature information Tj is sent to the control circuit board 111. When the temperature information Tj becomes equal to or exceeds a predetermined set value, the control circuit board 111 determines that the transistor 117 is in a predetermined stress state or deteriorated state, and changes the control of the test or stops the test.

[0400] In most cases, the parts of the transistor that deteriorate during testing are mainly the junctions within the transistor 117. The semiconductor itself does not deteriorate, but the junctions (bonding, die bonding, etc.) of the transistor 117 deteriorate, causing the resistance value of the junctions to increase. As the resistance value increases, the voltage Vce increases, generating heat and raising the temperature of the transistor 117.

[0401] When a semiconductor deteriorates, it is often the deterioration of the gate oxide film (insulating film) of the transistor 117. When the gate oxide film deteriorates, the oxide film (insulating film) is short-circuited and the voltage Vce drops. Alternatively, the transistor 117 is turned off, no current flows through the transistor 117, and the voltage Vce rises to the maximum value of the power supply voltage.

[0402] At the start of the test, the temperature information Tj varies between the minimum temperature T1 and the maximum temperature T2. When the transistor 117 is subjected to stress by the test, the Vce voltage of the transistor 117 varies, and the temperature information Tj usually varies in the increasing direction. Therefore, as shown in FIG. 47(c), the minimum temperature rises above temperature T1, and the maximum temperature approaches temperature information Tm (Tjmax). In the semiconductor testing method of the present invention, the test is terminated under any of the following conditions: When the temperature information Tj falls outside the specified range. When the channel voltage Vce falls outside the specified voltage range. If the thermal resistance is outside the specified range.

[0403] In the embodiments of Figures 44, 45, etc., the switch circuit Ssa124a and the switch circuit Sab124b use the symbols for the switch circuits. Any element can be used as the switch circuit for the switch circuit Ssa124a and the switch circuit Sab124b as long as the resistance (on resistance) when closed (on) is small. Examples include a transistor, a mechanical relay, a phototransistor, a photodiode switch, etc.

[0404] Fig. 45 is an equivalent circuit diagram of the semiconductor testing device in the first embodiment of the present invention. In this embodiment, the switch circuit Ssa and the switch circuit Sab use a power MOSFET 124 as shown in Fig. 45. The voltage (Vsd) between the channels of the power MOSFET is small.

[0405] It is to be noted that the switch circuits may be other than power MOSFETs. It goes without saying that the switch circuits Ssa and Sab may be power transistors or the like, in addition to power MOSFETs. Other examples include electromagnetic relays and electromagnetic switches.

[0406] The channel voltage (Vsdb) of the power MOSFET 124b when it is on is selected to be equal to or lower than the channel voltage (Vsda) of the power MOSFET 124a when it is on. In other words, the channel voltage (Vsdb) of the power MOSFET 124b when it is on is set to be smaller than the channel voltage (Vsda) of the power MOSFET 124a when it is on. This is to completely short-circuit the terminals of the current power supply device 121 when the switch circuit 124b is turned on, and to stably flow the current Im. The above also applies when the switch circuit 124 is a power transistor, etc. In the case of the power transistor 124, the channel voltage is Vce. When the switch circuit 124a is turned on, the current Id output by the current power supply device 121 can be supplied to the transistor 117 as a test current.

[0407] The switch circuit 124 is mounted on a switch circuit board 201. The switch circuit 124 is connected to a conductor plate 204 (metal plate, conductive plate). The conductor plate 204 is, for example, a copper plate having a thickness of 5 mm and a width of 50 mm. The length of the conductor plate 204 is the width of the circuit board plus the width for connecting the fork plug 205.

[0408] 31 illustrates the fork plug 205 and the connection (contact) state between the fork plug 205 and the conductor plate 204. Two conductor plates 204 are attached to the switch circuit board 201. The switch circuit board 201 has a full-surface earth layer (not shown), which is thermally connected to the conductor plate 204. Heat from the conductor plate 204 is dissipated via the full-surface earth layer. The conductor plate 204 and the switch circuit board 201 are secured with screws.

[0409] The switch circuit 124 is connected to two conductor plates. As shown in Fig. 45, when the switch circuit 124 is a MOS transistor, the drain terminal and the source terminal are connected to different conductor plates 204. When the switch circuit 124 is a bipolar transistor, the collector terminal and the emitter terminal are connected to different conductor plates 204. When the switch circuit 124 is turned on (conductive), the two conductor plates 204 are electrically connected. An IGBT can also be used as the switch circuit 124.

[0410] Fork plug 205 and conductor plate 204 are electrically connected by mechanically fitting them together. When the U-shaped portion of fork plug 205 is inserted into conductor plate 204, the U-shaped portion expands slightly, and fork plug 205 and conductor plate 204 are satisfactorily joined. The satisfactorily joined or fitted portion has extremely low electrical resistance at the connection, and no heat is generated or voltage drops occur even when a large current flows through the connection portion.

[0411] A connection bolt 219 is attached to the fork plug 205. A connection wiring 211 is connected to the connection bolt 219. A cross section taken along line AA' in Fig. 31(a) is shown in Fig. 31(b). The conductive plate 204 and the fork plug 205 are in contact with each other at contact parts 220a and 220b formed on the fork plug 205. The surface of the contact part 220 is silver plated. The contact part 220 is made of phosphor bronze and nickel alloy. The connection bolt 219 is not limited to a bolt, and may be anything that can electrically connect the fork plug 205 and a wire. At least the surface of the conductive plate 204 that comes into contact with the fork plug 205 is plated with silver.

[0412] 30 is a configuration diagram of a semiconductor testing device of the present invention. A connection structure 218a is inserted into an opening 216a of a partition wall 217, and a connection structure 218b is inserted into an opening 216b of the partition wall 217.

[0413] The connection structure 218a is connected to the connection portion 507a of the transistor 117, and the connection structure 218b is connected to the connection portion 507b of the transistor 117. A circulating water pipe 135 is built into the heating / cooling plate .

[0414] A connector 202 is connected to a terminal of the transistor 117, and a signal wiring 222 connected to the connector 202 is connected to a sample connection circuit 203. A signal wiring 235 of the sample connection circuit 203 is connected to a device control circuit board 209 via a connector 208.

[0415] 30 etc., the fork plug 205 and the conductor plate 204 are brought into contact with each other by inserting the fork plug 205 through the opening 216 of the partition wall 214. At the time of contact, the U-shaped portion of the fork plug 205 is expanded by the conductor plate 204, and a firm contact is made.

[0416] 29 shows a layout diagram of each component of the semiconductor testing device of the present invention. The housing 210 of the semiconductor testing device is separated into three parts. The lower part of the housing is separated into chamber A and chamber B. The power supply unit 132 is placed in chamber A. Chamber A and chamber B are separated by a partition wall 215.

[0417] Each chamber is shielded. The power supply device 132, switch circuit board 201, and transistor 117 generate large noise as they repeatedly operate and deactivate. Since noise can cause the circuit boards and other components to malfunction, the shielding prevents such malfunctions. The shielding is achieved by placing conductive plates, metal plates, and metal films around each chamber.

[0418] In the C1 room, a heating / cooling plate 134, a circulating water pipe 135, etc. shown in FIG. 27 are arranged, and a transistor 117 to be tested is arranged on the heating / cooling plate 134.

[0419] Partition walls 214 are formed between chamber C1 and chambers A and B. A water leakage sensor (not shown) is arranged around the heating and cooling plate in chamber C1. If circulating water (cooling medium) or the like leaks, the water leakage sensor will trip and stop the semiconductor testing equipment or sound an alarm.

[0420] In addition, a drainage groove is formed around the heating and cooling plate, so that if circulating water (cooling medium) leaks from the heating and cooling plate, the circulating water (cooling medium) flows into the drainage groove and is discharged outside the semiconductor testing equipment. As described above, the partition wall 214 is configured so that even if the circulating water pipe 135 is damaged, the circulating water (cooling medium) and the like will not leak into the lower chambers A and B.

[0421] A partition 215 is formed between chamber A in which the power supply unit 132 is disposed and chamber B in which the drive circuit system is disposed. Electrostatic shielding plates are disposed in the partitions 214, 215, and 217 to block noise from the power supply unit 132 and prevent the noise from being applied to the drive circuit system in chamber B.

[0422] In the embodiment of the present invention, the fork plug 205 is inserted from the C2 chamber and connected to the conductive plate 204 in the B chamber. The operation of pushing the fork plug 205 from the top to the bottom is easy. However, the present invention is not limited to this. For example, the conductive plate 204 may be placed in the C2 chamber, and the fork plug 205 may be inserted from the B chamber to establish an electrical connection. Furthermore, the connection structure 218 is inserted from the C2 chamber, and the connection portion 507 of the semiconductor element 117 and the connection structure 218 are connected.

[0423] 29 and other drawings, the connection structure 218 is inserted from the C2 chamber into the C1 chamber, and electrically connected to the connection portion 507 of the transistor 117. Furthermore, the fork plug 205 is inserted from the C2 chamber into the B chamber, and electrically connected to the fork plug 205 and the conductor plate 204. The transistor 117 is fixed to the heating / cooling plate 134, and the switch circuit board 201 is fixed at the position of the mother board 207. The connection structure 218 and the fork plug 205 are electrically connected by the connection wiring 211.

[0424] The position of the opening 216 can be selected with the connection structure 218 to select the transistor 117 to be tested. By selecting the opening into which the fork plug 205 is inserted, the switch circuit board 201 to be controlled can be easily selected and the test method and test conditions can be changed. Therefore, by using the connection structure 218 and the fork plug 205 in the present invention, the transistor 117 can be easily selected and the test method, etc. can be changed in a short time.

[0425] The partitions 214, 215, and 217 may be wall-shaped structures, plate-shaped structures, film-shaped objects, mesh-shaped objects, wire net-shaped objects, etc. One example is phenolic resin (phenolic resin, phenol-formaldehyde resin, phenolic resin). The partitions may be any object that separates the first and second parts of the semiconductor testing device.

[0426] 28, a connector 213 is attached to a motherboard 207. A control circuit board 111, a device control circuit board 209, and a switch circuit board 201 are attached to the connector of the motherboard 207. The number of switch circuit boards 201 to be prepared according to the number of transistors 117 to be tested can be easily realized by changing the number of switch circuit boards 201 to be attached to the motherboard 207.

[0427] The gate terminal g, collector terminal c, emitter terminal e, etc. of the semiconductor element 117 are electrically connected by anisotropic conductive rubber 504a. The electrical connection is performed by a pressing head 530 or the like, as shown in FIG.

[0428] Temperature information Tj, voltage Vi, a control signal for the variable resistance circuit 125, a control signal for the constant current circuit 118, etc. are transmitted to the mother board 207. In addition, power supply wiring and ground wiring for each circuit are formed and supplied to each circuit board via a connector 213. The conductive plate 204 is disposed so as to protrude from the switch circuit board 201. A fork plug 205 is connected to this protruding portion.

[0429] The fork plug 205a is connected to the conductor plate 204a of the switch circuit board 201a. The power supply wiring 212 is connected to the switch circuit board 201a through an opening 216 in the partition wall 215. The fork plug 205d is connected to the conductor plate 204c of the switch circuit board 201b. The power supply wiring 212 is connected to the switch circuit board 201b through an opening 216 in the partition wall 215. The fork plug 205b is connected to the conductor plate 204b of the switch circuit board 201a. The power supply wiring 212 is connected to the switch circuit board 201a through an opening 216 in the partition wall 215.

[0430] 44, etc., a switch circuit 124a is disposed between the conductor plate 204d and the conductor plate 204c of the switch circuit board 201b, and short-circuits the conductor plate 204d and the conductor plate 204c. By short-circuiting, the current Id output by the current power supply device 121 is supplied to the transistor 117 as a test current.

[0431] A switch circuit 124b is disposed between the conductor plates 204a and 204b of the switch circuit board 201a, and when the switch circuit 124b is turned on, the conductor plates 204a and 204b are short-circuited. When this is done, the current Id output by the current power supply device 121 flows to the ground as a discharge current Im, and the channels of the transistor 117 are short-circuited. When the channels are short-circuited, no overvoltage or overcurrent is applied to the transistor 117.

[0432] A fork plug 205 is connected to the conductive plate 204. A fork plug 205c is connected to the conductive plate 204b. A fork plug 205b is connected to the conductive plate 204a. A fork plug 205e is connected to the conductive plate 204d. A fork plug 205d is connected to the conductive plate 204c.

[0433] Fig. 31 is a configuration diagram of fork plug 205. Fig. 31(a) shows a state in which conductor plate 204 attached to switch circuit board 201 and fork plug 205 are coupled together. Fig. 31(b) shows a coupled state of conductor plate 204 and fork plug 205 when a cross section taken along line AA' in Fig. 31(a) is viewed from the direction of the arrow.

[0434] The fork plug 205 is made of a metal such as aluminum, stainless steel, or copper. The surface is nickel-plated and then silver-plated. The fork plug 205 has a threaded groove, and is configured so that the connection wiring 211 can be attached to the fork plug 205 with a connection bolt 219.

[0435] The convex contact portion 220 is made of phosphor bronze or copper alloy. The surface of the contact portion 220 is silver plated. The insertion force of the fork plug 205 into the conductive plate 204 is set to be 40 to 60 N.

[0436] Platinum, gold, silver, tungsten, copper, nickel, or alloys of combinations thereof may be used for the contact portion 220. It is also preferable to use silver-oxide contact materials (Ag+ZnO, Ag+SnO2, Ag+SnO2In2O3, Ag+, Ag+SnO2Sn2Bi2O7).

[0437] Although two switch circuit boards 201 are shown in FIG. 28, two or more switch circuit boards 201 may be required depending on the number of transistors 117 to be tested, and the switch circuit boards 201 are connected to connectors 213 of a mother board 207.

[0438] As shown in FIG. 30, the fork plug 205c is inserted through an opening 216 in a partition wall 214 provided between the C2 chamber and the B chamber, and the conductor plate 204b and the fork plug 205c are connected. The transistor 117 to be tested and the heating and cooling plate 134 are arranged in the C1 chamber, and a driving circuit for testing the transistor 117 and the like are arranged in the B chamber. Since the C1 chamber, the C2 chamber, and the B chamber are separated by the partition wall 214, even if the refrigerant liquid leaks from the heating and cooling plate 134, it will not leak into the B chamber. A water leakage sensor (not shown) is arranged around the heating and cooling plate 134. In addition, a groove is formed to discharge the refrigerant liquid to the outside of the testing device if the refrigerant leaks out. An electrostatic shield plate is disposed on the partition 214 so that noise generated from the transistor 117 does not cause the drive circuit system in the chamber B to malfunction.

[0439] The current passed through the transistor 117 under test is large, at several hundred amperes, and therefore the thickness of the connection wiring 211 used is also large, so that the connection wiring 211 does not have sliding properties and is hard, and it is not easy to change the connection of the connection wiring 211.

[0440] The semiconductor testing device of the present invention can be connected to the switch circuit board 201 by the fork plug 205 inserted from the C2 chamber. Therefore, changing the connection with the switch circuit board 201 to be used depending on the test conditions of the transistor 117 does not require changing the wiring of the connection wiring 211, but only requires changing the position of the opening 216 into which the fork plug 205 is inserted. Also, the switch circuit board 201 only requires changing the position of the connector 213 connected to the mother board 207.

[0441] 28, 29, 30, 31, 33, 34, 38, 44, 45, etc., the connection wiring 211b connected to the transistor 117 is connected to the fork plug 205c. The connection wiring 211a connected to the transistor 117 is connected to the fork plug 205e.

[0442] Even if there are a plurality of transistors 117 to be tested, the use of a single switch circuit board 201a is sufficient, because it is sufficient to make the output current Id of the current power supply device 121 flow as Im to the ground line.

[0443] Switch circuit boards 201b are required in the number of transistors 117 to be tested. For example, if there are 12 transistors 117 to be tested, it is preferable to prepare 12 switch circuit boards 201b. It is also advantageous in terms of cost to make switch circuit boards 201a and switch circuit boards 201b the same specifications.

[0444] A plurality of transistors or the like are mounted on the switch circuit board 201 as the switch circuits 124. The greater the number of switch circuits 124, the smaller the impedance that shorts between the two conductive plates 204. The number of switch circuits 124b mounted on the switch circuit board 201a is determined so that the on-resistance of the switch circuit 124b is smaller than the on-resistance of the transistor 117 to be tested.

[0445] Figures 33 and 34 show the state in which the fork plug 205 is inserted into the opening 216 of the partition wall 214. Figure 33 is a view of the partition wall 214 as seen from the front side, and Figure 34 is a view of the partition wall 214 as seen from the back side.

[0446] 33, fork plug 205b and multiple fork plugs 205c (fork plugs 205c1 to 205c5) are connected to conductive plate 204b. Fork plug 205e1 is connected to conductive plate 204d1, fork plug 205e2 is connected to conductive plate 204d2, fork plug 205e3 is connected to conductive plate 204d3, fork plug 205e4 is connected to conductive plate 204d4, and fork plug 205e5 is connected to conductive plate 204d5.

[0447] A transistor 117 to be tested is connected between the fork plug 205c and the fork plug 205e. The number of switch circuit boards 201b corresponding to the number of transistors 117 to be tested is mounted on the mother board 207. The openings 216 are formed in correspondence with the positions of the conductor plates 204 of the switch circuit boards 201.

[0448] Although not shown, a large amount of noise is generated by turning on and off the switch circuits 124 of the switch circuit boards 201. As a countermeasure against this, a metal plate is disposed between the switch circuit boards 201 and is earthed.

[0449] In each drawing, one switch circuit 124 is shown on switch circuit board 201. However, in reality, a plurality of switch circuits 124 are arranged between conductor plates 204. By arranging a plurality of switch circuits 124 on switch circuit board 201, it is possible to short-circuit between conductor plates 204 (for example, between conductor plate 204c and conductor plate 204e) with low resistance.

[0450] Heat generated by switch circuit 124 is dissipated to conductive plate 204. A heat sink is also attached to switch circuit 124. The ground terminal of switch circuit 124 is connected to the ground of switch circuit board 201, and heat is also dissipated via the copper foil of the ground.

[0451] As shown in Fig. 29, two conductive plates 204 are attached to a switch circuit board 201, and a switch circuit 124 is arranged so as to short-circuit the two conductive plates 204. Also, Fig. 44 is an equivalent circuit diagram of the semiconductor testing device of the present invention in the first embodiment.

[0452] 29, 30, etc., conductive plates 204a and 204b are attached to switch circuit board 201a. Conductive plate 204a is connected to fork plug 205a. Fork plug 205a is connected to an output terminal of current power supply 121. Conductive plate 204b is connected to fork plug 205b. Fork plug 205b is connected to a ground terminal of current power supply 121.

[0453] When the switch circuit 124b is turned on, the output terminals of the current power supply 121 are short-circuited, and a short-circuit current Im flows. Therefore, the output current of the current power supply 121 is not supplied to the transistor 117. When the switch circuit 124b is open, the output current Id of the current power supply 121 is supplied to the transistor 117.

[0454] Conductive plates 204c and 204d are attached to switch circuit board 201b. Conductive plate 204c is connected to fork plug 205d. Fork plug 205d is connected to an output terminal of current power supply 121. Conductive plate 204d is connected to fork plug 205e. Fork plug 205e is connected to the collector terminal of transistor 117 to be tested.

[0455] 29, 30, 33, 34, etc., fork plug 205e is inserted into opening 216 opened in partition wall 214 and coupled to conductive plate 204d. Also, fork plug 205c is inserted into opening 216 opened in partition wall 214 and coupled to conductive plate 204d.

[0456] A switch circuit 124 a is disposed on the switch circuit board 201 b , and when the switch circuit 124 a is turned on, an output current Id from the current power supply device 121 is supplied to the transistor 117 as a test current to be passed through the transistor 117 .

[0457] The switch circuit board 201b is disposed in the B chamber of the housing 210, and the switch circuit board 201b is electrically connected to the transistor 117 to be tested by a fork plug 205 inserted from the C2 chamber through an opening 216 in the partition wall 214.

[0458] As shown in Figures 29, 30, 33, 34, etc., fork plug 205 and conductor plate 204 are connected. In Figure 30, switch circuit boards 201 are illustrated as being arranged in parallel. In reality, switch circuit boards 201 are inserted in parallel and arranged in a board rack. A mother board is arranged on the side of the board rack, and control signals to each circuit board are applied from the mother board.

[0459] Fig. 46 is an explanatory diagram of a method for testing a semiconductor device of the present invention in the first embodiment. In Fig. 46, Vgs is a gate signal applied to the gate terminal of the transistor 117 to be tested. Id is a current passed through the transistor 117 during testing. For ease of explanation, it is assumed that a constant current Ia passes through the transistor 117 when it is on.

[0460] 46(c), St1 is a timing signal for causing a current Ic to flow through the diode Di, and when St1 is at H level, a current flows through the diode Di of the transistor 117. The operational amplifier circuit 116 acquires the terminal voltage of the diode Di, and the temperature measurement circuit 115 converts the terminal voltage into temperature information Tj. The temperature information Tj is sent to the control circuit board 111, and the control circuit board 111 tests the transistor 117 (semiconductor element 117) in accordance with the temperature information Tj.

[0461] Id is a current flowing through the transistor 117 to be tested, and is a current output from the current power supply device 121. St1 and St2 are the time for which a measurement current is passed through a diode for temperature measurement, or the time for which the temperature is measured. In FIG. 46(e), Ssa is the on / off signal of the switch circuit 124a, and in FIG. 46(f), Sab is the on / off signal of the switch circuit 124b.

[0462] 46(g), Vce indicates the voltage at the c terminal of the transistor 117 (the channel voltage of the transistor 117), and the temperature information Tj indicates the measured temperature change of the transistor 117.

[0463] 46(a), a gate signal Vgs is applied from the gate driver circuit 113 to the gate terminal g of the transistor 117. The gate signal Vgs has a cycle time tcycle and an on-time ton. The cycle time tcycle and the on-time ton can be set to any value by the gate signal control circuit 112. The on-voltage Vg can also be set to any voltage.

[0464] Fig. 46(d) St2 is a timing signal for causing a current Ic to flow through the diode Dsa and the diode Dsb in the embodiment shown in Fig. 49. When St2 is at H level, a current flows through the diode Dsa or Dsb of the transistor 117. This is the case where a constant current Ic is caused to flow through a device (diode) independent of the transistor 117 to acquire temperature information Tj.

[0465] An operational amplifier circuit 116 acquires the terminal voltage of the diode Dsa or Dsb, and a temperature measurement circuit 115 converts the terminal voltage into temperature information Tj. The temperature information Tj is sent to the control circuit board 111, which performs a test on the transistor 117 based on the temperature information Tj. Note that matters related to St2 will be described in FIG. 49 and other drawings.

[0466] For ease of understanding, the measured temperature information Tj will be described as changing between T1 and T2 as shown in Fig. 46(h). The temperature information Tj increases when a current is applied to the transistor 117, and decreases when the current is stopped. The temperature information Tj also changes with the change in the characteristics of the transistor 117.

[0467] Figure 46(e) Ssa shows the timing of the on / off control signal for the switch circuit Ssa. When Ssa is Von, the switch circuit Ssa is closed (on). When Ssa is 0, the switch circuit Ssa is open (off), and the application of current or voltage is cut off.

[0468] Figure 46(f) Ssb shows the timing of the on / off control signal for the switch circuit Ssb. When Ssb becomes Von, the switch circuit Ssb is closed (on). When Ssb is 0, the switch circuit Ssb is open (off).

[0469] 46(g), Vce is the channel voltage (voltage between the emitter terminal and the collector terminal) of the transistor 117. As the transistor 117 is turned on and off, a surge voltage and a surge current are generated, and the Vce waveform changes in a complex manner over time as the on-resistance of the transistor 117 changes. In addition, the Vce waveform of the transistor 117 changes as a result of the current Ic flowing through the diode Di.

[0470] In this specification and drawings, for ease of explanation or for ease of drawing, it is assumed that when transistor 117 is on, the voltage is Vn, and when the transistor is off, the voltage is Ve. A gate signal is applied to the gate terminal of the transistor 117 under test with a period tcycle, an on time ton and an off time toff.

[0471] For the gate signal Vgs, if the transistor 117 is an N-channel transistor, the ground voltage 0 (V) is the off voltage and Vg is the on voltage. If the transistor 117 is a P-channel transistor, the on voltage potential and the off voltage potential are changed.

[0472] During a period tn2 before the transistor 117 is turned on, the Vt voltage is set to a voltage more negative than the off voltage, and during a period tn1 after the transistor 117 is turned off, the Vt voltage is set to a voltage more negative than the off voltage. The Vt voltage is a voltage lower than 0 (V) and higher than -4 (V). Therefore, Vt is a voltage equal to or higher than -4 (V) and lower than 0 (V).

[0473] In addition, when transistor 117 is SiC, the off-voltage is set to the Vt voltage, and when transistor 117 is an IGBT, the off-voltage is set to 0 (V). As described above, the semiconductor testing device of the present invention is configured so that the off-voltage supplied to transistor 117 can be changed according to the type of transistor 117 to be tested.

[0474] When the Vt voltage is applied, St1 (St2) is set to the H level to measure the temperature of the transistor 117. While the Vt voltage is being applied, a constant current Ic is caused to flow through the diode Di. In addition, while St1 (St2) is at the H level, the constant current Ic is also caused to flow.

[0475] By applying the Vt voltage to the gate terminal of the transistor 117, the off state of the transistor 117 becomes stable, and the temperature information Tj can be stably measured. In addition, noise is less likely to be introduced during measurement of the temperature information Tj, improving the measurement accuracy of the temperature information Tj.

[0476] By applying the Vt voltage to the gate terminal of the transistor 117, the leakage current of the transistor 117 is reduced, the measurement accuracy of the Vi voltage is improved, and the measurement is stabilized.

[0477] The gate signal Vgs is set to the voltage Vt during the times tn1 and tn2. As an example, the times tn1 and tn2 are from 0.2 ms to 2 ms. The transistor 117 is turned off at 0V.

[0478] Therefore, three voltages, Vg, 0 (V), and Vt, are applied to the gate terminal g of the transistor 117. During the period in which Vt is being applied, a current is caused to flow through the diode Di of the transistor, and temperature information Tj is measured.

[0479] When the constant current Ic is made to flow through the diode Di, the switch circuit Ssa is turned off so that the current from the current power supply device 121 is not applied to the transistor 117 .

[0480] A terminal voltage of the diode Di is obtained by passing a constant current Ic through the diode Di, and an operational amplifier circuit 116 outputs a voltage Vi corresponding to the terminal voltage. The voltage Vi is input to a temperature measurement circuit 115, which obtains temperature information Tj corresponding to the temperature of a transistor 117.

[0481] The temperature information Tj is transferred to the control circuit board 111, and the control circuit board 111 controls the test of the transistor 117 (semiconductor element 117) by continuing, stopping, changing the conditions of the test of the transistor 117, etc., based on the temperature information Tj.

[0482] Fig. 46(e) Ssa is a timing signal for controlling the on / off of the switch circuit 124a, and Fig. 46(f) Ssb is a timing signal for controlling the on / off of the switch circuit 124b.

[0483] The switch circuit 124a is turned on with a delay of tm2 from when the Vgs signal of the transistor 117 becomes Vg. The time tm2 can be changed by the control circuit board 111.

[0484] The switch circuit 124b turns on a time tb2 before the switch circuit 124a turns on. The on state of the switch circuit 124b is maintained until tb1 after the switch circuit 124a turns on. The times tb2 and tb1 can be changed independently. In particular, the setting of tb1 is important. The time tb1 is set or changed appropriately by observing the waveform of the Vce voltage of the transistor 117.

[0485] The switch circuit 124a is turned off a time tm1 before the Vgs signal of the transistor 117 reaches Vt. The time tm1 can be changed by the control circuit board 111.

[0486] Switch circuit 124b turns on a time ta2 before switch circuit 124a turns off. Switch circuit 124b remains on until ta1 after switch circuit 124a turns off. The ta2 and ta1 times can be changed independently. In particular, the setting of ta1 is important. The time ta1 is set or changed appropriately by observing or measuring the waveform of the Vce voltage of the transistor 117.

[0487] When the switch circuit Ssb is turned on, the output terminal of the current power supply device 121 is shorted to the ground (ground line), and the charge is discharged. As a result of the charge being discharged, the terminal voltage of the current power supply device 121 becomes 0 (V) (ground voltage). In addition, the current Id output by the current power supply device 121 is caused to flow to the ground as a current Im. Therefore, the current Ia is not applied to the transistor 117, and the collector voltage of the transistor 117 does not rise.

[0488] The time tb2 is set by observing or measuring the time when the output voltage of the current power supply 121 becomes 0 (V) or close to 0 (V), or the time when the output voltage of the current power supply 121 becomes lower than the collector voltage of the transistor 117.

[0489] At the time when the above voltage relationship reaches a predetermined value (after tb2 has elapsed), the switch circuit 124a is turned on to apply the current Id from the current power supply device 121. However, at this time, the switch circuit 124b is on, so the current Id from the current power supply device 121 flows to the ground (ground line) as the current Im via the switch circuit 124b. Therefore, the constant current Id does not flow through the transistor 117. After the switch circuit 124 a is turned on and a time tb1 has elapsed, the switch circuit 124 b is turned off and the test current Id is supplied to the transistor 117 . The test current Id is supplied to the transistor 117 in synchronization with the switch circuit 124a as shown in FIG.

[0490] By operating the switch circuits 124a and 124b as described above, the surge voltage Vs or the inrush current Is is not applied to the transistor 117. Alternatively, the surge voltage Vs or the inrush current Is is suppressed, and the transistor 117 can be properly tested.

[0491] When the test current Id to the transistor 117 is stopped, the switch circuit 124b is turned on before the switch circuit 124a is turned off (ta2). The constant current Id output by the current power supply device 121 flows to the ground as the current Im via the switch circuit Ssb and is not supplied to the transistor 117.

[0492] The time ta2 is set by observing the time when the output voltage of the current power supply 121 becomes 0 (V) or close to 0 (V), or the time when the output voltage of the current power supply 121 becomes lower than the collector voltage of the transistor 117.

[0493] When the above voltage relationship reaches a predetermined value (after ta2 has elapsed), the switch circuit 124a is turned off. After ta1 has elapsed since the switch circuit 124a was turned off, the switch circuit 124b is turned off.

[0494] By operating or controlling the switch circuits 124a and 124b as described above, the surge voltage Vs or inrush current Is is not applied to the transistor 117. Alternatively, the surge voltage Vs or inrush current Is is suppressed, and the transistor 117 can be properly tested.

[0495] When the constant current Id is supplied to the transistor 117, the temperature information Tj increases. When the constant current Id to the transistor 117 is stopped, the temperature information Tj decreases. The temperature information Tj fluctuates between T1 and T2. When the characteristics of the transistor 117 fluctuate due to the test, the temperature information Tj gradually increases. In order to apply a constant value of current Id to the transistor 117, the current power supply device 121 is operated to apply the current Id to the transistor 117.

[0496] 44, 45, 47, 49, 50, etc., the resistance value of the variable resistance circuit 125 of the gate driver circuit 113 can also be set. By increasing the resistance value, the rising / falling waveform of the gate signal Vgs can be changed as shown by the dotted line or the dashed-dotted line in FIG. 47(a).

[0497] By changing or setting the gate signal Vgs, the current Id flowing through the transistor 117 can also be changed as shown by the dotted line or the dashed dotted line in FIG. By changing the rising and falling waveforms of the current Id, it is possible to adjust or suppress the surge voltage or inrush current.

[0498] As shown in Fig. 47(c), the temperature information Tj changes from a solid line to a dotted line and from a dotted line to a dashed line as the characteristics of the transistor 117 change due to the test. The test is stopped when the temperature information Tj reaches the level of Tm. Alternatively, the test is stopped when the rate of change of the temperature information Tj reaches a predetermined value. In addition, the test conditions are changed.

[0499] 48, when the switch circuit Ssa (switch circuit 124a) is in the off state, the St1 signal is set to H and temperature information Tj is measured. The St1 signal is set to H level when the gate signal is Vt. In the tn2 period, the signal is set to H level for a period tc2 and temperature information Tj is measured. In the tn1 period, temperature information Tj is measured for a period tc1.

[0500] The temperature information Tj measured during the period tc2 is the temperature information Tj at the time when the transistor 117 is cooled. The temperature information Tj measured during the period tc1 is the temperature information Tj immediately after the current Id to the transistor 117 is stopped. Stopping the test, changing the conditions, changing the control, etc. are determined based on the temperature information Tj measured during the period tc2 and the temperature information Tj measured during the period tc1.

[0501] If the rate of change of the temperature information Tj measured during the tc1 period is larger than that of the temperature information Tj measured during the tc2 period, or if the difference in absolute value between the temperature information Tj measured during the tc1 period and the temperature information Tj measured during the tc2 period is large, the test is controlled and changed in response to the measurement value temperature information Tj.

[0502] Moreover, if the temperature information Tj measured during the period tc2 differs from the standard value by a predetermined value, it is determined whether there is a problem with the connection state of the transistor 117 or the test equipment, and a decision is made to "not start the test", etc. During the period tc2 or tc1, Vi is measured multiple times, and temperature information Tj for Vi is obtained.

[0503] The embodiment of Fig. 49 is a semiconductor test device according to the second embodiment of the present invention. A transistor 117 in Fig. 49 is provided with a separate diode Ds (diode Dsa, diode Dsb) for temperature measurement. The diode Ds is formed in the same process as the transistor 117.

[0504] In the embodiment of FIG. 49, temperature information Tj is measured at the timing of the St2 signal in FIG. 46(d). When the switch circuit Ssa (switch circuit 124a) is in the off state, the St2 signal is set to H and temperature information Tj is measured. In the tn2 period, the signal is set to H level during the tc2 period and temperature information Tj is measured. During the tc1 period, temperature information Tj may be measured during either the ton period or the tn1 period. The temperature information Tj measured during the tc2 period and the temperature information Tj measured during the tc1 period are averaged to obtain the temperature information Tj.

[0505] During the period tc2 or tc1, Vi is measured multiple times to obtain temperature information Tj for Vi. The operations of other signals or switch circuits in Fig. 46 are the same as or similar to those in the embodiment described with reference to Fig. 28 and the like. In the above embodiment, the temperature information Tj is measured by a diode added to or formed in the transistor 117. In the embodiment of FIG. 49, a diode Ds that is not connected (independent) to the transistor 117 is formed.

[0506] The diode Dsa is oriented to pass the constant current Ic. The diode Dsb is oriented to pass the constant current Ic'. The constant current circuit 118 (Pc) generates the constant current Ic and the constant current Ic'.

[0507] The diodes Dsa and Dsb are diodes for measuring temperature. The structures of the diodes Dsa and Dsb are similar or identical to the diode Di in FIG. 28 and the like.

[0508] Diode Di is connected to the terminals (terminals c and e) of transistor 117, while diodes Dsa and Dsb are not connected to the terminals of transistor 117 but are connected to independent terminals, and temperature information Tj of diode Di is measured at timing St1 in Figure 46(c), while temperature information Tj of diode Dsa and diode Dsb is measured at timing St2 in Figure 46(d). Except for this, they have the same operation or configuration.

[0509] In the embodiment of Fig. 49, the diode Ds is separated from the path through which the constant current Id flows. Even when the current Id flows through the transistor 117, the constant current Ic can be made to flow through the diode. Therefore, the time for measuring the temperature information Tj can be freely set. The positions of tc1 and tc2 can be set as shown in Fig. 46(d).

[0510] However, in tc2, as shown in Fig. 46(d), the gate signal is placed or set in the period of Vt. The temperature information Tj measured in the period tc2 is used as the value before the transistor 117 operates. The period tc1 is preferably immediately before the constant current Id of the transistor 117 is stopped. However, it may be immediately after the constant current Id is stopped. It is preferable that "immediately before" and "immediately after" are within 1 ms. St2 in FIG. 46(d) is a timing signal for causing the current Ic (or current Ic') to flow through the diode Ds (Dsa, Dsb).

[0511] When St2 is at H level, a current flows through the diode Ds (Dsa, Dsb) of the transistor 117. The operational amplifier circuit 116 acquires the terminal voltage of the diode Ds, and the temperature measurement circuit 115 converts the terminal voltage into temperature information Tj.

[0512] The temperature information Tj is sent to the control circuit board 111, and the control circuit board 111 performs or stops the test of the transistor 117 or changes the control in accordance with the temperature information Tj.

[0513] When St2 is at H level, the constant current circuit 118 supplies a constant current Ic, which flows through the diode Dsa, and the constant current circuit 118 supplies a constant current Ic', which flows through the diode Dsb.

[0514] The constant current Ic and the constant current Ic' are currents of the same magnitude. However, when the threshold voltages of the diodes Dsa and Dsb are different, or when the characteristics of the diodes Dsa and Dsb are different, it is preferable to make the constant current Ic and the constant current Ic' different in magnitude.

[0515] The operational amplifier circuit 116 acquires the terminal voltage of the diode Dsa or Dsb, and the temperature measurement circuit 115 converts the terminal voltage into temperature information Tj. The temperature information Tj is sent to the control circuit board 111, and the control circuit board 111 performs a test of the transistor 117 based on the temperature information Tj.

[0516] The temperature information Tj obtained by passing a constant current Ic and the temperature information Tj obtained by passing a constant current Ic' are averaged or weighted to obtain a single value of temperature information Tj. Using this temperature information Tj, the control circuit board 111 starts or stops the test of the transistor 117, or changes the control. The other matters are the same as or similar to the matters or contents described in this specification and drawings, and therefore will not be described here.

[0517] It goes without saying that the present invention can be modified in various ways without departing from the spirit and scope of the present invention. It goes without saying that the matters or contents described in this specification and drawings can be combined with each other.

[0518] Fig. 50 is an explanatory diagram of a semiconductor testing device in an embodiment of the present invention. The difference from Fig. 28 is that a diode-connected transistor 117s is arranged in the path of a current Id to be passed through a transistor 117m to be tested. Other points are the same, so the explanation will be omitted.

[0519] As an example, the transistor 117s is a transistor having the same specifications as the transistor 117m to be tested. The gate terminal g2 and the emitter terminal e2 of the transistor 117s are connected, and the transistor 117s can be considered equivalent to a diode. The gate terminal g2 and the emitter terminal e2 of the transistor 117s are connected to the O terminal of the connection part 507. The collector terminal c2 of the transistor 117s is connected to the P terminal of the connection part 507.

[0520] 43, the terminals (gate terminal g2, emitter terminal e2, collector terminal c2) of the transistor 117s are connected to the connector 202b, and the connector 202b is connected to the sample connection circuit 203 by a signal wiring 222b. The terminals (gate terminal g2, emitter terminal e2, collector terminal c2) of the transistor 117s are connected in the sample connection circuit 203.

[0521] When the switch circuit 124b is turned on, a current Im flows, discharging the charge of the current power supply device 121. Alternatively, the current Id output by the current power supply device 121 flows to the ground via the switch circuit 124b.

[0522] When an inrush current Is flows through the transistor 117m to be tested, the transistor 117m is destroyed by the inrush current Is or the surge voltage Vs. To prevent the inrush current Is or the surge voltage Vs from occurring, the on / off control and the on / off sequence of the switch circuits 124a and 124b are controlled.

[0523] When the cycle tcycle is made faster to test the transistor 117m, it is necessary to turn on and off the switch circuits 124a and 124b at high speed. In this case, an inrush current Is or a surge voltage Vs may occur depending on the on / off timing of the switch circuit 124.

[0524] If the voltage Vm at the collector terminal of the transistor 117 is higher than the voltage Vp at the output of the current power supply device, the current flows toward ground as the current Im, and little or no current flows through the transistor 117m.

[0525] In order to create the relationship Vm > Vp, in the embodiment shown in Figure 50, a diode-connected transistor 117s is placed in the path of the current Id. When a current flows through the transistor 117s, the voltage Vm is built up by the channel voltage of the transistor 117s. Therefore, the voltage Vp is lower than the voltage Vm, and no inrush current is applied to the transistor 117m. The transistor 117m will not be destroyed by the inrush current Is or the surge voltage Vs.

[0526] Fig. 60 is a diagram showing the channel (Vce, Vds) voltage or waveform of a transistor during a power cycle test of a plurality of semiconductor elements (power transistors, etc.). Specific circuit configurations and test methods are shown in Figs. 51 and 52.

[0527] In the semiconductor device testing apparatus and semiconductor device testing method of the present invention, a method for simultaneously testing a plurality of devices is carried out. In the present invention, as an example of the simultaneous testing method, a time-share method is carried out. FIG. 60 shows waveforms obtained when power cycling is performed on four devices using one semiconductor device testing apparatus according to the present invention. From time 2(s) to 4(s), the first device is turned on, and the other devices (the second device, the third device, and the fourth device) are turned off. From time 4(s) to 6(s), the second device is turned on, and the other devices (the first device, the third device, and the fourth device) are turned off. From time 6(s) to 8(s), the third device is turned on, and the other devices (the first device, the second device, and the fourth device) are turned off. From time 8 (s) to 10 (s), the fourth device is turned on, and the other devices (the first device, the second device, and the third device) are turned off. Next, after 4.5 (s) (13.5 (s)), the first device is turned on again, and thereafter, the second device, the third device, and the fourth device are turned on in sequence.

[0528] In Fig. 60, for example, the first device is turned off and the second device is turned on at the same time, but in reality, the second device is turned on after a predetermined time (1 to 100 ms) has elapsed since the first device was turned off. The predetermined time tw is configured to be able to be set to a predetermined value or an arbitrary time.

[0529] The above also applies to the operation intervals with other devices, and the predetermined time tw between each device can be set arbitrarily. The above also applies to FIG.

[0530] In the semiconductor element testing apparatus and semiconductor testing method of the present invention, the on-time ton and off-time toff of each device can be set to a predetermined value. When each semiconductor device is a transistor element, the test cycle tc (tcycle), on-time ton or off-time toff, and predetermined time tw can be easily adjusted or set by the pulse time and cycle applied to the gate terminal of the transistor. When multiple devices are tested using multiple semiconductor device test equipment, the test results include variations between the equipment, making it impossible to accurately compare the devices.

[0531] In the semiconductor device testing apparatus and semiconductor device testing method of the present invention, while one device is turned off, another device is turned on. By repeatedly turning on and off the power at regular intervals, thermal stress is applied to the semiconductor device.

[0532] By testing multiple devices simultaneously (sequentially) using the same equipment (test environment for power supply, temperature measurement, control, bypass, etc.), it is possible to speed up device testing and accurately compare device performance.

[0533] 51 is an explanatory diagram of a semiconductor testing device in an embodiment of the present invention. In Fig. 51, a plurality of transistors 117 (transistors 117Q1 to 117Qn) to be tested are connected in parallel to a current power supply device 121.

[0534] In the embodiment of Fig. 51, it is necessary to arrange a plurality of transistors 117 on a positioning support plate 519. For this reason, as shown in Fig. 53, positioning holes 512 (positioning holes 512a, 512b, 512c, 512d, and 512e in Fig. 53) corresponding to the number of transistors 117 (SOP117, QFN117) to be tested are formed in the sample arrangement plate 511. The SOP117, QFN117, etc. are arranged in each of the positioning holes.

[0535] 54, electrode patterns 505 and 506 corresponding to the number of SOPs 117 and the number of QFNs 117 are formed on the connection board 514. Anisotropic conductive rubber 504 is arranged on the electrode patterns, and a plurality of SOPs 117 and QFNs 117 are pressed by one pressing head.

[0536] In the embodiment, there is one switch circuit board 201a and n switch circuit boards 201b (switch circuit boards 201b1 to 201bn). The number of transistors 117Q to be tested simultaneously or sequentially is n (transistors 117Q1 to 117Qn).

[0537] The collector terminal of the transistor Q1 is connected to the fork plug 205e1, and the emitter terminal of the transistor Q1 is connected to the fork plug 205c1.

[0538] The collector terminal of the transistor Q2 is connected to the fork plug 205e2, and the emitter terminal of the transistor Q2 is connected to the fork plug 205c2.

[0539] The collector terminal of the transistor Q3 is connected to the fork plug 205e3, and the emitter terminal of the transistor Q3 is connected to the fork plug 205c3.

[0540] Similarly, the collector terminal of the transistor Qn is connected to the fork plug 205en, and the emitter terminal of the transistor Qn is connected to the fork plug 205cn.

[0541] When the switch circuit Ssa1 is turned on, the current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Q1. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and is output from the operational amplifier circuit 116 as the Vi1 voltage.

[0542] When the switch circuit Ssa2 is turned on, the current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Q2. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and is output from the operational amplifier circuit 116 as the voltage Vi2.

[0543] Similarly, when the switch circuit Ssan is turned on, the current Ic of the constant current circuit 118 is supplied to the diode Ds of the transistor 117Qn. The terminal voltage of the diode Ds is applied to the operational amplifier (buffer) 116 and is output from the operational amplifier circuit 116 as the Vin voltage. One voltage is selected from voltages Vi 1 to Vin by selector 127 , and is output as Vi and input to temperature measurement circuit 115 .

[0544] The temperature measuring circuit 115 obtains temperature information Tj and outputs it to the control circuit board 111. In the embodiment of Fig. 51, one constant current circuit 118 is used, but this is not limited to this. A constant current circuit 118 may be provided for each transistor 117Q. Also, a temperature measuring circuit 115 may be formed or provided for each transistor 117Q. The voltage data Vi and the temperature information Tj are sent to the control circuit board 111 via the wiring of the mother board 207 .

[0545] The connection portion 507 (P terminal) of the transistor 117Q1 is connected to the connection structure 218a1, and the connection portion 507 (N terminal) of the transistor 117Q1 is connected to the connection structure 218b1.

[0546] The connection portion 507 (P terminal) of the transistor 117Q2 is connected to the connection structure 218a2, and the connection portion 507 (N terminal) of the transistor 117Q2 is connected to the connection structure 218b2.

[0547] Similarly, the connection portion 507 (P terminal) of the transistor 117Qn is connected to the connection structure 218an, and the connection portion 507 (N terminal) of the transistor 117Qn is connected to the connection structure 218bn, where n is a positive number equal to or greater than 1. The connection structure 218 is inserted from an opening 216 provided in the partition wall 217. The connection structure 218 is inserted in the direction from the C2 chamber to the C1 chamber.

[0548] The fork plug 205 is inserted into the B chamber from the C2 chamber side through an opening 216 formed in the partition wall 214. When the fork plug 205 is inserted, it is connected to the conductor plate 204 of the switch circuit board 201. The switch circuit board 201 can be selected depending on the position of the opening 216 into which the fork plug 205 is inserted.

[0549] By changing the position of the switch circuit board 201 connected to the connector 213 of the mother board 207, the switch circuit board 201 to be selected by the fork plug 205 can be selected.

[0550] Two conductive plates 204 are arranged on the switch circuit board 201. Of the two conductive plates 204, the conductive plate 204 closer to the C2 chamber and the fork plug 205 are arranged so as to be connected (in contact).

[0551] In the embodiment of the present invention, the fork plug 205 and the conductive plate 204 are electrically connected by contacting each other, but this is not limited to this. Any structure may be used as long as it can change between an electrically connected state and a non-connected state by a mechanical operation. Also, any structure may be used as long as it can stably maintain the connected state.

[0552] For example, a rotary connector, a rotary joint, a high-current connector, etc. may be used instead of the fork plug 205. A rotary connector, a rotary joint, a high-current connector, a cylindrical conductor rod, a rectangular conductor rod, a comb-shaped conductor plate, etc. may be used instead of the conductor plate 204.

[0553] Fig. 52 is an explanatory diagram of a method for testing a semiconductor device in an embodiment of the present invention, explaining the operation of Fig. 51. It is possible to perform a semiconductor test by simultaneously turning on transistors 117Q (transistors 117Q1 to 117Qn). In this case, it is necessary to pass a constant current Id through all of transistors 117Q (transistors 117Q1 to 117Qn). Therefore, if there are n transistors 117Q, current power supply device 121 must be able to output a current of Id x n (n is a positive number equal to or greater than 1). Therefore, a large-capacity current power supply device 121 is required.

[0554] If the test is performed by sequentially turning on the transistors 117Q and applying a constant current Id to the transistors 117Q, the constant current output from the current power supply device 121 may be Id. Fig. 52 shows an embodiment of a test method for a semiconductor test device that performs a test by sequentially turning on the transistors 117Q. The semiconductor element changes depending on the number of times the constant current Id is turned on and off.

[0555] Therefore, by performing a test by sequentially turning on the semiconductor elements (transistor 117Q and the like) as shown in FIG. 52, the test can be performed efficiently and the maximum output current capacity of the current power supply device 121 can be reduced.

[0556] 52, the number of transistors 117Q to be turned on is described as one, but this is not limited to this. For example, multiple transistors 117Q may be turned on at the same time. In this case, the maximum value of the constant current output by the current power supply device 121 is the number of transistors 117Q to be turned on × Id.

[0557] In the embodiment of the present invention, one current power supply device 121 is illustrated, but the present invention is not limited to this. The current power supply device 121 may be provided with a current power supply device 121b separately. Furthermore, two or more current power supply devices 121 may be provided. By providing a plurality of current power supply devices 121, the current Id flowing through the transistor 117 can have various waveforms. The above also applies to the embodiments of the present invention.

[0558] As shown in Fig. 52(a), when switch circuit St1 (151s1) to switch circuit Stn (151sn) are turned on, constant currents Id1 to Idn flow through transistor 117. For example, the application time of constant current Id is ton, and constant currents Id1 and Id2 are applied to transistor 117 sequentially at an interval of time tcycle. When transistor 117 is turned on, the channel voltage of transistor 117Q changes sequentially (Fig. 52(c)).

[0559] Therefore, for example, the constant current Id1 and the constant current Id2 do not overlap in time, and therefore the output capacitance of the current power supply device 121 may be the output capacitance required for testing one transistor 117Q.

[0560] The constant currents Id (Id1 to Idn) are controlled so as not to overlap each other. It is preferable that the constant currents Id (Id1 to Idn) are separated by an interval of 1 μsec or more. The driving method and control method described in FIG. 46 are implemented for each transistor 117Q.

[0561] The constant current Ic to be supplied to each transistor 117Q is supplied to the diode Ds of each transistor 117Q by sequentially turning on the switch circuits Ssa (Ssa1 to Ssan).

[0562] A voltage Vi (Vi1 to Vin) corresponding to the terminal voltage of diode Ds is selected by the selector 127 in synchronization with the switch circuit Ssa (Ssa1 to Ssan). For example, when a current Ic is supplied to the transistor 117Q1, the selector 127 selects the terminal voltage of the diode Ds of the transistor 117Q1. When a current Ic is supplied to the transistor 117Q3, the selector 127 selects the terminal voltage of the diode Ds of the transistor 117Q3. The selected voltage Vi is supplied to the temperature measurement circuit 115. The other configurations and operations are similar to those described in the other embodiments, and therefore the description thereof will be omitted. In the embodiment of the present invention, the transistor 117 is illustrated as an IGBT, but the present invention is not limited to this.

[0563] For example, it goes without saying that it may be an N-channel JFET (Figure 55(a)), a P-channel JFET (Figure 55(b)), an N-channel MOSFET (Figure 55(c)), a P-channel MOSFET (Figure 55(d)), an N-channel bipolar FET (Figure 55(e)), or a P-channel bipolar FET (Figure 55(f)).

[0564] Furthermore, the device is not limited to a three-terminal device, and may be a two-terminal element such as a diode shown in Fig. 55(g). A two-terminal element does not require a gate signal Vgs. It goes without saying that the semiconductor testing device and the semiconductor element testing method of the present invention can be applied by testing by passing a constant current Id from the current power supply device 121.

[0565] Furthermore, it goes without saying that the semiconductor testing apparatus and semiconductor element testing method of the present invention are not limited to transistors and diodes, but can also be applied to other semiconductor elements such as thyristors and triacs, varistors, diacs, or modules in which transistors, diode resistors, etc. are mixed or integrated.

[0566] Furthermore, the present invention is not limited to semiconductor elements, but can also be applied to, for example, resistance elements such as concrete resistors and enamel resistors, variable resistance elements, non-linear resistance elements such as thermistors and posistors, and bias elements such as transformers.

[0567] In the above, the present specification has specifically described the present invention based on the embodiment, but it goes without saying that the present invention is not limited thereto and various modifications are possible without departing from the spirit of the present invention. It goes without saying that the matters or contents described in this specification and the drawings can be mutually combined.

[0568] For example, the switch circuits 124a and 124b shown in Fig. 45 can be applied to the other embodiments. For example, it goes without saying that the configurations or operations of Fig. 51 and Fig. 52 can be applied to the other embodiments of Fig. 49, Fig. 50, etc.

[0569] For example, it goes without saying that the devices of the present invention shown in Figures 25, 68, and 72, the operations of the devices, and the configurations of the devices can be combined with each other in part or in whole. For example, it goes without saying that the present inventions described in FIG. 2, FIG. 5, FIG. 7, FIG. 58, etc. can be combined with each other in part or in whole.

[0570] For example, it goes without saying that the testing methods, inspection methods, and testing apparatus operating methods of the present invention described in Figures 46, 47, 48, 49, 50, 51, 53, 60, 61, 62, 63, 64, 65, 66, 67, etc. can be combined with each other in part or in whole. [Industrial Applicability]

[0571] The present invention can provide a semiconductor testing apparatus and a semiconductor testing method that can easily change connections depending on the test contents of semiconductor elements such as transistors and the number of semiconductor elements to be tested simultaneously, and can effectively implement measures against noise generated during testing. [Explanation of symbols]

[0572] 111 Control circuit board (controller) 112 Gate signal control circuit 113 Gate driver circuit 115 Temperature measurement circuit (not shown) 116 Op-amp circuit (buffer amplifier) 117 Power Transistor 121 Constant current circuit 122 Switch Circuit 123 Switch Circuit 124 Switch Circuit 125 Variable Resistor Circuit 126 Variable Resistor Circuit 127 Changeover switch circuit 128 Current Detection Circuit 129 Voltage detection circuit 130 Constant current setting circuit 131 Control Rack 132 Power supply 133 Control circuit 134 Heating and cooling plate 135 Circulating Water Pipe 136 Chiller 137 Short Circuit 138 Isolated DC / DC converter circuit 201 Switch circuit board 202 Connector 203 Sample connection circuit 204 Conductor plate 205 Fork plug 206 connection pins 207 Motherboard 208 Connector 209 Device control circuit board 210 Cabinet 211 Connection wiring 212 Power wiring 213 Connector 214 Bulkhead 215 Bulkhead 216 Opening 217 Bulkhead 218 Connection Structure 219 Connection bolt 220 Contact part 221 Fixing screw 222 Signal wiring 223 Heat Pipe 224 Fixing screw 225 Contact part 226 Electrode terminal 227 Signal terminal 228 Heat dissipation fin 229 Cooling Fan 230 Conductive Wire 231 Heat pipe fittings 232 Connection fittings 233 Connection fittings 234 Recess 235 Signal Wiring 239 Placement recess 301 Test Circuit Module 302 Voltage selection circuit 502 connection pin 503 Connection Wiring 504 Anisotropic conductive rubber 505 Electrode Pattern 506 Electrode Pattern 507 Connection 508 Signal Wiring 509 Positioning hole 510 fixing hole 511 Sample placement plate 512 Sample hole 514 Connection Board 515 Press Plate 516 Pressing tool 517 Rubber (elastic material) 518 Positioning Post 519 Positioning support plate 520 Surface Plate 521 Sample Plate 522 Foundation 523 Heat Resistant Resist 524 Ni-P plating film 525 Heat-resistant substrate 525 Gold plating film 530 Pressing head 531 Pressing Pillar 532 Arm 533 Arm stand 534 Post 601 Semiconductor Chip 602 Insulating substrate 604 Copper base 605 Solder 606 Aluminum Wire 607 Wiring electrode 608 Pressing member 609 Terminal connection part 610 Device fixing and connection equipment 611 Device Stand

Claims

1. A semiconductor testing apparatus for testing a power module, comprising: A connection structure; A support member; A first heating / cooling plate; A second heating / cooling plate; a circulation pipe attached to the first heating / cooling plate and the second heating / cooling plate; a power supply device that supplies a test current to the power module via the connection structure; a pressing member attached to the support member and holding the connection structure; the power module is disposed between the first heating / cooling plate and the second heating / cooling plate; A power cycle testing device, characterized in that the position of the connection structure can be moved and maintained by changing the mounting positions of the support member and the pressing member.

2. A semiconductor testing apparatus for testing a power module, comprising: a first switch circuit mounted or disposed on a first switch circuit board; A connection structure; A support member; A first heating / cooling plate; A second heating / cooling plate; a circulation pipe attached to the first heating / cooling plate and the second heating / cooling plate; a power supply device that supplies a test current to the power module via the connection structure and the first switch circuit; a pressing member attached to the support member and holding the connection structure; the power module is disposed between the first heating / cooling plate and the second heating / cooling plate; By changing the attachment positions of the support member and the pressing member, the position of the connection structure can be moved and maintained, the first switch circuit is disposed between the power supply device and the connection structure; When the first switch circuit is turned on, the test current is supplied to the power module via the connection structure, The power module is disposed in a first chamber; The power cycle testing apparatus according to claim 1, wherein the first switch circuit board is disposed in a second chamber.

3. A semiconductor testing apparatus for testing a power module, comprising: a first switch circuit mounted or disposed on a first switch circuit board; a second switch circuit mounted or disposed on a second switch circuit board; A connection structure; A support member; A first heating / cooling plate; A second heating / cooling plate; a circulation pipe attached to the first heating / cooling plate and the second heating / cooling plate; a power supply device that supplies a test current to the power module via the connection structure and the first switch circuit; a pressing member attached to the support member and holding the connection structure; the power module is disposed between the first heating / cooling plate and the second heating / cooling plate; By changing the attachment positions of the support member and the pressing member, the position of the connection structure can be moved and maintained, the first switch circuit is disposed between the power supply device and the connection structure; When the first switch circuit is turned on, the test current is supplied to the power module via the connection structure, the second switch circuit has a function of short-circuiting an output of the power supply device, The power module is disposed in a first chamber; The power cycle testing apparatus, wherein the first switch circuit board and the second switch circuit board are disposed in a second chamber.

4. A semiconductor testing apparatus for testing a power module, comprising: a constant current circuit that applies a constant current between terminals of the power module; a voltage output circuit that outputs a terminal voltage between terminals of the power module; A first switch circuit; A connection structure; A support member; A first heating / cooling plate; A second heating / cooling plate; a circulation pipe attached to the first heating / cooling plate and the second heating / cooling plate; a power supply device that supplies a test current to the power module via the connection structure and the first switch circuit; a pressing member attached to the support member and holding the connection structure; the power module is disposed between the first heating / cooling plate and the second heating / cooling plate; By changing the attachment positions of the support member and the pressing member, the position of the connection structure can be moved and maintained, the first switch circuit is disposed between the power supply device and the connection structure; When the first switch circuit is turned on, the test current is supplied to the power module via the connection structure, 2. A power cycle testing device comprising: a first switch circuit for applying a constant current between the terminals and a voltage output circuit for outputting a terminal voltage between the terminals during a period in which the first switch circuit is turned off;

5. A semiconductor testing apparatus for testing a power module, comprising: a gate driver circuit that outputs a gate voltage that turns on or off the power module; a voltage output circuit that outputs a terminal voltage between terminals of the power module; A connection structure; A support member; A first heating / cooling plate; A second heating / cooling plate; a circulation pipe attached to the first heating / cooling plate and the second heating / cooling plate; a power supply device that supplies a test current to the power module via the connection structure; a pressing member attached to the support member and holding the connection structure; the power module is disposed between the first heating / cooling plate and the second heating / cooling plate; By changing the attachment positions of the support member and the pressing member, the position of the connection structure can be moved and maintained, The gate driver circuit varies the gate voltage so that the power of the power module calculated from the terminal voltage output by the voltage output circuit and the test current becomes a designated power.

6. The apparatus further includes a cooling or heating device connected to the circulation pipe for adjusting a temperature of the liquid flowing through the circulation pipe, 4. The power cycle testing apparatus according to claim 2, wherein dry air is introduced into said first chamber.

7. a cooling or heating device connected to the circulation pipe and adapted to adjust the temperature of the liquid flowing through the circulation pipe; Further comprising a water leakage sensor for detecting the leaked liquid, 6. A power cycle testing device according to claim 1, 2, 3, 4 or 5, wherein the operation of the power cycle testing device is stopped or an alarm is issued in response to the operation of the water leakage sensor.

8. Further comprising a gate driver circuit that outputs a gate voltage that turns on or off the power module, 5. The power cycle testing device according to claim 1, 2, 3 or 4, wherein the wiring for outputting the gate voltage is a twisted wiring or a shielded wiring.

9. 6. The power cycle testing device according to claim 4, wherein the test is stopped, the control method is changed, or the test conditions are changed based on the terminal voltage.

10. n (n is a positive number equal to or greater than 2) power modules are disposed between the first heating / cooling plate and the second heating / cooling plate; 6. A power cycle testing device according to claim 1, 2, 3, 4 or 5, further comprising n switch circuit boards arranged corresponding to said n power modules.

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