Wiring Board

Abstract

To reduce impedance mismatching.SOLUTION: A wiring board includes an insulating layer formed using an insulating resin, and a wiring layer formed on the surface of the insulating layer, the wiring layer includes a first region in which wiring is formed, and a second region having a pad connected to the wiring formed in the first region and having a wiring width smaller than that of the first region, and the insulating layer is formed using a conductor only in a range overlapping with the second region in plan view, and has a conductor portion sandwiched by the insulating resin.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] In general, a wiring board on which a semiconductor chip or the like is mounted is provided with pads for bonding the semiconductor chip, etc. That is, when a semiconductor chip is mounted by flip-chip connection, for example, bumps are formed on each of a plurality of pads formed on the wiring board, and a plurality of terminals of the semiconductor chip are bonded to the bumps.

[0003] Since the pads of the wiring board are densely formed according to the positions of the terminals of the semiconductor chip, the area in the fan-out area near the pads where the wiring drawn from the pads can be formed is limited. Therefore, the wiring width in the fan-out area is sometimes made smaller than that in the global area where the wiring width optimized for impedance is adopted. By making the wiring width smaller, it is possible to ensure the distance between the wirings and between the wirings and the pads even in the fan-out area, and to reduce crosstalk. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-18097 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the above-mentioned wiring board has a problem that impedance mismatching may occur. Specifically, when the wiring width is narrowed in the fan-out area, the impedance of the wiring in the fan-out area increases. On the other hand, in the global area away from the pads, the wiring width can be set relatively freely, so that the wiring is formed with a wiring width that optimizes the impedance.

[0006] As a result, the wiring width changes at the boundary between the fan-out area and the global area, causing impedance mismatching. The greater the difference in impedance in this mismatch, the greater the signal reflection, and the worse the signal passing characteristics become. Here, the worsening of the passing characteristics refers to a state in which the voltage of the input signal is not obtained at the output side and is attenuated. Impedance mismatching can also cause reflected noise.

[0007] The disclosed technology has been made in consideration of the above points, and has an object to provide a wiring board capable of reducing impedance mismatching. [Means for solving the problem]

[0008] In one aspect, the wiring board disclosed in the present application has an insulating layer formed using an insulating resin and a wiring layer formed on a surface of the insulating layer, the wiring layer having a first region in which wiring is formed and a second region having a pad to which the wiring formed in the first region is connected and having a wiring width smaller than that of the first region, and the insulating layer has a conductor formed using a conductor only in an area that overlaps with the second region in a planar view and has a conductor portion sandwiched by the insulating resin. Effect of the Invention

[0009] According to one aspect of the wiring board disclosed in the present application, it is possible to reduce impedance mismatching. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a partial plan view showing the configuration of a wiring board according to a first embodiment. [Diagram 2] FIG. 2 is a diagram for explaining the position of the plane layer according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view showing the configuration of the wiring board according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing a specific example of a plane layer forming step. [Diagram 5] FIG. 5 is a diagram showing a specific example of the second insulating layer forming step. [Figure 6] FIG. 6 is a diagram showing a specific example of the polishing process. [Figure 7] FIG. 7 is a diagram showing a specific example of a wiring layer forming step. [Figure 8] FIG. 8 is a diagram showing the simulation results. [Figure 9] FIG. 9 is a diagram for explaining the position of the plane layer according to the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a configuration of a wiring board according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a modified example of the wiring board. [Figure 12] FIG. 12 is a diagram showing the simulation results. [Figure 13] FIG. 13 is a cross-sectional view showing another modified example of the wiring board. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of a wiring board disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiment.

[0012] (Embodiment 1) Fig. 1 is a partial plan view showing a configuration of a wiring board 100 according to embodiment 1. The wiring board 100 is a wiring board on which electronic components such as semiconductor chips can be mounted, and Fig. 1 is a partial plan view of the vicinity of an area where the semiconductor chip is mounted. The wiring board 100 shown in Fig. 1 has a fan-out area 110 and a global area 120.

[0013] The fan-out area 110 is an area having pads 101 for mounting a semiconductor chip. In the fan-out area 110, a plurality of pads 101 are formed in accordance with the positions of terminals of the semiconductor chip, and wiring 102 is drawn out from each pad 101. Since the wiring 102 is also formed between the pads 101, the wiring width of the wiring 102 is small in the fan-out area 110. Specifically, in the fan-out area 110, for example, L / S can be set to about 9 / 12 μm. The wiring width of the wiring 102 in the fan-out area 110 may be changed, for example, in the range of 5 to 20 μm, and the wiring interval of the wiring 102 in the fan-out area 110 may be changed, for example, in the range of 5 to 20 μm.

[0014] The global area 120 is an area that is away from the pads 101 and allows the wiring 102 to be routed relatively freely. For this reason, in the global area 120, the wiring width of the wiring 102 is adjusted to optimize the impedance, and the wiring width of the wiring 102 is larger than that of the fan-out area 110, for example. Specifically, in the global area 120, for example, L / S may be about 25 / 25 μm. The wiring width of the wiring 102 in the global area 120 may be changed within a range of, for example, 20 to 40 μm, and the wiring interval of the wiring 102 in the global area 120 may be changed within a range of, for example, 20 to 40 μm. Therefore, the wiring width of the wiring 102 changes at the boundary between the fan-out area 110 and the global area 120.

[0015] Furthermore, a ground pattern 103 connected to a ground power supply (not shown) is formed in the fan-out area 110 and the global area 120. The pads 101, the wiring 102, and the ground pattern 103 are all formed using a conductor such as copper or a copper alloy, and may have a thickness of, for example, about 10 to 20 μm.

[0016] In the wiring board 100 according to the present embodiment, a plane layer made of a conductor is formed in the inner layer of the region of the wiring 102 in the fan-out area 110, and the impedance of the wiring 102 in the fan-out area 110 is reduced. Therefore, even if the wiring width of the wiring 102 changes at the boundary between the fan-out area 110 and the global area 120, impedance mismatching at this boundary is reduced.

[0017] 2 is an enlarged plan view showing the fan-out area 110 and its vicinity of the wiring board 100. As shown in FIG. 2, the fan-out area 110 has a pad region 111 in which the pad 101 is formed, and a fine line region 112 in which the wiring 102 drawn from the pad 101 has a small wiring width. A plane layer made of a conductor is formed in the inner layer of the fine line region 112 surrounded by a dashed line in FIG. 2. The wiring 102 in the fine line region 112 faces the plane layer, generating a capacitance component, and the impedance of the wiring 102 decreases. As a result, it is possible to reduce impedance mismatching at the boundary between the fan-out area 110 and the global area 120.

[0018] Fig. 3 is a cross-sectional view showing the configuration of wiring board 100 according to embodiment 1. That is, Fig. 3(a) shows a cross section taken along line II in Fig. 2, and Fig. 3(b) shows a cross section taken along line II-II in Fig. 2. As shown in Fig. 3, wiring board 100 according to the present embodiment has a microstrip line.

[0019] 3(a), in the fine line region 112 of the fan-out area 110, a first insulating layer 210 is formed to cover the conductor layer 205, and a plane layer 215 is formed on the upper surface of the first insulating layer 210. Then, a second insulating layer 220 is formed to cover the plane layer 215, and a wiring 102a having a narrow wiring width is formed on the upper surface of the second insulating layer 220.

[0020] The conductor layer 205 is a ground pattern formed using a conductor such as copper or a copper alloy, and is connected to a ground power source (not shown). The thickness of the conductor layer 205 may be, for example, about 10 to 20 μm.

[0021] First insulating layer 210 is formed using an insulating resin such as epoxy resin or polyimide resin, and is laminated on conductor layer 205. First insulating layer 210 may have a thickness of, for example, about 5 to 15 μm.

[0022] The plane layer 215 is formed of a conductor such as copper or a copper alloy so as to cover the upper surface of the first insulating layer 210, and is a ground pattern connected to a ground power source (not shown). The plane layer 215 is formed only in an area overlapping with the fine line region 112 of the fan-out area 110 in a plan view, and generates a capacitance component between the plane layer 215 and the wiring 102a of the fine line region 112. This reduces the impedance of the wiring 102a. The thickness of the plane layer 215 can be, for example, about 5 to 20 μm.

[0023] The magnitude of the capacitance component generated between the plane layer 215 and the wiring 102a is determined according to the distance between the plane layer 215 and the wiring 102a, the surface area of ​​the wiring 102a, and the dielectric constant of the second insulating layer 220. Therefore, by adjusting the thickness of the second insulating layer 220, a desired capacitance component can be generated between the plane layer 215 and the wiring 102a, and the impedance of the wiring 102a can be reduced. Specifically, the thinner the thickness of the second insulating layer 220 is made to reduce the distance between the plane layer 215 and the wiring 102a, the larger the generated capacitance component becomes, and the lower the impedance of the wiring 102a becomes.

[0024] The second insulating layer 220 is formed using an insulating resin such as an epoxy resin or a polyimide resin, and is laminated on the plane layer 215. The thickness of the second insulating layer 220 may be, for example, about 5 to 10 μm, and is adjusted according to the desired capacitance component between the plane layer 215 and the wiring 102a.

[0025] A wiring layer including wires 102a having a small wiring width is formed on the upper surface of second insulating layer 220. In the wiring layer in fine line region 112, ground pattern 103 may be formed in addition to wires 102a.

[0026] 3(b), in the global area 120, the conductor layer 205 is integrally covered with the first insulating layer 210 and the second insulating layer 220, and the wiring 102b having a large wiring width is formed on the upper surface of the second insulating layer 220. That is, in the global area 120, the plane layer 215 is not formed, and a microstrip line is formed in which an insulating layer consisting of the first insulating layer 210 and the second insulating layer 220 is disposed between the wiring 102b and the conductor layer 205.

[0027] In this way, the plane layer 215 is formed in the fine line region 112 of the fan-out area 110, while the plane layer 215 is not formed in the global area 120. In other words, the plane layer 215 is formed only in an area overlapping with the fine line region 112 in a plan view, and is sandwiched between the insulating resins of the first insulating layer 210 and the second insulating layer 220. For this reason, a capacitance component is generated between the plane layer 215 and the wiring 102a having a small wiring width in the fine line region 112, and the impedance of only the wiring 102a decreases. As a result, it is possible to reduce impedance mismatching between the wiring 102a having a small wiring width and the wiring 102b having a large wiring width.

[0028] Next, a method for manufacturing the wiring board 100 configured as above will be described.

[0029] First, for example, copper foil is formed on the upper surface of the first insulating layer 210 laminated on the conductor layer 205. The thickness of the copper foil can be, for example, about 5 to 20 μm. Then, the copper foil in the unnecessary region is removed by, for example, etching, to form the plane layer 215 as shown in Fig. 4. That is, the copper foil in the regions corresponding to the pad region 111 of the fan-out area 110 and the global area 120 is removed, so that the copper foil only in the fine line region 112 of the fan-out area 110 remains, and the plane layer 215 is formed.

[0030] When the plane layer 215 is formed, the second insulating layer 220 is laminated on the first insulating layer 210 and the plane layer 215. That is, for example, as shown in Fig. 5, in the fine line region 112 of the fan-out area 110, the second insulating layer 220 is laminated on the plane layer 215, and in the pad region 111 and global area 120 of the fan-out area 110, the second insulating layer 220 is laminated on the first insulating layer 210.

[0031] The second insulating layer 220 is polished, for example, by CMP (Chemical Mechanical Polishing) or blasting, and processed to a thickness that reduces the impedance of the narrow-width wiring 102a to a desired value. That is, for example, as shown in Fig. 6, the upper surface of the second insulating layer 220 is polished to adjust the distance between the plane layer 215 and the upper surface of the second insulating layer 220. This polishing reduces the thickness of the second insulating layer 220 to, for example, about 5 to 10 µm.

[0032] Then, a wiring layer is formed on the upper surface of the second insulating layer 220. Specifically, a wiring layer having the pads 101, the wiring 102, and the ground pattern 103 is formed on the upper surface of the second insulating layer 220. The wiring layer may be formed by a semi-additive method using plating, or may be formed by a subtractive method using etching. At this time, as shown in FIG. 7, for example, in the fan-out area 110, a wiring 102a having a small wiring width is formed. On the other hand, in the global area 120, a wiring 102b having a large wiring width is formed. The wiring 102a in the fan-out area 110 may have a wiring width of, for example, about 10 to 20 μm, and the wiring 102b in the global area 120 may have a wiring width of, for example, about 20 to 40 μm.

[0033] By the above steps, it is possible to manufacture the wiring board 100 having the plane layer 215 only in the fine line region 112 of the fan-out area 110.

[0034] FIG. 8 shows a simulation result of the impedance in the wiring 102 of the wiring board 100 configured as described above. The wiring 102 forms a microstrip line shown in FIG. 8(a). As shown in FIGS. 8(a) and 8(b), the wiring width w of the wiring 102a in the fan-out area 110 is 13 μm, and the wiring width w of the wiring 102b in the global area 120 is 40 μm. In addition, in the global area 120, the distance h from the wiring 102b to the conductor layer 205 (i.e., the sum of the thicknesses of the first insulating layer 210 and the second insulating layer 220) is 20 μm, and in the fan-out area 110, the distance h from the wiring 102a to the plane layer 215 (i.e., the thickness of the second insulating layer 220) is 7 μm. The thickness t of each of the wirings 102a and 102b is 15 μm.

[0035] In this case, the impedance of the wiring 102b in the global area 120 is optimized to about 50Ω. In the fan-out area 110, the impedance of the wiring 102a would be about 81Ω if the plane layer 215 was not present, but the impedance of the wiring 102a is reduced to about 52Ω by forming the plane layer 215. In other words, the impedance mismatching at the boundary between the global area 120 and the fan-out area 110 can be reduced by forming the plane layer 215.

[0036] As described above, according to this embodiment, since the plane layer is formed inside the thin line region of the fan-out area, a capacitance component occurs between the wiring in the thin line region and the plane layer, and the impedance of the wiring decreases. As a result, it is possible to reduce the impedance mismatch between the wiring in the global area, which has a large wiring width, and the wiring in the fan-out area, which has a small wiring width.

[0037] (Embodiment 2) The second embodiment is characterized in that a plane layer is provided that extends over the entire fan-out area and does not overlap with the pads.

[0038] A plan view of wiring board 100 according to the second embodiment is similar to that of the first embodiment (FIG. 1), and therefore a description thereof will be omitted.

[0039] FIG. 9 is an enlarged plan view showing the vicinity of the fan-out area 110 of the wiring board 100 according to the second embodiment. As shown in FIG. 9, the fan-out area 110 has a pad region 111 in which the pad 101 is formed, and a fine line region 112 in which the wiring 102 drawn from the pad 101 has a small wiring width. A plane layer 215 made of a conductor is formed in the inner layer of the fan-out area 110 surrounded by a dashed line in FIG. 9. This plane layer 215 has a through hole at a position overlapping with the pad 101 in a plan view, and faces only the wiring 102 in the pad region 111 and the fine line region 112. The wiring 102 in the fan-out area 110 faces the plane layer 215, generating a capacitance component, and the impedance of the wiring 102 decreases. As a result, it is possible to reduce impedance mismatching at the boundary between the fan-out area 110 and the global area 120.

[0040] 10 is a cross-sectional view showing the configuration of wiring board 100 according to embodiment 2. That is, Fig. 10 is a cross-sectional view showing the cross section taken along line III-III in Fig. 9.

[0041] 10, in the pad region 111 of the fan-out area 110, a first insulating layer 210 is formed to cover the conductor layer 205, and a plane layer 215 is formed on the upper surface of the first insulating layer 210. Then, a second insulating layer 220 is formed to cover the plane layer 215, and a wiring 102a having a small wiring width is formed on the upper surface of the second insulating layer 220.

[0042] The plane layer 215 according to this embodiment covers the upper surface of the first insulating layer 210 only in the region facing the wiring 102a having a small wiring width, and has a through hole 215a formed in the region overlapping with the pad 101. Therefore, no capacitance component is generated in the pad 101, and the impedance of only the wiring 102a can be reduced even in the pad region 111. As a result, the impedance of the wiring 102a in the entire fan-out area 110 can be reduced, and the impedance mismatch with the wiring 102b in the global area 120 having a large wiring width can be reduced.

[0043] As described above, according to this embodiment, a plane layer facing the wiring is formed in the inner layer of the fan-out area, so that a capacitance component is generated between the wiring in the fan-out area and the plane layer, and the impedance of the wiring is reduced. As a result, it is possible to reduce impedance mismatching between the wiring in the global area, which has a large wiring width, and the wiring in the fan-out area, which has a small wiring width.

[0044] In the above first and second embodiments, wiring board 100 has a microstrip line. However, even if wiring board 100 has a strip line, impedance mismatching can be reduced by providing plane layer 215.

[0045] Fig. 11 is a cross-sectional view showing a modified example of the wiring board 100. That is, Fig. 11(a) shows a cross-section of the fine line region 112 of the fan-out area 110, and Fig. 11(b) shows a cross-section of the global area 120. As shown in Fig. 11, this wiring board 100 has a stripline.

[0046] As shown in FIG. 11(a), in the fine line region 112 of the fan-out area 110, a third insulating layer 310 and a conductor layer 315 are formed on top of the conductor layer 205, the first insulating layer 210, the plane layer 215, the second insulating layer 220 and the wiring 102a shown in FIG. 3(a).

[0047] The third insulating layer 310 is formed using an insulating resin such as an epoxy resin or a polyimide resin, and is laminated on the wiring layer having the wiring 102a. The thickness of the third insulating layer 310 can be, for example, about 20 to 40 μm.

[0048] Conductive layer 315 is formed using a conductor such as copper or a copper alloy so as to cover the upper surface of third insulating layer 310, and is a ground pattern connected to a ground power source (not shown). Conductive layer 315 may have a thickness of, for example, about 10 to 20 μm.

[0049] 11(b), in the global area 120, the conductor layer 205 is integrally covered with the first insulating layer 210 and the second insulating layer 220, and the wiring 102b having a large wiring width is formed on the upper surface of the second insulating layer 220. Then, the third insulating layer 310 and the conductor layer 315 are formed on the upper layer of the wiring 102b. That is, in the global area 120, the plane layer 215 is not formed, and the wiring 102b is sandwiched between the insulating layer consisting of the first insulating layer 210 and the second insulating layer 220 and the third insulating layer 310, and the conductor layer 205 and the conductor layer 315 are laminated on these insulating layers to form a stripline.

[0050] Even when the wiring board 100 has a stripline in this manner, by forming the plane layer 215 only in the fine line region 112 of the fan-out area 110, the impedance of only the wiring 102a is reduced, thereby reducing the impedance mismatch with the wiring 102b.

[0051] FIG. 12 shows the results of a simulation of the impedance of the wiring 102 of the wiring board 100 configured as described above. The wiring 102 forms a strip line shown in FIG. 12(a). As shown in FIGS. 12(a) and 12(b), the wiring width w of the wiring 102a in the fan-out area 110 is 14 μm, and the wiring width w of the wiring 102b in the global area 120 is 28 μm. In addition, in the global area 120, the distance h1 from the wiring 102b to the conductor layer 205 (i.e., the sum of the thicknesses of the first insulating layer 210 and the second insulating layer 220) is 33 μm, and in the fan-out area 110, the distance h1 from the wiring 102a to the plane layer 215 (i.e., the thickness of the second insulating layer 220) is 14 μm. The thicknesses t of the wirings 102a and 102b are both 15 μm, and the thickness h2 of the third insulating layer 310 is 33 μm.

[0052] In this case, the impedance of the wiring 102b in the global area 120 is optimized to about 50Ω. In the fan-out area 110, the impedance of the wiring 102a would be about 64Ω if the plane layer 215 was not present, but the impedance of the wiring 102a is reduced to about 51Ω by forming the plane layer 215. In other words, the impedance mismatching at the boundary between the global area 120 and the fan-out area 110 can be reduced by forming the plane layer 215.

[0053] Furthermore, even when wiring board 100 has a strip line, it is possible to provide plane layer 215 that spreads over the entire fan-out area and does not overlap pads 101, as in the second embodiment.

[0054] Specifically, Fig. 13 is a cross-sectional view showing a modified example of the cross section taken along line III-III in Fig. 9. In Fig. 13, the same parts as those in Figs. 10 and 11 are given the same reference numerals. As shown in Fig. 13, this wiring board 100 has a strip line. That is, as shown in Fig. 13, in the pad region 111 of the fan-out area 110, a third insulating layer 310 and a conductor layer 315 are formed on the conductor layer 205, the first insulating layer 210, the plane layer 215, the second insulating layer 220, and the wiring 102a.

[0055] This plane layer 215 covers the top surface of the first insulating layer 210 only in the region facing the wiring 102a with a small wiring width, and has a through hole 215a formed in the region overlapping with the pad 101. Therefore, no capacitance component is generated in the pad 101, and the impedance of only the wiring 102a can be reduced even in the pad region 111. As a result, the impedance of the wiring 102a in the entire fan-out area 110 can be reduced, and the impedance mismatch with the wiring 102b in the global area 120 with a large wiring width can be reduced.

[0056] In the above-described embodiments, wiring board 100 has wiring 102 in one wiring layer, but wiring board 100 may be a multi-layer board. That is, one or more insulating layers and conductor layers may be laminated below conductor layer 205 of wiring board 100 according to the first and second embodiments. [Explanation of symbols]

[0057] 101 Pad 102, 102a, 102b Wiring 103 Grand Pattern 110 Fanout Area 111 Pad Area 112 Thin line area 120 Global Area 205, 315 Conductor layer 210 First insulating layer 215 Plain Layer 215a Through hole 220 Second insulating layer 310 3rd insulating layer

Claims

1. an insulating layer formed using an insulating resin; a wiring layer formed on a surface of the insulating layer, The wiring layer is a first region in which wiring is formed, and a second region having a pad to which the wiring formed in the first region is connected and having a wiring width smaller than that of the first region; The insulating layer is a conductor portion formed using a conductor only in an area overlapping with the second region in a plan view and sandwiched by the insulating resin; The conductor portion is A through hole is provided at a position corresponding to the pad. A wiring board comprising:

2. a conductor layer that covers a surface of the insulating layer opposite to a surface on which the wiring layer is formed and is formed in a range that overlaps with the first region and the second region in a plan view; 2. The wiring board according to claim 1, further comprising:

3. The conductor portion is Connected to the ground power supply 2. The wiring board according to claim 1.

4. Another insulating layer covering the wiring layer; Another conductor layer laminated on the other insulating layer; 2. The wiring board according to claim 1, further comprising:

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