Power diode element and its manufacturing method

Abstract

To provide a power diode element having a reduced surface field (RESURF) effect, and a manufacturing method thereof.SOLUTION: In a power diode element 1 having a substrate 10, the substrate 10 includes a core layer 10b having a first conductivity type, a first diffusion layer 10a having the first conductivity type, a second diffusion layer 10c having a second conductivity type, and a highly doped contact region 11 having the second conductivity type. The thickness of the core layer 10b is thicker than the second diffusion layer 10c. The core layer 10b is located between the first diffusion layer 10a and the second diffusion layer 10c. The highly doped contact region 11 extends toward the core layer 10b, thereby forming a first PN junction S1 between the highly doped contact region 11 and the core layer 10b.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power diode element and a manufacturing method thereof, and more particularly to a power diode element having a reduced surface field (RESURF) effect. [Background technology]

[0002]

[0002] Well-known power diodes have a mesa structure to define an active area and a junction termination. The mesa structure can be formed by etching the side of a substrate through an etching process. Since the mesa is formed on the upper half of the substrate, the thickness is relatively thin and the structural strength may be reduced. In addition, if the slope of the mesa side is not precisely controlled during the etching process, the electrical performance of the power diode may be affected, such as insufficient breakdown voltage.

[0003]

[0003] Also, by using a power diode having a planar structure and forming a guard ring, the distribution of the electric field can be made gentler, and the breakdown voltage of the power diode can be increased. However, for a high-voltage power diode (for example, a voltage exceeding 600V), the number of guard rings must be increased to further increase the breakdown voltage, but the size of the guard ring may be limited by the line width capability of the manufacturing process. In addition, as the number of guard rings increases, the proportion of the area occupied also increases, which is disadvantageous in reducing the volume of the device and increases the cost of the manufacturing process. Summary of the Invention

[0004]

[0004] An embodiment of the present invention relates to a power diode device. The power diode device includes a substrate including a core layer having a first conductivity type, a first diffusion layer having the first conductivity type, a second diffusion layer having a second conductivity type, and a heavily doped contact region having the second conductivity type. The core layer has a first surface and a second surface opposite the first surface. The first diffusion layer has a first surface and a second surface opposite the first surface. The second diffusion layer has a first surface and a second surface opposite the first surface. The core layer has a thickness greater than that of the second diffusion layer. The core layer is located between the first and second diffusion layers such that the first surface of the core layer faces the second surface of the first diffusion layer and the second surface of the core layer faces the first surface of the second diffusion layer, the second surface of the second diffusion layer forms the upper surface of the substrate, and the first surface of the first diffusion layer forms the lower surface of the substrate. The heavily doped contact region has a first surface and a second surface opposite the first surface, the second surface of the heavily doped contact region is coplanar with the second surface of the second diffusion layer, and the heavily doped contact region extends toward the core layer such that the first surface of the heavily doped contact region reaches the second surface of the core layer or reaches between the first surface of the core layer and the second surface of the core layer, but not the first surface of the core layer. A first PN junction is formed between the heavily doped contact region and the core layer.

[0005]

[0005] An embodiment of the present invention relates to a method for manufacturing a power diode device. The method includes forming a first diffusion layer having a first conductivity type in a substrate having a first conductivity type. The first diffusion layer has a first surface and a second surface opposite to the first surface. The first surface of the first diffusion layer forms a lower surface of the substrate. The method further includes forming a second diffusion layer having a second conductivity type in the substrate, where the second diffusion layer has a first surface and a second surface opposite to the first surface, and the second surface of the second diffusion layer forms a upper surface of the substrate. The first diffusion layer is not in contact with the second diffusion layer, and a portion interposed between the first diffusion layer and the second diffusion layer is a core layer. The method further includes forming a highly doped contact region having the second conductivity type in the second diffusion layer. The heavily doped contact region has a first surface and a second surface opposite the first surface, the second surface of the heavily doped contact region being coplanar with the top surface of the substrate. The method further includes diffusing the heavily doped contact region into the core layer to form a first PN junction between the heavily doped contact region and the core layer. [Brief description of the drawings]

[0006] Some exemplary embodiments of the present invention are best understood from the following detailed description when read in conjunction with the drawings, in which: It should be noted that the various features are not necessarily drawn to scale, and in fact the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. [Figure 1] FIG. 1 is a cross-sectional view of a power diode device according to some embodiments of the present application. [Figure 2A] FIG. 2 is a partial enlarged view of a power diode device according to some embodiments of the present application. [Figure 2B] 2B is a diagram showing an electric field strength curve along a tangent line X of the power diode element in FIG. 2A. FIG. [Figure 3A] 1 illustrates one or more stages in a method for manufacturing a power diode device according to some embodiments of the present application. [Figure 3B]1 illustrates one or more stages in a method for manufacturing a power diode device according to some embodiments of the present application. [Figure 3C] 1 illustrates one or more stages in a method for manufacturing a power diode device according to some embodiments of the present application. [Figure 3D] 1 illustrates one or more stages in a method for manufacturing a power diode device according to some embodiments of the present application. [Figure 3E] 1 illustrates one or more stages in a method for manufacturing a power diode device according to some embodiments of the present application. [Figure 3F] 1 illustrates one or more stages in a method for manufacturing a power diode device according to some embodiments of the present application. [Figure 3G] 1 illustrates one or more stages in a method for manufacturing a power diode device according to some embodiments of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007]

[0007] The same or similar components are designated by like reference numerals in the drawings and detailed description. Some embodiments of the present invention can be more readily understood from the following detailed description and drawings, in which:

[0008]

[0008] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are merely exemplary and are not intended to be limiting. In the present invention, a reference to forming a first feature above or on a second feature can include an embodiment in which the first feature and the second feature are formed in direct contact, and can also include an embodiment in which another feature is formed between the first feature and the second feature without the first feature and the second feature being in direct contact. Also, in the present invention, drawing numbers and / or letters may be duplicated among the embodiments. This duplication is done for simplicity and clarity, and does not in itself indicate a relationship between the embodiments and / or configurations discussed.

[0009]

[0009] In the following, the embodiments of the present invention are discussed in detail. However, it should be understood that the present invention provides many application concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are illustrative and do not limit the scope of the present invention.

[0010]

[0010] The present invention provides a power diode element and a manufacturing method thereof. Compared with a power diode element having a mesa structure, the power diode element of the present invention has a relatively high structural strength. Also, compared with a power diode element that forms a guard ring to make the electric field distribution gentle, the power diode element of the present invention is not limited by the line width capability of the manufacturing process, and has a relatively short terminal length, which is advantageous for reducing the volume of the element.

[0011]

[0011] Referring to Figure 1, Figure 1 is a cross-sectional view of a power diode device 1 according to some embodiments of the present application. The power diode device 1 can include a substrate 10, a heavily doped contact region 11, an isolation structure 12, an electrode layer 13, a passivation layer 14, and an electrode layer 15.

[0012]

[0012] The substrate 10 may include a semiconductor substrate. The substrate 10 may include, but is not limited to, silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), silicon carbide (SiC), indium phosphide (InP), zinc selenide (ZnSe) or other group VI, group III-V or group II-VI semiconductor materials. In some embodiments, the substrate 10 may be formed using an N-type single crystal silicon wafer having a volume resistivity between about 45 and about 60 Ohm-cm. The substrate 10 may include a first diffusion layer 10a (hereinafter referred to as diffusion layer 10a), a core layer 10b and a second diffusion layer 10c (hereinafter referred to as diffusion layer 10c).

[0013]

[0013] The core layer 10b can be located between the diffusion layer 10a and the diffusion layer 10c. For example, the core layer 10b can be sandwiched between the diffusion layer 10a and the diffusion layer 10c. The core layer 10b can be a part of the original semiconductor substrate. The core layer 10b can be doped with N-type impurities, for example, the region marked "N" in FIG. 1. The N-type impurities can include pentavalent elements such as phosphorus, arsenic, and antimony. In another embodiment, the core layer 10b can be doped with P-type impurities, which are trivalent elements such as boron, aluminum, and gallium. The core layer 10b can include a first surface 10b1 (hereinafter, abbreviated as surface 10b1) and a second surface 10b2 (hereinafter, abbreviated as surface 10b2) facing the surface 10b1. A surface 10b1 of the core layer 10b faces the diffusion layer 10a, and a surface 10b2 of the core layer 10b faces the diffusion layer 10c.

[0014]

[0014] The diffusion layer 10a may include a semiconductor layer doped with N-type impurities. The diffusion layer 10a and the core layer 10b may have the same conductivity type, but the diffusion layer 10a may have a higher impurity concentration than the core layer 10b, and are therefore shown as "N+" regions in FIG. 1. The impurity concentration in the "N+" region or "P+" region used in the present invention is higher than the impurity concentration in its adjacent region. The diffusion layer 10a may include a first surface 10a1 (hereinafter abbreviated as surface 10a1) and a second surface (not shown in the figure, facing surface 10b1 of the core layer 10b) opposite to the surface 10a1. The surface 10a1 of the diffusion layer 10a forms the lower surface of the substrate 10.

[0015] In some embodiments, the diffusion layer 10a may be formed by diffusing N-type impurities from the bottom surface of the substrate 10 into the core layer 10b (e.g., as shown in FIG. 3A). In some embodiments, a diffusion boundary may be formed between the diffusion layer 10a and the core layer 10b. In some embodiments, the diffusion boundary between the diffusion layer 10a and the core layer 10b is a boundary between a high concentration N-type impurity (N+) region and an N-type impurity (N) region.

[0016]

[0016] The diffusion layer 10c may include a semiconductor layer doped with P-type impurities, as in the region indicated by "P" in FIG. 1. The diffusion layer 10c and the core layer 10b may have opposite conductivity types. The diffusion layer 10c and the diffusion layer 10a may have opposite conductivity types. The diffusion layer 10c may include a first surface (not shown in the figure, facing the surface 10b2 of the core layer 10b) and an opposing second surface 10c2 (hereinafter abbreviated as surface 10c2). The surface 10c2 of the diffusion layer 10c forms the upper surface of the substrate 10. That is, the surface 10c2 of the diffusion layer 10c and the surface 10a1 of the diffusion layer 10a may be two opposing surfaces of the substrate 10.

[0017]

[0017] In some embodiments, the diffusion layer 10c can be formed by inverting a part of the N-type core layer 10b from the top surface of the substrate 10 to P-type (e.g., as shown in FIG. 3C) and further diffusing it (e.g., as shown in FIG. 3F). For example, in some embodiments, the diffusion layer 10c can diffuse toward the core layer 10b simultaneously with the heavily doped contact region 11 during the diffusion of the heavily doped contact region 11, and form a diffusion boundary between the diffusion layer 10c and the core layer 10b. In some embodiments, the diffusion boundary between the diffusion layer 10c and the core layer 10b is a boundary between a P-type impurity (P) region and an N-type impurity (N) region or a PN junction S2.

[0018]

[0018] The heavily doped contact region 11 may be located in the substrate 10. In some embodiments, the heavily doped contact region 11 may be surrounded by the diffusion layer 10c. For example, the heavily doped contact region 11 may be located in the diffusion layer 10c. For example, in a cross-sectional view, the heavily doped contact region 11 may be located between two diffusion layers 10c on the left and right.

[0019]

[0019] The heavily doped contact region 11 may include a semiconductor layer doped with P-type impurities. The heavily doped contact region 11 and the diffusion layer 10c may have the same conductivity type, but the impurity concentration of the heavily doped contact region 11 may be higher than that of the diffusion layer 10c, and therefore is shown as a "P+" region in FIG.

[0020] In some embodiments, the heavily doped contact region 11 may be formed by diffusing P-type impurities from the top surface of the substrate 10 into the core layer 10b (e.g., as shown in FIG. 3F). In some embodiments, a diffusion boundary may be formed between the heavily doped contact region 11 and the core layer 10b. In some embodiments, the diffusion boundary between the heavily doped contact region 11 and the core layer 10b is a boundary between a P-type impurity (P) region and an N-type impurity (N) region or a PN junction S1.

[0021] In some embodiments, the PN junction S1 between the highly doped contact region 11 and the core layer 10b may be referred to as a first PN junction, and the PN junction S2 between the diffusion layer 10c and the core layer 10b may be referred to as a second PN junction. In some embodiments, the PN junction S2 and the PN junction S1 may be continuous junctions. In some embodiments, the PN junction S1 protrudes from the PN junction S2 in a direction from the upper surface of the substrate 10 toward the lower surface of the substrate 10.

[0022]

[0022] The heavily doped contact region 11 may include a first surface (coincident with the PN junction S1) and an opposing second surface (hereinafter abbreviated as surface 112). The surface 112 and the surface 10c2 of the diffusion layer 10c may be coplanar. In other words, the surface 112 and the top surface of the substrate 10 may be coplanar.

[0023]

[0023] In some embodiments, the heavily doped contact region 11 extends toward the core layer 10b, and its first surface (at the same position as the PN junction S1) can reach the surface 10b2 of the core layer 10b. For example, the PN junction S1 can be coplanar with the surface 10b2 of the core layer 10b. In some embodiments, the heavily doped contact region 11 extends toward the core layer 10b, and its first surface (at the same position as the PN junction S1) can reach between the surfaces 10b2 and 10b1 of the core layer 10b, but not to the surface 10b1. For example, the PN junction S1 can be located between the surfaces 10b2 and 10b1 of the core layer 10b. For example, the PN junction S1 can exceed the surface 10b2, but not exceed the surface 10b1.

[0024]

[0024] The isolation structure 12 may be located in the substrate 10. The isolation structure 12 may include a semiconductor layer doped with N-type impurities. The isolation structure 12 and the core layer 10b may have the same conductivity type, but the impurity concentration of the isolation structure 12 may be higher than the impurity concentration of the core layer 10b, which is shown as an "N+" region in FIG.

[0025]

[0025] In some embodiments, the isolation structure 12 can surround the diffusion layer 10c. In some embodiments, the isolation structure 12 can surround the heavily doped contact region 11. For example, in a cross-sectional view, the heavily doped contact region 11 can be located between two left and right isolation structures 12. The diffusion layer 10c can separate the heavily doped contact region 11 from the two left and right isolation structures 12. For example, the diffusion layer 10c can be located between the heavily doped contact region 11 and the isolation structure 12.

[0026]

[0026] In some embodiments, the isolation structure 12 may be formed by diffusing N-type impurities from the top surface of the substrate 10 into the core layer 10b (e.g., as shown in FIG. 3F). In some embodiments, a diffusion boundary may be formed between the isolation structure 12 and the diffusion layer 10c. In some embodiments, the diffusion boundary between the isolation structure 12 and the diffusion layer 10c is a boundary between an N-type impurity (N) region and a P-type impurity (P) region or a PN junction S3. In some embodiments, the PN junction S3 between the isolation structure 12 and the diffusion layer 10c may be referred to as a third PN junction. In some embodiments, the PN junction S3 and the PN junction S2 may be continuous junctions.

[0027] In some embodiments, a diffusion boundary may be formed between the isolation structure 12 and the core layer 10b. In some embodiments, the diffusion boundary between the isolation structure 12 and the core layer 10b is a boundary between a high concentration N-type impurity (N+) region and an N-type impurity (N) region.

[0028] In some embodiments, the isolation structure 12 can be diffused simultaneously with the heavily doped contact region 11. For example, the isolation structure 12 and the heavily doped contact region 11 can be formed in the same step. In some embodiments, the isolation structure 12 can extend toward the core layer 10b, and one of its surfaces can reach the surface 10b2 of the core layer 10b. For example, the diffusion boundary between the isolation structure 12 and the core layer 10b can be coplanar with the surface 10b2 of the core layer 10b. In some embodiments, the isolation structure 12 can extend toward the core layer 10b, and one of its surfaces can reach between the surface 10b2 and the surface 10b1 of the core layer 10b, but not to the surface 10b1. For example, the diffusion boundary between the isolation structure 12 and the core layer 10b can be between the surface 10b2 and the surface 10b1 of the core layer 10b. For example, the diffusion boundary between the isolation structure 12 and the core layer 10b can exceed the surface 10b2, but not exceed the surface 10b1.

[0029]

[0029] The electrode layer 15 (also referred to as the first electrode layer 15) may be located on the lower surface of the substrate 10. For example, the electrode layer 15 may be disposed on the surface 10a1 of the diffusion layer 10a. For example, the electrode layer 15 may contact or cover a portion of the diffusion layer 10a. For example, the electrode layer 15 may completely cover the surface 10a1 of the diffusion layer 10a. The electrode layer 15 may be considered an electrical terminal of the power diode element 1. For example, the electrode layer 15 may be electrically connected to an electrical terminal of the power diode element 1.

[0030]

[0030] An electrode layer 13 (also referred to as a second electrode layer 13) may be located on the upper surface of the substrate 10. For example, the electrode layer 13 may be disposed on the surface 112 of the heavily doped contact region 11. For example, the electrode layer 13 may contact or cover a portion of the heavily doped contact region 11. For example, the electrode layer 13 may contact or cover a portion of the isolation structure 12. The electrode layer 13 may be considered an electrical terminal of the power diode element 1. For example, the electrode layer 13 may be electrically connected to an electrical terminal of the power diode element 1. The substrate 10 may be sandwiched between the electrode layer 15 and the electrode layer 13.

[0031] In some embodiments, when viewed in cross-section, the width of electrode layer 15 may be greater than the width of electrode layer 13. In some embodiments, the total surface area of ​​electrode layer 15 may be greater than the total surface area of ​​electrode layer 13.

[0032] In some embodiments, electrode layer 15 and electrode layer 13 may comprise copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys. In some embodiments, electrode layer 15 and electrode layer 13 may comprise the same material, for example, both may comprise aluminum. In some embodiments, electrode layer 15 and electrode layer 13 may comprise different materials, for example, electrode layer 15 may be aluminum and electrode layer 13 may be silver, nickel, or titanium.

[0033]

[0033] The passivation layer 14 may be located on the upper surface of the substrate 10. For example, the passivation layer 14 may be disposed on the surface 112 of the heavily doped contact region 11. For example, the passivation layer 14 may be disposed on the surface 10c2 of the diffusion layer 10c. For example, the passivation layer 14 may contact or cover a portion of the surface 112 of the heavily doped contact region 11. For example, the passivation layer 14 may contact or cover a portion of the surface 10c2 of the diffusion layer 10c. For example, the passivation layer 14 may completely cover the surface 10c2 of the diffusion layer 10c. For example, the passivation layer 14 may contact or cover a portion of the isolation structure 12.

[0034]

[0034] In some embodiments, the passivation layer 14 may surround the electrode layer 13. For example, in a cross-sectional view, the electrode layer 13 may be located between two passivation layers 14 on the left and right. In some embodiments, the passivation layer 14 and the electrode layer 13 may be coplanar. However, in other embodiments, the passivation layer 14 and the electrode layer 13 may not be coplanar. For example, the edge of the passivation layer 14 may be covered by the electrode layer 13. For example, in a direction from the top surface of the substrate 10 toward the bottom surface of the substrate 10, the passivation layer 14 and the electrode layer 13 may overlap each other.

[0035] In some embodiments, the diffusion layer 10c can be a reduced surface field layer, for example, the diffusion layer 10c can achieve a more uniform electric field distribution, thereby increasing the breakdown voltage of the power diode device 1.

[0036]

[0036] In some embodiments, the diffusion layer 10c and the core layer 10b can be a depletion extension region DR. The diffusion layer 10c and the core layer 10b can relax the electric field that is originally concentrated between the highly doped contact region 11 and the isolation structure 12. For example, the impurity doping concentration of the diffusion layer 10c and the core layer 10b is lower than that of the isolation structure 12, so that when a reverse bias is applied to the power diode element 1, the carriers in the diffusion layer 10c and the core layer 10b are depleted, and the depletion extension region DR expands, thereby increasing the breakdown voltage of the power diode element 1. In other words, the length of the diffusion layer 10c can be adjusted based on the difference in the withstand voltage demand to relax the electric field strength.

[0037]

[0037] Fig. 2A is a partially enlarged view of the power diode element 1. Specifically, Fig. 2A shows the portion 2a of the power diode element in Fig. 1. The same or similar elements in Fig. 2 and Fig. 1 are represented by the same element reference numerals, and detailed descriptions of the elements will not be repeated.

[0038] In some embodiments, the thickness 10h of the substrate 10 may be between about 240 micrometers (μm) and about 280 μm, such as about 260 μm. In some embodiments, the thickness 10ah of the diffusion layer 10a may be between about 110 μm and about 150 μm, such as about 130 μm. In some embodiments, the thickness 10bh of the core layer 10b may be between about 80 μm and about 120 μm, such as about 100 μm. In some embodiments, the thickness 10ch of the diffusion layer 10c may be between about 10 μm and about 50 μm, such as about 30 μm.

[0039] In some embodiments, the thickness 10ch of the diffusion layer 10c and the thickness 10bh of the core layer 10b may be different. For example, the thickness 10ch of the diffusion layer 10c may be thinner than the thickness 10bh of the core layer 10b. For example, the thickness 10bh of the core layer 10b may be three or more times the thickness 10ch of the diffusion layer 10c.

[0040] In some embodiments, the thickness 10ch of the diffusion layer 10c may be different from the thickness 10ah of the diffusion layer 10a. For example, the thickness 10ch of the diffusion layer 10c may be thinner than the thickness 10ah of the diffusion layer 10a. For example, the thickness 10ah of the diffusion layer 10a may be four or more times the thickness 10ch of the diffusion layer 10c.

[0041] In some embodiments, the depth 11h of the heavily doped contact region 11 may be between about 10 μm and about 50 μm, e.g., about 30 μm. In some embodiments, the depth 12h of the isolation structure 12 may be between about 30 μm and about 70 μm, e.g., about 50 μm. In some embodiments, the depth 12h of the isolation structure 12 may be deeper than the depth 11h of the heavily doped contact region 11. For example, the isolation structure 12 and the heavily doped contact region 11 may be diffused simultaneously (e.g., as shown in FIG. 3F), and the carrier diffusion rate of the isolation structure 12 may be faster than the carrier diffusion rate of the heavily doped contact region 11.

[0042]

[0042] In some embodiments, the depth 11h of the heavily doped contact region 11 and the thickness 10ch of the diffusion layer 10c may be approximately equal. In some embodiments, the depth 11h of the heavily doped contact region 11 may be greater than the thickness 10ch of the diffusion layer 10c. In some embodiments, making the thickness 10ch of the diffusion layer 10c thinner than the thickness 10bh of the core layer 10b may increase manufacturing costs. However, controlling the thickness 10ch of the diffusion layer 10c to be between about 10 μm and about 50 μm (e.g., about 30 μm) to allow the heavily doped contact region 11 to diffuse into the core layer 10b can improve the surge capacity of the power diode device 1.

[0043] In some embodiments, the distance D1 between the heavily doped contact region 11 and the isolation structure 12 may be between about 160 μm and about 140 μm, for example about 150 μm. In some embodiments, the breakdown voltage can be adjusted by adjusting the distance D1. The higher the breakdown voltage to be experienced, the larger the distance D1 should be. In some embodiments, the isolation structure 12 may be a scribe line. In some embodiments, the distance D2 of the isolation structure 12 may be about 2.5 mils (mils) or 63.5 μm.

[0044] In some embodiments, the passivation layer 14 may include a laminate structure having multiple layers. For example, the passivation layer 14 may include an oxide layer 14a, a nitride layer 14b, an oxide layer 14c, and an insulating layer 14d. The oxide layer 14a and the oxide layer 14c may include low temperature oxide (LTO) layers. The oxide layer 14a and the oxide layer 14c may be arranged as a stress buffer layer. The nitride layer 14b may be silicon nitride (Si 3 N 4) The nitride layer 14b may be arranged to provide insulation against moisture and contamination. The insulating layer 14d may include a semi-insulating polycrystalline silicon (SIPOS) layer. The insulating layer 14d may be arranged to remove surface charge, for example to prevent leakage current caused by carriers accumulating on the surface of the power diode element.

[0045]

[0045] Figure 2B is a curve diagram of electric field strength along line XX in part 2a of the power diode element in Figure 2A. The X-axis represents the position along line XX in μm, and the Y-axis represents the electric field strength in volts / meter (V / m). Position L1 in Figure 2B corresponds to position L1 in Figure 2A, and position L2 in Figure 2B corresponds to position L2 in Figure 2A. The electric field peak value P1 is 1.05×10 5 V / m, its location being adjacent to the junction between the isolation structure 12 and the diffusion layer 10c. The electric field peak value P2 is 1.2×10 5 V / m, the location of which is adjacent to the junction between diffusion layer 10c and heavily doped contact region 11. The electric field peak value P2 is greater than the electric field peak value P1, i.e., the electric field adjacent to the junction between diffusion layer 10c and heavily doped contact region 11 is greater than the electric field adjacent to the junction between isolation structure 12 and diffusion layer 10c.

[0046]

[0046] The above embodiments relate to power diode elements fabricated using N-type monocrystalline silicon wafers. It should be noted that power diode elements fabricated using P-type monocrystalline silicon wafers with the opposite doping type are also within the scope of protection of the present invention. In one embodiment, the first conductivity type refers to doping with N-type impurities and the second conductivity type refers to doping with P-type impurities. In another embodiment, the first conductivity type refers to doping with P-type impurities and the second conductivity type refers to doping with N-type impurities.

[0047]

[0047] Referring to Figures 3A to 3G, Figures 3A to 3G are schematic diagrams of an embodiment of a method for manufacturing a power diode element 1. As in Figure 2A, the embodiment of Figures 3A to 3G will be illustratively described by the structure of the power diode element 2a of Figure 1 at each stage. Therefore, the same or similar elements in Figures 3A to 3G and Figure 1 are represented by the same element symbols, and detailed descriptions of the elements will not be repeated. At least some of these drawings have already been simplified to allow a better understanding of the aspects of the present invention.

[0048]

[0048] Referring to FIG. 3A, the manufacturing method includes forming a diffusion layer 10a in a substrate 10. The substrate 10 may include a semiconductor substrate doped with N-type or P-type impurities. In the embodiments shown in FIGS. 3A-3G and the following description, an N-type silicon wafer is used as the substrate 10. In some embodiments, the thickness 10h' of the substrate 10 may be between about 480 μm and about 520 μm. In some embodiments, an N-type silicon wafer with a volume resistivity between about 45 and about 60 Ohm-cm may be used.

[0049] In some embodiments, the N-type impurities can be diffused from the bottom surface of the substrate 10 through a backside diffusion technique. For example, the bottom surface of the substrate 10 can be covered with phosphorus paper before diffusion, and a relatively deep N+ layer can be formed by widening the diffusion boundary. In some embodiments, the diffusion can be performed at a temperature of about 1280° C. for about 22 hours. In some embodiments, the thickness 10ah of the diffusion layer 10a can be between about 110 μm and about 150 μm, for example about 130 μm. The remaining portion of the substrate 10 can form the core layer 10b. In some embodiments, the surface 10a1 of the diffusion layer 10a can form the bottom surface of the substrate 10, and a diffusion boundary (coincident with the surface 10b1 of the core layer 10b) can be formed between the diffusion layer 10a and the core layer 10b. In other embodiments, a gas or liquid phase N-type impurity diffusion source can be used.

[0050]

[0050] In another embodiment, N-type impurities can be diffused from the top and bottom surfaces of the substrate 10 through a double-side diffusion technique. The substrate 10 forms an N+ / N / N+ structure after double-side diffusion. The remaining part of the substrate 10 can form a core layer 10b. For example, the core layer 10b can be sandwiched between two upper and lower diffusion layers with relatively high impurity concentrations.

[0051]

[0051] Referring to Figure 3B, the manufacturing method includes grinding and buffing the substrate 10 to remove a portion of the core layer 10b and reduce the thickness 10h of the substrate 10 to between about 240 μm and about 280 μm, for example to about 260 μm.

[0052]

[0052] In another embodiment, when N-type impurities are diffused from the top and bottom surfaces of the substrate 10 by a double-sided diffusion technique, the manufacturing method includes polishing and buffing the substrate 10 to remove one diffusion layer therein to expose the core layer 10b and reducing the thickness 10h of the substrate 10 to between about 240 μm and about 280 μm, for example about 260 μm.

[0053]

[0053] Referring to FIG. 3C, the method includes forming a diffusion layer 10c in the substrate 10. Taking boron as an example, a part of the core layer 10b can be inverted from N-type to P-type using a method of liquid-phase source diffusion, solid-phase source diffusion, or ion implantation. In some embodiments, the method of ion implantation is adopted. In some embodiments, the diffusion layer 10c can be formed by annealing, oxidation, and diffusion. In some embodiments, before forming the diffusion layer 10c, an oxide layer can be first formed on the core layer 10b as a buffer layer to avoid the generation of defects during ion implantation. In some embodiments, the surface 10c2 of the diffusion layer 10c can form the upper surface of the substrate 10, and a diffusion boundary (same position as the surface 10b2' of the core layer 10b) can be formed between the diffusion layer 10c and the core layer 10b.

[0054]

[0054] Referring to Figure 3D, the manufacturing method includes forming an isolation structure 12 in a substrate 10. In some embodiments, a protective layer 30, such as a mask or photomask, can be formed on a surface 10c2 of the diffusion layer 10c. An opening 30h can be formed in the protective layer 30 to define a location where the isolation structure 12 is to be formed. In some embodiments, phosphorus can be used as an example, by forming phosphorus oxychloride (POCl 3 ) as a phosphorus source. A primary diffusion is then performed on the pre-deposited substrate 10 to extend the diffusion boundary and form a relatively deep N+ layer. Similar to the diffusion layer 10a, the isolation structure 12 can be permeable to phosphorus paper, a gas-phase or liquid-phase N-type impurity diffusion source.

[0055]

[0055] Referring to FIG. 3E, the method includes forming a heavily doped contact region 11 in the substrate 10. In some embodiments, the protective layer 30 can be removed. The protective layer 30 can be removed by etching, stripping, or other suitable manufacturing process. A protective layer 31, such as a mask or photomask, can be formed on the surface 10c2 of the diffusion layer 10c. An opening 31h can be formed in the protective layer 31 to define a location where the heavily doped contact region 11 is to be formed. In some embodiments, using boron as an example, boron trichloride (BCl 3 ) as a boron source. A primary diffusion is then performed on the pre-deposited substrate 10 to extend the diffusion boundary and form a relatively deep P+ layer. The heavily doped contact region 11 can include a surface 112. In some embodiments, the surface 112 can be coplanar with the surface 10c2. The surface 112 can be coplanar with the top surface of the substrate 10.

[0056]

[0056] Referring to Fig. 3F, the manufacturing method includes diffusing the highly doped contact region 11 toward the core layer 10b. In some embodiments, the highly doped contact region 11 can be diffused toward the core layer 10b so that the surface of the highly doped contact region 11 reaches the surface 10b2 of the core layer 10b or reaches between the surface 10b2 and the surface 10b1 of the core layer 10b, but does not reach the surface 10b1. In some embodiments, the highly doped contact region 11 can be diffused toward the core layer 10b so that a PN junction S1 is formed between the highly doped contact region 11 and the core layer 10b.

[0057] In some embodiments, the protective layer 31 may be removed. The protective layer 31 may be removed by etching, stripping, or other suitable manufacturing process. A protective layer 32, such as a mask or photomask, may be formed on the surface 10c2 of the diffusion layer 10c and the surface 112 of the highly doped contact region 11. In some embodiments, the diffusion may be performed at a temperature of about 1250° C. for about 15 hours.

[0058] In some embodiments, the diffusion layer 10c can be diffused simultaneously with the heavily doped contact region 11. For example, the diffusion layer 10c and the heavily doped contact region 11 can be formed in the same step. In some embodiments, the diffusion layer 10c can diffuse toward the core layer 10b, and the surface 10b2' (as shown in FIG. 3E) between the diffusion layer 10c and the core layer 10b can move downward to become the surface 10b2, forming the PN junction S2.

[0059] In some embodiments, the PN junction S2 and the PN junction S1 may be continuous. In some embodiments, the PN junction S1 protrudes from the PN junction S2 in a direction from the top surface of the substrate 10 toward the bottom surface of the substrate 10.

[0060]

[0060] In some embodiments, the isolation structure 12 can be diffused simultaneously with the heavily doped contact region 11. For example, the isolation structure 12 and the heavily doped contact region 11 can be formed in the same step. In some embodiments, the isolation structure 12 can diffuse toward the core layer 10b so that its surface can reach the surface 10b2 of the core layer 10b, or can reach between the surface 10b2 and the surface 10b1 of the core layer 10b, but not reach the surface 10b1. In some embodiments, the carrier diffusion rate of the isolation structure 12 can be faster than that of the heavily doped contact region 11, so that the depth 12h of the isolation structure 12 can be greater than the depth 11h of the heavily doped contact region 11.

[0061] 3G, the manufacturing method includes forming a passivation layer 14 on an upper surface of the substrate 10. In some embodiments, the protective layer 32 may be removed. The protective layer 32 may be removed by etching, stripping, or other suitable manufacturing process.

[0062]

[0062] Then, the electrode layer 13 and the electrode layer 15 are formed on the upper and lower surfaces of the substrate 10 through a metal mask (not shown in the figure). In some embodiments, the electrode layer 13 and the electrode layer 15 can be formed by sputtering, chemical plating, electroplating, printing or other suitable manufacturing process. The metal mask can be removed by etching, stripping or other suitable manufacturing process. The semiconductor structure formed through the above steps may be the same as the portion 2a of the power diode element in FIG. 2A.

[0063]

[0063] In the manufacturing method of the power diode element of the present application, the diffusion layer 10c is formed using an N-type (or P-type) single crystal silicon wafer. Compared with the case of using an epitaxial layer, the cost of forming the diffusion layer 10c is relatively low. In addition, in the diffusion process, the thickness 10ch of the diffusion layer 10c is controlled not to exceed 50 μm or not to exceed 30 μm, so that the highly doped contact region 11 can be diffused relatively easily into the core layer 10b, and the surge capability of the power diode element 1 can be improved.

[0064]

[0064] In addition, the manufacturing method of the power diode element of the present application uses three photomasks. Compared with the manufacturing method of the power diode element in which a protective ring is formed to alleviate the electric field distribution (which usually requires at least four photomasks), the number of photomasks required in the present application is relatively small, which simplifies the manufacturing process and reduces the cost.

[0065]

[0065] For ease of description, spatially-corresponding terms such as "below," "lower," "lower," "upper," "top," "left," and "right" are used in the text to describe the relationship of one component or feature to another or multiple components or features as shown in the drawings. In addition to the orientations shown in the drawings, the spatially-corresponding terms may cover different orientations in use or operation of the device. Other manners of orientation (rotated 90 degrees or other orientations) of the device may be used, and the spatially-corresponding terms used in the text may be interpreted accordingly. When a component is referred to as being "connected" or "coupled" to another component, it should be understood that the component may be directly connected or coupled to the other component, or intermediate components may be present.

[0066]

[0066] As used herein, the terms "generally," "essentially," "approximately," and "about" are used to describe and interpret small variations. When used in conjunction with an event or circumstance, the term can refer to instances where the event or circumstance definitely occurred, and instances where the event or circumstance is about to occur. When used herein with respect to a given value or range, the term "about" means generally within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges are expressed herein as from one endpoint to another endpoint, or between two endpoints. All ranges disclosed herein include the endpoints unless expressly stated otherwise. The term "approximately coplanar" can refer to two surfaces positioned along the same plane being within a few micrometers (μm) of difference, for example, within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of difference in positions positioned along the same plane. When numerical values ​​or characteristics are referred to as "essentially" the same, the term can refer to values ​​within ±10%, ±5%, ±1% or ±0.5% of the mean value of the value.

[0067]

[0067] The foregoing has outlined several exemplary embodiments and detailed aspects of the present invention. The described embodiments of the present invention may be readily utilized as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages of the embodiments presented herein. Various modifications, substitutions and alterations may be made thereto without departing from the spirit and scope of the present invention, provided that such equivalent structures are within the scope of the present invention. [Explanation of symbols]

[0068]

[0068] 1 Power diode element 2a Part of a power diode element 10 Substrate 10a Diffusion layer 10a1 surface 10ah thickness 10b Core layer 10b1 surface 10b2 surface 10b2' surface 10bh thickness 10c Diffusion layer 10c2 surface 10ch Thickness 10h thickness 10h' thickness 11 Highly doped contact region 11h Depth 12 Isolation structure 12h depth 13 Electrode layer 14 Passive layer 14a Oxide layer 14b Nitride layer 14c oxide layer 14d Insulation layer 15 Electrode layer 30 protective layer 30h opening 31 Protective layer 31h opening 32 Protective layer 112 Surface D1 Distance D2 distance DR Depletion Extension Region L1 position L2 position P1 Peak value P2 peak value S1 PN junction S2 PN junction S3 PN junction X tangent

Claims

1. A power diode element, a substrate, the substrate comprising: a core layer having a first surface and a second surface opposite to the first surface, the core layer having a first conductivity type; a first diffusion layer having a first surface and a second surface opposite to the first surface, the first diffusion layer having the first conductivity type; a second diffusion layer having a first surface and a second surface opposite to the first surface, the second diffusion layer having a second conductivity type, the core layer having a thickness greater than that of the second diffusion layer, the core layer being positioned between the first diffusion layer and the second diffusion layer such that the first surface of the core layer faces the second surface of the first diffusion layer and the second surface of the core layer faces the first surface of the second diffusion layer, the second surface of the second diffusion layer forming an upper surface of the substrate, and the first surface of the first diffusion layer forming a lower surface of the substrate; a heavily doped contact region having the second conductivity type, the heavily doped contact region having a first surface and a second surface opposite the first surface, the second surface of the heavily doped contact region being coplanar with the second surface of the second diffusion layer, and the heavily doped contact region extending toward the core layer, the first surface of the heavily doped contact region reaching the second surface of the core layer or reaching between the first and second surfaces of the core layer but not reaching the first surface, forming a first PN junction between the heavily doped contact region and the core layer; an isolation structure having the first conductivity type is formed in the second diffusion layer; Power diode element.

2. 2. The power diode element of claim 1, wherein said core layer and said second diffusion layer form a second PN junction, and said first PN junction and said second PN junction form a continuous PN junction.

3. 3. The power diode element of claim 2, wherein a first direction is a direction from the top surface of the substrate toward the bottom surface of the substrate, and in the continuous PN junctions, the first PN junction protrudes from the second PN junction along the first direction.

4. The substrate further comprises: an isolation structure surrounding the heavily doped contact region, the isolation structure and the heavily doped contact region being separated by the second diffusion layer; 2. The power diode element of claim 1.

5. 5. The power diode device of claim 4, wherein the isolation structure has a depth greater than that of the highly doped contact region.

6. a first electrode layer located on the lower surface of the substrate and in contact with the first diffusion layer; a second electrode layer located on the top surface of the substrate and in contact with the highly doped contact region.

2. The power diode element of claim 1.

7. a passivation layer located on the top surface of the substrate, contacting the highly doped contact region and surrounding the second electrode layer. The power diode element of claim 6.

8. 1. A method for manufacturing a power diode element, the method comprising: forming a first diffusion layer having a first conductivity type in the substrate having a first conductivity type, the first diffusion layer having a first surface and a second surface opposite the first surface, the first surface forming a lower surface of the substrate; forming a second diffusion layer in the substrate having a second conductivity type, the second diffusion layer having a first surface and a second surface opposite the first surface, the second surface forming a top surface of the substrate, the second surface not in contact with the first diffusion layer, and a portion between the second diffusion layer and the first diffusion layer being a core layer; forming a heavily doped contact region of the second conductivity type in the second diffusion layer having a first surface and a second surface opposite the first surface, the second surface being coplanar with the top surface of the substrate; diffusing the heavily doped contact region into the core layer to form a first PN junction between the heavily doped contact region and the core layer; Diffusing the highly doped contact region into the core layer further comprises: simultaneously diffusing the second diffusion layer and the highly doped contact region into the core layer to form a second PN junction between the core layer and the second diffusion layer. Manufacturing method.

9. forming the second diffusion layer having a second conductivity type in the substrate, further comprising: removing a portion of the substrate; forming the second diffusion layer by inverting another portion of the substrate from the first conductivity type to the second conductivity type. The method of claim 8.

10. Diffusing the highly doped contact region into the core layer further comprises: having the first surface of the highly doped contact region reach or protrude from the second PN junction. The method of claim 8.

11. The method of claim 10 , wherein the first PN junction and the second PN junction form a continuous PN junction.

12. forming an isolation structure having the first conductivity type in the second diffusion layer. The method of claim 8.

13. The method of claim 12 , wherein the isolation structure is formed before the highly doped contact region.

14. Diffusing the highly doped contact region into the core layer further comprises: simultaneously diffusing said isolation structure and said highly doped contact region into said core layer. The method of claim 12.

15. Simultaneously diffusing the isolation structure and the highly doped contact region into the core layer further comprises: a depth of the isolation structure that is greater than a depth of the highly doped contact region; The method of claim 14.

16. forming a passivation layer on the top surface of the substrate contacting the isolation structure and the highly doped contact region. The method of claim 12.

17. forming a first electrode layer on the lower surface of the substrate in contact with the first diffusion layer; forming a second electrode layer on the top surface of the substrate in contact with the highly doped contact region. The method of claim 8.

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