Semiconductor device and method for manufacturing the same

Abstract

To prevent short circuit of a junction layer due to molten metal at heat treatment, and to suppress a leak current to an adjoining semiconductor device when an overvoltage is applied.SOLUTION: The semiconductor device includes: a first substrate 11 having a diode structure section 80 composed of a first well region 81 formed in a first region having a first conductivity type along a bottom face, and exposed at a first opening OP1 and having a second conductivity type, and a second well region 82 having the first conductivity type; a semiconductor element 40 arranged on the first substrate 11 and having a semiconductor layer; a first external electrode 21 formed on a bottom face of a thermal oxide film 17, and brought into contact with the first well region in the first opening OP1; and a second external electrode 22 formed on the bottom face of the thermal oxide film 17, being apart from the first external electrode 21, and brought into contact with the second well region in a second opening OP2. The second well region extends along the bottom face of the substrate to a side of the first opening OP1, while exceeding an intermediate line of the first opening OP1 and the second opening OP2.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In recent years, light emitting devices incorporating an overvoltage protection element inside a mounting substrate on which a semiconductor element such as a light emitting element is mounted have become widespread.

[0003] For example, Patent Document 1 discloses a semiconductor device in which a Zener diode is formed as a semiconductor element, the semiconductor element being made of a semiconductor substrate (i.e., a P-type silicon semiconductor substrate) made of silicon in which P-type impurities have been diffused in advance, and an N-layer in which N-type impurities have been injected and diffused on the mounting surface side, which is the upper surface of the semiconductor substrate, on which a light-emitting element is mounted. In the semiconductor device, the light-emitting element is connected in a flip-chip manner to a pair of upper-surface wiring layers formed on the upper surface of the semiconductor substrate via bumps made of gold (Au). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-21987 A Summary of the Invention [Problem to be solved by the invention]

[0005] In general, the distance between the anode and cathode electrodes of a semiconductor element such as a light-emitting element is smaller than the distance between the electrodes of the mounting electrodes formed on the outside of the semiconductor device. Therefore, in Patent Document 1, when the upper wiring layer of the semiconductor substrate and the light-emitting element are bonded using a molten metal such as a gold-tin (AuSn) alloy as a bonding layer, the molten bonding layer on the electrode of one polarity may come into contact with the other polarity part of the semiconductor element (Zener diode) formed on the upper surface side inside the semiconductor substrate during the heat treatment for bonding, which may cause a short circuit in the semiconductor device.

[0006] In Patent Document 1, the entire semiconductor substrate functions as the P layer of the semiconductor element (Zener diode). Therefore, when an overvoltage is applied to a semiconductor device mounted on a mounting substrate, a current caused by avalanche breakdown of the semiconductor element (Zener diode) may be transmitted as a leak current to other semiconductor elements or semiconductor devices adjacent to the semiconductor device on the mounting substrate, possibly resulting in malfunction.

[0007] The present invention has been made in consideration of the above points, and has an object to provide a semiconductor device and a method for manufacturing a semiconductor device that are capable of preventing a short circuit caused by molten metal during heat treatment of a bonding layer, and that are capable of suppressing leakage current to adjacent semiconductor devices when an overvoltage is applied after being mounted on a mounting board. [Means for solving the problem]

[0008] A semiconductor device according to the present invention has a diode structure having a first conductivity type, thermal oxide films formed on an upper surface and a lower surface, a first opening and a second opening spaced apart from each other formed in the thermal oxide film formed on the lower surface, a first well region having a second conductivity type different from the first conductivity type formed in a first region along the lower surface and exposed at the first opening, and a second well region having the first conductivity type formed in a second region along the lower surface within the first region and exposed at the second opening. The semiconductor device includes a substrate made of single crystal silicon, a semiconductor element disposed on the substrate and having a semiconductor layer, a first external electrode formed on the underside of the thermal oxide film and in contact with the first well region at the first opening, and a second external electrode formed on the underside of the thermal oxide film, spaced apart from the first external electrode and in contact with the second well region at the second opening, wherein the second well region extends along the underside of the substrate, beyond a midline between the first opening and the second opening, to the side of the first opening.

[0009] A method for manufacturing a semiconductor device according to the present invention includes the steps of: preparing a substrate made of single crystal silicon having a first conductivity type; a first diffusion step of forming a first well region having a second conductivity type different from the first conductivity type in a first region along a bottom surface of the substrate; a second diffusion step of forming a second well region having the first conductivity type in a second region along the bottom surface of the substrate within the first region; and forming a first opening exposing the first well region and a second opening exposing the second well region in the bottom surface of the substrate. and an external electrode forming step of forming, on a lower surface of the thermal oxide film, a first external electrode in contact with the first well region at the first opening and a second external electrode spaced from the first external electrode and in contact with the second well region at the second opening, wherein, in the second diffusion step, the second well region is formed along the lower surface of the substrate so as to extend beyond a midline between the first opening and the second opening to the side of the first opening. [Brief description of the drawings]

[0010] [Figure 1] 1 is a top view of a semiconductor device according to a first embodiment of the present invention. [Diagram 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. [Diagram 3] 1 is an enlarged view of an element mounting surface of a semiconductor device according to a first embodiment of the present invention. [Figure 4] 3 is an enlarged cross-sectional view of a bonding region between a composite substrate and frit glass in the semiconductor device according to the first embodiment of the present invention. FIG. [Diagram 5] 1 is an enlarged view of a cross section of a diode structure portion of a semiconductor device according to a first embodiment of the present invention. [Figure 6] 3 is a diagram showing a manufacturing flow of the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 7] 3 is a diagram showing a manufacturing flow of the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 8] 3 is a diagram showing a manufacturing flow of the semiconductor device according to the first embodiment of the present invention. FIG. [Figure 9] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 10] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 11] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 12] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 13] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 14] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 15] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 16]1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 17] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 18] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 19] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 20] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 21] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 22] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Diagram 23] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Figure 24] 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention at one step during manufacture thereof. [Diagram 25] 10 is an enlarged view of a cross section of a diode structure portion of a semiconductor device according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The following is a detailed description of an embodiment of the present invention. In the following description and the accompanying drawings, substantially the same or equivalent parts are given the same reference numerals. In the following description, the term "material 1 / material 2" refers to a laminated structure in which material 2 is laminated on material 1. Furthermore, the term "material 1 material 2" refers to an alloy of materials 1 and 2. EXAMPLES

[0012] Fig. 1 shows a top view of a semiconductor device 100 according to the first embodiment. Fig. 2 shows a cross-sectional view of the semiconductor device 100 taken along line AA in Fig. 1.

[0013] The semiconductor device 100 includes a composite substrate 10 having a cavity as a recess on the upper surface, a semiconductor element 40 mounted on an element mounting surface 13 which is the bottom surface of the cavity of the composite substrate 10, and a lid member 50 formed on the upper surface of the composite substrate 10 so as to cover the cavity of the composite substrate 10. The semiconductor device 100 also includes a plurality of through holes 16 penetrating from the bottom surface of the cavity to the bottom surface of the composite substrate 10. The semiconductor device 100 also includes a first external electrode 21 and a second external electrode 22 which are a pair of mounting electrodes formed on the bottom surface of the composite substrate 10, and a plurality of through electrodes 30 which fill the plurality of through holes 16 of the composite substrate 10 and are electrically connected to the first external electrode 21 and the second external electrode 22. The semiconductor device 100 also includes a diode structure 80 formed in a region along the bottom surface of the composite substrate 10 inside the composite substrate 10. In FIG. 1, the lid member 50 is omitted in order to clarify the structure and positional relationship of each element. In FIG. 1, the semiconductor element 40 is shown by a dashed line in order to clarify the structure and positional relationship of each element.

[0014] As shown in FIG. 2, the composite substrate 10 includes a first substrate 11 made of single crystal silicon (Si) of a first conductivity type having a (100) crystal plane as a main surface, and a silicon oxide (SiO 2 The substrate is an SOI (Silicon On Insulator) having a buried oxide film (BOX: Buried Oxide) 14 made of a (100) crystal plane and a second substrate 12 made of single crystal silicon (Si) whose main surface is a (100) crystal plane and bonded onto the upper surface of the first substrate 11 via the buried oxide film 14.

[0015] The first substrate 11 is, for example, an N-type semiconductor substrate having a first conductivity type in which Si is doped with an N-type impurity such as phosphorus (P) or arsenic (As). 15 cm -3 The first substrate 11 is doped with an N-type impurity so as to obtain the following: The first substrate 11 is, for example, a flat semiconductor substrate having a thickness of about 50 μm.

[0016] The second substrate 12 is, for example, a substrate made of non-doped single crystal Si. The second substrate 12 is, for example, a substrate having a thickness of about 250 μm. The second substrate 12 has an upper surface opening 15 formed therein so as to penetrate from the upper surface to the lower surface. In other words, the composite substrate 10 has an upper surface opening 15 formed therein so as to penetrate from the upper surface of the second substrate 12 to the upper surface of the first substrate 11.

[0017] The upper surface opening 15 is formed such that the opening surface narrows from the upper surface to the lower surface of the second substrate 12 so that the inner surface of the upper surface opening 15 is, for example, a (111) crystal plane of the second substrate 12. Specifically, the inner surface of the upper surface opening 15 is formed at an angle of approximately 54.74° with respect to the upper surface of the first substrate 11.

[0018] Composite substrate 10 forms a cavity consisting of first substrate 11 and top surface opening 15 of second substrate 12. That is, second substrate 12 functions as a side wall of the cavity of composite substrate 10. The top surface of first substrate 11 exposed from top surface opening 15 of second substrate 12 is the bottom surface of the cavity and functions as element mounting surface 13 on which semiconductor element 40 is placed.

[0019] In this embodiment, the case where the second substrate 12 is a substrate made of undoped single crystal Si will be described, but the second substrate 12 may be a semiconductor substrate having the same conductivity type as the first substrate 11.

[0020] As described above, the semiconductor device 100 includes a composite substrate 10 made of single crystal silicon having a first conductivity type, that is, N-type conductivity. The composite substrate 10 is formed by bonding together a first substrate 11 made of plate-shaped single crystal silicon having a first conductivity type and a second substrate 12 provided with an upper surface opening 15 having an inner side surface that forms a cavity as a recess together with the upper surface of the first substrate 11, and a buried oxide film 14 is formed on the surface of the first substrate 11 on the side of the second substrate 12.

[0021] The plurality of through holes 16 are formed in a columnar shape on the lower surface of the composite substrate 10, penetrating from the lower surface of the first substrate 11 to the element mounting surface 13. The plurality of through holes 16 are also formed in a predetermined region within the region of the element mounting surface 13, which is the bottom surface of the cavity when viewed from above. The plurality of through holes 16 are also regularly arranged in the predetermined region.

[0022] Thermal oxide film 17 is formed on element mounting surface 13, the bottom surface, and the inner surfaces of the multiple through holes 16 of first substrate 11 so as to cover first substrate 11. Thermal oxide film 18 is formed on the top surface of second substrate 12 and the inner surfaces of top surface openings 15 so as to cover second substrate 12. In other words, thermal oxide films 17 and 18 are formed on the top and bottom surfaces of composite substrate 10.

[0023] Each of the thermal oxide films 17 and 18 is, for example, a SiO 2 film formed by subjecting the first substrate 11 and the second substrate 12, which are made of single crystal Si, to a thermal oxidation treatment. 2 The thermal oxide films 17 and 18 are oxide films made of, for example, about 0.5 μm in thickness. If the thermal oxide films 17 and 18 are thin, defects such as cracks may occur in the bonding portion between the upper surface of the second substrate 12 and the frit glass layer 60, which is a bonding layer with the lid member 50 described later.

[0024] Similarly, thermal oxide film 17 formed on the inner surface of through hole 16 has a thickness of about 0.5 μm. As a result, thermal oxide films 17 and 18 insulate the surface of composite substrate 10. In other words, composite substrate 10 is formed with a plurality of through holes 16 that penetrate in a columnar shape from the bottom surface of the cavity to the back surface of composite substrate 10 and have their inner surfaces covered with thermal oxide film 17.

[0025] In this embodiment, the semiconductor device 100 is in the form of a wafer level package (WLP) in which a plurality of semiconductor devices 100 are manufactured in a batch in a continuous grid pattern on a wafer-like composite substrate 10. The semiconductor devices 100 are formed in a matrix pattern on the wafer so as to be continuously arranged in the front, back, left and right directions. The wafer is then diced into individual pieces to manufacture a plurality of semiconductor devices 100. Thus, the side surfaces of the first substrate 11 and the second substrate 12, which are the outer surfaces of the semiconductor device 100, are cut surfaces by dicing. Therefore, the thermal oxide films 17 and 18 are not formed on the outer surfaces of the first substrate 11 and the second substrate 12. Note that SiO 2 is formed on the outer surfaces of the first substrate 11 and the second substrate 12 by natural oxidation after the dicing process. 2 In this explanation, the SiO film is formed by natural oxidation. 2 The membrane is not shown.

[0026] Each of the plurality of through electrodes 30 is formed in a columnar shape so as to fill the plurality of through holes 16 from the lower surface of the first substrate 11 and to protrude from the element mounting surface 13 of the first substrate 11. The plurality of through electrodes 30 are formed, for example, by laminating a Cu layer 31, a Ni layer 32, and an AuSn layer 33 as a metal bonding layer in this order from the lower surface of the first substrate 11. In other words, the plurality of through holes 16 are formed with a plurality of columnar through electrodes 30 that fill the plurality of through holes 16 of the composite substrate 10 and protrude from the bottom surface of the cavity.

[0027] The Cu layer 31 is filled into each of the through holes 16 to a thickness of, for example, about 49 μm from the lower surface of the composite substrate 10. That is, the Cu layer 31 is formed so as to fill from the lower surface of the first substrate 11 to a height lower than the element mounting surface 13.

[0028] The Ni layer 32 is filled into each of the through holes 16 to a thickness of, for example, about 1 μm on the upper surface of the Cu layer 31. That is, the Ni layer 32 is formed so that the upper surface of the Ni layer 32 and the upper surface of the element mounting surface 13 are at the same height as each other, as shown in FIG.

[0029] The AuSn layer 33 is formed on the upper surface of the Ni layer 32 to a thickness of about 5 μm so as to protrude above the upper surface of the element mounting surface 13. That is, the AuSn layer 33 is formed so as to have an upper surface shape that follows the upper surface shape of the Ni layer 32, as shown in FIG.

[0030] The AuSn layer 33 melts when heated and functions as a metal bonding layer that is eutectic bonded to an anode electrode 42 or a cathode electrode 41 formed on the bottom surface of the semiconductor element 40, which will be described later. The Ni layer 32 functions as a barrier layer that suppresses the Cu layer 31 and the AuSn layer 33 from diffusing and mixing.

[0031] In order to ensure bonding stability with a semiconductor element 40 described below, it is preferable that the height position of the upper surface of the Ni layer 32 of the multiple through electrodes 30 is the same as or lower than the element mounting surface 13 of the first substrate 11. If the Ni layer 32 is located higher than the element mounting surface 13, contact between the electrode of the semiconductor element 40 and the Ni layer 32 may occur when bonding the semiconductor element 40 described below, which may affect the bonding stability of the semiconductor element 40.

[0032] Further, the plurality of through electrodes 30 are formed in each of the plurality of through holes 16 regularly arranged on the element mounting surface 13, and each of the plurality of through electrodes 30 is joined to the cathode electrode 41 and the anode electrode 42 of the semiconductor element 40. This makes it possible to prevent voids from being generated between the cathode electrode 41 and the anode electrode 42 of the semiconductor element 40 and each of the plurality of through electrodes 30. Specifically, when the cathode electrode 41 and the anode electrode 42 of the semiconductor element 40 are joined face-to-face to an internal electrode having a substantially identical upper surface shape, air bubbles may be trapped in the molten AuSn, causing voids to be generated in unintended random positions.

[0033] Each of the first external electrode 21 and the second external electrode 22 is an electrode made of a metal layer laminated in the order of titanium (Ti) / copper (Cu) / nickel (Ni) / gold (Au) from the thermal oxide film 17 side of the composite substrate 10. The first external electrode 21 and the second external electrode 22 are formed so as to cover each of the plurality of through electrodes 30 formed on the lower surface of the composite substrate 10 while being spaced apart from each other. The first external electrode 21 and the second external electrode 22 are in electrical contact with the plurality of through electrodes 30 on the lower surface of the composite substrate 10. That is, the lower surface side of the semiconductor device 100 becomes a mounting surface for a mounting substrate (not shown), and the first external electrode 21 and the second external electrode 22 function as mounting electrodes for the mounting substrate.

[0034] Moreover, each of the plurality of through electrodes 30 is formed so as to fill each of the plurality of through holes 16. Moreover, each of the first external electrode 21 and the second external electrode 22 is formed so as to cover each of the plurality of through electrodes 30 on the lower surface of the composite substrate 10. In other words, the plurality of through electrodes 30 electrically connect each of a pair of electrodes of the semiconductor element 40 to each of the first external electrode 21 and the second external electrode 22.

[0035] As a result, the inside of the cavity of composite substrate 10 is airtightly sealed against the lower surface side of composite substrate 10 via multiple through holes 16 .

[0036] The semiconductor element 40 is placed on the upper surface of the element mounting surface 13. In this embodiment, the semiconductor element 40 is, for example, a light-emitting element that emits deep ultraviolet light using an aluminum gallium nitride (AlGaN)-based semiconductor layer as a light-emitting layer. Specifically, the semiconductor element 40 is a semiconductor element in which an N-type AlGaN semiconductor layer, an AlGaN active layer, and a P-type AlGaN semiconductor layer are laminated on an aluminum nitride (AlN) substrate, and deep ultraviolet light is emitted from the AlGaN active layer. In this embodiment, an AlN substrate, an N-type AlGaN semiconductor layer, an AlGaN active layer, and a P-type AlGaN semiconductor layer are formed from the upper surface side of the semiconductor element 40. In other words, the semiconductor device 100 includes a semiconductor element 40 that is disposed on the composite substrate 10 and has a semiconductor layer. The semiconductor element 40 is also a light-emitting element that emits ultraviolet light from the semiconductor layer.

[0037] In addition, the semiconductor element 40 has a cathode electrode 41 made of a metal electrically connected to the N-type AlGaN semiconductor layer and an anode electrode 42 made of a metal electrically connected to the P-type AlGaN semiconductor layer formed on the underside of the semiconductor element 40.

[0038] The exposed surfaces of the cathode electrode 41 and the anode electrode 42 are covered with a metal layer made of Au. That is, the semiconductor element 40 is a flip-chip connected semiconductor element having a pair of electrodes, the cathode electrode 41 and the anode electrode 42, formed on the underside. That is, the semiconductor element 40 has the cathode electrode 41 and the anode electrode 42 as a pair of electrodes on the underside.

[0039] Therefore, in the semiconductor element 40, deep ultraviolet light emitted from the AlGaN active layer passes through the AlN substrate and is emitted from the upper surface of the semiconductor element 40. That is, the upper surface of the AlN substrate, which is the upper surface of the semiconductor element 40, functions as a light extraction surface for the semiconductor element 40, and the lower surface on which the cathode electrode 41 and the anode electrode 42 are formed functions as a mounting surface for mounting on the composite substrate 10.

[0040] The semiconductor element 40 is bonded such that the cathode electrode 41 and the anode electrode 42 are mounted on the upper surface of each of the plurality of through electrodes 30. Specifically, the cathode electrode 41 and the anode electrode 42 of the semiconductor element 40 are bonded to the AuSn layer 33 of each of the through electrodes 30. As shown in FIG. 2, the semiconductor element 40 has the cathode electrode 41 electrically connected to the first external electrode 21 via the through electrode 30, and the anode electrode 42 electrically connected to the second external electrode 22 via the through electrode 30. That is, in the semiconductor device 100, the first external electrode 21 functions as a cathode mounting electrode (negative electrode), and the second external electrode 22 functions as an anode mounting electrode (positive electrode).

[0041] In this embodiment, the semiconductor element 40 is a light emitting element that emits ultraviolet light from an AlGaN active layer. The semiconductor element 40 is driven by applying a voltage of 6 V or more in the direction from the anode electrode 42 to the cathode electrode 41 (forward potential).

[0042] The lid member 50 is disposed on the upper surface of the composite substrate 10 so as to cover the cavity of the composite substrate 10. The lid member 50 is made of, for example, SiO 2 The cover member 50 is a deep ultraviolet ray transmitting glass that transmits deep ultraviolet rays emitted from the semiconductor element 40. The thermal expansion coefficient of the cover member 50 is, for example, 3×10 -6 / ℃ or more 5×10 -6 / ° C. or less, and the thermal expansion coefficients of the first substrate 11 and the second substrate 12, which are single crystal Si (3.9×10 -6 / °C).

[0043] In addition, the lid member 50 is bonded to the upper surface of the composite substrate 10 via the glass frit layer 60. In other words, the semiconductor device 100 further includes the lid member 50 made of glass bonded to the upper surface of the composite substrate 10 via the glass frit layer 60.

[0044] The frit glass layer 60 is a glass-like bonding layer made of, for example, a paste containing powdered frit glass. The frit glass layer 60 is formed by applying the paste, which is a raw material, to the surface of the lid member 50 facing the upper surface of the second substrate 12 in advance so as to surround the periphery of the cavity of the composite substrate 10. The lid member 50 to which the paste has been applied is pre-fired at about 500° C. before bonding to the composite substrate 10.

[0045] The frit glass layer 60 is, for example, SiO 2 The glass is made mainly from fluorine. The frit glass layer 60 is heated and melted to bond the lid member 50 and the second substrate 12, surrounding the periphery of the cavity of the composite substrate 10. The frit glass layer 60 is also melted by heating locally for a short period of time with a laser, which will be described later, to bond the lid member 50 and the second substrate 12.

[0046] By bonding the lid member 50 to the upper surface of the second substrate 12 via the frit glass layer 60, the inside of the cavity of the composite substrate 10 is airtight with respect to the side of the upper surface of the composite substrate 10 via the lid member 50 and the frit glass layer 60. That is, the semiconductor device 100 has a housing space HS in which the inside of the cavity formed by the first substrate 11 and the second substrate 12 is hermetically sealed. In addition, the housing space HS is filled with, for example, nitrogen (N 2 The chamber is filled with a sealing gas such as .

[0047] Similarly to the composite substrate 10, the lid member 50 and the frit glass layer 60 are formed in a continuous grid pattern on the surface of the wafer-shaped lid member 50 facing the composite substrate 10. That is, the lid member 50 is bonded via the frit glass layer 60 so as to collectively cover the multiple cavities formed in a grid pattern on the composite substrate 10 during the manufacture of the semiconductor device 100. The lid member 50 is cut simultaneously with the composite substrate 10 during a dicing process during the manufacture. Thus, by using a wafer-shaped composite substrate 10 for the composite substrate 10, the semiconductor device 100 can be manufactured as a wafer level package (WLP) in which the semiconductor device 100 is formed in a grid pattern on a wafer.

[0048] Conventionally, individual AlN substrates were used and it was necessary to hermetically seal each of the substrates, which resulted in problems with tact time and cost during manufacturing. In this embodiment, the semiconductor device 100 can be manufactured by forming cavities in a lattice pattern on a wafer-like composite substrate 10, hermetically sealing the substrate 10 all at once with a lid member 50 having a frit glass layer 60 formed thereon, and then dicing the substrate into individual pieces. This allows the semiconductor device 100 to improve tact time and cost during manufacturing.

[0049] In addition, conventionally, the AlN substrate and the lid member are hermetically sealed by eutectic bonding using AuSn. Therefore, in the semiconductor device, eutectic bonding using AuSn is performed twice: when the semiconductor element is bonded to the element mounting portion and when the lid member is bonded to the AlN substrate. In this case, during the second AuSn eutectic bonding when the lid member is bonded for hermetic sealing, the AuSn that has bonded the semiconductor element may remelt, resulting in manufacturing defects such as misalignment of the semiconductor element.

[0050] In this embodiment, the semiconductor device 100 is manufactured such that the only location where eutectic bonding is performed using AuSn is the bonding of the semiconductor element 40, and the lid member 50 is locally heated for a short period of time by the laser of the frit glass layer 60. This makes it possible to prevent remelting of the eutectic bonding layer between the semiconductor element 40 and each of the plurality of through electrodes 30 using AuSn when the lid member 50 and the composite substrate 10 are bonded. Therefore, the semiconductor device 100 can prevent manufacturing defects such as deviation in the placement position of the semiconductor element due to remelting of AuSn during manufacturing.

[0051] The diode structure 80 is formed in a region along the lower surface of the first substrate 11 so as to be spaced apart from the multiple through holes 16. The diode structure 80 has, for example, a P-type well region 81 as a first well region of a second conductivity type obtained by diffusing a P-type impurity such as boron (B) from the lower surface side of the first substrate 11 in a first region across the first external electrode 21 and the second external electrode 22 on the lower surface of the first substrate 11. The diode structure 80 also has, for example, an N-type well region 82 as a second well region of a first conductivity type obtained by diffusing an N-type impurity such as phosphorus (P) from the lower surface side of the first substrate 11 in a second region within the first region on the lower surface of the first substrate 11. + It has a mold well region 82 .

[0052] Further, the thermal oxide film 17 formed on the lower surface of the P-type well region 81 has a first opening OP1 that is opened so as to penetrate to the lower surface of the P-type well region 81. Further, the first opening OP1 is formed so as to be filled with a first external electrode 21. That is, the P-type well region 81 and the first external electrode 21 are in electrical contact with each other at the first opening OP1.

[0053] Also, N + The thermal oxide film 17 formed on the lower surface of the N well region 82 is + A second opening OP2 is formed so as to penetrate to the lower surface of the type well region 82. The second opening OP2 is filled with the second external electrode 22. +The P-type well region 82 is in electrical contact with the second external electrode 22. In other words, the semiconductor device 100 has a first opening OP1 and a second opening OP2 spaced apart from each other formed in the thermal oxide film 17 formed on the lower surface of the composite substrate 10, and has a P-type well region 81 as a first well region having a second conductivity type different from the first conductivity type formed in a first region along the lower surface of the composite substrate 10 and exposed at the first opening OP1, and an N-type well region as a second well region having the first conductivity type formed in a second region along the lower surface in the first region and exposed at the second opening OP2. + 1 includes a diode structure 80 consisting of a well region 82 .

[0054] Therefore, the diode structure 80 is formed by a P-type well region 81 and an N-type well region 82 formed between the first external electrode 21 and the second external electrode 22 inside the first substrate 11, which is an N-type semiconductor substrate. + The pn junction diode is made of a type well region 82.

[0055] The first external electrode 21 is connected to the cathode electrode 41 of the semiconductor element 40 and the P-type well region 81 which is the anode of the diode structure 80. The second external electrode 22 is connected to the anode electrode 42 of the semiconductor element 40 and the N-type well region 81 which is the cathode of the diode structure 80. + The diode structure 80 functions as a Zener diode connected in parallel with the semiconductor element 40 and with reverse polarity between the first external electrode 21 and the second external electrode 22. In other words, the semiconductor device 100 includes a first external electrode 21 formed on the lower surface of the thermal oxide film 17 and in contact with the P-type well region 81 at a first opening OP1, and an N-type well region 82 formed on the lower surface of the thermal oxide film 17, separated from the first external electrode 21 and in contact with the N-type well region 82 at a second opening OP2. + and a second external electrode 22 in contact with the mold well region 82 .

[0056] In addition, the P-type well region 81 has a carrier density of about 1E 17 cm -3The P-type impurity boron is diffused so that + The well region 82 has a carrier density of about 1E 19 cm -3 In other words, the diode structure 80 has a higher N-type impurity concentration than the P-type well region 81. + The Zener diode has a one-sided abrupt junction structure in which the type well region 82 has a higher carrier density.

[0057] The diode structure 80 operates to protect the semiconductor element 40 when an overvoltage such as static electricity is applied from the outside to the semiconductor element 40. Specifically, when an overvoltage caused by static electricity is applied in the direction from the second external electrode 22 to the first external electrode 21 (forward potential), the diode structure 80 is connected to the cathode N + A current flows from the P-type well region 82 to the P-type well region 81, which is the anode. This enables the diode structure 80 to keep the potential of the semiconductor element 40 constant, thereby protecting the semiconductor element 40.

[0058] As described above, the semiconductor element 40 is a semiconductor element that is driven by applying a voltage value of 6 V or more to the anode electrode 42 and the cathode electrode 41. That is, the diode structure 80 having a one-sided abrupt junction structure is a Zener diode in which avalanche breakdown predominates when an overvoltage is applied. That is, the diode structure 80 is a Zener diode or an avalanche diode.

[0059] Thus, in this embodiment, the Zener diode is formed as the diode structure 80 inside the composite substrate 10 of the semiconductor device 100. This makes it possible to provide the semiconductor element 40 and the diode structure 80 as the Zener diode without juxtaposing the semiconductor element 40 and the Zener diode of the discrete semiconductor in the cavity, which is the recess of the composite substrate 10. Therefore, the area of ​​the bottom surface of the cavity of the composite substrate 10 can be reduced, and the external shape of the semiconductor device 100 can also be reduced. According to the verification by the inventors, the semiconductor device 100 of this embodiment can reduce the mounting area (bottom surface area) of the semiconductor device 100 by about 50% compared to a semiconductor device having a structure in which the Zener diode of the discrete semiconductor and the semiconductor element 40 are juxtaposed in the cavity.

[0060] In this embodiment, the semiconductor element 40 is a light-emitting element that emits ultraviolet light from the semiconductor layer. By forming the Zener diode as the diode structure 80 inside the composite substrate 10 of the semiconductor device 100, it is possible to place the semiconductor element 40 in the center of the cavity. As a result, the light emitted from the semiconductor element 40 is uniformly irradiated onto the inner surface of the upper surface opening 15, and it is possible to suppress uneven brightness and deviation in the direction of light emitted from the semiconductor device 100. In addition, compared to the case where the semiconductor element 40 and the Zener diode of the discrete semiconductor are juxtaposed in the cavity, the light emitted from the semiconductor element 40 is not blocked or absorbed by the Zener diode of the discrete semiconductor, so that it is possible to improve the light extraction efficiency of the semiconductor device 100. According to the verification by the inventors, the semiconductor device 100 of this embodiment can improve the light output of the semiconductor device 100 by about 14% compared to a semiconductor device having a structure in which the Zener diode of the discrete semiconductor and the semiconductor element 40 are juxtaposed in the cavity.

[0061] In this embodiment, the semiconductor device 100 is in the form of a wafer level package (WLP) in which a plurality of semiconductor devices 100 are manufactured in a continuous grid pattern on a wafer-shaped composite substrate 10. That is, the diode structure portion 80 is formed in a batch on the lower surface of the manufacturing area of ​​each semiconductor device 100 of the wafer-shaped composite substrate 10. As a result, the semiconductor device 100 of this embodiment can omit a dicing process, a die bonding process, etc. for the Zener diode of the discrete semiconductor, compared to a semiconductor device having a structure in which the Zener diode of the discrete semiconductor and the semiconductor element 40 are juxtaposed in a cavity. Therefore, the semiconductor device 100 of this embodiment can improve productivity and reduce manufacturing costs.

[0062] Fig. 3 is an enlarged view of the upper surface of the element mounting surface 13, showing the structure of the plurality of through electrodes 30 of the semiconductor device 100 according to the first embodiment. In Fig. 3, the semiconductor element 40, the cathode electrode 41, the anode electrode 42, and the diode structure portion 80 are shown by dashed lines in order to clarify the structure and positional relationship of the plurality of through electrodes 30.

[0063] 3, each of the plurality of through electrodes 30 is formed in a region where each of the cathode electrode 41 and the anode electrode 42 of the semiconductor element 40 is placed. Each of the plurality of through electrodes 30 is formed so as to be separated from a region where the diode structure portion 80 is formed. That is, the plurality of through electrodes 30 and the diode structure portion 80 are insulated from each other by the thermal oxide film 17 formed on the inner side surface of the plurality of through holes 16.

[0064] Each of the plurality of through electrodes 30 is formed in a cylindrical shape with a diameter of, for example, 30 μm. In the semiconductor element 40, the plurality of through electrodes 30 are joined to one electrode surface of each of the cathode electrode 41 and the anode electrode 42.

[0065] If an internal electrode having the same shape as the cathode electrode 41 and anode electrode 42 of the semiconductor element 40 is formed on the element mounting surface 13, the internal electrode and the cathode electrode 41 or the anode electrode 42 are AuSn bonded to each other on one surface. In this case, unpredictable or uncontrollable voids may occur in the AuSn bonding layer at the bonding surface between the internal electrode and the cathode electrode 41 or the anode electrode 42. These voids may affect reliability, such as cracking the bonding layer, when heat is generated during operation of the semiconductor element after manufacture.

[0066] In this embodiment, the plurality of through electrodes 30 are formed to be spaced apart from each other. The semiconductor element 40 is bonded to the plurality of through electrodes 30 so as to rest on the upper surfaces of the plurality of through electrodes 30. This makes it possible to suppress the occurrence of unpredictable or uncontrollable voids at the bonding interface between the semiconductor element 40 and the plurality of through electrodes 30, and to reduce the influence of voids on reliability at the bonding portions between the semiconductor element 40 and the plurality of through electrodes 30 after the semiconductor device 100 is manufactured.

[0067] 3, the plurality of through electrodes 30 are arranged on the lattice points of an equilateral triangular lattice on the bottom surface of the cavity. Each of the plurality of through electrodes 30 is formed, for example, as a cylinder having a diameter of 30 μm, and is arranged such that the distance between the centers of adjacent through electrodes 30 is 60 μm. By arranging the plurality of through electrodes 30 in the above-mentioned arrangement, each of the plurality of through electrodes 30 is arranged such that the distance between one through electrode 30 and the other through electrodes 30 arranged around it is uniform.

[0068] If the plurality of through electrodes 30 are formed in a matrix on the lattice points of a square lattice, the spacing between one through electrode 30 and the other through electrodes 30 arranged above, below, left and right in top view will be equal. However, the spacing between one through electrode 30 and the other through electrodes 30 arranged diagonally from it will be different. This causes a bias in the stress acting within the upper surface of the element mounting surface 13 when the semiconductor element 40 is bonded or when the semiconductor element 40 is driven and generates heat, and this may cause minute cracks in the first substrate 11, breaking the airtightness of the cavity.

[0069] In this embodiment, as described above, each of the plurality of through electrodes 30 is arranged on the lattice points of an equilateral triangular lattice. This makes it possible to suppress cracks in the first substrate 11 since stress applied to the upper surface of the element mounting surface 13 becomes uniform during bonding of the semiconductor element 40 or heat generation during operation of the semiconductor element 40.

[0070] Furthermore, by arranging each of the plurality of through electrodes 30 on the lattice points of a regular triangular lattice as in this embodiment, it is possible to form a greater number of through electrodes 30 than by arranging the plurality of through electrodes 30 in a matrix shape. This makes it possible to dissipate more heat generated during operation of the semiconductor element 40 to the mounting board. According to verification by the inventors, by arranging each of the plurality of through electrodes 30 on the lattice points of a regular triangular lattice as in this embodiment, it is possible to arrange a plurality of through electrodes 30 in a quantity 1.2 times greater than by arranging the plurality of through electrodes 30 in a matrix shape.

[0071] FIG. 4 is an enlarged view of a bonding area CA between the frit glass layer 60 and the second substrate 12 shown in FIG.

[0072] As described above, the composite substrate 10 is bonded to the cover member 50 via the frit glass layer 60. In addition, the thermal oxide film 18 is formed on the upper surface of the second substrate 12. At this time, between the frit glass layer 60 and the second substrate 12, the frit glass layer 60, an interdiffusion layer 70 as a reaction layer in which the thermal oxide film 18 and the frit glass layer 60 are mutually diffused, and a remaining thermal oxide film 18R are formed in this order from above. In other words, at the bonding portion between the composite substrate 10 and the frit glass layer 60, the remaining thermal oxide film 18R of the thermal oxide film 18 and the interdiffusion layer 70 as a reaction layer between the thermal oxide film 18 and the frit glass layer 60 are formed in this order from the surface of the composite substrate 10.

[0073] The interdiffusion layer 70 is formed by heating and melting the frit glass layer 60 to form the SiO 2 of the thermal oxide film 18 formed on the upper surface of the second substrate 12. 2 and a frit glass layer 60 of SiO 2 The thermal oxide film 18 is formed by interdiffusion of the remaining thermal oxide film 18R and the interdiffusion layer 70. That is, the joint of the frit glass layer 60 has a structure in which the remaining thermal oxide film 18R, the interdiffusion layer 70, and the frit glass layer 60 are laminated in this order from the upper surface of the second substrate 12. The thermal oxide film 18 is formed in the thermal oxidation process so that the film thickness (T1) of the thermal oxide film 18 is about 0.5 μm.

[0074] The thickness (T2) of the remaining thermal oxide film 18R is preferably 0.5 times or more the thickness (T1) of the thermal oxide film 18. That is, the thickness (T2) of the remaining thermal oxide film 18R is preferably 0.25 μm or more. By setting the thickness of the thermal oxide film 18 to about 0.5 μm, the remaining thermal oxide film 18R can be reliably left after the heat treatment.

[0075] If the thickness (T2) of the remaining thermal oxide film 18R is small or if the remaining thermal oxide film 18R is not formed, cracks may occur near the lower end of the interdiffusion layer 70, and the airtight sealing of the storage space HS may be broken.

[0076] The thermal oxide film 18 is formed by diffusing oxygen from the surface of the second substrate 12, which is single crystal Si, through a thermal oxidation process to form SiO 2 Therefore, the thermal oxide film 18 is formed as a uniform and complete SiO 2 The SiO 2 As the amount of oxygen vacancies in the second substrate 12 increases, the crystallinity of the second substrate 12 approaches that of single crystal Si. 2 In other words, the thermal oxide film 18 near the surface of the second substrate 12 partially retains the crystallinity of Si and is a mixture of Si and SiO 2 and are mixed together.

[0077] The interdiffusion layer 70 between the thermal oxide film 18 and the frit glass layer 60 is made of amorphous SiO 2 That is, when the thickness (T2) of the remaining thermal oxide film 18R is thin, the upper end of the remaining thermal oxide film 18R may partially contain Si and its crystallinity.

[0078] Suppose SiO2 has an amorphous structure. 2 The layer is made of Si and some of its crystallinity is contained in SiO 2 When the layers are bonded, the arrangement of atoms changes drastically at the bonded interface. In this case, it is expected that the bond strength at the bonded interface will be low. As a result, if stress is generated at the bonded interface due to heat generated during operation of the semiconductor element 40, cracks may occur at the bonded interface, causing the airtight seal of the storage space HS to be broken. In contrast, when the SiO 2 When the layers are bonded together, neither of them has crystallinity, so that the atomic arrangement does not change suddenly, and therefore stress is unlikely to occur when heat is generated, etc. In other words, the remaining thermal oxide film 18R functions as a buffer layer that relieves the lattice mismatch between the second substrate 12 and the interdiffusion layer 70.

[0079] Therefore, the remaining thermal oxide film 18R is a SiO 2By remaining with a thickness of 0.25 μm or more, which is estimated to be a thickness greater than or equal to the thickness required for the desired thickness, composite substrate 10 and lid member 50 can be bonded with high bonding strength via glass frit layer 60.

[0080] That is, the remaining thermal oxide film 18R is a film formed by interposing the second substrate 12, which is single crystal silicon, and the SiO 2 The remaining thermal oxide film 18R functions as a buffer layer that relieves internal stress caused by the difference in crystal structure between the frit glass layer 60 and the remaining thermal oxide film 18R. 2 Any film thickness greater than or equal to this may be used.

[0081] As described above, at the joint between the frit glass layer 60 and the second substrate 12, the remaining thermal oxide film 18R, the mutual diffusion layer 70, and the frit glass layer 60 are formed in this order from the upper surface of the second substrate 12, thereby making it possible to maintain high airtightness of the accommodation space HS. According to verification by the inventors, in a helium (He) leak test specified in the Japanese Industrial Standard JIS-Z2331, the accommodation space HS of the semiconductor device 100 was able to obtain airtightness equal to or greater than that of a conventional AlN substrate and a product in which the AlN substrate and a lid member are joined with AuSn.

[0082] FIG. 5 is an enlarged view of the ZD portion showing the diode structure 80 shown in FIG.

[0083] As described above, the diode structure 80 is formed in a region along the inner lower surface of the first substrate 11. A thermal oxide film 17 is formed on the lower surface of the first substrate 11 by wet thermal oxidation processing. A first external electrode 21 and a second external electrode 22, which are a pair of external electrodes formed to be spaced apart from each other, are formed on the lower surface of the thermal oxide film 17.

[0084] The diode structure 80 includes a P-type well region 81 formed in a region across the first external electrode 21 and the second external electrode 22 on the lower surface of the first substrate 11, and an N +and a mold well region 82.

[0085] The P-type well region 81 is a high-concentration well region in which boron, an impurity, is segregated in the region along the lower surface of the first substrate 11. + The segregation layer 81H is included. + The segregation layer 81H is formed, for example, with a thickness of about several nm to 10 and several nm from the lower surface of the first substrate 11. + The segregation layer 81H has a carrier density of, for example, about 1E 19 cm -3 In other words, the P-type well region 81 has a P-type well region having a higher carrier density in one region facing the first opening OP1 than in other regions. + It has a segregation layer 81H.

[0086] In addition, a first opening OP1 is formed in the thermal oxide film 17 formed on the lower surface of the first substrate 11 so as to penetrate a part of the region where the P-type well region 81 and the first external electrode 21 overlap from the lower surface of the thermal oxide film 17 to the lower surface of the P-type well region 81. In addition, the thermal oxide film 17 contains N + A part of the region where the type well region 82 and the second external electrode 22 overlap is exposed from the lower surface of the thermal oxide film 17 to the N + A second opening OP2 is formed by removing the P-type well region 81 so as to penetrate to the lower surface of the P-type well region 82. + The lower surface of the segregation layer 81H is exposed at the first opening OP1. + The bottom surface of the mold well region 82 is exposed at the second opening OP2.

[0087] The first external electrode 21 is formed in a region including the first opening OP1 on the lower surface of the thermal oxide film 17. The second external electrode 22 is formed in a region including the second opening OP2 on the lower surface of the thermal oxide film 17. The first external electrode 21 and the second external electrode 22 are formed by sequentially laminating, from the lower surface side of the thermal oxide film 17, Ti seed layers 21A and 22A made of titanium (Ti), Cu seed layers 21B and 22B made of copper (Cu), Ni plating layers 21C and 22C made of nickel (Ni), and AuSn plating layers 21D and 22D made of a gold-tin (AuSn) alloy. In the first opening OP1 and the second opening OP2, the Ti seed layers 21A and 22A are formed of P + The exposed surface of the lower surface of the segregation layer 81H, N + It is formed so as to cover the exposed surface of the lower surface of the mold well region 82 .

[0088] That is, the first external electrode 21 is formed by disposing the Ti seed layer 21A and the P + The second external electrode 22 is electrically connected to the Ti seed layer 22A through the second opening OP2. + A first contact portion C1 is formed in electrical contact with the mold well region 82. In other words, in each of the first external electrode 21 and the second external electrode 22, Ti seed layers 21A and 22A, Cu seed layers 21B and 22B, and Ni plating layers 21C and 22C are laminated in this order from the lower surface of the composite substrate 10 at the first opening OP1 and the second opening OP2.

[0089] Typically, P-type semiconductors, especially those with carrier densities of around 1E 17 cm -3 When bonding the P-type semiconductor and a metal layer such as Ti so as to form an ohmic contact between them, the P-type semiconductor and the metal layer are subjected to a heat treatment, a laser irradiation treatment, or the like so as to alloy them at the bonding interface to form the ohmic contact.

[0090] In this embodiment, the P-type well region 81 has a carrier density of about 1E at the contact region between the P-type well region 81 and the Ti seed layer 21A.19 cm -3 P + The segregation layer 81H is formed to a thickness of about several nm to several tens of nm. + The width of the depletion layer between the segregation layer 81H and the Ti seed layer 21A can be reduced, and P + It is possible to realize an ohmic contact by causing a tunnel effect in the depletion layer between the segregation layer 81H and the Ti seed layer 21A.

[0091] Specifically, boron contained as an impurity in the P-type well region 81 has a segregation coefficient of 0.8 inside single crystal silicon, which is one of the larger impurities used in semiconductors. Therefore, the boron contained in the P-type well region 81 segregates near the interface of the thermal oxide film 17 during the thermal oxide film formation process by wet thermal oxidation (approximately 950° C.) which is performed multiple times in the manufacturing method described below, and becomes P + A segregation layer 81H is formed. As a result, in the first contact portion C1, P + The segregation layer 81H and the Ti seed layer 21A are joined together, making it possible to achieve ohmic contact.

[0092] According to the inventors, when a reverse voltage of 7 V (voltage in the direction from the second external electrode 22 to the first external electrode 21) is applied to the diode structure 80 of this embodiment, it has been confirmed that the leakage current flowing through the diode structure 80 is a small leakage current of 94 nA. + It was shown that a good PN junction with the type well region 82 was obtained, and good ohmic contact was obtained at the first contact portion C1 and the second contact portion C2.

[0093] In addition, N + The carrier density of the well region 82 is about 1E 19 cm -3 Therefore, it is possible to achieve ohmic contact with the Ti seed layer 21A.

[0094] During operation of the diode structure 80, carriers move between the P-type well region 81 electrically contacting the first external electrode 21 and the N-type well region 82 electrically contacting the second external electrode 22. + The P-type well region 81 is electrically connected to the first substrate 11, which is an N-type semiconductor substrate, via a contact hole 82. A depletion layer is formed by an internal electric field at the junction interface between the P-type well region 81 and the first substrate 11, which is an N-type semiconductor substrate. That is, the first substrate 11 is substantially insulated from the P-type well region 81 and is in an electrically floating state. This makes it possible for the semiconductor device 100 to suppress leakage current from the side surface of the first substrate 11 to other adjacent semiconductor devices on the mounting substrate when an overvoltage is applied on the mounting substrate.

[0095] The inter-electrode distance D1 between the pair of mounting electrodes, the first external electrode 21 and the second external electrode 22, is, for example, about 0.5 mm. The first contact portion C1 and the second contact portion C2 are formed so as to be located inward from the opposing sides of the first external electrode 21 and the second external electrode 22, respectively. The distance D2 between the first contact portion C1 and the second contact portion C2 is, for example, 0.7 mm.

[0096] Between the first external electrode 21 and the second external electrode 22, the diode structure portion 80 is covered with a thermal oxide film 17. That is, the diode structure portion 80 is insulated by the thermal oxide film 17 in an area other than the first contact portion C1 and the second contact portion C2. Therefore, when mounting the semiconductor device 100 on a mounting board, it is possible to suppress leakage current to the diode structure portion 80 even when the first external electrode 21 and the second external electrode 22 are joined using a molten metal such as AuSn or solder.

[0097] As described above, the semiconductor element 40 is a light-emitting element that is driven by applying a voltage of 6 V or more. Therefore, it is preferable that the diode structure 80 has a breakdown voltage in the reverse direction to the voltage application direction of the drive voltage of the semiconductor element 40 that is at least twice as large.

[0098] In this embodiment, the diode structure 80 includes a P-type well region 81 and a N + The diode structure 80 is a Zener diode having a one-sided abrupt junction structure consisting of a type well region 82. The diode structure 80 has a one-sided abrupt junction structure, which makes it possible for the avalanche breakdown to act predominantly as a Zener diode, thereby ensuring a high breakdown voltage.

[0099] In this embodiment, N + The N-type well region 82 is formed to extend from the second contact portion C2 to the first contact portion C1 side from the middle between the first contact portion C1 and the second contact portion C2. In other words, the N-type well region 82 extends from the second contact portion C2 to the first contact portion C1 side from the middle between the first contact portion C1 and the second contact portion C2. + The width D3 of the N-type well region 82 is set to be 0.5 times or more the distance D2 between the first contact portion C1 and the second contact portion C2. + The mold well region 82 extends along the lower surface of the composite substrate 10 beyond the midline between the first opening OP1 and the second opening OP2 to the side of the first opening OP1.

[0100] This makes it possible to increase the voltage (withstand voltage) at which avalanche breakdown occurs in the diode structure 80. The inventors have verified that when a reverse voltage (voltage in the direction from the second external electrode 22 to the first external electrode 21) is applied to the diode structure 80 of this embodiment, a breakdown voltage of −33.5 V can be obtained.

[0101] Next, a manufacturing procedure for the semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIGS.

[0102] 6 to 8 are diagrams showing a manufacturing flow of the semiconductor device 100 according to the first embodiment of the present invention. Also, FIGS. 9 to 24 are cross-sectional views of the semiconductor device 100 in each step of the manufacturing procedure shown in FIGS. 6 to 8. In FIGS. 9 to 24, the cross section along the line AA shown in FIG. 1 will be used for the explanation, as in FIG. 2. In this embodiment, as described above, the semiconductor device 100 is a WLP in which the semiconductor device 100 is formed in a lattice pattern on the wafer-like composite substrate 10. Therefore, the composite substrate 10 has a plurality of element mounting regions R1 defined by predetermined lattice-like division lines CL on the wafer-like composite substrate 10. That is, the processing of each step described below is performed continuously in a lattice pattern on the wafer-like composite substrate 10. Also, in the explanation of the processing of each step below, the explanation will be given for the case where the processing is basically performed on one element mounting region R1.

[0103] First, as shown in FIG. 9, a SiO 2 A step of preparing a substrate is performed to prepare a composite substrate 10 in which a second substrate 12 made of single crystal silicon is bonded to the first substrate 11 via a buried oxide film 14 made of silicon (SiO 2 ). Thermal oxide films 17A and 18A are formed on the upper surface of the first substrate 11 and the lower surface of the second substrate 12. In other words, the manufacturing method of the semiconductor device 100 includes a step of preparing a composite substrate 10 including a first substrate 11 made of single crystal silicon having a first conductivity type.

[0104] Next, as shown in FIG. 10, a first diffusion step is performed in which boron is diffused into a first region along the lower surface of the composite substrate 10 to form a P-type well region 81 (step S102: first diffusion step). In this step, first, the first region of the thermal oxide film 17A formed on the lower surface of the composite substrate 10 is etched from the lower surface side using buffered hydrofluoric acid (BHF) to expose the lower surface of the first substrate 11 in the first region. Next, for example, boron silicate glass (BSG) is formed on the lower surface of the composite substrate 10 in a nitrogen atmosphere at 900° C. for 1 hour to attach boron to the first region of the first substrate 11. Thereafter, the BSG and the thermal oxide films 17A and 18A are removed, and a drive-in heat treatment is performed in a nitrogen atmosphere at 1100° C. for 2.5 hours to diffuse boron into the inside of the first substrate 11. In other words, the manufacturing method of semiconductor device 100 includes a first diffusion step of forming P-type well region 81 having a second conductivity type different from the first conductivity type in a first region along the lower surface of composite substrate 10. Also, in the first diffusion step, boron silicate glass is formed on the lower surface of composite substrate 10 in the first region to diffuse boron into first substrate 11 through solid phase diffusion.

[0105] In this embodiment, a case where solid-phase diffusion is used to form BSG in the first region of the first substrate 11 will be described, but the method of diffusing boron into the first substrate 11 is not limited to this. For example, other diffusion methods such as an ion implantation method in which boron ions are implanted from below the first region may be used.

[0106] Next, as shown in FIG. 11, thermal oxide films 17B and 18B are formed on the lower surface of the first substrate 11 and the upper surface of the second substrate 12 (step S103: first thermal oxidation step). In this step, the wafer in which the P-type well region 81 is formed is oxidized with oxygen (O 2 ) and water (H 2 C. for 2.5 hours in a SiO.sub.2O) atmosphere to form thermal oxide films 17B and 18B.

[0107] Next, as shown in FIG. 12, phosphorus is diffused into a second region along the underside of the composite substrate 10 in the first region, and N +A second diffusion step is performed to form the P-type well region 82 (step S104: second diffusion step). In this step, first, the second region of the thermal oxide film 17B formed on the lower surface of the composite substrate 10 is etched from the lower surface side using BHF, and the lower surface of the P-type well region 81 is exposed in the second region. Next, for example, phosphorus silicate glass (PSG) is formed on the lower surface of the composite substrate 10 at 900° C. for 1 hour in a nitrogen atmosphere to attach phosphorus to the second region in the P-type well region 81. Thereafter, the PSG and the thermal oxide films 17B and 18B are removed, and a drive-in heat treatment is performed at 1100° C. for 2.5 hours in a nitrogen atmosphere to diffuse phosphorus into the P-type well region 81. In other words, the manufacturing method of the semiconductor device 100 is a method of forming an N-type fluorine-containing oxide having a first conductivity type in the second region along the lower surface of the composite substrate 10 in the P-type well region 81. + The method includes a second diffusion step of forming a mold well region 82. In the second diffusion step, phosphorus is diffused into the first substrate 11 through solid-phase diffusion by forming phosphosilicate glass on the lower surface of the composite substrate 10 in the second region.

[0108] In this embodiment, as in step S102, a case will be described in which solid-phase diffusion is used to form PSG in the second region of the P-type well region 81, but other diffusion methods such as an ion implantation method in which phosphorus ions are implanted from below the second region may also be used. In other words, in the first diffusion step and the second diffusion step, a dopant is diffused from the lower surface of the composite substrate 10 into the interior of the composite substrate 10 using an ion implantation method.

[0109] Next, as shown in FIG. 13, thermal oxide films 17C and 18C are formed on the lower surface of the first substrate 11 and the upper surface of the second substrate 12 (step S105: second thermal oxidation step). In this step, the wafer in which the P-type well region 81 is formed is oxidized with oxygen (O 2 ) and water (H 2 C. for 2.5 hours in a SiO.sub.2O) atmosphere to form thermal oxide films 17B and 18B.

[0110] Next, as shown in FIG. 14, a hole forming step is performed in which etching is performed from the lower surface side of the composite substrate 10 to form a plurality of columnar holes 16A that will become a plurality of through holes 16 in a subsequent step (step S106: hole forming step). In this step, each of the plurality of holes 16A is formed from the lower surface side of the first substrate 11 by deep reactive ion etching (DRIE) using the Bosch process. The DRIE is performed until the lower surface of the buried oxide film 14 is exposed in the plurality of holes 16A. At this time, the buried oxide film 14 functions as an etch stopper. In other words, the manufacturing method of the semiconductor device 100 includes a hole forming step in which a plurality of columnar holes 16A are formed from the lower surface in the region of the lower surface of the composite substrate 10 except for the P-type well region 81.

[0111] Each of the plurality of holes 16A is formed in a region separated from the P-type well region 81 and in a region corresponding to the cathode electrode 41 and the anode electrode 42 of the semiconductor element 40 in an element mounting step described later. Although not shown, this step includes the steps of applying photoresist to the lower surface of the composite substrate 10, exposing the photoresist to light so as to remove each region of the plurality of holes 16A and removing the photoresist from those regions, etching the first substrate 11 in the photoresist opening portions, and removing the photoresist.

[0112] Next, as shown in FIG. 15, a thermal oxide film 17D is formed on the inner side surface of the plurality of holes 16A (step S107: third thermal oxidation step). In this step, the wafer in which the plurality of holes 16A are formed is oxidized with oxygen (O 2 ) and water (H 2 In this step, the thermal oxide film 17D is formed on the inner surface of the holes 16A, so that the holes 16A become the holes 16B by performing a wet thermal oxidation treatment at 950° C. for 2.5 hours in a SiO 2 (O) atmosphere.

[0113] Next, as shown in FIG. 16, etching is performed from the upper surface side of the composite substrate 10 to form a recess on the upper surface of the composite substrate 10 (step S108: recess forming step). In this step, an upper surface opening 15A is formed on the upper surface of the second substrate 12 by crystal anisotropic wet etching using a tetramethylammonium hydroxide aqueous solution (TMAH). The upper surface opening 15A is formed by etching from the upper surface of the second substrate 12 until it penetrates the second substrate and exposes the upper surface of the buried oxide film 14. The upper surface opening 15A is formed by forming an area including the area where each of the multiple holes 16A is formed as the bottom surface of the recess. The upper surface opening 15A is etched so that its inner surface becomes the (111) crystal plane of the single crystal silicon of the second substrate 12. This step includes the processes of applying photoresist to the upper surface of second substrate 12, exposing the photoresist to light so as to remove the regions of each recess, removing the photoresist from those regions, etching thermal oxide film 18B and second substrate 12 in the photoresist openings, and removing the photoresist.

[0114] 17, the thermal oxide film 17D formed on the first substrate 11, the thermal oxide film 18C formed on the second substrate 12, and the buried oxide film 14 exposed on the bottom surface of the upper surface opening 15A are removed (step S109: thermal oxide film removal process). In this step, these oxide films are removed using BHF. As a result, the buried oxide film 14 exposed on the bottom surface of the upper surface opening 15A is removed, and each of the multiple holes 16B is connected to the bottom surface of the upper surface opening 15A.

[0115] In this step, the thermal oxide film 17D formed on the inner side surface of the plurality of holes 16B is removed, and the plurality of holes 16B are connected to the bottom surface of the upper surface opening 15A to become the plurality of through holes 16C. That is, steps S108 and S109 are processed as a cavity forming step of forming a cavity in the composite substrate 10 whose bottom surface is connected to the plurality of through holes 16C. In other words, the manufacturing method of the semiconductor device 100 includes a cavity forming step of forming a recessed portion such that a region including the plurality of holes 16B from the upper surface of the composite substrate 10 serves as the bottom surface and the bottom surface is connected to the plurality of holes 16B.

[0116] Next, as shown in FIG. 18, thermal oxide films 17 and 18 are formed on the exposed surfaces of first substrate 11 and second substrate 12 (step S110: fourth thermal oxidation step). Specifically, thermal oxide film 17 is formed on the lower surface of first substrate 11, the upper surface of first substrate 11 exposed at the bottom surface of upper surface opening 15A, and the inner surfaces of each of the multiple through holes 16. Thermal oxide film 18 is also formed on the upper surface of second substrate 12 and the inner surface of upper surface opening 15A. In this step, the wafer from which thermal oxide films 17D and 18C have been removed is oxidized with oxygen (O 2 ) and water (H 2 Then, wet thermal oxidation treatment is performed in a 0) atmosphere at 950° C. for 2.5 hours to form thermal oxide films 17 and 18 on the exposed surfaces of first substrate 11 and second substrate 12.

[0117] In this step, a thermal oxide film 17 is formed on the inner surface of the plurality of through holes 16C, thereby becoming a plurality of through holes 16. A thermal oxide film 18 is formed on the inner surface of the upper surface opening 15A, thereby becoming an upper surface opening 15. As a result, the space surrounded by the first substrate 11 and the upper surface opening 15 functions as a cavity of the composite substrate 10.

[0118] 19, a first opening OP1 and a second opening OP2 are formed in each of the regions spaced apart from each other in the thermal oxide film 17 formed on the lower surface of the first substrate 11 (step S111: thermal oxide film opening step). + A first opening OP1 and a second opening OP2 are opened in the thermal oxide film 17 so as to expose the lower surface of each of the mold well regions 82. In this step, these oxide films are removed using BHF.

[0119] By carrying out the above steps S110 and S111, a thermal oxide film forming process is performed in which a thermal oxide film 17 having a first opening OP1 and a second opening OP2 is formed on the lower surface of the composite substrate 10. In other words, the method for manufacturing the semiconductor device 100 is a process for forming a first opening OP1 exposing the P-type well region 81 and a second opening OP2 on the lower surface of the composite substrate 10.+ The method includes a thermal oxide film forming step of forming a thermal oxide film 17 having a second opening OP2 that exposes the mold well region 82.

[0120] In the second diffusion step of step S104, N + As shown in FIG. 5, in the thermal oxide film opening process of step S111, the N well region 82 is formed in the thermal oxide film 17 so as to extend beyond the midpoint between the first opening OP1 and the second opening OP2. + In other words, in the second diffusion step, N + A mold well region 82 is formed along the lower surface of the composite substrate 10, extending beyond the midline between the first opening OP1 and the second opening OP2 to the side of the first opening OP1.

[0121] In addition, by the wet thermal oxidation treatment in the first to fourth thermal oxidation processes of steps S103, S105, S107, and S110, boron is segregated near the lower surface side of the P-type well region 81 as shown in FIG. + In other words, the first diffusion step and the second diffusion step form the P-type well region 81 and the N + After forming each of the P-type well regions 81 and N-type well regions 82, + Thermal oxide films 17B, 17C, 17D and 17C are formed on the lower surface of each of the P-type well regions 82 by wet thermal oxidation, and a P-type well region 81 having a higher carrier density than other regions is formed in a region 1 facing the first opening OP1 of the P-type well region 81. + A segregation layer 81H is formed.

[0122] Next, a Ti seed layer and a Cu seed layer are formed from the lower surface of the first substrate 11 (step S112: sputtering process). In this step, a titanium seed layer and a copper seed layer are formed in this order from the lower surface of the thermal oxide film 17 by sputtering film formation over the entire lower surface of the thermal oxide film 17. The titanium seed layer and the copper seed layer are formed by stacking in order from the lower surface of each well region in the first opening OP1 and the second opening OP2 so as to cover the P-type well region 81 and the N+-type well region 82 exposed in each opening. The titanium seed layer and the copper seed layer are also formed by stacking in order on a part of the inner surface on the lower surface side of each of the multiple through holes 16 in the multiple through holes 16.

[0123] 20, a through electrode forming step is performed in which a plurality of through electrodes 30 each consisting of a Cu layer 31, a Ni layer 32, and an AuSn layer 33 is formed inside each of the plurality of through holes 16 (step S113: first plating step). In this step, the lower surface of the composite substrate 10 is masked, and the Cu layer 31, the Ni layer 32, and the AuSn layer 33 are formed inside each of the plurality of through holes 16 by electrolytic plating in the order of Cu, Ni, and AuSn from the lower surface of the composite substrate 10. The plurality of through electrodes 30 are formed so that the AuSn layer 33 protrudes from the thermal oxide film 17. In other words, the manufacturing method of the semiconductor device 100 includes a through electrode forming step in which a plurality of columnar through electrodes 30 are formed by electrolytic plating so as to fill the inside of each of the plurality of through holes 16 and protrude from the bottom surface of the cavity.

[0124] Furthermore, by forming the plurality of through electrodes 30, the upper surface of the first substrate 11, which is the bottom surface of the upper surface opening 15, functions as the element mounting surface 13. Thereafter, the mask on the lower surface of the first substrate 11 is removed, thereby exposing the Cu layer 31 of each of the plurality of through electrodes 30 on the lower surface of the first substrate 11.

[0125] Next, as shown in FIG. 21, the first external electrode 21 and the second external electrode 22 are formed on the lower surface of the composite substrate 10 (step S114: second plating step). In this step, first, a mask made of resist is applied to open the formation areas of the first external electrode 21 and the second external electrode 22 on the lower surface of the composite substrate 10. Next, Ni plating layers 21C and 22C, and AuSn plating layers 21D and 22D are laminated in this order on the copper seed layer exposed in the opening areas of the resist and the lower surfaces of each of the Cu layers 31 of the multiple through electrodes 30 by using electric field plating. This allows each of the Ni plating layers 21C and 22C to be in electrical contact with each of the lower surfaces of the Cu layers 31, which are the lower surfaces of the multiple through electrodes 30.

[0126] Thereafter, the resist is removed, and the Ti seed layer and the copper seed layer remaining in the region excluding the region where the Ni plating layers 21C and 22C and the AuSn plating layers 21D and 22D are formed on the lower surface of the thermal oxide film 17 are removed. As a result, the Ti seed layer and the copper seed layer become Ti seed layers 21A and 22A and Cu seed layers 21B and 22B that are spaced apart from each other, as shown in Fig. 5. That is, in this step, the first external electrode 21 and the second external electrode 22 that are a pair of external electrodes that are electrically insulated from each other are formed.

[0127] By carrying out the above steps S112 and S114, the process is processed as an external electrode formation step in which Ti seed layers 21A and 22A, Cu seed layers 21B and 22B, and Ni plating layers 21C and 22C are laminated in this order from the lower surface of the composite substrate 10, forming a pair of external electrodes, a first external electrode 21 and a second external electrode 22, which are spaced apart from each other. In other words, the manufacturing method of the semiconductor device 100 includes forming, on the lower surface of the thermal oxide film 17, the first external electrode 21 in contact with the P-type well region 81 at the first opening OP1 and the second external electrode 22 spaced from the first external electrode 21 and spaced apart from the first external electrode 21 at the second opening OP2. +The method includes an external electrode forming step of forming a second external electrode 22 in contact with the mold well region 82. In the external electrode forming step, the first external electrode 21 and the second external electrode 22 are formed in the first opening OP1 and the second opening OP2 by laminating Ti seed layers 21A and 22A, Cu seed layers 21B and 22B, and Ni plating layers 21C and 22C in this order from the lower surface of the composite substrate 10.

[0128] 22, the composite substrate 10 is set in a die bonding device, and a die bonding process is performed in which a semiconductor element 40 is mounted on the element mounting surface 13 (step S115: element bonding process). In this step, the semiconductor element 40 is mounted after alignment is performed so that the cathode electrode 41 of the semiconductor element 40 corresponds to the through electrode 30 electrically connected to the first external electrode 21, and the anode electrode 42 of the semiconductor element 40 corresponds to the through electrode 30 electrically connected to the second external electrode 22. Thereafter, the wafer on which the semiconductor element 40 is mounted is heated in a nitrogen (N 2 ) atmosphere at 340° C. for 30 seconds to melt the AuSn layer 33 of the plurality of through electrodes 30, thereby bonding each of the plurality of through electrodes 30 to the cathode electrode 41 and the anode electrode 42 of the semiconductor element 40. In other words, the manufacturing method of the semiconductor device 100 includes a die bonding process of placing the semiconductor element 40 on the bottom surface of the recess.

[0129] 23, a lid member bonding step is performed in which the lid member 50 is bonded to the upper surface of the second substrate 12 via the frit glass layer 60 (step S116: lid member bonding step). In this step, first, a lid member 50 is prepared on which the frit glass layer 60 has been formed in advance on the surface facing the upper surface of the second substrate 12. The frit glass layer 60 is printed on the surface of the wafer-shaped lid member 50 facing the second substrate 12 so as to surround the upper surface opening 15, and is pre-fired at a temperature of about 500° C. for one hour in an oxygen (O2) atmosphere. The lid member 50 is aligned and placed at a position that surrounds the upper surface opening 15 and does not overlap the parting line CL of the composite substrate 10.

[0130] Next, a laser is irradiated from above onto the composite substrate 10 on which the lid member 50 is placed, melting the glass frit layer 60 and bonding the composite substrate 10 and the lid member 50. The laser is, for example, a laser beam having a wavelength of near-infrared light. 2 The frit glass layer 60 is irradiated in a vacuum atmosphere, and the frit glass layer 60 is locally heated and melted, thereby bonding it to the composite substrate 10. At this time, as described in FIG. 4, the melted frit glass layer 60 and the thermal oxide film 18 on the upper surface of the second substrate 12 interdiffuse to form an interdiffusion layer 70. As a result, the inside of the cavity is filled with inert gas N 2 In other words, the manufacturing method of the semiconductor device 100 includes a lid member bonding step of placing a lid member 50 made of glass having a glass frit layer 60 on one surface facing the upper surface of the composite substrate 10 so as to cover the recess, and bonding the lid member 50 to the upper surface of the composite substrate 10 by scanning the glass frit layer 60 from above along the periphery of the recess with a laser.

[0131] In this step, various conditions for the laser irradiation are set so that the remaining thermal oxide film 18R is formed after the formation of the interdiffusion layer 70. That is, the laser irradiation conditions are set so that the remaining thermal oxide film 18R, the interdiffusion layer 70, and the frit glass layer 60 are laminated in this order from the upper surface of the second substrate 12 at the joint between the second substrate 12 and the frit glass layer 60.

[0132] In this embodiment, the frit glass layer 60 surrounding the cavity is scanned with a laser along the periphery of the cavity. The scanning time of the laser is about 2 to 3 seconds per semiconductor device 100. By melting and bonding the frit glass layer 60 by irradiating the laser, the bonding portion of the frit glass layer 60 is heated locally and in a short time to bond the frit glass layer 60. This makes it possible to prevent remelting due to overheating of the AuSn layer 33 of the through electrode 30, which is the bonding portion with the semiconductor element 40, and makes it possible to suppress manufacturing defects such as misalignment of the semiconductor element 40.

[0133] In addition, the inside of the cavity is N 2 The space is filled with a gas having a thermal conductivity that is extremely low compared to that of the composite substrate 10 whose main material is single crystal Si. Furthermore, the heat of the element mounting surface 13 is dissipated to the lower surface side of the composite substrate 10 (for example, a mounting table of a laser irradiation device) due to the high thermal conductivity of single crystal Si, making it possible to further suppress overheating of the AuSn layer 33. According to the inventors' verification, the temperature of the element mounting surface 13 during laser irradiation was 250° C. or lower.

[0134] 24, the composite substrate 10 to which the lid member 50 is joined is set in a dicing device, and the composite substrate 10 and the lid member 50 are cut along the division lines CL to separate them (step S117: dicing process). In this way, the wafer is diced into individual semiconductor devices 100, and a plurality of semiconductor devices 100 are manufactured.

[0135] According to this embodiment, the semiconductor device 100 has a diode structure 80 formed inside the composite substrate 10 in a region along the lower surface of the composite substrate 10. The diode structure 80 also has a P-type well region 81 of a second conductivity type in which a P-type impurity such as boron (B) is diffused from the lower surface side of the first substrate 11 in a first region across the first external electrode 21 and the second external electrode 22 on the lower surface of the composite substrate 10.

[0136] The diode structure 80 is, for example, an N-type impurity such as phosphorus (P) diffused from the lower surface side of the first substrate 11 into a second region in a first region on the lower surface of the first substrate 11. + The diode structure 80 has a type well region 82. The diode structure 80 also functions as a Zener diode connected in parallel with the semiconductor element 40 and with reverse polarity between the first external electrode 21 and the second external electrode 22.

[0137] The diode structure 80 has a larger N + The Zener diode has a one-sided abrupt junction structure in which the N well region 82 has a higher carrier density. +The diode structure 80 is a Zener diode in which avalanche breakdown is dominant when an overvoltage is applied from the N-type well region 82 to the P-type well region 81. The diode structure 80 is also formed by a first contact portion C1 and a second contact portion C2. + The width D3 of the type well region 82 is set to be equal to or greater than 0.5 times the distance D2 between the first contact portion C1 and the second contact portion C2. With these configurations, the diode structure 80 can function as a Zener diode having a high breakdown voltage.

[0138] Furthermore, the lower surface of the diode structure 80 is covered and insulated by a thermal oxide film 17 between the first external electrode 21 and the second external electrode 22. With this configuration, when the semiconductor device 100 is mounted on a mounting board, the first external electrode 21 and the second external electrode 22 are joined using a molten metal such as AuSn or solder, and thus it is possible to suppress leakage current to the diode structure 80.

[0139] Furthermore, a depletion layer due to an internal electric field is formed between the P-type well region 81 of the diode structure portion 80 and the first substrate 11, and they are substantially insulated from each other. With this configuration, the first substrate 11 is substantially insulated from the P-type well region 81 and is in an electrically floating state. This makes it possible for the semiconductor device 100 to suppress leakage current from the side surface of the first substrate 11 to other adjacent semiconductor devices on the mounting substrate when an overvoltage is applied on the mounting substrate.

[0140] As described above, the semiconductor device 100 of this embodiment can prevent short circuits caused by molten metal during heat treatment of the bonding layer, and can suppress leakage current to adjacent semiconductor devices when an overvoltage is applied after mounting on a mounting substrate, making it possible to provide a semiconductor device 100 and a manufacturing method for the semiconductor device 100. EXAMPLES

[0141] 25 is an enlarged cross-sectional view of a diode structure 80A of a semiconductor device 100A according to a second embodiment of the present invention, taken at a position corresponding to the ZD portion shown in FIG.

[0142] The semiconductor device 100A has a basically similar configuration to the semiconductor device 100 of the first embodiment, and has a similar appearance. The semiconductor device 100A has a P-type well region 81 and an N-type well region 82 in the thermal oxide film 17 formed on the lower surface of the diode structure portion 80. + This embodiment differs from the first embodiment in that an interface opening EX is formed by opening a region corresponding to the junction interface of the mold well region 82.

[0143] In Example 1, the cathode is N + When an overvoltage such as static electricity is applied from the N-type well region 82 to the P-type well region 81, the diode structure 80 undergoes avalanche breakdown and a current flows. At this time, hot electrons due to the avalanche breakdown flow between the P-type well region 81 and the N-type well region 82. + The P-type well region 81 and the N-type well region 82 may be trapped in the thermal oxide film 17 in the region corresponding to the junction interface, and the thermal oxide film 17 in the region may become charged. + If thermal electrons are trapped in the thermal oxide film 17 near the junction interface of the type-well region 82, the diode structure 80 becomes more susceptible to avalanche breakdown, which may reduce the effective breakdown voltage of the diode structure 80. In other words, if an overvoltage is applied to the semiconductor device 100 multiple times, the breakdown voltage of the diode structure 80 decreases, and if the breakdown voltage falls below the drive voltage of the semiconductor element 40, this may affect the operation of the semiconductor element 40.

[0144] In the second embodiment, the P-type well region 81 and the N + By providing the interface opening EX in the thermal oxide film 17 in a region corresponding to the junction interface of the type well region 82, it becomes possible to suppress trapping of thermoelectrons in the thermal oxide film 17 in that region when avalanche breakdown occurs in the diode structure portion 80. In other words, it becomes possible to maintain the breakdown voltage of the diode structure portion 80 at a desired voltage value even if an overvoltage is applied to the semiconductor device 100 multiple times.

[0145] Within the interface opening EX, a P-type well region 81 and an N + The exposed surface of the P-type well region 82 is insulated only by the native oxide film of Si. Therefore, the insulation inside the interface opening EX is lower than the region where the thermal oxide film 17 is formed. However, the P-type well region 81 and the N-type well region 82 are insulated only by the native oxide film of Si. + Even in consideration of the width of the depletion layer formed at the junction interface of the P-type well region 82, the width of the interface opening EX is about several μm. Therefore, when the semiconductor device 100 is mounted on a mounting substrate, a joining material such as solder enters the interface opening EX and the joining material is mixed with the P-type well region 81 and the N-type well region 82. + The likelihood of contacting the mold well region 82 is low.

[0146] Moreover, the configuration of the semiconductor device 100A of the second embodiment is the same as that of the first embodiment, except for the interface opening EX. That is, since a depletion layer is formed at the interface between the P-type well region 81 and the first substrate 11, the diode structure 80 and the first substrate 11 are substantially insulated from each other.

[0147] Therefore, in the second embodiment as well, it is possible to provide a semiconductor device that can prevent a short circuit caused by molten metal during heat treatment of the bonding layer, while suppressing leakage current to other semiconductor devices when an overvoltage is applied on the mounting board, and a semiconductor device.

[0148] In this embodiment, the semiconductor element 40 mounted on the semiconductor device 100 is a light-emitting element that emits ultraviolet light. However, the semiconductor element 40 mounted on the semiconductor device 100 is not limited to this. The semiconductor element 40 may be, for example, another light-emitting element such as a laser diode, or a light-receiving element such as a photodiode.

[0149] In the present embodiment, the semiconductor element 40 mounted on the semiconductor device 100 is a two-terminal semiconductor element having a pair of electrodes consisting of an anode and a cathode. However, the semiconductor element 40 may be a three-terminal semiconductor element having three electrodes. Also, three electrodes may be formed on the external electrodes provided on the semiconductor device 100. In that case, the diode structure portion 80 can be arbitrarily formed between desired electrodes.

[0150] In this embodiment, the lid member 50 is a light-transmitting member that transmits light of a desired wavelength. However, the lid member 50 is not limited to this, and in the case where the semiconductor element 40 is an element that is not related to light, the lid member 50 may be a lid member made of metal or ceramic. Even if the lid member 50 is made of metal or ceramic, it is possible to hermetically seal the storage space HS in the cavity by joining it to the composite substrate 10 with frit glass.

[0151] In this embodiment, the semiconductor element 40 is mounted on a plurality of through electrodes 30 formed to protrude from the element mounting surface 13. However, the method of mounting the semiconductor element 40 is not limited to this. For example, a block-shaped element mounting electrode having an upper surface shape substantially the same as the lower surface shape of the cathode electrode 41 and the anode electrode 42 of the semiconductor element 40 may be formed on the upper surface of the element mounting surface 13. In this case, a metal such as Cu is filled into the inside of the plurality of through holes 16 by plating to form a plurality of through electrodes, and Ni and AuSn are plated in this order so as to contact the upper surfaces of the plurality of through electrodes to form a pair of block-shaped element mounting electrodes. This makes it possible to self-align the mounting position of the semiconductor element 40 in the element bonding process. [Explanation of symbols]

[0152] 100 Semiconductor device 10 Substrate 11 First substrate 12 Second board 13 Element mounting surface 14 Buried oxide film 15 Opening 16 Through hole 17, 18 Thermal oxide film 21 First external electrode 22 Second external electrode 30 Through electrode 31 Cu layer 32 Ni layer 33 AuSn layer 40 Semiconductor elements 41 Anode electrode 42 Cathode electrode 50 Lid member 60 frit glass layers 70 Interdiffusion Layer 80 Diode structure 81 P-type well region 82 N + Mold Well Area

Claims

1. a substrate made of single crystal silicon having a first conductivity type, thermal oxide films formed on an upper surface and a lower surface, a first opening and a second opening spaced apart from each other formed in the thermal oxide film formed on the lower surface, a diode structure including a first well region having a second conductivity type different from the first conductivity type formed in a first region along the lower surface and exposed at the first opening, and a second well region having the first conductivity type formed in a second region along the lower surface within the first region and exposed at the second opening; a semiconductor element disposed on the substrate and having a semiconductor layer; a first external electrode formed on a lower surface of the thermal oxide film and in contact with the first well region at the first opening; a second external electrode formed on a lower surface of the thermal oxide film, spaced apart from the first external electrode and in contact with the second well region at the second opening; The second well region extends along the lower surface of the substrate, beyond a midline between the first opening and the second opening, to the side of the first opening.

2. 2. The semiconductor device according to claim 1, wherein each of the first external electrode and the second external electrode is formed by stacking a titanium seed layer, a copper seed layer, and a nickel plating layer in that order from the bottom surface of the substrate in the first opening and the second opening.

3. 3. The semiconductor device according to claim 1, wherein the second well region has a high-concentration well region in one region facing the second opening, the high-concentration well region having a higher carrier density than other regions.

4. 4. The semiconductor device according to claim 1, wherein the diode structure is a Zener diode or an avalanche diode.

5. the first well region is doped with boron; 5. The semiconductor device according to claim 1, wherein the second well region is doped with phosphorus.

6. the substrate is formed by bonding together a first substrate made of plate-shaped single crystal silicon having the first conductivity type and a second substrate disposed on the first substrate and having an opening with an inner side surface forming a recess together with an upper surface of the first substrate; 6. The semiconductor device according to claim 1, further comprising an oxide film formed on a surface of said first substrate facing said second substrate.

7. The semiconductor element has a pair of electrodes on a lower surface thereof, the substrate is provided with a plurality of through holes each extending in a columnar shape from a bottom surface of the recess to a rear surface of the substrate, the inner surface of the through hole being covered with the thermal oxide film; a plurality of columnar through electrodes are formed in the plurality of through holes, the columnar through electrodes filling the plurality of through holes of the substrate and protruding from the bottom surface; 7. The semiconductor device according to claim 6, wherein the plurality of through electrodes electrically connect each of the pair of electrodes of the semiconductor element to the first external electrode and each of the second external electrodes.

8. 8. The semiconductor device according to claim 7, wherein the plurality of through electrodes are arranged on lattice points of an equilateral triangular lattice on the bottom surface of the recess.

9. a cover member made of glass bonded to the top surface of the substrate via a glass frit layer; 9. The semiconductor device according to claim 1, wherein the thermal oxide film and a reaction layer between the thermal oxide film and the glass frit layer are formed in this order from a surface of the substrate between the substrate and the glass frit layer at a bonding portion between the substrate and the glass frit layer.

10. 10. The semiconductor device according to claim 1, wherein the semiconductor element is a light-emitting element that emits ultraviolet light from the semiconductor layer.

11. A method for manufacturing a semiconductor device, comprising: providing a substrate made of single crystal silicon having a first conductivity type; a first diffusion step of forming a first well region having a second conductivity type different from the first conductivity type in a first region along a bottom surface of the substrate; a second diffusion step of forming a second well region having the first conductivity type in a second region along the bottom surface of the substrate within the first region; a thermal oxide film forming step of forming a thermal oxide film on the lower surface of the substrate, the thermal oxide film having a first opening exposing the first well region and a second opening exposing the second well region; an external electrode forming step of forming, on a lower surface of the thermal oxide film, a first external electrode in contact with the first well region at the first opening and a second external electrode spaced apart from the first external electrode and in contact with the second well region at the second opening; a second well region formed along the lower surface of the substrate, the second well region extending beyond a midline between the first opening and the second opening to the side of the first opening, in the second diffusion step.

12. 12. The method for manufacturing a semiconductor device according to claim 11, characterized in that in the external electrode formation process, the first external electrode and the second external electrode are formed in the first opening and the second opening by stacking a titanium seed layer, a copper seed layer, and a nickel plating layer in that order from the lower surface of the substrate.

13. In the first diffusion step, boron silicate glass is formed on the lower surface of the substrate in the first region to diffuse boron into the substrate in a solid phase; 13. The method for manufacturing a semiconductor device according to claim 11, wherein in the second diffusion step, phosphorus is diffused into the inside of the substrate in a solid phase by forming phosphosilicate glass on the lower surface of the substrate in the second region.

14. 14. The method for manufacturing a semiconductor device according to claim 11, wherein in the first diffusion step and the second diffusion step, a dopant is diffused from the lower surface of the substrate into the inside of the substrate by using an ion implantation method.

15. 15. The method for manufacturing a semiconductor device according to claim 11, wherein after forming the first well region and the second well region in the first diffusion step and the second diffusion step, the thermal oxide film is formed on an underside of the first well region and the second well region by wet thermal oxidation, and a high-concentration well region having a higher carrier density than other regions is formed in one region of the first well region facing the first opening.

16. a hole forming step of forming a plurality of columnar holes from the lower surface of the substrate in a region of the lower surface excluding the first region; a cavity forming step of forming a recess having a bottom surface that is a region including the plurality of holes from the upper surface of the substrate and communicating the bottom surface with the plurality of holes; 16. The method for manufacturing a semiconductor device according to claim 11, further comprising a through electrode formation process for forming a plurality of columnar through electrodes by electrolytic plating so as to fill the interior of each of the plurality of holes and protrude from the bottom surface.

17. a die bonding step of mounting a semiconductor element on the bottom surface of the recess; 17. The method for manufacturing a semiconductor device according to claim 16, further comprising a lid member bonding step of placing a lid member made of glass having a frit glass layer on one surface facing the top surface of the substrate so as to cover the recess, and scanning a laser from above on the frit glass layer along a periphery of the recess to bond the lid member to the top surface of the substrate.

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