Manufacturing method for electronic components

Abstract

A semiconductor device including a substrate, a wiring section, a joined section, a semiconductor element, and a sealing resin. The substrate has a substrate main surface and a substrate rear surface that each face the opposite direction. The wiring section has a conductive layer formed on the substrate main surface. The joined section has: a first plated layer formed on an upper surface of the wiring section; and a first soldered layer formed on an upper surface of the first plated layer. The semiconductor element has: an element main surface facing the substrate main surface; an element electrode formed on the element main surface; and a second soldered layer formed on the lower surface of the element electrode and joined to the first soldered layer. The sealing resin covers the semiconductor element. The joined section is larger than the element electrode, when viewed from a thickness direction perpendicular to the substrate main surface.

Description

[Technical field]

[0001] This disclosure , electric This relates to a manufacturing method for small parts. [Background technology]

[0002] Conventionally, electronic components including elements such as resistors and semiconductor chips include a substrate on which the elements are mounted and a sealing resin that covers the elements. For example, Patent Document 1 discloses a semiconductor device including a wiring body having an external connection terminal on one side and a semiconductor chip mounted on the other side, and a sealing resin formed on the other side of the wiring body so as to seal the semiconductor chip.

[0003] In addition, with the miniaturization of electronic devices in recent years, there is a demand for miniaturization of semiconductor devices applied to the electronic devices. In response to this demand, Patent Document 2 discloses an example of a miniaturized semiconductor device. The semiconductor device includes a semiconductor wafer, a flip-chip mounted semiconductor chip, and a sealing sheet containing a thermosetting synthetic resin. The semiconductor wafer serves as a substrate on which the semiconductor chip is mounted. The semiconductor chip is flip-chip mounted on wiring provided on the upper surface of the semiconductor wafer. The sealing sheet is laminated on the semiconductor wafer and covers the semiconductor chip. Since the semiconductor wafer is relatively thin, the semiconductor device is miniaturized.

[0004] In the manufacture of the semiconductor device described above, there is a concern that the semiconductor device may warp when the sealing sheet is thermally cured due to the linear expansion coefficient of the sealing sheet being larger than that of the semiconductor wafer. Therefore, the sealing sheet of the semiconductor device disclosed in Patent Document 2 has a two-layer structure of an embedding resin layer having different minimum melt viscosities and a hard layer laminated on the embedding resin layer. The embedding resin layer contacts the semiconductor wafer and covers the semiconductor chip. The hard layer is located on the opposite side of the semiconductor wafer from the embedding resin layer in the thickness direction of the semiconductor device. The minimum melt viscosity of the hard layer is larger than the minimum melt viscosity of the embedding resin layer. This makes it possible to reduce the warp of the semiconductor device. However, the semiconductor device disclosed in Patent Document 2 has a problem that the overall thickness of the sealing sheet becomes larger in order to reduce the warp of the sealing sheet, which hinders the miniaturization of the semiconductor device.

[0005] Furthermore, as an example of an electronic component, an electronic component module is known that includes a circuit board, a plurality of functional elements placed on the upper surface of the circuit board, and a sealing resin that seals the plurality of functional elements (see, for example, Patent Document 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2013-197263 A [Patent Document 2] JP 2015-32648 A [Patent Document 3] JP 2011-124413 A Summary of the Invention [Problem to be solved by the invention]

[0007] Incidentally, semiconductor chips are soldered to the conductive layer of the wiring body by reflow processing. The conductive layer is made of Cu (copper). For this reason, the solder becomes liquid when heated during the reflow process and may flow out along the conductive layer. If the solder flows out in an unintended direction like this, it may cause a short circuit problem.

[0008] A first object of the present disclosure is to provide a semiconductor device capable of suppressing solder outflow.

[0009] A second object of the present disclosure is to provide a semiconductor device that can be miniaturized while reducing warping of the device.

[0010] Furthermore, since conventional electronic components are configured such that multiple functional elements are arranged side by side on the same plane of a circuit board, there is room for improvement in terms of miniaturization in the planar direction along the top surface of the circuit board, i.e., in the direction perpendicular to the height direction of the electronic component.

[0011] A third object of the present disclosure is to provide an electronic component and a method for manufacturing an electronic component that can be made smaller in size in a direction perpendicular to the height direction of the electronic component. [Means for solving the problem]

[0012] A semiconductor device according to a first aspect of the present disclosure comprises a substrate having a substrate main surface and a substrate back surface facing opposite each other, a wiring portion having a conductive layer formed on the substrate main surface, a joint having a first plating layer formed on an upper surface of the wiring portion and a first solder layer formed on an upper surface of the first plating layer, a semiconductor element having an element main surface facing the substrate main surface, an element electrode formed on the element main surface, and a second solder layer formed on a lower surface of the element electrode and joined to the first solder layer, and a sealing resin covering the semiconductor element, wherein the joint is larger than the element electrode when viewed from a thickness direction perpendicular to the substrate main surface.

[0013] According to this configuration, the first solder layer is joined to the second solder layer of the semiconductor element by a reflow process to form a solder layer. In this reflow process, the molten second solder layer is fused with the first solder layer and is therefore less likely to flow out beyond the plating layer. This makes it possible to suppress the flow of solder during the reflow process when mounting the semiconductor element.

[0014] A semiconductor device according to a second aspect of the present disclosure comprises a sealing resin including a first layer having a first main surface and a first back surface facing opposite each other in a thickness direction, and a second layer having a second back surface in contact with the first main surface, and a second main surface facing the opposite side to the second back surface in the thickness direction, a wiring in contact with the first main surface and partially covered by the second layer, a bottom surface facing the first main surface, and a plurality of pads provided on the bottom surface, at least one of the plurality of pads being joined to the wiring and covered by the second layer.

[0015] An electronic component according to a third aspect of the present disclosure comprises: an electrically insulating insulating member having an insulating main surface and an insulating back surface facing opposite each other in a thickness direction; main surface wiring formed on the insulating main surface and having a wiring main surface facing the same direction as the insulating main surface and a wiring back surface opposite the insulating main surface; a first functional element conductive to the main surface wiring and arranged on the opposite side of the main surface wiring from the insulating member in the thickness direction; a sealing resin covering the main surface wiring and the first functional element and having an element mounting surface facing the same direction as the insulating main surface; a connecting conductor conductive to the main surface wiring, extending from the wiring main surface to the element mounting surface in the thickness direction and exposed from the element mounting surface; a through wiring conductive to the main surface wiring, extending in the thickness direction from the wiring back surface to the insulating back surface and exposed from the insulating back surface; and a second functional element mounted on the element mounting surface and electrically connected to the connecting conductor.

[0016] According to this configuration, the first functional element and the second functional element are disposed at different positions in the thickness direction, so that the first functional element and the second functional element can be disposed so as to overlap when viewed from the thickness direction. Therefore, compared to a configuration in which the first functional element and the second functional element are disposed side by side on the same plane in the direction perpendicular to the thickness direction, it is possible to reduce the size of the electronic component in the direction perpendicular to the thickness direction.

[0017] An electronic component according to a fourth aspect of the present disclosure comprises: an electrically insulating insulating member having an insulating main surface and an insulating back surface facing opposite each other in a thickness direction; main surface wiring formed on the insulating main surface and having a wiring main surface facing the same direction as the insulating main surface and a wiring back surface opposite the insulating main surface; a through wiring that is conductive to the main surface wiring, extends in the thickness direction from the wiring back surface to the insulating back surface and is exposed from the insulating back surface; a first functional element that is conductive to the main surface wiring and is arranged on the opposite side of the insulating member with respect to the main surface wiring in the thickness direction; a sealing resin that covers the main surface wiring and the first functional element, and has an element mounting surface that faces the same direction as the insulating main surface; and a connecting conductor that is conductive to the main surface wiring, extends in the thickness direction from the wiring main surface to the element mounting surface and is exposed from the element mounting surface, and the connecting conductor is configured to be electrically connected to a second functional element mounted on the element mounting surface.

[0018] According to this configuration, the first functional element and the second functional element are disposed at different positions in the thickness direction, so that the first functional element and the second functional element can be disposed so as to overlap when viewed from the thickness direction. Therefore, compared to a configuration in which the first functional element and the second functional element are disposed side by side on the same plane in the direction perpendicular to the thickness direction, it is possible to reduce the size of the electronic component in the direction perpendicular to the thickness direction.

[0019] A method for manufacturing an electronic component according to a fifth aspect of the present disclosure includes a step of forming a plurality of through wirings on a support substrate, an insulating layer forming step of forming an insulating layer formed so as to fill spaces between the plurality of through wirings on the support substrate and expose the through wirings from both an insulating main surface and an insulating back surface facing opposite sides in a thickness direction, a main surface wiring forming step of forming a main surface wiring on the insulating main surface having a wiring main surface and a wiring back surface facing opposite sides in the thickness direction, the main surface wiring being formed on the insulating main surface so that the wiring back surface is conductive with the through wiring, a conductor forming step of forming a connecting conductor on the wiring main surface, a first element mounting step of mounting a first functional element on the wiring main surface, and a first element mounting step of mounting the main surface wiring on the wiring main surface. the resin layer forming process includes a resin layer forming step of forming a resin layer covering the connecting conductor and the first functional element; and a cutting process of forming an insulating member having the through wiring and a sealing resin covering the main surface wiring, the connecting conductor and the first functional element by cutting the insulating layer, the resin layer, the main surface wiring and the through wiring in the thickness direction, wherein the resin layer forming process includes forming the resin layer so that the connecting conductor is exposed from the surface of the resin layer opposite the insulating member, and a second element mounting process includes mounting a second functional element on the surface of the sealing resin opposite the insulating member so as to be electrically connected to the connecting conductor.

[0020] According to this configuration, the first functional element and the second functional element are disposed at different positions in the thickness direction, so that the first functional element and the second functional element can be disposed so as to overlap when viewed from the thickness direction. Therefore, compared to a configuration in which the first functional element and the second functional element are disposed side by side on the same plane in the direction perpendicular to the thickness direction, it is possible to reduce the size of the electronic component in the direction perpendicular to the thickness direction.

[0021] A method for manufacturing an electronic component according to a sixth aspect of the present disclosure includes an insulating layer forming step of forming an insulating layer having an insulating main surface and an insulating back surface facing opposite sides in a thickness direction, a first internal electrode forming step of forming a through wiring exposed from the insulating back surface and a main surface wiring having a wiring main surface and a wiring back surface facing opposite sides in the thickness direction and laminated on the insulating main surface so as to be conductive with the through wiring on the wiring back surface, a second internal electrode forming step of forming a connecting conductor to be laminated on the wiring main surface, a first element mounting step of mounting a first functional element on the wiring main surface, and a second internal electrode forming step of forming a first ... The method includes a resin layer formation process for forming a resin layer covering the first functional element, and a cutting process for forming an insulating member provided with the through wiring, and a sealing resin covering the main surface wiring, the connecting conductor, and the first functional element by cutting the insulating layer, the through wiring, the wiring main surface, and the resin layer in the thickness direction, wherein the resin layer is formed in the resin layer so that the connecting conductor is exposed from the surface of the resin layer opposite the insulating member, and a second element mounting process for mounting a second functional element on the surface of the sealing resin opposite the insulating member so as to be electrically connected to the connecting conductor.

[0022] According to this configuration, the first functional element and the second functional element are disposed at different positions in the thickness direction, so that the first functional element and the second functional element can be disposed so as to overlap when viewed from the thickness direction. Therefore, compared to a configuration in which the first functional element and the second functional element are disposed side by side on the same plane in the direction perpendicular to the thickness direction, it is possible to reduce the size of the electronic component in the direction perpendicular to the thickness direction.

[0023] A method for manufacturing an electronic component according to a seventh aspect of the present disclosure includes the steps of: forming a plurality of through wirings on a support substrate; forming an insulating layer on the support substrate so as to fill spaces between the plurality of through wirings and expose the through wirings from both an insulating main surface and an insulating back surface facing opposite sides in a thickness direction; forming a main surface wiring on the insulating main surface, the main surface having a wiring main surface and a wiring back surface facing opposite sides in the thickness direction, the main surface wiring being formed on the insulating main surface so that the wiring back surface is conductive with the through wiring; forming a conductor on the wiring main surface; The method includes a resin layer formation process for forming a resin layer that covers a first functional element, and a cutting process for forming an insulating member having the through wiring and a sealing resin that covers the main surface wiring, the connecting conductor and the first functional element by cutting the insulating layer, the resin layer, the main surface wiring and the through wiring in the thickness direction, wherein in the resin layer formation process, the resin layer is formed so that the connecting conductor is exposed from the surface of the resin layer opposite the insulating member, and the sealing resin has an element mounting surface on which a second functional element electrically connected to the connecting conductor is mounted, and the element mounting surface is formed on the surface of the sealing resin opposite the insulating layer in the thickness direction.

[0024] According to this configuration, the first functional element and the second functional element are disposed at different positions in the thickness direction, so that the first functional element and the second functional element can be disposed so as to overlap when viewed from the thickness direction. Therefore, compared to a configuration in which the first functional element and the second functional element are disposed side by side on the same plane in the direction perpendicular to the thickness direction, it is possible to reduce the size of the electronic component in the direction perpendicular to the thickness direction.

[0025] A method for manufacturing an electronic component according to an eighth aspect of the present disclosure includes an insulating layer forming step of forming an insulating layer having an insulating main surface and an insulating back surface facing opposite sides in a thickness direction, a first internal electrode forming step of forming a through wiring exposed from the insulating back surface and a main surface wiring having a wiring main surface and a wiring back surface facing opposite sides in the thickness direction and laminated on the insulating main surface so as to be conductive with the through wiring on the wiring back surface, a second internal electrode forming step of forming a connecting conductor laminated on the wiring main surface, a first element mounting step of mounting a first functional element on the wiring main surface, and a resin layer forming step of covering the main surface wiring, the connecting conductor, and the first functional element. The method includes a resin layer forming process, and a cutting process for forming an insulating member provided with the through wiring, and a sealing resin covering the main surface wiring, the connecting conductor, and the first functional element by cutting the insulating layer, the through wiring, the wiring main surface, and the resin layer in the thickness direction, wherein in the resin layer forming process, the resin layer is formed so that the connecting conductor is exposed from the surface of the resin layer opposite the insulating member, and the sealing resin has an element mounting surface on which a second functional element electrically connected to the connecting conductor is mounted, and the element mounting surface is formed on the surface of the sealing resin opposite the insulating layer in the thickness direction.

[0026] According to this configuration, the first functional element and the second functional element are disposed at different positions in the thickness direction, so that the first functional element and the second functional element can be disposed so as to overlap when viewed from the thickness direction. Therefore, compared to a configuration in which the first functional element and the second functional element are disposed side by side on the same plane in the direction perpendicular to the thickness direction, it is possible to reduce the size of the electronic component in the direction perpendicular to the thickness direction. [Brief description of the drawings]

[0027] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 25 is a schematic rear view showing the semiconductor device of the first embodiment. [Diagram 3] FIG. 2 is a partially enlarged plan view of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a partially enlarged cross-sectional view of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 4 is an enlarged cross-sectional view showing a wiring portion and a part of a semiconductor element before reflow treatment. [Figure 6] FIG. 11 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 7] FIG. 11 is a schematic plan view showing a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a partially enlarged plan view of a semiconductor device according to a second embodiment. [Figure 9] FIG. 13 is a partially enlarged plan view of a semiconductor device according to a modified example. [Figure 10] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 11] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 12] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 13] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 14] FIG. 11 is a plan view of a semiconductor device according to a third embodiment of the present invention, seen through a second layer of a sealing resin. [Figure 15] 15 is a plan view corresponding to FIG. 14, showing the semiconductor element in a more transparent manner than in FIG. [Figure 16] 15 is a bottom view of the semiconductor device shown in FIG. 14. [Figure 17] FIG. 15 is a front view of the semiconductor device shown in FIG. [Figure 18] 15 is a cross-sectional view taken along line VV in FIG. 14. [Figure 19] 15 is a cross-sectional view taken along line VI-VI in FIG. 14. [Figure 20] FIG. 19 is a partially enlarged view of FIG. [Figure 21] FIG. 13 is a plan view of a semiconductor device according to a modified example of the third embodiment of the present invention, seen through a second layer of the sealing resin. [Figure 22] 22 is a cross-sectional view taken along line IX-IX in FIG. 21. [Figure 23] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 24]15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 25] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 26] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 27] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 28] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 29] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 30] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 31] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 32] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 33] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 34] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 35] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 36] 15A to 15C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 37] FIG. 11 is a plan view of a semiconductor device according to a fourth embodiment of the present invention, seen through a second layer of a sealing resin. [Figure 38] FIG. 38 is a front view of the semiconductor device shown in FIG. [Figure 39] 38 is a cross-sectional view taken along line XXVI-XXVI in FIG. 37. [Diagram 40] FIG. 13 is a plan view of a semiconductor device according to a fifth embodiment of the present invention, seen through a second layer of a sealing resin. [Diagram 41] 41 is a bottom view of the semiconductor device shown in FIG. 40. [Diagram 42]FIG. 49 is a cross-sectional view taken along line XXIX-XXIX in FIG. 40. [Diagram 43] 41 is a cross-sectional view taken along line XXX-XXX in FIG. 40. [Diagram 44] FIG. 43 is a partially enlarged view of FIG. 42. [Diagram 45] FIG. 13 is a plan view of a semiconductor device according to a sixth embodiment of the present invention. [Figure 46] 46 is a plan view corresponding to FIG. 45, seen through the second layer of the sealing resin with respect to FIG. 45. [Figure 47] FIG. 46 is a cross-sectional view taken along line XXXIV-XXXIV in FIG. 45. [Figure 48] 46 is a cross-sectional view taken along line XXXV-XXXV in FIG. 45. [Figure 49] FIG. 13 is a perspective view of an electronic component according to a seventh embodiment, as viewed from the planar side. [Figure 50] FIG. 50 is a perspective view of the electronic component in FIG. 49 as viewed from the back side. [Figure 51] FIG. 50 is an exploded perspective view of the electronic component of FIG. 49 . [Figure 52] FIG. 49 is a back view of the electronic component. [Figure 53] FIG. 50 is a plan view of the electronic component of FIG. 49 . [Figure 54] FIG. 50 is a side view of the electronic component of FIG. [Figure 55] Cross-sectional view of line 7-7 in Figure 53. [Figure 56] An enlarged view of the connecting conductor and its surroundings of Figure 55. [Figure 57] FIG. 56 is an enlarged view of the electrode pads and their surroundings of the first functional element of FIG. 55. [Figure 58] FIG. 57 is an enlarged view of the top surface of the connecting conductor of FIG. 56 and its surroundings. [Figure 59] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 60] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 61] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 62] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 63] An enlarged view of a portion of Figure 62. [Figure 64] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 65] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 66] An enlarged view of a portion of Figure 65. [Figure 67] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 68] Enlarged view of a portion of Figure 67. [Figure 69] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 70] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 71] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 72] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 73] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 74] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 75] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 76] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 77] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 78] FIG. 23 is an explanatory view showing an example of a step of a method for manufacturing an electronic component according to the seventh embodiment. [Figure 79] FIG. 13 is a cross-sectional view of an electronic component according to an eighth embodiment. [Figure 80] An enlarged view of a portion of Figure 79. [Figure 81] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 82]FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 83] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 84] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 85] An enlarged view of a portion of Figure 84. [Figure 86] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 87] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 88] An enlarged view of a portion of Figure 87. [Figure 89] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 90] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 91] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 92] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 93] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 94] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 95] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 96] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 97] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 98] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 99] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 100] FIG. 23 is an explanatory diagram showing an example of a step of a method for manufacturing an electronic component according to the eighth embodiment. [Figure 101] FIG. 13 is a perspective view of an electronic component according to a ninth embodiment, as viewed from the planar side. [Figure 102] FIG. 102 is a plan view of the electronic component of FIG. [Figure 103] FIG. 102 is a back view of the electronic component of FIG. [Figure 104] Cross-sectional view of line 56-56 in Figure 102. [Figure 105] Schematic circuit diagram of the electronic component of FIG. 101. [Fig. 106] FIG. 11 is a schematic circuit diagram of an electronic component according to a modified example. [Figure 107] FIG. [Figure 108] FIG. 13 is an enlarged cross-sectional view of an electrode pad of a first functional element and its periphery in a modified electronic component. [Fig. 109] FIG. [Figure 110] FIG. 11 is a plan view of an electronic component according to a modified example. [Figure 111] FIG. 11 is a cross-sectional view of an electronic component according to a modified example. [Figure 112] FIG. 11 is a cross-sectional view of an electronic component according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, the embodiments and modified examples will be described with reference to the drawings. The embodiments and modified examples shown below are merely examples of configurations and methods for embodying the technical ideas, and are not intended to limit the materials, shapes, structures, arrangements, dimensions, etc. of the components to those described below. Various modifications can be made to the following embodiments and modified examples. Furthermore, the following embodiments and modified examples can be implemented in combination with each other to the extent that there is no technical contradiction.

[0029] (First embodiment) The semiconductor device A1 of the first embodiment will be described below with reference to FIGS.

[0030] 1 and 2, the semiconductor device A1 includes a substrate 10, a wiring section 20, a bonding section 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The wiring section 20 includes main surface wiring 21 and through wiring 22.

[0031] FIG. 1 is a cross-sectional view of the semiconductor device A1 of the first embodiment. FIG. 2 is a schematic plan view of the semiconductor device A1. For ease of understanding, in FIG. 2, the sealing resin 60 is removed and the semiconductor element 50 is indicated by a two-dot chain line. FIG. 3 is a partially enlarged plan view of the semiconductor device A1, showing a part of the wiring portion 20. FIG. 4 is a partially enlarged cross-sectional view of the semiconductor device A1, showing the wiring portion 20, the joint portion 40, and a part of the semiconductor element 50. FIG. 5 shows the wiring portion 20, the joint portion 40, and a part of the semiconductor element 50 before mounting.

[0032] The semiconductor device A1 shown in these figures is a device that is surface-mounted on the circuit board of various electronic devices. For ease of explanation, the thickness direction of the substrate 10 is referred to as the thickness direction Z. Also, the direction along one side of the semiconductor device A1 that is perpendicular to the thickness direction Z (the left-right direction in the plan view) is referred to as the first direction X. Also, the direction that is perpendicular to both the thickness direction Z of the substrate 10 and the first direction X (the up-down direction in the plan view) is referred to as the second direction Y.

[0033] As shown in FIG. 2, the semiconductor device A1 has a rectangular shape when viewed in the thickness direction Z.

[0034] 2, the semiconductor element 50 has a rectangular shape when viewed in the thickness direction Z. The semiconductor element 50 of this embodiment has a square shape when viewed in the thickness direction Z.

[0035] The semiconductor element 50 is an integrated circuit (IC) such as an LSI (Large Scale Integration). The semiconductor element 50 may be a voltage control element such as an LDO (Low Drop Out), an amplifying element such as an operational amplifier, or a discrete semiconductor element such as a diode or various sensors. For example, in the case of an LSI, the element main surface 501 is a surface on which components for the function of the semiconductor element 50 are formed. The semiconductor element 50 is not limited to an element on which a plurality of components are formed, but may be an element on which a single component is formed, such as a chip capacitor or a chip inductor, or an element on which a component is formed on a base material other than a semiconductor. In this embodiment, the semiconductor element 50 is an LSI.

[0036] 2, the semiconductor device A1 has a plurality of external connection terminals 70. The external connection terminals 70 are located outside the periphery of the semiconductor element 50. The semiconductor device A1 is a packaged semiconductor device called a Fan-Out type.

[0037] As shown in FIGS. 1 and 2, the semiconductor element 50 has an element main surface 501 and an element back surface 502 facing in opposite directions in the thickness direction Z, and element side surfaces 503, 504, 505, and 506 extending in the thickness direction Z. The element side surface 503 intersects with the element main surface 501 and the element back surface 502. The element main surface 501 faces the substrate main surface 101 of the substrate 10. The element back surface 502 faces in the same direction as the substrate main surface 101 of the substrate 10. The element side surfaces 503 and 504 face in opposite directions from each other in the first direction X. The element side surfaces 505 and 506 face in opposite directions from each other in the second direction Y.

[0038] The element principal surface 501 is a surface on which components for the function of the semiconductor element 50 are formed. The semiconductor element 50 has element electrodes 55 for mounting on the element principal surface 501 side. The element electrodes 55 are mounted on the substrate 10 by the first solder layer 42 of the joint portion 40 and the second solder layer 56 of the semiconductor element 50. In other words, the semiconductor element 50 is mounted with the element principal surface 501 facing the substrate 10. Therefore, the element principal surface 501 can be said to be an element mounting surface for mounting the semiconductor element 50.

[0039] 4, the semiconductor element 50 has an element substrate 51, electrode pads 52, an insulating film 53, a protective film 54, and element electrodes 55. The electrode pads 52 are made of, for example, Al (aluminum). The insulating film 53 covers the surface of the element substrate 51 and also covers the peripheral edge of the electrode pads 52. The insulating film 53 is made of, for example, SiN. The protective film 54 covers the surface of the insulating film 53 and part of the electrode pads 52, and exposes part of the surface of the electrode pads 52 as a connection terminal. The protective film 54 is made of, for example, polyimide resin.

[0040] The element electrode 55 is connected to a connection terminal which is an exposed portion of the electrode pad 52. The element electrode 55 includes a metal layer 551, a conductive layer 552, and a barrier layer 553 as a second plating layer. The metal layer 551 is formed so as to cover the exposed portion of the electrode pad 52 and the edge of the opening of the protective film 54 which exposes the electrode pad 52. The metal layer 551 is made of, for example, titanium (Ti) / Cu, and is formed as a seed layer for forming the conductive layer 32.

[0041] The conductive layer 552 is formed to cover the lower surface of the metal layer 551. The conductive layer 32 is made of, for example, CU or a Cu alloy. The barrier layer 553 is formed to cover the lower surface of the conductive layer 552. The barrier layer 553 is made of Ni, an alloy containing Ni, or a plurality of metal layers containing Ni. For example, Ni, Pd, Au, an alloy containing two or more of these metals, or the like can be used as the barrier layer 553. A second solder layer 56 is formed on a lower surface 553d of the barrier layer 553. In other words, the lower surface 553d of the barrier layer 553 is the lower surface of the element electrode 55.

[0042] 1, the substrate 10 is a supporting member on which the semiconductor element 50 is mounted and which serves as the base of the semiconductor device A1. As shown in Fig. 2, the shape of the substrate 10 as viewed in the thickness direction Z is a rectangle in which the length of the side in the first direction X is approximately equal to the length of the side in the second direction Y. The shape of the substrate 10 and the length of each side may be changed as appropriate.

[0043] The substrate 10 has a substrate main surface 101, a substrate back surface 102, and multiple substrate side surfaces 103. The substrate main surface 101 and the substrate back surface 102 face in opposite directions in the thickness direction Z. The substrate main surface 101 is flat. The substrate back surface 102 is flat. Each substrate side surface 103 intersects with the substrate main surface 101 and the substrate back surface 102. The substrate side surface 103 faces either a first direction X or a second direction Y. Each substrate side surface 103 is flat. Each substrate side surface 103 intersects with the substrate main surface 101 and the substrate back surface 102, and in the first embodiment, is perpendicular to them.

[0044] The substrate 10 is made of, for example, a material having electrical insulation properties. Examples of the material that can be used include synthetic resins based on epoxy resins, ceramics, glass, and the like. The substrate 10 has a plurality of through holes 105 penetrating the substrate 10 from the substrate main surface 101 to the substrate rear surface 102 in the thickness direction Z. In the first embodiment, the substrate 10 has four through holes 105. The through holes 105 are provided in the vicinity of the four corners of the substrate 10, respectively. The through holes 105 are, for example, rectangular when viewed from the thickness direction Z. The shape of the through holes 105 may be circular or polygonal.

[0045] The wiring section 20 includes a plurality of main surface wirings 21 , a plurality of through wirings 22 , and a plurality of columnar wirings 27 .

[0046] Each through wiring 22 is disposed in each through hole 105. Each through wiring 22 has an upper surface 221, a lower surface 222, and a plurality of side surfaces 223. The upper surface 221 and the lower surface 222 face opposite each other in the thickness direction Z. Each side surface 223 intersects with the upper surface 221 and the lower surface 222. In the first embodiment, the upper surface 221 of the through wiring 22 is flush with the substrate main surface 101 of the substrate 10. In addition, in the first embodiment, the lower surface 222 of the through wiring 22 is flush with the substrate back surface 102 of the substrate 10. This lower surface 222 is an exposed surface exposed from the substrate back surface 102 of the substrate 10. At least one of the upper surface 221 and the lower surface 222 of the through wiring 22 may not be flush with the substrate main surface 101 and the substrate back surface 102 of the substrate 10. Furthermore, a side surface 223 of the through wire 22 is in contact with an inner wall surface 106 of the through hole 105. The through wire 22 is made of an electrically conductive material. Examples of the material that can be used for the through wire 22 include Cu and a Cu alloy.

[0047] The main surface wiring 21 is formed on the substrate main surface 101 of the substrate 10. The main surface wiring 21 is made of an electrically conductive material and is electrically connected to the through wiring 22. The main surface wiring 21 has an upper surface 211, a lower surface 212, and a side surface 213. The upper surface 211 of the main surface wiring 21 faces the same direction as the substrate main surface 101 of the substrate 10. The lower surface 212 of the main surface wiring 21 faces the same direction as the substrate rear surface 102 of the substrate 10, and faces the substrate main surface 101 of the substrate 10. The side surface 213 of the main surface wiring 21 faces the same direction as the substrate side surface 103 of the substrate 10. In addition, the side surface 213 of the main surface wiring 21 intersects with the upper surface 211 and the lower surface 212 of the main surface wiring 21.

[0048] The columnar wiring 27 extends in the thickness direction Z from the upper surface 211 of the main surface wiring 21. More specifically, the columnar wiring 27 extends from the upper surface 211 of the main surface wiring 21 to the opposite side to the through wiring 22 in the thickness direction Z. The shape of the columnar wiring 27 as viewed from the thickness direction Z is, for example, rectangular. That is, the columnar wiring 27 of this embodiment is a prism. Note that the shape of the columnar wiring 27 is not limited to this and may be a cylinder, a polygonal prism, or the like.

[0049] The columnar wiring 27 has an upper surface 271, a lower surface 272, and a plurality of side surfaces 273. The upper surface 271 and the lower surface 272 face in opposite directions in the thickness direction Z. Each side surface 273 is sandwiched between the upper surface 271 and the lower surface 272. In this embodiment, the upper surface 271 of the columnar wiring 27 is, for example, flat. The shape of the upper surface 271 can be changed arbitrarily. The lower surface 272 of the columnar wiring 27 is a surface that contacts the upper surface 211 of the main surface wiring 21. The lower surface 272 is, for example, flat. In this embodiment, one side surface 273 of the plurality of side surfaces 273 is exposed from the sealing resin 60. In FIG. 1, the side surface 273a facing the first direction X is an exposed side surface exposed from the resin side surface 603 of the sealing resin 60.

[0050] 4 and 5, the main surface wiring 21 includes a metal layer 31 and a conductive layer 32. The metal layer 31 and the conductive layer 32 are laminated on the substrate main surface 101 of the substrate 10 in this order.

[0051] The metal layer 31 is made of, for example, a Ti layer in contact with the main surface 101 of the substrate 10 and the upper surface 221 of the through wiring 22 shown in Fig. 1, and a Cu layer in contact with the Ti layer. The metal layer 31 is formed as a seed layer for forming the conductive layer 32. The metal layer 31 has an upper surface 311 and a lower surface 312 facing opposite sides to each other in the thickness direction Z.

[0052] The conductive layer 32 is formed on an upper surface 311 of the metal layer 31. The conductive layer 32 is made of Cu or a Cu alloy. The conductive layer 32 has an upper surface 321 and a lower surface 322 facing opposite sides to each other in the thickness direction Z. The thickness of the conductive layer 32 is, for example, not less than 15 μm and not more than 20 μm.

[0053] 1, 2, and 4, the bonding portion 40 is formed on the main surface wiring 21. The bonding portion 40 is electrically connected to the wiring portion 20. The bonding portion 40 bonds the semiconductor element 50 to the wiring portion 20.

[0054] The joint 40 has a plating layer 41 as a first plating layer formed on the upper surface 321 of the conductive layer 32 of the main surface wiring 21, and a first solder layer 42 formed on the upper surface of the plating layer 41. The semiconductor element 50 has an element electrode 55 formed on the element main surface 501, and a second solder layer 56 formed on the lower surface of the element electrode 55. The joint 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed from the thickness direction Z. The first solder layer 42 and the second solder layer 56 are joined to each other by a reflow process in the process of mounting the semiconductor element 50 on the substrate 10, and form an integral solder layer 45. That is, the semiconductor element 50 is connected to the main surface wiring 21 by the solder layer 45 and mounted on the substrate 10.

[0055] FIG. 5 shows the joint 40, the element electrode 55 of the semiconductor element 50, and the second solder layer 56 before the reflow process.

[0056] The joint portion 40 includes a plating layer 41 and a first solder layer 42. The plating layer 41 and the first solder layer 42 are laminated in this order on the main surface wiring 21 of the wiring portion 20. The plating layer 41 is made of a conductive metal material. For example, the plating layer 41 is made of Ni (nickel). The first solder layer 42 is made of Sn (tin) or an alloy containing Sn. This alloy is, for example, a Sn-Ag (silver) based alloy, a Sn-Sb (antimony) based alloy, or the like.

[0057] As shown in FIGS. 3, 4, and 5, the plating layer 41 is formed on the upper surface 321 of the conductive layer 32 constituting the wiring portion 20. The plating layer 41 has an upper surface 411, a lower surface 412, and a side surface 413. The upper surface 411 faces the same direction as the upper surface 321 of the conductive layer 32. The lower surface 412 faces the upper surface 321 of the conductive layer 32. The lower surface 412 is in contact with the upper surface 321 of the conductive layer 32. The side surface 413 intersects with the upper surface 411 and the lower surface 412. An oxide film may be formed on the side surface 413. The thickness T1 of the plating layer 41 is, for example, 3 μm or more and 5 μm or less.

[0058] As shown in FIG. 5, the first solder layer 42 has an upper surface 421, a lower surface 422, and a side surface 423. The upper surface 421 and the lower surface 422 face opposite each other in the thickness direction Z. The side surface 423 intersects with the upper surface 421 and the lower surface 422. The lower surface 422 of the first solder layer 42 contacts the upper surface 411 of the plating layer 41. When viewed from the thickness direction Z, the first solder layer 42 is formed to have the same size as the plating layer 41. The first solder layer 42 is formed to a thickness equal to or less than the thickness T1 of the plating layer 41. The thickness of the first solder layer 42 is preferably, for example, 1 μm or more and 5 μm or less. In the first solder layer 42, the aspect ratio in a cross section perpendicular to the substrate main surface 101 of the substrate 10, for example, a cross section along the first direction X, is preferably, for example, 40 or more and 80 or less. The aspect ratio of the first solder layer 42 is the ratio of the length to the width of a rectangle including the first solder layer 42, and is the ratio (L1 / T2) of the length L1 of the first solder layer 42 in the first direction X to the thickness T2 of the first solder layer 42.

[0059] FIG. 4 shows the solder layer 45 after the reflow process.

[0060] The solder layer 45 has an upper surface 451, a lower surface 452, and a side surface 453. The upper surface 451 and the lower surface 452 face in opposite directions in the thickness direction Z. The side surface 453 intersects with the upper surface 451 and the lower surface 452. The upper surface 451 of the solder layer 45 contacts the lower surface of the element electrode 55, that is, the lower surface 553d of the barrier layer 553. The lower surface 452 of the solder layer 45 contacts the upper surface 411 of the plating layer 41. The solder layer 45 is formed in a roughly trapezoidal shape in a cross section perpendicular to the substrate main surface 101. More specifically, the side surface of the solder layer 45 extends from the outer peripheral end of the upper surface 411 of the plating layer 41 to the outer peripheral end of the element electrode 55, more specifically, to the outer peripheral end of the lower surface 553d of the barrier layer 553. Furthermore, the side surface 453 of the solder layer 45 is inclined so that the width in the first direction X and the width in the second direction Y become larger toward the substrate 10.

[0061] 1, the sealing resin 60 is formed so as to contact the substrate main surface 101 of the substrate 10 and cover the semiconductor element 50. More specifically, the sealing resin 60 covers the element main surface 501, the element back surface 502, and the element side surface 503 of the semiconductor element 50. Furthermore, in the first embodiment, the sealing resin 60 covers the main surface wiring 21 and the bonding portion 40.

[0062] The sealing resin 60 overlaps with the substrate 10 when viewed from the thickness direction Z. The sealing resin 60 has a resin upper surface 601 facing in the same direction as the substrate main surface 101 of the substrate 10, and a resin side surface 603 facing in the same direction as the substrate side surface 103.

[0063] The sealing resin 60 has a first resin portion 60A which is a portion on the side of the substrate 10 in the thickness direction Z, and a second resin portion 60B on the side of the resin upper surface 601. The first resin portion 60A has a first resin side surface 603a which constitutes a part of the resin side surface 603, and the second resin portion 60B has a second resin side surface 603b which constitutes a part of the resin side surface 603. When viewed from the thickness direction Z, the first resin portion 60A has the same size as the substrate 10. When viewed from the thickness direction Z, the second resin portion 60B is formed to be larger than the first resin portion 60A. The second resin side surface 603b is located outside the first resin side surface 603a. In this way, the sealing resin 60 has a step 61 which is recessed inward of the sealing resin 60 due to the difference in size between the first resin portion 60A and the second resin portion 60B. As shown in FIG. 2, the step 61 is provided over the entire circumference of the sealing resin 60.

[0064] The sealing resin 60 is made of, for example, an electrically insulating resin. For example, a synthetic resin containing an epoxy resin as a main component can be used as the resin. The sealing resin 60 is colored, for example, black.

[0065] The external connection terminal 70 is formed so as to cover the wiring portion 20 exposed from the substrate 10 and the sealing resin 60. The external connection terminal 70 has a first conductive film 71 covering the lower surface 222 of the through wiring 22, and a second conductive film 72 covering the side surface 223 of the through wiring 22, the side surface 213 of the main surface wiring 21, and the side surface 273a of the columnar wiring 27. The external connection terminal 70 having the first conductive film 71 and the second conductive film 72 becomes the external connection terminal of the semiconductor device A1. The external connection terminal 70 is composed of, for example, a plurality of metal layers stacked on each other. The metal layer is, for example, a Ni layer, a Pd (palladium) layer, and an Au (gold) layer. The material of the external connection terminal 70 is not limited, but may be, for example, a Ni layer and an Au layer stacked, or may be Sn.

[0066] When the semiconductor device A1 is mounted on a mounting board, the solder that connects the external connection terminal 70 to the connection pad of the mounting board is interposed between the first conductive film 71 and the connection pad, and also adheres to the second conductive film 72. In other words, the solder that has become liquid phase by the reflow process creeps up the second conductive film 72 and forms a solder fillet between the second conductive film 72 and the connection pad. In this way, the semiconductor device A1 makes it easier to form the solder fillet. The solder fillet increases the solder joint area, and the connection strength can be further increased. The solder fillet also allows the state of the soldering of the semiconductor device A1 to be confirmed from the outside.

[0067] Fig. 3 shows a semiconductor element 50 and a part of the main surface wiring 21 in the semiconductor device A1 of this embodiment. In Fig. 3, the semiconductor element 50 and the element electrodes 55 are shown by dashed lines. The main surface wiring 21 is connected to the element electrodes 55 of the semiconductor element 50 and extends from the element electrodes 55 toward the outside of the semiconductor element 50.

[0068] The joint 40 consisting of the plating layer 41 and the first solder layer 42 has end sides 40a, 40c extending in the first direction X and end sides 40b, 40d extending in the second direction Y. The element electrode 55 is formed in a rectangular shape when viewed from the thickness direction Z, and has side sides 55a, 55c along the first direction X and side sides 55b, 55d along the second direction Y.

[0069] The distance L2a from the side surface 55a of the element electrode 55 to the edge 40a of the joint 40 is, for example, 4 μm or more and 10 μm or less. The distance L2b from the side surface 55b of the element electrode 55 to the edge 40b of the joint 40 is, for example, 4 μm or more and 10 μm or less. The distance L2c from the side surface 55c of the element electrode 55 to the edge 40c of the joint 40 is, for example, 4 μm or more and 10 μm or less. The distance L2d from the side surface 55d of the element electrode 55 to the edge 40d of the joint 40 is, for example, 4 μm or more and 10 μm or less.

[0070] In the main surface wiring 21, the ends 40b to 40d of the joint 40, i.e., the ends of the plating layer 41 and the first solder layer 42, are located inside the main surface wiring 21 with respect to the inner end side 21a of the semiconductor element 50 and the side sides 21b, 21c on both sides of the end side 21a and intersecting with the end side 21a. The distance L3a between the end side 21a and the joint 40 is, for example, 0.5 μm or more and 1.0 μm or less. The distance L3b between the side side 21b and the joint 40 is, for example, 0.5 μm or more and 1.0 μm or less. Moreover, the distance L3c between the side side 21c and the joint 40 is, for example, 0.5 μm or more and 1.0 μm or less.

[0071] (manufacturing process) Next, an example of a manufacturing process for the above-mentioned semiconductor device A1 will be described.

[0072] First, a support substrate is prepared. The support substrate is made of, for example, a single crystal material of Si. Note that, as the support substrate, a substrate made of a synthetic resin material such as epoxy resin may be used. A terminal pillar that becomes the through wiring 22 is formed on the upper surface of the support substrate. The terminal pillar is made of, for example, Cu or a Cu alloy. The terminal pillar is made of, for example, a seed layer formed on the upper surface of the support substrate and a plating metal formed on the upper surface of the seed layer. Note that, the terminal pillar may be formed of a columnar material of Cu.

[0073] Next, a base material is formed in contact with the upper surface of the support substrate and covering the terminal pillar. The base material is formed so as to cover the upper surface of the terminal pillar. The material constituting the substrate 10 shown in FIG. 1 can be used as the material of this base material. In this embodiment, a synthetic resin containing an epoxy resin or the like as a main component can be used as the material of the base material.

[0074] Next, the substrate and a portion of the terminal pillar are ground to form the through wiring 22 exposed on the upper surface of the substrate and the upper surface 221 of the through wiring 22. The substrate is to become the substrate 10 shown in Fig. 1. In grinding the substrate, the substrate is made to have the same thickness as the substrate 10.

[0075] Next, the main surface wiring 21 is formed on the upper surface of the base material and the upper surface 221 of the through wiring 22. The main surface wiring 21 includes a metal layer 31 and a conductive layer 32. First, the metal layer 31 is formed by, for example, a sputtering method. For example, the metal layer 31 including a Ti layer and a Cu layer is formed by forming a Ti layer on the upper surface of the base material and the upper surface 221 of the through wiring 22, and then forming a Cu layer in contact with the Ti layer. Next, for example, by an electrolytic plating method using the metal layer 31 as a conductive path, a plating metal is deposited on the surface of the metal layer 31 to form the conductive layer 32.

[0076] Next, a joint 40 is formed on the main surface wiring 21. The joint 40 includes a plating layer 41 and a first solder layer 42. First, the plating layer 41 is formed on the main surface wiring 21 by, for example, electrolytic plating. Next, the first solder layer 42 is formed on the plating layer 41 by, for example, electrolytic plating.

[0077] Further, the pillar wiring 27 is formed on the main surface wiring 21. The pillar wiring 27 includes, for example, a seed layer and a plating layer. The seed layer is composed of, for example, a first layer whose main component is Ti and a second layer whose main component is Cu. The plating layer is, for example, composed mainly of Cu. First, the seed layer is formed on the main surface wiring 21 by, for example, a sputtering method, and then the plating layer is formed by, for example, an electrolytic plating method using the seed layer as a conductive path, thereby forming the pillar wiring 27.

[0078] Next, the semiconductor element 50 is mounted. The semiconductor element 50 is mounted by flip chip bonding (FCB). For example, a flip chip bonder is used to pin-transfer-apply flux to the second solder layer 56 of the semiconductor element 50, and then flip chip mounting is performed. This temporarily attaches the semiconductor element 50 to the joint 40. Thereafter, the first solder layer 42 of the joint 40 and the second solder layer 56 of the semiconductor element 50 are brought into a liquid phase state by reflow, and then the first solder layer 42 and the second solder layer 56 are solidified by cooling to form a solder layer 45. The semiconductor element 50 is mounted on the substrate 10 by this solder layer 45.

[0079] Next, a resin layer is formed to cover the upper surface of the base material, the wiring portion 20, and the semiconductor element 50. The resin layer is a member that becomes the sealing resin 60 shown in Fig. 1. The resin layer is, for example, a synthetic resin whose main material is epoxy resin. For example, the resin layer is formed by transfer molding.

[0080] Next, the support substrate is removed by, for example, grinding. Alternatively, a method may be used in which a release film is formed in advance between the support substrate and the base material, and the support substrate is removed by a release method.

[0081] Next, grooves are formed from the base material side to partway through the resin layer using a dicing blade or the like, and the side surfaces 223 of the through wirings 22, the side surfaces 213 of the main surface wirings 21, and the side surfaces 273a of the columnar wirings 27 are exposed in the grooves.

[0082] Next, the external connection terminals 70 are formed on the surfaces of the through wiring 22, the main surface wiring 21, and the columnar wiring 27 exposed from the base material and the resin layer. The external connection terminals 70 are made of, for example, a plated metal. For example, the external connection terminals 70 are formed by precipitating plated metals, such as Ni, Pd, and Au, in this order, by electroless plating. The structure and method of forming the external connection terminals 70 are not limited.

[0083] Next, a dicing tape is applied to the resin layer, and the substrate and the resin layer are cut to separate the semiconductor element 50 into individual pieces each consisting of a single unit. For example, a dicing blade is used to cut from the substrate to the dicing tape, separating the substrate and the resin layer. Each individual piece is a semiconductor device A1 including a substrate 10 and a sealing resin 60.

[0084] (action) Next, the operation of the above-mentioned semiconductor device A1 will be described.

[0085] The semiconductor device A1 has a joint 40 on the upper surface 211 of the main surface wiring 21. The joint 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The joint 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed from the thickness direction Z. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 by a reflow process to form a solder layer 45. In this reflow process, the molten second solder layer 56 is fused with the first solder layer 42, so that it is difficult for the second solder layer 56 to flow outward beyond the plating layer 41. This makes it possible to suppress the flow of solder during the reflow process when mounting the semiconductor element 50.

[0086] The joint 40 has a plating layer 41 on the upper surface of the main surface wiring 21, and a first solder layer 42 on the plating layer 41. The main surface wiring 21 is made of Cu and a Cu alloy, and the first solder layer 42 is made of SnAg. The plating layer 41 is a barrier metal, and therefore prevents alloying of the Cu of the main surface wiring 21 with the Sn of the first solder layer 42 and the second solder layer 56. This makes it possible to suppress the occurrence of voids (Kirkendall voids) between the SnAg and Cu.

[0087] The joint 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The first solder layer 42 is joined to a second solder layer 56 of the semiconductor element 50 to form a solder layer 45. An upper surface 411 of the plating layer 41 may have irregularities due to the formation of the main surface wiring 21 and the plating layer 41. When the second solder layer 56 is directly joined to the plating layer 41, there is a risk that voids (vacancies) will occur in the solder layer due to the roughness of the upper surface 211 of the main surface wiring 21 and the upper surface 411 of the plating layer 41. In response to this, the first solder layer 42 formed on the plating layer 41 is melted by a reflow process before mounting the semiconductor element 50, so that the rough surface is smoothed. This smoothing can suppress the occurrence of voids when the first solder layer 42 and the second solder layer 56 are joined. First solder layer 42 has a thickness T2 that is small relative to the size in a direction parallel to upper surface 411 of plating layer 41 on which first solder layer 42 is formed. In other words, because first solder layer 42 has a small aspect ratio, solder flow in a reflow process before mounting semiconductor element 50 can be suppressed.

[0088] As described above, according to the present embodiment, the following effects are achieved.

[0089] (1-1) The semiconductor device A1 has a joint 40 on the upper surface 211 of the main surface wiring 21. The joint 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The joint 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed from the thickness direction Z. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 by a reflow process to form a solder layer 45. In this reflow process, the molten second solder layer 56 fuses with the first solder layer 42 and is therefore less likely to flow outward beyond the plating layer 41. This makes it possible to suppress the flow of solder during the reflow process when the semiconductor element 50 is mounted.

[0090] (1-2) First solder layer 42 has a thickness T2 that is small relative to the size in a direction parallel to upper surface 411 of plating layer 41 on which first solder layer 42 is formed. In other words, because first solder layer 42 has a small aspect ratio, solder flow in a reflow process before mounting semiconductor element 50 can be suppressed.

[0091] (1-4) The joint 40 has a plating layer 41 on the upper surface of the main surface wiring 21, and a first solder layer 42 on the plating layer 41. The main surface wiring 21 is made of Cu and a Cu alloy, and the first solder layer 42 is made of SnAg. The plating layer 41 is a barrier metal, and prevents alloying of the Cu of the main surface wiring 21 with the Sn of the first solder layer 42 and the second solder layer 56. This makes it possible to suppress the occurrence of voids (Kirkendall voids) between the SnAg and Cu.

[0092] (1-5) The joint 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 to form a solder layer 45. The upper surface 411 of the plating layer 41 may have irregularities due to the formation of the main surface wiring 21 and the plating layer 41. When the second solder layer 56 is directly joined to the plating layer 41, there is a risk that voids (vacancies) will occur in the solder layer due to the roughness of the upper surface 211 of the main surface wiring 21 and the upper surface 411 of the plating layer 41. In response to this, the first solder layer 42 formed on the plating layer 41 is melted by a reflow process before mounting the semiconductor element 50, so that the rough surface is smoothed. This smoothing can suppress the occurrence of voids when the first solder layer 42 and the second solder layer 56 are joined.

[0093] (1-6) When the semiconductor device A1 is mounted on a mounting board, the solder that connects the external connection terminal 70 to the connection pad of the mounting board is interposed between the first conductive film 71 and the connection pad, and also adheres to the second conductive film 72. In other words, the solder that has become liquid phase by the reflow process creeps up the second conductive film 72 and forms a solder fillet between the second conductive film 72 and the connection pad. This solder fillet increases the solder joint area, and the connection strength can be further increased. In addition, the solder fillet allows the state of soldering of the semiconductor device A1 to be confirmed from outside.

[0094] Second embodiment A semiconductor device A2 according to the second embodiment will be described below with reference to Figures 6 to 8. In the second embodiment, the same members as those in the first embodiment will be described using the same reference numerals.

[0095] 6 and 7, the semiconductor device A2 includes a substrate 10, a wiring section 20, a bonding section 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The wiring section 20 includes main surface wiring 21 and through wiring 22.

[0096] Fig. 6 is a cross-sectional view of the semiconductor device A2 of the second embodiment. Fig. 7 is a schematic plan view of the semiconductor device A2. For ease of understanding, in Fig. 7, the sealing resin 60 is removed and the semiconductor element 50 is indicated by a two-dot chain line. Fig. 8 is a partially enlarged plan view of the semiconductor device A2, showing a part of the wiring portion 20.

[0097] The semiconductor device A2 shown in these figures is a device that is surface-mounted on the circuit board of various electronic devices. For ease of explanation, the thickness direction of the substrate 10 is referred to as the thickness direction Z. Also, the direction along one side of the semiconductor device A2 that is perpendicular to the thickness direction Z (the left-right direction in the plan view) is referred to as the first direction X. Also, the direction that is perpendicular to both the thickness direction Z of the substrate 10 and the first direction X (the up-down direction in the plan view) is referred to as the second direction Y.

[0098] As shown in FIG. 7, the semiconductor device A2 has a rectangular shape when viewed in the thickness direction Z.

[0099] 7, the semiconductor element 50 has a rectangular shape when viewed in the thickness direction Z. The semiconductor element 50 has a rectangular shape that is longer in the second direction Y than in the first direction X.

[0100] The semiconductor element 50 is an integrated circuit (IC) such as an LSI (Large Scale Integration). The semiconductor element 50 may be a voltage control element such as an LDO (Low Drop Out), an amplifying element such as an operational amplifier, or a discrete semiconductor element such as a diode or various sensors. For example, in the case of an LSI, the element main surface 501 is a surface on which components for the function of the semiconductor element 50 are formed. The semiconductor element 50 is not limited to an element on which a plurality of components are formed, but may be an element on which a single component is formed, such as a chip capacitor or a chip inductor, or an element on which a component is formed on a base material other than a semiconductor. In this embodiment, the semiconductor element 50 is an LSI.

[0101] 7, the semiconductor device A2 has a plurality of external connection terminals 70. The external connection terminals 70 are located outside the periphery of the semiconductor element 50. The semiconductor device A2 is a packaged semiconductor device called a Fan-Out type.

[0102] 6 and 7, the semiconductor element 50 has an element main surface 501 and an element back surface 502 facing opposite directions in the thickness direction Z, and an element side surface 503 extending in the thickness direction Z. The element side surface 503 intersects with the element main surface 501 and the element back surface 502. The element main surface 501 faces the substrate main surface 101 of the substrate 10. The element back surface 502 faces in the same direction as the substrate main surface 101 of the substrate 10.

[0103] The element principal surface 501 is a surface on which components for the function of the semiconductor element 50 are formed. The semiconductor element 50 has element electrodes 55 for mounting on the element principal surface 501 side. The element electrodes 55 are mounted on the substrate 10 by the first solder layer 42 of the joint portion 40 and the second solder layer 56 of the semiconductor element 50. In other words, the semiconductor element 50 is mounted with the element principal surface 501 facing the substrate 10. Therefore, the element principal surface 501 can be said to be an element mounting surface for mounting the semiconductor element 50.

[0104] As shown in Fig. 6, the substrate 10 is a support member on which the semiconductor element 50 is mounted and which serves as the base of the semiconductor device A2. As shown in Fig. 7, the shape of the substrate 10 as viewed in the thickness direction Z is a rectangle in which the length of the side in the first direction X is approximately equal to the length of the side in the second direction Y. The shape of the substrate 10 and the length of each side may be changed as appropriate.

[0105] The substrate 10 has a substrate main surface 101, a substrate back surface 102, and multiple substrate side surfaces 103. The substrate main surface 101 and the substrate back surface 102 face in opposite directions in the thickness direction Z. The substrate main surface 101 is flat. The substrate back surface 102 is flat. Each substrate side surface 103 is sandwiched between the substrate main surface 101 and the substrate back surface 102. The substrate side surface 103 faces either a first direction X or a second direction Y. Each substrate side surface 103 is flat. Each substrate side surface 103 intersects with the substrate main surface 101 and the substrate back surface 102, and in this embodiment, is perpendicular to them.

[0106] The substrate 10 is made of, for example, a material having electrical insulation properties. Examples of the material that can be used include synthetic resins based on epoxy resins, ceramics, glass, and the like. The substrate 10 has a plurality of through holes 105 penetrating the substrate 10 from the substrate main surface 101 to the substrate rear surface 102 in the thickness direction Z. In this embodiment, the substrate 10 has four through holes 105. The through holes 105 are provided in the vicinity of the four corners of the substrate 10, respectively. The through holes 105 are, for example, rectangular when viewed from the thickness direction Z. The shape of the through holes 105 may be circular or polygonal.

[0107] The wiring section 20 includes a plurality of main surface wirings 21 and a plurality of through wirings 22 .

[0108] Each through wiring 22 is disposed in each through hole 105. Each through wiring 22 has an upper surface 221, a lower surface 222, and a plurality of side surfaces 223. The upper surface 221 and the lower surface 222 face opposite each other in the thickness direction Z. Each side surface 223 is sandwiched between the upper surface 221 and the lower surface 222. In this embodiment, the upper surface 221 of the through wiring 22 is flush with the substrate main surface 101 of the substrate 10. In addition, in this embodiment, the lower surface 222 of the through wiring 22 is flush with the substrate back surface 102 of the substrate 10. This lower surface 222 is an exposed surface exposed from the substrate back surface 102 of the substrate 10. At least one of the upper surface 221 and the lower surface 222 of the through wiring 22 may not be flush with the substrate main surface 101 and the substrate back surface 102 of the substrate 10. Furthermore, a side surface 223 of the through wire 22 is in contact with an inner wall surface 106 of the through hole 105. The through wire 22 is made of an electrically conductive material. Examples of the material that can be used for the through wire 22 include Cu and a Cu alloy.

[0109] The external connection terminal 70 is formed on the rear surface 102 of the substrate 10. The external connection terminal 70 is formed so as to cover the lower surface 222 of the through-hole 22. The external connection terminal 70 extends from the through-hole 22 along the rear surface 102 of the substrate, and is formed so as to cover the rear surface 102 of the substrate around the through-hole 105. The external connection terminal 70 is composed of, for example, a plurality of metal layers stacked on each other. The metal layers are, for example, a Ni layer, a Pd (palladium) layer, and a Au (gold) layer. The material of the external connection terminal 70 is not limited, and may be, for example, a stack of Ni layers and Au layers, or may be Sn.

[0110] The main surface wiring 21 is formed on the substrate main surface 101 of the substrate 10. The main surface wiring 21 is made of an electrically conductive material and is electrically connected to the through wiring 22. The main surface wiring 21 has an upper surface 211, a lower surface 212, and a side surface 213. The upper surface 211 of the main surface wiring 21 faces the same direction as the substrate main surface 101 of the substrate 10. The lower surface 212 of the main surface wiring 21 faces the same direction as the substrate rear surface 102 of the substrate 10, and faces the substrate main surface 101 of the substrate 10. The side surface 213 of the main surface wiring 21 faces the same direction as the substrate side surface 103 of the substrate 10. In addition, the side surface 213 of the main surface wiring 21 intersects with the upper surface 211 and the lower surface 212 of the main surface wiring 21.

[0111] As shown in FIG. 7, the main surface wiring 21 has individual first wiring portions 23 each connected to an element electrode 55 of the semiconductor element 50, and a planar second wiring portion 24 connected to a plurality of element electrodes 55.

[0112] The first wiring portion 23 and the second wiring portion 24 are formed so as to extend from a portion overlapping with the element electrode 55 of the semiconductor element 50 to a portion overlapping with the corresponding through wiring 22 when viewed from the thickness direction Z. In other words, the first wiring portion 23 and the second wiring portion 24 extend from the semiconductor element 50 toward the outside of the semiconductor element 50.

[0113] 6 and 7, the bonding portion 40 is formed on the main surface wiring 21. The bonding portion 40 is electrically connected to the wiring portion 20. The bonding portion 40 bonds the semiconductor element 50 to the wiring portion 20.

[0114] The joint 40 has a plating layer 41 as a first plating layer formed on the upper surface 321 of the conductive layer 32 of the main surface wiring 21, and a first solder layer 42 formed on the upper surface of the plating layer 41. The semiconductor element 50 has an element electrode 55 formed on the element main surface 501, and a second solder layer 56 formed on the lower surface of the element electrode 55. The joint 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed from the thickness direction Z. The first solder layer 42 and the second solder layer 56 are joined to each other by a reflow process in the process of mounting the semiconductor element 50 on the substrate 10, and form an integral solder layer 45. That is, the semiconductor element 50 is connected to the main surface wiring 21 by the solder layer 45 and mounted on the substrate 10.

[0115] As shown in FIG. 8, the plating layer 41 is formed on the upper surface 321 of the conductive layer 32 constituting the wiring portion 20. The plating layer 41 has an upper surface 411, a lower surface 412, and a side surface 413. The upper surface 411 faces the same direction as the upper surface 321 of the conductive layer 32. The lower surface 412 faces the upper surface 321 of the conductive layer 32. The lower surface 412 is in contact with the upper surface 321 of the conductive layer 32. The side surface 413 intersects with the upper surface 411 and the lower surface 412. An oxide film may be formed on the side surface 413. The thickness T1 of the plating layer 41 is, for example, 3 μm or more and 5 μm or less.

[0116] 6, the sealing resin 60 is formed so as to contact the substrate main surface 101 of the substrate 10 and cover the semiconductor element 50. More specifically, the sealing resin 60 covers the element main surface 501, element back surface 502, and element side surface 503 of the semiconductor element 50. Furthermore, in this embodiment, the sealing resin 60 covers the main surface wiring 21 and the bonding portion 40.

[0117] The sealing resin 60 overlaps with the substrate 10 when viewed from the thickness direction Z. The sealing resin 60 has a resin upper surface 601 facing in the same direction as the substrate main surface 101 of the substrate 10, and a resin side surface 603 facing in the same direction as the substrate side surface 103.

[0118] The sealing resin 60 is made of, for example, an electrically insulating resin. For example, a synthetic resin containing an epoxy resin as a main component can be used as the resin. The sealing resin 60 is colored, for example, black.

[0119] Fig. 8 shows a semiconductor element 50 and a part of the main surface wiring 21 in the semiconductor device A2 of this embodiment. In Fig. 8, the semiconductor element 50 and the element electrodes 55 are indicated by dashed lines. The main surface wiring 21 is connected to the element electrodes 55 of the semiconductor element 50 and extends from the element electrodes 55 toward the outside of the semiconductor element 50.

[0120] The joint 40 consisting of the plating layer 41 and the first solder layer 42 has end sides 40a, 40c extending in the first direction X and end sides 40b, 40d extending in the second direction Y. The element electrode 55 is formed in a rectangular shape when viewed from the thickness direction Z, and has side sides 55a, 55c along the first direction X and side sides 55b, 55d along the second direction Y.

[0121] The distance L2a from the side surface 55a of the element electrode 55 to the edge 40a of the joint 40 is, for example, 4 μm or more and 10 μm or less. The distance L2b from the side surface 55b of the element electrode 55 to the edge 40b of the joint 40 is, for example, 4 μm or more and 10 μm or less. The distance L2c from the side surface 55c of the element electrode 55 to the edge 40c of the joint 40 is, for example, 4 μm or more and 10 μm or less. The distance L2d from the side surface 55d of the element electrode 55 to the edge 40d of the joint 40 is, for example, 4 μm or more and 10 μm or less.

[0122] In the first wiring portion 23, the ends 40b to 40d of the joint 40, i.e., the ends of the plating layer 41 and the first solder layer 42, are located inside the main surface wiring 21 with respect to the inner end side 23a of the semiconductor element 50 and the sides 23b, 23c on both sides of the end side 23a and intersecting with the end side 23a. The distance L3a between the end side 23a and the joint 40 is, for example, 0.5 μm or more and 1.0 μm or less. The distance L3b between the side 23b and the joint 40 is, for example, 0.5 μm or more and 1.0 μm or less. The distance L3c between the side 23c and the joint 40 is, for example, 0.5 μm or more and 1.0 μm or less.

[0123] The second wiring part 24 is provided with a joint 40 for each element electrode 55. That is, the multiple joints 40 formed on the upper surface of one second wiring part 24 are formed apart from each other. In the second wiring part 24 provided with the multiple joints 40, the positional relationship between each joint 40 and the element electrode 55 connected to each joint 40 is the same as the positional relationship in the first wiring part 23 described above. In addition, the positional relationship between the end side 24a and the side sides 24b, 24c of the second wiring part 24 and the joints 40 is the same as the positional relationship in the first wiring part 23 described above. In this embodiment, the multiple joints 40 are provided along the end side 24a of the second wiring part 24, but the position at which the joints 40 are provided can be appropriately changed depending on the semiconductor element to be mounted.

[0124] (manufacturing process) Next, an example of a manufacturing process for the above-mentioned semiconductor device A2 will be described.

[0125] First, a support substrate is prepared. The support substrate is made of, for example, a single crystal material of Si. Note that, as the support substrate, a substrate made of a synthetic resin material such as epoxy resin may be used. A terminal pillar that becomes the through wiring 22 is formed on the upper surface of the support substrate. The terminal pillar is made of, for example, Cu or a Cu alloy. The terminal pillar is made of, for example, a seed layer formed on the upper surface of the support substrate and a plating metal formed on the upper surface of the seed layer. Note that, the terminal pillar may be formed of a columnar material of Cu.

[0126] Next, a base material is formed in contact with the upper surface of the support substrate and covering the terminal pillar. The base material is formed so as to cover the upper surface of the terminal pillar. The material constituting the substrate 10 shown in FIG. 6 can be used as the material of this base material. In this embodiment, the material of the base material can be a synthetic resin mainly composed of an epoxy resin or the like.

[0127] Next, the substrate and a portion of the terminal pillar are ground to form the through wiring 22 exposed on the upper surface of the substrate and the upper surface 221 of the through wiring 22. The substrate is to become the substrate 10 shown in Fig. 6. In grinding the substrate, the substrate is made to have the same thickness as the substrate 10.

[0128] Next, the main surface wiring 21 is formed on the upper surface of the base material and the upper surface 221 of the through wiring 22. The main surface wiring 21 includes a metal layer 31 and a conductive layer 32. First, the metal layer 31 is formed by, for example, a sputtering method. For example, the metal layer 31 including a Ti layer and a Cu layer is formed by forming a Ti layer on the upper surface of the base material and the upper surface 221 of the through wiring 22, and then forming a Cu layer in contact with the Ti layer. Next, for example, by an electrolytic plating method using the metal layer 31 as a conductive path, a plating metal is deposited on the surface of the metal layer 31 to form the conductive layer 32.

[0129] Next, a joint 40 is formed on the main surface wiring 21. The joint 40 includes a plating layer 41 and a first solder layer 42. First, the plating layer 41 is formed on the main surface wiring 21 by, for example, electrolytic plating. Next, the first solder layer 42 is formed on the plating layer 41 by, for example, electrolytic plating.

[0130] Next, the semiconductor element 50 is mounted. The semiconductor element 50 is mounted by flip chip bonding (FCB). For example, a flip chip bonder is used to pin-transfer-apply flux to the second solder layer 56 of the semiconductor element 50, and then flip chip mounting is performed. This temporarily attaches the semiconductor element 50 to the joint 40. Thereafter, the first solder layer 42 of the joint 40 and the second solder layer 56 of the semiconductor element 50 are brought into a liquid phase state by reflow, and then the first solder layer 42 and the second solder layer 56 are solidified by cooling to form a solder layer 45. The semiconductor element 50 is mounted on the substrate 10 by this solder layer 45.

[0131] Next, a resin layer is formed to cover the upper surface of the base material, the wiring portion 20, and the semiconductor element 50. The resin layer is a member that becomes the sealing resin 60 shown in Fig. 6. The resin layer is, for example, a synthetic resin whose main material is epoxy resin. For example, the resin layer is formed by transfer molding.

[0132] Next, the support substrate is removed by, for example, grinding. Alternatively, a method may be used in which a release film is formed in advance between the support substrate and the base material, and the support substrate is removed by a release method.

[0133] Next, the external connection terminal 70 is formed on the surface of the through wiring 22 exposed from the base material (the lower surface 222 shown in FIG. 6). The external connection terminal 70 is made of, for example, a plated metal. For example, the external connection terminal 70 is formed by precipitating plated metals, such as Ni, Pd, and Au, in this order, by electroless plating. Note that the structure and method of forming the external connection terminal 70 are not limited.

[0134] Next, a dicing tape is applied to the resin layer, and the substrate and the resin layer are cut to separate the semiconductor element 50 into individual pieces, each of which is a unit. For example, a dicing blade is used to cut from the substrate side to the dicing tape, and the substrate and the resin layer are separated. Each individual piece is a semiconductor device A2 including a substrate 10 and a sealing resin 60.

[0135] (action) Next, the operation of the semiconductor device A2 will be described.

[0136] The semiconductor device A2 has a joint 40 on the upper surface 211 of the main surface wiring 21. The joint 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The joint 40 is formed larger than the element electrode 55 of the semiconductor element 50 when viewed from the thickness direction Z. The first solder layer 42 is joined to the second solder layer 56 of the semiconductor element 50 by a reflow process to form a solder layer 45. In this reflow process, the molten second solder layer 56 is fused with the first solder layer 42, so that it is difficult for the second solder layer 56 to flow outward beyond the plating layer 41. This makes it possible to suppress the flow of solder during the reflow process when mounting the semiconductor element 50.

[0137] As shown in FIG. 8, a plurality of joints 40 formed on the upper surface 211 of one main surface wiring 21 (second wiring portion 24) are formed apart from each other. Each joint 40 is connected to an element electrode 55 of a semiconductor element 50. Each joint 40 suppresses the outflow of solder. Therefore, in the plurality of element electrodes 55 connected to one main surface wiring 21 (second wiring portion 24), a solder layer 45 is formed between each element electrode 55 and the joint 40, so that the amount of solder is secured for each element electrode 55. This ensures the electrical connection between each element electrode 55 and one main surface wiring 21 (second wiring portion 24).

[0138] For example, when one joint 40 is provided for a plurality of element electrodes 55, solder may concentrate near a certain element electrode 55, causing a shortage of solder at the other element electrodes 55. When there is a shortage of solder in this way, there is a risk that the element electrode 55 will not be connected to the main surface wiring 21. In contrast, in this embodiment, each element electrode 55 can be connected to one main surface wiring 21.

[0139] The joint 40 has a plating layer 41 on the upper surface of the main surface wiring 21, and a first solder layer 42 on the plating layer 41. The main surface wiring 21 is made of Cu and a Cu alloy, and the first solder layer 42 is made of SnAg. The plating layer 41 is a barrier metal, and prevents alloying of the Cu of the main surface wiring 21 with the Sn of the first solder layer 42 and the second solder layer 56. This makes it possible to suppress the occurrence of voids (Kirkendall voids) between the SnAg and Cu.

[0140] The joint 40 has a plating layer 41 and a first solder layer 42 on the plating layer 41. The first solder layer 42 is joined to a second solder layer 56 of the semiconductor element 50 to form a solder layer 45. An upper surface 411 of the plating layer 41 may have irregularities due to the formation of the main surface wiring 21 and the plating layer 41. When the second solder layer 56 is directly joined to the plating layer 41, there is a risk that voids (vacancies) will occur in the solder layer due to the roughness of the upper surface 211 of the main surface wiring 21 and the upper surface 411 of the plating layer 41. In response to this, the first solder layer 42 formed on the plating layer 41 is melted by a reflow process before mounting the semiconductor element 50, so that the rough surface is smoothed. This smoothing can suppress the occurrence of voids when the first solder layer 42 and the second solder layer 56 are joined. First solder layer 42 has a thickness T2 that is small relative to the size in a direction parallel to upper surface 411 of plating layer 41 on which first solder layer 42 is formed. In other words, because first solder layer 42 has a small aspect ratio, solder flow in a reflow process before mounting semiconductor element 50 can be suppressed.

[0141] As described above, according to the second embodiment, the following effects are achieved.

[0142] (2-1) The same effects as those (1-1) to (1-5) in the first embodiment can be obtained.

[0143] (2-2) The multiple joints 40 formed on the upper surface 211 of the second wiring portion 24 that becomes one main surface wiring 21 are formed away from each other. Each joint 40 is connected to an element electrode 55 of the semiconductor element 50. Each joint 40 suppresses the outflow of solder. For this reason, in the multiple element electrodes 55 connected to the second wiring portion 24 that becomes one main surface wiring 21, a solder layer 45 is formed between each element electrode 55 and the joint 40, so that the amount of solder is secured for each element electrode 55. This ensures electrical connection between each element electrode 55 and the second wiring portion 24 that becomes one main surface wiring 21.

[0144] (Example of change) The above-described embodiments can be modified as follows.

[0145] The size of the joint 40 may be changed as appropriate.

[0146] 9 shows a modified joint 40. For example, in the first wiring section 23, it is preferable to make the distance L2a between the element electrode 55 and the edge 40a of the joint 40 on the outside of the semiconductor element 50 larger than the distance L2c between the element electrode 55 and the edge 40c of the joint 40 on the inside of the semiconductor element 50. In the case of the second wiring section 24, it is preferable to make the distance L2d from the element electrode 55 to the end of the joint 40 on the element side surface 504 side of the semiconductor element 50 larger than the distance L2c from the element electrode 55 to the end of the joint 40 on the inside of the semiconductor element 50. In this way, the flow of solder toward the inside of the semiconductor element 50 can be further suppressed.

[0147] The configuration of the semiconductor device may be changed as appropriate.

[0148] 10 includes a substrate 10, a wiring portion 20, a bonding portion 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The wiring portion 20 includes main surface wiring 21 formed on the substrate main surface 101 of the substrate 10, and through wiring 22 penetrating the substrate 10.

[0149] The through wiring 22 extends to the substrate side surface 103 of the substrate 10. That is, the side surface 223 of the through wiring 22 is flush with the substrate side surface 103 of the substrate 10. The external connection terminal 70 extends to the substrate side surface 103 of the substrate 10. Therefore, the lower surface 222 of the through wiring 22 is exposed at the substrate rear surface 102 of the substrate 10, and the side surface 223 of the through wiring 22 is exposed at the substrate side surface 103 of the substrate 10. The external connection terminal 70 is formed so as to cover the lower surface 222 of the through wiring 22. In such a semiconductor device A11, the same effects as those of the above embodiment can be obtained.

[0150] 11 includes a substrate 10, a wiring portion 20, a bonding portion 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70. The wiring portion 20 includes main surface wiring 21 formed on the substrate main surface 101 of the substrate 10, and through wiring 22 penetrating the substrate 10.

[0151] The through wiring 22 extends to the substrate side surface 103 of the substrate 10. That is, the side surface 223 of the through wiring 22 is flush with the substrate side surface 103 of the substrate 10. Therefore, the lower surface 222 of the through wiring 22 is exposed at the substrate back surface 102 of the substrate 10, and the side surface 223 of the through wiring 22 is exposed at the substrate side surface 103 of the substrate 10.

[0152] The external connection terminal 70 of the semiconductor device A12 is formed so as to cover the through wiring 22 exposed from the substrate 10. The external connection terminal 70 has a first conductive film 71 covering the lower surface 222 of the through wiring 22 and a second conductive film 72 covering the side surface 223 of the through wiring 22. The external connection terminal 70 having the first conductive film 71 and the second conductive film 72 becomes the external connection terminal of the semiconductor device A12, similar to the external connection terminal 70 of the above embodiment. The external connection terminal 70 is composed of, for example, a plurality of metal layers stacked on each other. The metal layers are, for example, Ni layers, Pd layers, and Au layers. The material of the external connection terminal 70 is not limited, but may be, for example, Ni layers and Au layers stacked on each other, or may be Sn.

[0153] In this semiconductor device A12, when mounted on a mounting board, the solder connecting the external connection terminal 70 to the connection pad of the mounting board is interposed between the first conductive film 71 and the connection pad, and also adheres to the second conductive film 72. That is, the solder that has become liquid phase by the reflow process creeps up the second conductive film 72 and forms a solder fillet between the second conductive film 72 and the connection pad. Although the solder fillet is also formed in the semiconductor device A11 shown in FIG. 10, the solder fillet is formed more easily in the semiconductor device A12 of this modified example. The solder fillet increases the solder joint area, and the connection strength can be further increased. In addition, the solder fillet allows the state of soldering of the semiconductor device A12 to be confirmed from the outside.

[0154] A semiconductor device A13 shown in FIG. 12 includes a substrate 11, a wiring portion 20, a bonding portion 40, a semiconductor element 50, a sealing resin 60, and an external connection terminal 70.

[0155] The substrate 11 is in the form of a thin plate, and has no through-holes. The substrate 11 has a substrate main surface 111, a substrate back surface 112, and a plurality of substrate side surfaces 113. The substrate main surface 111 and the substrate back surface 112 face in opposite directions in the thickness direction Z. The substrate main surface 111 and the substrate back surface 112 are flat. The substrate 11 may be made of a material such as a synthetic resin mainly made of epoxy resin, ceramics, glass, or a semiconductor material such as Si. In the case of the substrate 11 made of a semiconductor material such as Si, an insulating layer is provided to cover the substrate main surface 111. The insulating layer may be made of, for example, SiO 2 For example, an oxide film such as a polyimide film or a resin film such as a polyimide film is used.

[0156] The wiring section 20 has main surface wiring 21 and through wiring 22 .

[0157] The main surface wiring 21 is formed on the substrate main surface 111 of the substrate 11. An upper surface 211 of the main surface wiring 21 faces the same direction as the substrate main surface 111 of the substrate 11. A lower surface 212 of the main surface wiring 21 faces the same direction as the substrate rear surface 112 of the substrate 11, and faces the substrate main surface 111 of the substrate 11. A side surface 213 of the main surface wiring 21 faces the same direction as the substrate side surface 113 of the substrate 11.

[0158] The sealing resin 60 is formed so as to contact the substrate main surface 111 of the substrate 11 and cover the semiconductor element 50. The sealing resin 60 has a plurality of through holes 605 penetrating the sealing resin 60 in the thickness direction Z. The through holes 605 extend from a resin upper surface 601 of the sealing resin 60 to an upper surface 211 of the main surface wiring 21. The shape of the through holes 605 is, for example, rectangular when viewed from the thickness direction Z. The shape of the through holes 605 may be circular or polygonal.

[0159] The through wiring 22 is disposed in each through hole 605. The through wiring 22 has an upper surface 221, a lower surface 222, and multiple side surfaces 223. The upper surface 221 of the through wiring 22 is flush with the resin upper surface 601 of the sealing resin 60. The upper surface 221 of the through wiring 22 is exposed from the sealing resin 60. The lower surface 222 of the through wiring 22 is in contact with the upper surface 211 of the main surface wiring 21. The side surface 223 of the through wiring 22 is in contact with the inner wall surface 606 of the through hole 605 of the sealing resin 60.

[0160] The external connection terminals 70 are formed on a resin upper surface 601 of the sealing resin 60. The external connection terminals 70 are formed so as to cover the exposed upper surfaces 221 of the through-wires 22. The external connection terminals 70 become external connection terminals of the semiconductor device A13.

[0161] This semiconductor device A13 is mounted on a mounting substrate with the external connection terminals 70 facing the mounting substrate, i.e., with the element main surface 501 of the semiconductor element 50 facing away from the mounting substrate. This semiconductor device A13 can also provide the same effects as the above-described embodiment. In addition, in this semiconductor device A13, the thickness of the substrate 11 can be made thinner than that of the substrate 10 of the semiconductor device A2 of the embodiment, so that the semiconductor device A13 can be made thinner.

[0162] 13 includes a substrate 12, a wiring portion 20, external connection terminals 70, a semiconductor element 50, and a sealing resin 60. The wiring portion 20 includes a main surface wiring 21 and a columnar body 25 serving as a through wiring.

[0163] FIG. 13 is a schematic cross-sectional view of a semiconductor device A14 according to a modified example.

[0164] The substrate 12 has a rectangular shape when viewed in the thickness direction Z. The substrate 12 includes a base material 13 and an insulating layer 14.

[0165] The substrate 13 has a main surface 131, a back surface 132, and a number of side surfaces 133. The main surface 131 and the back surface 132 face in opposite directions in the thickness direction Z. The main surface 131 and the back surface 132 are flat. The substrate 13 is made of, for example, an electrically insulating material. This material may be, for example, a single crystal intrinsic semiconductor material such as Si, or a synthetic resin mainly composed of an epoxy resin or the like. As the main surface 131 of the substrate 13, for example, a (100) plane having a crystal orientation of (100) may be used.

[0166] The base material 13 has a plurality of through holes 135. Each through hole 135 penetrates the base material 13 in the thickness direction Z from the main surface 131 to the back surface 132. Each through hole 135 is, for example, rectangular when viewed from the thickness direction Z. The shape of the through hole 135 may be circular or polygonal. An inner wall surface 136 of each through hole 135 intersects with the back surface 132. In this semiconductor device A14, the inner wall surface 136 is perpendicular to the back surface 132. The inner wall surface 136 may be inclined at a predetermined angle with respect to the back surface 132. The inclination angle of the inner wall surface 136 is an angle determined by the configuration of the base material 13 made of, for example, a semiconductor material, for example, a crystal orientation.

[0167] The insulating layer 14 is formed on the base material 13. The insulating layer 14 is formed so as to cover the main surface 131 of the base material 13 and the inner wall surface 136 of the through hole 135. The insulating layer 14 has a first insulating layer 141 covering the main surface 131 of the base material 13, and a second insulating layer 142 covering the inner wall surface 136 of the through hole 135. The insulating layer 14 is a coating having electrical insulation properties. The insulating layer 14 in this modified example is made of SiO 2 The insulating layer 14 is formed, for example, by thermally oxidizing the base material 13. The thickness of the insulating layer 14 is, for example, 0.7 μm or more and 2.0 μm or less. The material, thickness, and forming method of the insulating layer 14 are not limited. For example, the insulating layer 14 may be made of SiO 2 and a resin layer. Also, the insulating layer 14 may be made of a resin layer.

[0168] Thus, the substrate 12 has the base material 13 and the insulating layer 14. The base material 13 is made of a single crystal intrinsic semiconductor material, and has a through hole 135 penetrating the base material 13 from the main surface 131 to the back surface 132. The insulating layer 14 is formed so as to cover the main surface 131 of the base material 13 and the inner wall surface 136 of the through hole 135 of the base material 13. Therefore, the upper surface of the insulating layer 14 (first insulating layer 141) becomes the substrate main surface 121 of the substrate 12, and the back surface 132 of the base material 13 becomes the substrate back surface 122 of the substrate 12. The substrate 12 has a through hole 125 covered with the insulating layer 14 (second insulating layer 142).

[0169] An insulating layer may be formed on the rear surface 132 of the base material 13. The insulating layer is a coating having electrical insulation properties. The insulating layer formed on the rear surface 132 may be the same as the insulating layer 14.

[0170] The wiring portion 20 of the semiconductor device A14 includes a plurality of main surface wirings 26 and a plurality of pillars 25.

[0171] The main surface wiring 26 is a part of the wiring section 20 formed on the substrate main surface 121 side of the substrate 12. The main surface wiring 26 has an upper surface 261, a lower surface 262, and a side surface 263. The main surface wiring 26 of this modified example includes a metal layer and a conductive layer.

[0172] A joint 40 is formed on the main surface wiring 26. The joint 40 includes a plating layer 41 and a first solder layer 42. A second solder layer 56 of the semiconductor element 50 is connected to the first solder layer 42.

[0173] The multiple pillars 25 are formed to penetrate the substrate 12. Each pillar 25 is formed inside the through-hole 125 so as to fill a portion surrounded by the insulating layer .

[0174] Each of the columns 25 is exposed from the substrate main surface 121 and the substrate rear surface 122 of the substrate 12. Each of the columns 25 has an upper surface 251, a rear surface 252, and a number of side surfaces 253. The upper surface 251 and the rear surface 252 face opposite each other in the thickness direction Z. The upper surface 251 is a curved surface that is curved so as to be recessed toward the inside of the column 25, that is, toward the rear surface 252 of the column 25. The rear surface 252 is a surface exposed from the substrate rear surface 122. The rear surface 252 of the column 25 is flush with the substrate rear surface 122. The side surface 253 is in contact with the second insulating layer 142 of the insulating layer 14.

[0175] The shape of each columnar body 25 is not limited and may be, for example, a cylindrical shape. In the semiconductor device A14 of the modified example, the main surface wiring 26 and the columnar body 25 are integrally formed of the same material. The main surface wiring 26 and the columnar body 25 may be separately formed of different materials.

[0176] The sealing resin 60 is disposed on the substrate main surface 121 side of the substrate 12, and is formed so as to cover the semiconductor element 50. The sealing resin 60 is in contact with the substrate main surface 121 of the substrate 12, and is formed so as to cover the semiconductor element 50 and the wiring portion 20 (the main surface wiring 25 and the upper surfaces 152 of the columns 25). The sealing resin 60 overlaps with the substrate 12 when viewed from the thickness direction Z. The sealing resin 60 is rectangular when viewed from the thickness direction Z.

[0177] The sealing resin 60 has electrical insulation properties. The sealing resin 60 is made of a resin material that is colored, for example, black. The resin material is, for example, a synthetic resin such as an epoxy resin. The material and shape of the sealing resin 60 are not limited.

[0178] The external connection terminal 70 is formed on the back surface 122 of the substrate 12. The external connection terminal 70 is formed so as to cover the upper surface 251 of the columnar body 25. The external connection terminal 70 becomes the external connection terminal of the semiconductor device A14. The external connection terminal 70 is composed of, for example, a plurality of metal layers stacked on top of each other. The metal layers are, for example, Ni layers, Pd layers, and Au layers. The material of the external connection terminal 70 is not limited, and may be, for example, a stack of Ni layers and Au layers, or may be Sn.

[0179] In this semiconductor device A14, the base material 13 made of a single crystal semiconductor material is used, and it is possible to suppress the outflow of solder during the reflow process when mounting the semiconductor element 50.

[0180] Third Embodiment A semiconductor device A10 according to a third embodiment of the present invention will be described with reference to Figs. 14 to 20. The semiconductor device A10 includes a sealing resin 710, wiring 721, a plurality of interconnecting wirings 722, a semiconductor element 730, and a plurality of terminals 741. The semiconductor device A10 is in a resin package format that is surface-mounted on a wiring board. For ease of understanding, Fig. 14 shows a second layer 712 (described in detail later) of the sealing resin 710 in a transparent manner. Furthermore, in Fig. 14, the VV line is shown by a dashed line. For ease of understanding, Fig. 15 shows the semiconductor element 730 in a transparent manner in comparison with Fig. 14. The semiconductor element 730 in Fig. 15 is shown by an imaginary line (double-dashed line).

[0181] In the description of the semiconductor device A10, for convenience, the thickness direction of the semiconductor device A10 is referred to as the "thickness direction z." The direction perpendicular to the thickness direction z is referred to as the "first direction x." The direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y." As shown in FIG. 14, the semiconductor device A10 is rectangular when viewed along the thickness direction z.

[0182] As shown in FIGS. 17 to 19, the sealing resin 710 includes a first layer 711 and a second layer 712. Both the first layer 711 and the second layer 712 are made of a material containing a synthetic resin. An example of the synthetic resin is an epoxy resin. In order to minimize the difference between the linear expansion coefficient of the first layer 711 and the linear expansion coefficient of the second layer 712, it is preferable that the synthetic resins contained in the first layer 711 and the second layer 712 are the same. The first layer 711 has a first main surface 711A, a first back surface 711B, and a side surface 711C. The first main surface 711A and the first back surface 711B face opposite each other in the thickness direction z. Of these, the first back surface 711B faces the wiring board when the semiconductor device A10 is mounted on the wiring board. The side surface 711C faces a direction perpendicular to the thickness direction z and is connected to the first main surface 711A and the first back surface 711B. In the semiconductor device A10, the side surface 711C includes a pair of regions that face the first direction x and are spaced apart from each other, and a pair of regions that face the second direction y and are spaced apart from each other. The second layer 712 is stacked in the thickness direction z on the first main surface 711A. The second layer 712 has a second main surface 712A and a second back surface 712B. The second main surface 712A and the second back surface 712B face opposite sides to each other in the thickness direction z. Of these, the second back surface 712B is in contact with the first main surface 711A. When viewed along the thickness direction z, the periphery of the second layer 712 coincides with the periphery of the first layer 711. Furthermore, the distance between the first main surface 711A and the first back surface 711B is smaller than the distance between the second main surface 712A and the second back surface 712B. That is, the thickness of the first layer 711 is smaller than the thickness of the second layer 712 .

[0183] As shown in FIG. 20, the first layer 711 is mixed with a filler 788. The filler 788 is a fine powder. The filler 788 includes an inorganic compound. The inorganic compound is glass or ceramics. An example of the ceramic is alumina (Al 2 O 3 ) are mentioned.

[0184] The wiring 721 is disposed in contact with the first main surface 711A of the first layer 711, as shown in FIG. 14, FIG. 15, FIG. 18, and FIG. 19. The wiring 721 constitutes a part of a conductive path between the semiconductor element 730 and a wiring board on which the semiconductor device A10 is mounted. The wiring 721 includes a plurality of regions. When viewed along the thickness direction z, each of the plurality of regions is strip-shaped. Note that the semiconductor device A10 includes eight regions. A part of the wiring 721 is covered by the second layer 712. When viewed along the thickness direction z, the wiring 721 is located inward from the periphery of the sealing resin 710 (the first layer 711 and the second layer 712). Therefore, the wiring 721 is not exposed from the sealing resin 710 to the outside of the semiconductor device A10.

[0185] As shown in FIG. 20, each of the multiple regions of the wiring 721 has an underlayer 789 and a main layer 790. The underlayer 789 is in contact with the first main surface 711A of the first layer 711 and any of the multiple interconnecting wires 722. The underlayer 789 is composed of a barrier layer in contact with them and a seed layer stacked on the barrier layer in the thickness direction z. The composition of the barrier layer includes titanium (Ti). The composition of the seed layer includes copper (Cu). The main layer 790 is stacked on the underlayer 789 in the thickness direction z. The thickness of the main layer 790 is greater than the thickness of the underlayer 789. Therefore, in each of the multiple regions of the wiring 721, the main layer 790 serves as a main conductive path. The composition of the main layer 790 is the same as the composition of the seed layer of the underlayer 789. Therefore, the composition of the main layer 790 includes copper.

[0186] Each of the multiple interconnections 722 is connected to one of the multiple regions of the interconnection 721, as shown in Figures 14, 15, and 18. Each of the multiple interconnection wires 722 reaches the first back surface 711B of the first layer 711 from the interconnection 721, and is partially covered by the first layer 711. The multiple interconnection wires 722, together with the interconnection 721, form part of a conductive path between the semiconductor element 730 and a wiring board on which the semiconductor device A10 is mounted. The composition of each of the multiple interconnection wires 722 includes copper.

[0187] As shown in FIG. 16, FIG. 18, and FIG. 19, each of the multiple interconnects 722 has a bottom surface 722A and an end surface 722B. The bottom surface 722A is exposed on a first back surface 711B of the first layer 711. The end surface 722B is connected to the bottom surface 722A and faces a direction perpendicular to the thickness direction z. In the semiconductor device A10, the end surface 722B faces the second direction y. As shown in FIG. 17, the end surface 722B is exposed in one of a pair of regions of the side surface 711C of the first layer 711. In the semiconductor device A10, the end surface 722B is exposed in one of a pair of regions of the side surface 711C that are spaced apart from each other in the second direction y. In each of the multiple interconnections 722, the surface facing the opposite side to the bottom surface 722A in the thickness direction z is flush with the first main surface 711A of the first layer 711 and is in contact with the second back surface 712B of the second layer 712.

[0188] As shown in FIG. 18 and FIG. 19, the semiconductor element 730 is bonded to the wiring 721 via a plurality of bonding layers 739. The plurality of bonding layers 739 are conductive. Each of the plurality of bonding layers 739 is composed of a nickel (Ni) layer laminated in the thickness direction z on the wiring 721 and an alloy layer laminated on the nickel layer and containing tin (Sn) in its composition. The semiconductor element 730 is a flip-mount type element. In the semiconductor device A10, the semiconductor element 730 is an LSI. The semiconductor element 730 is covered with a second layer 712.

[0189] As shown in FIGS. 18 to 20, the semiconductor element 730 has a lower surface 730A and a plurality of pads 731. The lower surface 730A faces the first main surface 711A of the first layer 711 and the wiring 721. The plurality of pads 731 are provided on the lower surface 730A. In the semiconductor device A10, each of the plurality of pads 731 is electrically connected to a circuit (not shown) configured inside the semiconductor element 730. Each of the plurality of pads 731 is bonded to the wiring 721 via any one of a plurality of bonding layers 739. As a result, the semiconductor element 730 is electrically connected to the wiring 721.

[0190] As shown in FIG. 16 and FIG. 18, the terminals 741 individually cover the bottom surfaces 722A of the interconnection wirings 722. The terminals 741 are exposed to the outside of the semiconductor device A10. Each of the terminals 741 is joined to a wiring board via solder, whereby the semiconductor device A10 is mounted on the wiring board. In the semiconductor device A10, each of the terminals 741 includes a plurality of metal layers stacked in the thickness direction z with respect to the bottom surface 722A. The metal layers are stacked in the order of proximity to the bottom surface 722A, that is, a nickel layer and a gold (Au) layer. Therefore, the composition of the metal layers includes nickel and gold. As another example of the configuration of the metal layers, a nickel layer, a palladium (Pd) layer, and a gold layer may be stacked in the order of proximity to the bottom surface 722A.

[0191] <Modification of the third embodiment> A semiconductor device A11 according to a modified example of the third embodiment of the present invention will be described with reference to Fig. 21 and Fig. 22. Here, for ease of understanding, Fig. 21 is seen through the second layer 712 of the sealing resin 710. Furthermore, in Fig. 21, line IX-IX is indicated by a dashed line.

[0192] In the semiconductor device A11, the configuration of the multiple terminals 741 is different from that of the semiconductor device A10 described above. As shown in Fig. 22, each of the multiple terminals 741 includes a solder ball. Each of the multiple terminals 741 protrudes in the thickness direction z from a bottom surface 722A of any one of the multiple interconnections 722. As shown in Figs. 21 and 22, each of the multiple terminals 741 is substantially spherical.

[0193] Next, an example of a manufacturing method of the semiconductor device A10 will be described with reference to Figures 23 to 36. The cross-sectional positions of Figures 23 to 36 are the same as the cross-sectional position of Figure 18.

[0194] First, as shown in FIG. 23, an insulating film 781 is formed on one surface of a base material 780 in the thickness direction z. The base material 780 is a semiconductor wafer (silicon wafer). The insulating film 781 is an oxide film (SiO 2 ), or nitride film (Si3 N 4 Regarding the insulating film 781, if it is an oxide film, it is formed by thermal oxidation. On the other hand, if it is a nitride film, it is formed by plasma CVD (Chemical Vapor Deposition).

[0195] 24, a release layer 782 is formed to cover the upper surface of the insulating film 781. The release layer 782 is made of a metal thin film made of titanium that is in contact with the insulating film 781, and a metal thin film made of copper that is stacked on the metal thin film in the thickness direction z. The release layer 782 is formed by depositing these metal thin films by a sputtering method.

[0196] 25, a plurality of pillars 783 are formed so as to protrude from the upper surface of the release layer 782 in the thickness direction z. The pillars 783 are made of copper. The pillars 783 are formed by subjecting the upper surface of the release layer 782 to lithographic patterning, and then by electrolytic plating using the release layer 782 as a conductive path. The height of each of the pillars 783 is set to be 100 μm or more.

[0197] 26, a first resin layer 784 is formed in contact with the release layer 782 and covering the plurality of columns 783. The first resin layer 784 is made of a material containing a black epoxy resin and a filler made of an inorganic compound that is mixed into the epoxy resin. The first resin layer 784 is formed by compression molding. In this process, the thickness of the first resin layer 784 is set to be 150 μm or more and greater than the height of each of the plurality of columns 783.

[0198] 27, a portion of each of the first resin layer 784 and the multiple columns 783 is removed by grinding. The portion to be removed is the portion on the opposite side to the side on which the base material 780 is located in the thickness direction z. Through this process, the height of each of the multiple columns 783 becomes equal to the thickness of the first resin layer 784. Furthermore, the upper surface of each of the multiple columns 783 is exposed at the upper surface of the first resin layer 784.

[0199] Next, as shown in FIGS. 28 to 31, wiring 721 in contact with the upper surface of the first resin layer 784 and the upper surfaces of each of the multiple columns 783, and multiple bonding layers 739 are formed on the upper surface of the wiring 721.

[0200] First, as shown in Fig. 28, an underlayer 789 is formed to cover the upper surface of the first resin layer 784 and the upper surfaces of each of the multiple columns 783. The underlayer 789 is formed by forming a barrier layer covering these upper surfaces by sputtering, and then forming a seed layer by sputtering on the upper surface of the barrier layer. The barrier layer is made of titanium and has a thickness of 100nm to 300nm. The seed layer is made of copper and has a thickness of 200nm to 600nm.

[0201] 29, a plurality of main body layers 790 are formed on the upper surface of the base layer 789. The plurality of main body layers 790 are formed by performing lithography patterning on the upper surface of the base layer 789 and then performing electrolytic plating using the base layer 789 as a conductive path.

[0202] 30, a plurality of bonding layers 739 are formed on the upper surfaces of the plurality of main body layers 790. The plurality of bonding layers 739 are formed by performing lithography patterning on the upper surfaces of the base layer 789 and the plurality of main body layers 790, and then performing electrolytic plating using the base layer 789 and the plurality of main body layers 790 as conductive paths.

[0203] 31, a part of the underlayer 789 is removed. The part of the underlayer 789 that is to be removed is the part where the plurality of main layers 790 are not laminated. The underlayer 789 is removed by dissolving sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ) is removed by wet etching using a mixed solution. Through this process, the wiring 721 is formed.

[0204] 32, the semiconductor element 730 is bonded to the wiring 721 via a plurality of bonding layers 739. First, a collet is used to temporarily attach the plurality of pads 731 of the semiconductor element 730 to the plurality of bonding layers 739 individually. Next, the plurality of bonding layers 739 are melted by reflow. Finally, the melted plurality of bonding layers 739 are solidified by cooling. This completes the bonding of the semiconductor element 730 to the wiring 721.

[0205] 33, a second resin layer 785 is formed in contact with the first resin layer 784. The second resin layer 785 is made of a material containing black epoxy resin. The second resin layer 785 is formed by compression molding. Through this process, a part of the wiring 721 and the semiconductor element 730 are covered with the second resin layer 785.

[0206] 34, the base material 780, the insulating film 781, and the release layer 782 are removed. The base material 780 and the insulating film 781 are removed by grinding. The release layer 782 is removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide. Through this process, a portion of each of the multiple columns 783 is exposed from the first resin layer 784.

[0207] 35, a plurality of metal layers 786 are formed to individually cover a portion of each of the plurality of columns 783 exposed from the first resin layer 784. Each of the plurality of metal layers 786 is formed by depositing a nickel layer in contact with any one of the plurality of columns 783 by electroless plating, and then depositing a gold layer on the nickel layer by electroless plating.

[0208] Finally, after a tape 787 is attached to the surface of the second resin layer 785 facing the thickness direction z, the multiple columns 783, the first resin layer 784, the second resin layer 785, and the multiple metal layers 786 are cut into a lattice shape along both the first direction x and the second direction y, to be divided into multiple individual pieces. A dicing blade or the like is used for cutting. Through this process, the first resin layer 784 and the second resin layer 785 that have become the individual pieces become the first layer 711 of the sealing resin 710 of the semiconductor device A10, and the second layer 712 of the sealing resin 710 of the semiconductor device A10. In addition, the multiple columns 783 that have become the individual pieces and the multiple metal layers 786 that individually cover them become the multiple interconnects 722 of the semiconductor device A10, and the multiple terminals 741 of the semiconductor device A10. Through the above processes, the semiconductor device A10 is manufactured.

[0209] Next, the effects of the semiconductor device A10 will be described.

[0210] The semiconductor device A10 includes a sealing resin 710, wiring 721, and a semiconductor element 730. The sealing resin 710 includes a first layer 711 having a first main surface 711A and a first back surface 711B, and a second layer 712 having a second main surface 712A and a second back surface 712B. The second back surface 712B is in contact with the first main surface 711A. The wiring 721 is in contact with the first main surface 711A. A part of the wiring 721 is covered by the second layer 712. The semiconductor element 730 is bonded to the wiring 721 and is covered by the second layer 712. As a result, the difference between the linear expansion coefficient of the first layer 711 on which the semiconductor element 730 is mounted and the linear expansion coefficient of the second layer 712 covering the semiconductor element 730 is smaller than that in the case where the first layer 711 is a semiconductor wafer. Furthermore, the thickness of the second layer 712 can be made as small as possible under the condition that it covers the semiconductor element 730. Therefore, according to the semiconductor device A10, it is possible to reduce the warpage of the semiconductor device A10 while achieving miniaturization.

[0211] The distance between the first main surface 711A and the first back surface 711B of the first layer 711 is smaller than the distance between the second main surface 712A and the second back surface 712B of the second layer 712. In other words, the thickness of the first layer 711 is smaller than the thickness of the second layer 712. This makes it possible to reduce the size of the semiconductor device A10.

[0212] Filler 788 containing an inorganic compound is mixed into first layer 711. Filler 788 serves as a reinforcing material for first layer 711. This makes it possible to ensure the mechanical strength of first layer 711 even when the thickness of first layer 711 is made as small as possible.

[0213] The semiconductor device A10 further includes a plurality of interconnect wirings 722 connected to the wiring 721. Each of the plurality of interconnect wirings 722 reaches the first back surface 711B of the first layer 711 from the wiring 721, and is partially covered by the first layer 711. Each of the plurality of interconnect wirings 722 has a bottom surface 722A exposed at the first back surface 711B. As a result, in the semiconductor device A10, the conductive member connected to the interconnect wiring 721 does not protrude from the sealing resin 710 when viewed along the thickness direction z, so that the semiconductor device A10 can be configured to be suitable for miniaturization. In addition, when the first layer 711 is a semiconductor wafer, it is necessary to form a plurality of holes necessary for arranging the plurality of interconnect wirings 722 in the semiconductor wafer. The plurality of holes can be formed by deep excavation RIE (Reactive Ion Etching) or the like. However, the formation of the plurality of holes requires time and cost. Therefore, according to the first layer 711 of the semiconductor device A10, it is not necessary to form the plurality of holes, so that the time and cost required for manufacturing the semiconductor device A10 can be reduced.

[0214] The semiconductor device A10 further includes a plurality of terminals 741 that individually cover the bottom surfaces 722A of the plurality of interconnecting wires 722. As a result, when the semiconductor device A10 is mounted on a wiring board, the solder adheres to the plurality of terminals 741. Therefore, the plurality of terminals 741 can reduce the thermal shock caused by the solder acting on the plurality of interconnecting wires 722.

[0215] Each of the multiple terminals 741 includes multiple metal layers stacked in the thickness direction z. The multiple metal layers include nickel and gold. This makes it possible to more effectively reduce the thermal shock caused by the solder acting on the multiple interconnects 722. Furthermore, since the solder has good wettability, the mounting strength of the semiconductor device A10 on the wiring board can be improved.

[0216] When viewed along the thickness direction z, the wiring 721 is located inward from the periphery of the sealing resin 710. This results in a configuration in which the wiring 721 is entirely covered with the sealing resin 710. Therefore, it is possible to suppress a decrease in the dielectric strength voltage of the semiconductor device A10 caused by the wiring 721.

[0217] [Fourth embodiment] A semiconductor device A20 according to a fourth embodiment of the present invention will be described with reference to Figs. 37 to 39. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Fig. 37 is taken through the second layer 712 of the sealing resin 710. Furthermore, in Fig. 37, the line XXVI-XXVI is indicated by a dashed line.

[0218] In the semiconductor device A20, the configuration of the multiple terminals 741 differs from that of the semiconductor device A10 described above.

[0219] As shown in FIG. 39, in the semiconductor device A20, each of the multiple terminals 741 has a bottom 791 and a side 792. The bottom 791 covers a bottom surface 722A of one of the multiple interconnections 722. The bottom 791 includes multiple metal layers stacked in the thickness direction z with respect to the bottom surface 722A. The configuration of the multiple metal layers is the same as the configuration of the multiple metal layers included in each of the multiple terminals 741 of the semiconductor device A10. The side 792 is connected to the bottom 791 of one of the multiple terminals 741. The side 792 extends from the bottom 791 in the thickness direction z. The side 792 covers an end surface 722B of one of the multiple interconnections 722. As a result, as shown in FIG. 38, in the semiconductor device A20, the multiple interconnections 722 are configured not to be exposed to the outside of the semiconductor device A10. The side portion 792 includes a plurality of metal layers stacked in a direction perpendicular to the thickness direction z (the second direction y in the semiconductor device A20). The configuration of the metal layers is the same as the configuration of the plurality of metal layers included in the bottom portion 791.

[0220] Next, the effects of the semiconductor device A20 will be described.

[0221] The semiconductor device A20 includes a sealing resin 710, a wiring 721, and a semiconductor element 730. The sealing resin 710 includes a first layer 711 having a first main surface 711A and a first back surface 711B, and a second layer 712 having a second main surface 712A and a second back surface 712B. The second back surface 712B is in contact with the first main surface 711A. The wiring 721 is in contact with the first main surface 711A. A part of the wiring 721 is covered with the second layer 712. The semiconductor element 730 is bonded to the wiring 721 and is covered with the second layer 712. Therefore, the semiconductor device A20 can also reduce the warpage of the semiconductor device A20 while achieving miniaturization.

[0222] In the semiconductor device A20, each of the multiple terminals 741 has a bottom 791 and a side 792 connected to the bottom 791. The bottom 791 covers a bottom surface 722A of one of the multiple interconnections 722. The side 792 covers an end surface 722B of one of the multiple interconnections 722. As a result, when the semiconductor device A10 is mounted on a wiring board, the solder adheres not only to the bottom 791 but also to the side 792 of each of the multiple terminals 741. Therefore, the solder adhesion area of ​​each of the multiple terminals 741 becomes larger, and the mounting strength of the semiconductor device A20 on the wiring board can be improved. Furthermore, the solder adhered to the side 792 can be easily seen, so that the mounting state of the semiconductor device A20 on the wiring board can be visually confirmed by appearance.

[0223] Fifth embodiment A semiconductor device A30 according to a fifth embodiment of the present invention will be described with reference to Figs. 40 to 44. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Fig. 40 is viewed through the second layer 712 of the sealing resin 710. Furthermore, in Fig. 40, the line XXIX-XXIX is indicated by a dashed line.

[0224] The semiconductor device A30 differs from the previously described semiconductor device A10 in that a heat sink 750 is provided.

[0225] As shown in FIG. 40 to FIG. 43, the semiconductor device A30 includes a heat sink 750. At least a part of the heat sink 750 overlaps the semiconductor element 730 when viewed along the thickness direction z. The heat sink 750 includes a base 751, a covering 752, and a bump 753. The base 751 is embedded in the first layer 711 of the sealing resin 710, and is in contact with the second layer 712 of the sealing resin 710. The thickness of the base 751 is equal to the distance between the first main surface 711A of the first layer 711 and the first back surface 711B of the first layer 711, that is, the thickness of the first layer 711. The composition of the base 751 includes copper. The covering 752 includes a plurality of metal layers stacked on the base 751 in the thickness direction z, and is exposed at the first back surface 711B. Therefore, the covering 752 is exposed to the outside of the semiconductor device A30. The configuration of the plurality of metal layers is the same as the configuration of the plurality of metal layers included in each of the plurality of terminals 741 of the semiconductor device A10.

[0226] As shown in FIG. 42 and FIG. 43, the bump portion 753 is located on the opposite side of the base portion 751 from the covering portion 752 in the thickness direction z. The bump portion 753 protrudes from the base portion 751 toward the lower surface 730A of the semiconductor element 730 in the thickness direction z. As shown in FIG. 44, the bump portion 753 has an underlayer 793 and a main body layer 794. The underlayer 793 is in contact with the base portion 751. The underlayer 793 is composed of a barrier layer in contact with the base portion 751 and a seed layer stacked on the barrier layer in the thickness direction z. The composition of the barrier layer includes titanium. The composition of the seed layer includes copper. The thickness of the underlayer 793 is equal to the thickness of the underlayer 789 of the wiring 721. The main body layer 794 is stacked on the underlayer 793 in the thickness direction z. The composition of the main body layer 790 is the same as the composition of the seed layer of the underlayer 789. Therefore, the composition of main body layer 790 contains copper. The thickness of main body layer 794 is greater than the thickness of underlayer 793 and is equal to the thickness of main body layer 790 of wiring 721. Therefore, the thickness of bump portion 753 is equal to the thickness of wiring 721.

[0227] 42 and 43, any one of a plurality of pads 731 of a semiconductor element 730 is bonded to a bump portion 753 via a bonding layer 739. The pad 731 bonded to the bump portion 753 is a so-called dummy pad that is not electrically connected to a circuit configured inside the semiconductor element 730. Alternatively, the pad 731 bonded to the bump portion 753 is related to the grounding of the semiconductor element 730.

[0228] Next, the effects of the semiconductor device A30 will be described.

[0229] The semiconductor device A30 includes a sealing resin 710, a wiring 721, and a semiconductor element 730. The sealing resin 710 includes a first layer 711 having a first main surface 711A and a first back surface 711B, and a second layer 712 having a second main surface 712A and a second back surface 712B. The second back surface 712B is in contact with the first main surface 711A. The wiring 721 is in contact with the first main surface 711A. A part of the wiring 721 is covered with the second layer 712. The semiconductor element 730 is bonded to the wiring 721 and is covered with the second layer 712. Therefore, the semiconductor device A30 can also reduce the warpage of the semiconductor device A30 while achieving miniaturization.

[0230] The semiconductor device A30 further includes a heat sink 750. The heat sink 750 has a base 751. The base 751 is embedded in the first layer 711 and contacts the second back surface 712B of the second layer 712. When viewed along the thickness direction z, at least a part of the heat sink 750 overlaps the semiconductor element 730. This allows the heat generated from the semiconductor element 730 to be efficiently dissipated to the outside of the semiconductor device A30 during use of the semiconductor device A30. The thickness of the base 751 is equal to the distance between the first main surface 711A and the first back surface 711B of the first layer 711. This allows the method of forming the base 751 to be the same as the method of forming the multiple interconnects 722 (see FIGS. 25 to 27) in the manufacture of the semiconductor device A30.

[0231] The heat sink 750 has a covering portion 752. The covering portion 752 is laminated on the base portion 751 and exposed on the first back surface 711B of the first layer 711. The covering portion 752 includes a plurality of metal layers constituting the plurality of terminals 741. This allows the heat sink 750 to be joined to the wiring board by solder when the semiconductor device A30 is mounted on the wiring board, so that the heat conducted from the semiconductor element 730 to the heat sink 750 can be more effectively transferred to the wiring board. Furthermore, in manufacturing the semiconductor device A30, the method for forming the covering portion 752 can be the same as the method for forming the plurality of terminals 741 (see FIG. 35).

[0232] The heat sink 750 has a bump portion 753. The bump portion 753 protrudes from the base portion 751 toward the lower surface 730A of the semiconductor element 730 in the thickness direction z. Any of the pads 731 of the semiconductor element 730 is bonded to the bump portion 753. This makes it possible to more effectively transfer heat generated from the semiconductor element 730 to the heat sink 750. In addition, the heights of the multiple bonding layers 739 located individually with respect to the multiple pads 731 can all be made equal. Furthermore, in the manufacture of the semiconductor device A30, the method for forming the bump portion 753 can be the same as the method for forming the wiring 721 (see FIGS. 28, 29, and 31).

[0233] Sixth Embodiment A semiconductor device A40 according to a sixth embodiment of the present invention will be described with reference to Figs. 45 to 48. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, Fig. 46 is seen through the second layer 712 of the sealing resin 710 for ease of understanding. In Fig. 45, the line XXXIV-XXXIV is indicated by a dashed line.

[0234] The semiconductor device A40 differs from the configuration of the semiconductor device A10 described above in that, instead of the multiple interconnection wirings 722 and the multiple terminals 741, the semiconductor device A40 has multiple first interconnection wirings 723, multiple second interconnection wirings 724, multiple first terminals 742, and multiple second terminals 743.

[0235] As shown in FIGS. 46 to 48, the semiconductor device A40 includes a plurality of first interconnections 723. Each of the plurality of first interconnections 723 is connected to one of a plurality of regions of the interconnection 721. Each of the plurality of first interconnections 723 reaches the first rear surface 711B of the first layer 711 from the interconnection 721, and is partially covered by the first layer 711. The plurality of first interconnections 723, together with the interconnection 721, constitute a part of a conductive path between the semiconductor element 730 and a wiring board on which the semiconductor device A40 is mounted. The composition of each of the plurality of first interconnections 723 includes copper.

[0236] As shown in FIG. 47, each of the multiple first interconnects 723 has a bottom surface 723A and an end surface 723B. The bottom surface 723A is exposed on a first back surface 711B of the first layer 711. The end surface 723B is connected to the bottom surface 723A and faces a direction perpendicular to the thickness direction z. In the semiconductor device A40, the end surface 723B faces the second direction y. As shown in FIG. 46 and FIG. 47, the end surface 723B is exposed in one of a pair of regions of the side surface 711C of the first layer 711. In the semiconductor device A40, the end surface 723B is exposed in one of a pair of regions of the side surface 711C that are spaced apart from each other in the second direction y. In each of the multiple first interconnections 723, the surface facing the opposite side to the bottom surface 723A in the thickness direction z is flush with the first main surface 711A of the first layer 711 and is in contact with the second back surface 712B of the second layer 712.

[0237] As shown in FIGS. 45 to 48, the semiconductor device A40 includes a plurality of second interconnections 724. Each of the plurality of second interconnections 724 is connected to one of a plurality of regions of the interconnection 721. Each of the plurality of second interconnections 724 reaches the second main surface 712A of the second layer 712 from the interconnection 721, and is partially covered by the second layer 712. The plurality of second interconnections 724, together with the interconnection 721, constitute a part of the conductive path between the semiconductor element 730 and the wiring board on which the semiconductor device A40 is mounted. The composition of each of the plurality of second interconnections 724 includes copper.

[0238] As shown in Figures 46 to 48, each of the multiple second interconnections 724 has a top surface 724A and a side surface 724B. The top surface 724A is exposed on the second main surface 712A of the second layer 712. The side surface 724B is connected to the top surface 724A, and faces in a direction perpendicular to the thickness direction z. The side surface 724B is covered by the second layer 712.

[0239] 47, when viewed along the thickness direction z, the shortest distance L2 from the center C of the semiconductor element 730 to any one of the multiple second interconnecting wirings 724 is smaller than the shortest distance L1 from the center C of the semiconductor element 730 to any one of the multiple first interconnecting wirings 723. Here, the center C of the semiconductor element 730 refers to the intersection of the diagonals of the semiconductor element 730 when viewed along the thickness direction z.

[0240] As shown in FIG. 47 and FIG. 48, the semiconductor device A40 includes a plurality of first terminals 742. The plurality of first terminals 742 individually cover the bottom surfaces 723A of the plurality of first interconnections 723. The plurality of first terminals 742 are exposed to the outside of the semiconductor device A40. Each of the plurality of first terminals 742 is joined to a wiring board via solder, whereby the semiconductor device A40 is mounted on the wiring board. Each of the plurality of first terminals 742 includes a plurality of metal layers stacked in the thickness direction z with respect to the bottom surface 723A. The configuration of the plurality of metal layers is the same as the configuration of the plurality of metal layers included in each of the plurality of terminals 741 of the semiconductor device A10.

[0241] As shown in FIG. 45, FIG. 47, and FIG. 48, the semiconductor device A40 includes a plurality of second terminals 743. The plurality of second terminals 743 individually cover the top surfaces 724A of the plurality of second interconnections 724. The plurality of second terminals 743 are exposed to the outside of the semiconductor device A40. Each of the plurality of second terminals 743 is joined to a wiring board via solder, whereby the semiconductor device A40 is mounted on the wiring board. Each of the plurality of second terminals 743 includes a plurality of metal layers stacked in the thickness direction z with respect to the top surface 724A. The configuration of the plurality of metal layers is the same as the configuration of the plurality of metal layers included in each of the plurality of terminals 741 of the semiconductor device A10.

[0242] Next, the function and effect of the semiconductor device A40 will be described.

[0243] The semiconductor device A40 includes a sealing resin 710, a wiring 721, and a semiconductor element 730. The sealing resin 710 includes a first layer 711 having a first main surface 711A and a first back surface 711B, and a second layer 712 having a second main surface 712A and a second back surface 712B. The second back surface 712B is in contact with the first main surface 711A. The wiring 721 is in contact with the first main surface 711A. A part of the wiring 721 is covered by the second layer 712. The semiconductor element 730 is bonded to the wiring 721 and is covered by the second layer 712. Therefore, the semiconductor device A40 can also reduce the warpage of the semiconductor device A40 while achieving miniaturization.

[0244] The semiconductor device A40 includes a plurality of first interconnections 723 and a plurality of second interconnections 724 instead of the plurality of interconnections 722. Each of the plurality of first interconnections 723 extends from the interconnection 721 to the first back surface 711B of the first layer 711, and is partially covered by the first layer 711. Each of the plurality of first interconnections 723 has a bottom surface 723A exposed at the first back surface 711B. Each of the plurality of second interconnections 724 extends from the interconnection 721 to the second main surface 712A of the second layer 712, and is partially covered by the second layer 712. Each of the plurality of second interconnections 724 has a top surface 724A exposed at the second main surface 712A. This allows the semiconductor device A40 to be mounted on a wiring board with not only the first back surface 711B but also the second main surface 712A facing the wiring board. Therefore, the semiconductor device A40 can be mounted on the wiring board regardless of the orientation of the semiconductor device A40, thereby improving the efficiency of the mounting operation.

[0245] When viewed along the thickness direction z, the shortest distance L2 from the center C of the semiconductor element 730 to any one of the multiple second interconnects 724 is smaller than the shortest distance L1 from the center C of the semiconductor element 730 to any one of the multiple first interconnects 723. This allows a configuration in which the side surface 724B of each of the multiple second interconnects 724 is covered with the second layer 712. Here, the thickness of the second layer 712 is greater than the thickness of the first layer 711. Therefore, the height of each of the multiple second interconnects 724 is greater than the height of each of the multiple first interconnects 723, and therefore the volume of each of the multiple second interconnects 724 tends to be greater than the volume of each of the multiple first interconnects 723. Therefore, by adopting this configuration, it is possible to suppress a decrease in the dielectric strength voltage of the semiconductor device A40 caused by the multiple second interconnects 724.

[0246] The semiconductor device A40 includes a plurality of first terminals 742 and a plurality of second terminals 743 instead of the plurality of terminals 741. The plurality of first terminals 742 individually cover the bottom surfaces 723A of the plurality of first interconnecting wires 723. The plurality of second terminals 743 individually cover the top surfaces 724A of the plurality of second interconnecting wires 724. As a result, when the semiconductor device A40 is mounted on a wiring board, the solder adheres to either the plurality of first terminals 742 or the plurality of second terminals 743. Therefore, the plurality of first terminals 742 and the plurality of second terminals 743 can reduce the thermal shock caused by the solder acting on either the plurality of first interconnecting wires 723 or the plurality of second interconnecting wires 724.

[0247] The present invention is not limited to the semiconductor devices A10 to A40 described above. The specific configuration of each part of the present invention can be freely designed in various ways.

[0248] Hereinafter, embodiments of electronic components and methods for manufacturing electronic components will be described with reference to the drawings. Each embodiment shown below is an example of a configuration and method for embodying a technical idea, and the material, shape, structure, arrangement, dimensions, etc. of each component are not limited to those described below. Various modifications can be made to each of the following embodiments.

[0249] [Seventh embodiment] (Electronic component configuration) The configuration of an electronic component 801A according to a seventh embodiment of the present disclosure will be described with reference to Figs. 49 to 58. Note that, for convenience, in Figs. 49 and 51, the solder SD that joins the second functional element 860 and the sealing resin 840 is omitted. In Fig. 53, the second functional element 860 is shown by a two-dot chain line. In Fig. 55, the second functional element 860 is shown as a side structure rather than a cross-sectional structure for convenience. In Figs. 56 and 58, the second functional element 860 and the solder SD are omitted for convenience. Also, the solder SD is marked with a dot even when viewed from the side in order to easily distinguish it from other components.

[0250] As shown in Figs. 49 to 52, the electronic component 801A includes a substrate 810, which is an example of an insulating member, an internal electrode 820, a first functional element 830, a sealing resin 840, an external electrode 850, and a second functional element 860. The electronic component 801A is a component that is surface-mounted on a wiring board (not shown) of various electronic devices. As shown in Figs. 49 and 52, the first functional element 830 is disposed inside the sealing resin 840, and as shown in Figs. 49 to 51, the second functional element 860 is disposed in the sealing resin 840 outside the sealing resin 840. The sealing resin 840 is layered on the substrate 810. The second functional element 860 is layered on the sealing resin 840. As shown in Fig. 52, in the electronic component 801A of this embodiment, the internal electrode 820 is drawn outward from the first functional element 830, so that the external electrode 850 is located outside the first functional element 830.

[0251] In the following description, for convenience, the thickness direction of the substrate 810 is referred to as the thickness direction z. Furthermore, among the directions perpendicular to the thickness direction z, two directions perpendicular to each other are referred to as the first direction x and the second direction y, respectively.

[0252] 49 and 52, the substrate 810 is a support member on which the first functional element 830 is mounted and which serves as a base for the electronic component 801A. As shown in Fig. 52, in this embodiment, the shape of the substrate 810 as viewed in the thickness direction z is a substantially square having a pair of sides along the first direction x and a pair of sides along the second direction y.

[0253] The shape of the substrate 810 as viewed in the thickness direction z is not limited to a square and can be arbitrarily changed. In one example, the shape of the substrate 810 as viewed in the thickness direction z is a rectangle whose long side is in either the first direction x or the second direction y and whose short side is in the other of the first direction x and the second direction y.

[0254] As shown in FIG. 52 and FIG. 55, the substrate 810 has a substrate main surface 810s which is an example of an insulating main surface, a substrate back surface 810r which is an example of an insulating back surface, and a plurality of substrate side surfaces 811-814 which are an example of insulating side surfaces (four in this embodiment). As shown in FIG. 55, the substrate main surface 810s and the substrate back surface 810r face in opposite directions to each other in the thickness direction z. The substrate main surface 810s and the substrate back surface 810r are each flat. As shown in FIG. 52, the substrate side surfaces 811-814 are provided between the substrate main surface 810s and the substrate back surface 810r in the thickness direction z, and face in the first direction x or the second direction y. The substrate side surfaces 811, 812 face in opposite directions to each other in the second direction y, and extend along the first direction x when viewed from the thickness direction z. The substrate side surfaces 813, 814 are surfaces facing opposite each other in the first direction x, and extend along the second direction y when viewed from the thickness direction z.

[0255] In the following description, for convenience, the direction from the substrate back surface 810r toward the substrate main surface 810s in the thickness direction z is referred to as "upward," and the direction from the substrate main surface 810s toward the substrate back surface 810r is referred to as "downward." Therefore, the substrate main surface 810s can be said to be the upper surface of the substrate 810, and the substrate back surface 810r can be said to be the lower surface of the substrate 810.

[0256] As shown in FIG. 52, the substrate 810 is made of, for example, a material having electrical insulation. For example, synthetic resins mainly made of epoxy resin, ceramics, glass, etc. can be used as the material. In this embodiment, the substrate 810 is made of synthetic resins mainly made of epoxy resin. The substrate 810 has a plurality of recesses 815 recessed inward from each of the substrate side surfaces 811 to 814 so as to penetrate the substrate 810 in the thickness direction z. In this embodiment, the plurality of recesses 815 are provided four on each side of the substrate 810. The shape of each recess 815 as viewed from the thickness direction z is a rectangular recess. The shape of each of the four recesses 815 arranged near the substrate side surface 811 and the four recesses 815 arranged near the substrate side surface 812 as viewed from the thickness direction z is a rectangular recess with the short side in the first direction x and the long side in the second direction y. The four recesses 815 arranged near the substrate side surface 813 and the four recesses 815 arranged near the substrate side surface 814 each have a rectangular recess shape viewed in the thickness direction z with the long side extending in the first direction x and the short side extending in the second direction y.

[0257] The four recesses 815 provided on the substrate side surface 811 are formed so as to be outward of the first functional element 830 in the second direction y. The four recesses 815 provided on the substrate side surface 812 are formed so as to be outward of the first functional element 830 in the second direction y. The four recesses 815 provided on the substrate side surface 813 are formed so as to be outward of the first functional element 830 in the first direction x. The four recesses 815 provided on the substrate side surface 814 are formed so as to be outward of the first functional element 830 in the first direction x. In this way, the recesses 815 do not overlap with the first functional element 830 when viewed from the thickness direction z.

[0258] The substrate 810 has a through hole 816 penetrating the substrate 810 in the thickness direction z. The through hole 816 is provided in the center of the substrate 810 in the first direction x and the second direction y. When viewed from the thickness direction z, the through hole 816 overlaps with the first functional element 830. When viewed from the thickness direction z, the through hole 816 has a rectangular shape. In this embodiment, when viewed from the thickness direction z, the through hole 816 has a rectangular shape with a long side in the first direction x and a short side in the second direction y.

[0259] The shape of each recess 815 as viewed from the thickness direction z can be changed arbitrarily. The shape of each recess 815 as viewed from the thickness direction z can be a square concave shape, an arc shape, or the like, or a polygonal shape other than a rectangle. The shape of the through hole 816 as viewed from the thickness direction z can be changed arbitrarily. The shape of the through hole 816 as viewed from the thickness direction z can be a square, a circle, an ellipse, or the like, or a polygonal shape other than a rectangle.

[0260] 52, 54, and 55, the sealing resin 840 is provided so as to cover the entire substrate main surface 810s of the substrate 810. In other words, the sealing resin 840 overlaps the entire substrate 810 when viewed from the thickness direction z. As shown in FIG. 55, the sealing resin 840 covers the internal electrode 820 and the first functional element 830.

[0261] As shown in FIG. 49 to FIG. 53, the sealing resin 840 has a resin main surface 840s, which is an example of an element mounting surface, a resin back surface 840r, and a plurality of (four in this embodiment) resin side surfaces 841 to 844. The resin main surface 840s and the resin back surface 840r face in opposite directions to each other in the thickness direction z. The resin main surface 840s and the resin back surface 840r are both flat. The resin main surface 840s faces in the same direction as the substrate main surface 810s, and the resin back surface 840r faces in the same direction as the substrate back surface 810r. The resin side surfaces 841 to 844 are provided between the resin main surface 840s and the resin back surface 840r in the thickness direction z, and face in the first direction x or the second direction y. The resin side surfaces 841 and 842 face in opposite directions to each other in the second direction y, and extend along the first direction x when viewed from the thickness direction z. The resin side surface 841 faces the same direction as the substrate side surface 811 in the second direction y, and the resin side surface 842 faces the same direction as the substrate side surface 812 in the second direction y. The resin side surfaces 843 and 844 face opposite each other in the first direction x, and extend along the second direction y when viewed from the thickness direction z. The resin side surface 843 faces the same direction as the substrate side surface 813 in the first direction x, and the resin side surface 844 faces the same direction as the substrate side surface 814 in the first direction x. In this embodiment, a part of the thickness direction z of the resin side surface 841 is flush with the substrate side surface 811, a part of the thickness direction z of the resin side surface 842 is flush with the substrate side surface 812, a part of the thickness direction z of the resin side surface 843 is flush with the substrate side surface 813, and a part of the thickness direction z of the resin side surface 844 is flush with the substrate side surface 814.

[0262] As shown in Figs. 49 to 52, each of the resin side surfaces 841 to 844 of the sealing resin 840 has a step 845 recessed inward from the resin side surface 841 to 844. The step 845 divides the sealing resin 840 into a first resin portion 846 and a second resin portion 847 in the thickness direction z. The first resin portion 846 is a portion from the step 845 to the resin main surface 840s, and the second resin portion 847 is a portion from the step 845 to the resin back surface 840r. As shown in Figs. 49 to 52, the second resin portion 847 is a portion recessed inward from the first resin portion 846.

[0263] The sealing resin 840 is made of, for example, a resin material having electrical insulation properties. As the resin material, for example, a synthetic resin mainly composed of epoxy resin can be used. In this embodiment, the material constituting the substrate 810 is the same as the material constituting the sealing resin 840. Moreover, the sealing resin 840 is colored, for example, black. The sealing resin 840 is formed on the substrate main surface 810s by molding so as to cover the substrate main surface 810s of the substrate 810. Therefore, the resin back surface 840r is in contact with the substrate main surface 810s. More specifically, the resin back surface 840r and the substrate main surface 810s are melted and adhered to each other. In this way, the resin back surface 840r and the substrate main surface 810s become the interface between the substrate 810 and the sealing resin 840.

[0264] As shown in Fig. 51 and Fig. 53, an upper surface wiring 870 and an insulating film 873 are provided on the resin main surface 840s. The upper surface wiring 870 is a wiring electrically connected to the second functional element 860, and constitutes a part of a conductive path electrically connecting the second functional element 860 and the internal electrode 820. The upper surface wiring 870 is made of, for example, Cu, and is formed on the resin main surface 840s. The insulating film 873 is made of an electrically insulating material, for example, polyimide resin.

[0265] The upper surface wiring 870 has a first upper surface electrode 871 and a second upper surface electrode 872. The first upper surface electrode 871 and the second upper surface electrode 872 are arranged spaced apart from each other in a first direction x. The first upper surface electrode 871 and the second upper surface electrode 872 each extend in the first direction x. When viewed from the thickness direction z, the first upper surface electrode 871 and the second upper surface electrode 872 each have a rectangular shape whose long side direction is the first direction x and whose short side direction is the second direction y.

[0266] The first upper surface electrode 871 and the second upper surface electrode 872 are exposed from the insulating film 873. In other words, the insulating film 873 covers the resin main surface 840s and the portion of the upper surface wiring 870 other than the first upper surface electrode 871 and the second upper surface electrode 872.

[0267] 52 and 55, the internal electrode 820 has a plurality of (16 in this embodiment) main surface wirings 821, a plurality of (16 in this embodiment) through wirings 822, and a plurality of (2 in this embodiment) connecting conductors 823. The plurality of main surface wirings 821 are electrically connected to the plurality of through wirings 822 and the plurality of connecting conductors 823. Therefore, the plurality of main surface wirings 821, the plurality of through wirings 822, and the plurality of connecting conductors 823 are electrically connected to one another. In the following description, for convenience, in order to distinguish between the two connecting conductors 823, one connecting conductor 823 will be referred to as a first connecting conductor 823A, and the other connecting conductor 823 will be referred to as a second connecting conductor 823B.

[0268] Each through wiring 822 is a wiring that connects the external electrode 850 and the main surface wiring 821, and is disposed in each recess 815 and through hole 816. As shown in FIG. 52, the through wiring 822 disposed in each of the four recesses 815 provided on the substrate side surface 811 is formed so as to be located outside the first functional element 830 in the second direction y. The through wiring 822 disposed in each of the four recesses 815 provided on the substrate side surface 812 is formed so as to be located outside the first functional element 830 in the second direction y. The through wiring 822 disposed in each of the four recesses 815 provided on the substrate side surface 813 is formed so as to be located outside the first functional element 830 in the first direction x. The through wiring 822 disposed in each of the four recesses 815 provided on the substrate side surface 814 is formed so as to be located outside the first functional element 830 in the first direction x. In this manner, each through-wire 822 does not overlap with the first functional element 830 when viewed in the thickness direction z.

[0269] It should be noted that, for each through wiring 822 disposed in the recess 815 of the substrate 810, the positional relationship between each through wiring 822 and the first functional element 830 as viewed from the thickness direction z can be changed arbitrarily. In one example, a part of each through wiring 822 may overlap the first functional element 830 as viewed from the thickness direction z. In short, each through wiring 822 is preferably configured to extend outward beyond the first functional element 830 in a direction perpendicular to the thickness direction z.

[0270] In this embodiment, each through wiring 822 is provided separately from the main surface wiring 821. The shape of each through wiring 822 as viewed from the thickness direction z is determined according to the shape of each recess 815 and through hole 816 as viewed from the thickness direction z. In this embodiment, the shape of each through wiring 822 as viewed from the thickness direction z is rectangular. Each through wiring 822 is made of a material having electrical conductivity. For example, Cu, Cu alloy, etc. can be used as the material of each through wiring 822. In this embodiment, each through wiring 822 includes a plating layer.

[0271] 55, each through wire 822 has a main surface 822s, a back surface 822r, and a plurality of (four in this embodiment) side surfaces 822x. Each through wire 822 penetrates the substrate 810 in the thickness direction z.

[0272] The main surface 822s and the back surface 822r face in opposite directions to each other in the thickness direction z. The main surface 822s faces in the same direction as the substrate main surface 810s, and is flush with the substrate main surface 810s in this embodiment. The back surface 822r faces in the same direction as the substrate back surface 810r, and is flush with the substrate back surface 810r in this embodiment. In this manner, the main surface 822s is exposed from the substrate main surface 810s, and the back surface 822r is exposed from the substrate back surface 810r.

[0273] Each side surface 822x is provided between the main surface 822s and the back surface 822r in the thickness direction z, and faces the first direction x or the second direction y. One of the four side surfaces 822x of the through wiring 822 arranged in each recess 815 forms an exposed side surface 822xa exposed from the substrate side surfaces 811 to 814 of the substrate 810. The four side surfaces 822x of the through wiring 822 arranged in the through hole 816 are each surrounded by the substrate 810. That is, the four side surfaces 822x of the through wiring 822 arranged in the through hole 816 are not exposed.

[0274] Each of the main surface wirings 821 is formed on a substrate main surface 810s of the substrate 810. It can also be said that each of the main surface wirings 821 is provided in a second resin portion 847 of the sealing resin 840. Each of the main surface wirings 821 is made of a material having electrical conductivity. For example, Cu, a Cu alloy, or the like can be used as the material of each of the main surface wirings 821. In this embodiment, each of the main surface wirings 821 includes a plating layer.

[0275] The multiple main surface wirings 821 include multiple main surface wirings 821 extending in a first direction x and multiple main surface wirings 821 extending in a second direction y. The multiple main surface wirings 821 extending in the first direction x are arranged at a distance from each other in the second direction y, and the multiple main surface wirings 821 extending in the second direction y are arranged at a distance from each other in the first direction x. The thickness of each main surface wiring 821 (the dimension of each main surface wiring 821 in the thickness direction z) is thinner than the thickness of each through wiring 822 (the dimension of each through wiring 822 in the thickness direction z). In other words, the thickness of each through wiring 822 is thicker than the thickness of each main surface wiring 821.

[0276] Each main surface wiring 821 has a wiring main surface 821s, a wiring back surface 821r, and a wiring side surface 821x. The wiring main surface 821s faces the same direction as the substrate main surface 810s. The wiring back surface 821r faces the same direction as the substrate back surface 810r and faces the substrate main surface 810s. The wiring side surface 821x is provided between the wiring main surface 821s and the wiring back surface 821r in the thickness direction z and faces the same direction as the substrate side surfaces 811 to 814. Of the wiring side surface 821x, the wiring side surface 821xa facing the same direction as the exposed side surface 822xa of the through wiring 822 is exposed from the resin side surfaces 841 to 844. The wiring side surface 821xa is flush with the exposed side surface 822xa.

[0277] 55, the main surface wiring 821 is disposed so as to cover the through wiring 822 from above. Therefore, the wiring back surface 821r is in contact with the main surface 822s of the through wiring 822. This electrically connects the main surface wiring 821 and the through wiring 822. In this manner, the through wiring 822 extends from the wiring back surface 821r to the substrate back surface 810r in the thickness direction z, and can also be said to be exposed from the substrate back surface 810r.

[0278] The main surface wiring 821 extending in the first direction x has inner portions 821p that extend further inward in the first direction x of the substrate 810 than the through wiring 822 arranged in the recess 815 of the substrate 810. The main surface wiring 821 extending in the second direction y has inner portions 821p that extend further inward in the second direction y of the substrate 810 than the through wiring 822 arranged in the recess 815. Tip portions of these inner portions 821p overlap the outer periphery of the first functional element 830 when viewed from the thickness direction z.

[0279] The main surface wiring 821 has main surface wiring 821 electrically connected to a through wiring 822 disposed in a through hole 816 of the substrate 810. This main surface wiring 821 covers a main surface 822s of the through wiring 822. The dimensions of this main surface wiring 821 in the first direction x and the dimensions of the through wiring 822 in the first direction x and the second direction y are the same as the dimensions of the through wiring 822 in the first direction x and the second direction y.

[0280] 56, the main surface wiring 821 includes a metal layer 821a and a conductive layer 821b. The metal layer 821a and the conductive layer 821b are laminated in this order on the substrate main surface 810s.

[0281] The metal layer 821a is made of, for example, a Ti (titanium) layer in contact with the substrate main surface 810s and the main surface 822s of the through wiring 822, and a Cu layer in contact with the Ti layer. The metal layer 821a is formed as a seed layer for forming the conductive layer 821b. The metal layer 821a has an upper surface 821as and a lower surface 821ar facing in opposite directions in the thickness direction z. The lower surface 821ar constitutes the wiring back surface 821r of the main surface wiring 821.

[0282] The conductive layer 821b is formed on an upper surface 821as of the metal layer 821a. The conductive layer 821b is made of Cu or a Cu alloy. The conductive layer 821b has an upper surface 821bs and a lower surface 821br that face opposite to each other in the thickness direction z. In this embodiment, the lower surface 821br of the conductive layer 821b is in contact with the upper surface 821as of the metal layer 821a. The upper surface 821bs of the conductive layer 821b is covered by a second resin portion 847 of the sealing resin 840. The upper surface 821bs of the conductive layer 821b constitutes the wiring main surface 821s of the main surface wiring 821.

[0283] As shown in FIG. 55, the first connection conductor 823A extends in the thickness direction z from a wiring main surface 821s of one of the multiple main surface wirings 821 closer to the substrate side surface 811 in the first direction x. As shown in FIG. 52, the first connection conductor 823A is connected to a main surface wiring 821 that is closest to the substrate side surface 814 in the second direction y among the multiple main surface wirings 821 closer to the substrate side surface 811 in the first direction x. As shown in FIG. 55, the second connection conductor 823B extends in the thickness direction z from a wiring main surface 821s of one of the multiple main surface wirings 821 closer to the substrate side surface 812. As shown in FIG. 52, the second connection conductor 823B is connected to a main surface wiring 821 that is closest to the substrate side surface 813 in the second direction y among the multiple main surface wirings 821 closer to the substrate side surface 812 in the first direction x.

[0284] Each of the connecting conductors 823A, 823B is disposed closer to the through wiring 822 than the first functional element 830 in the inner portion 821p of the main surface wiring 821. Each of the connecting conductors 823A, 823B is disposed more inward than the through wiring 822 when viewed from the thickness direction z. Specifically, as shown in Fig. 55, each of the connecting conductors 823A, 823B is disposed in a portion of the inner portion 821p of the main surface wiring 821 between the through wiring 822 and the first functional element 830 when viewed from the thickness direction z.

[0285] As shown in Fig. 52 and Fig. 53, the shape of each of the connecting conductors 823A, 823B is rectangular when viewed from the thickness direction z. That is, each of the connecting conductors 823A, 823B is a prism. The shape of each of the connecting conductors 823A, 823B is not limited to this, and may be, for example, a cylinder or a polygonal prism. Each of the connecting conductors 823A, 823B is made of a material having electrical conductivity. For example, Cu, Cu alloy, etc. can be used as the material of each of the connecting conductors 823A, 823B. In this embodiment, each of the connecting conductors 823A, 823B includes a plating layer.

[0286] As shown in Fig. 55, each of the connecting conductors 823A, 823B has an upper surface 823s, a lower surface 823r, and a side surface 823x. The upper surface 823s of each of the connecting conductors 823A, 823B faces the same direction as the substrate main surface 810s, and the lower surface 823r of each of the connecting conductors 823A, 823B faces the same direction as the substrate back surface 810r. The side surface 823x of each of the connecting conductors 823A, 823B is provided between the upper surface 823s and the lower surface 823r in the thickness direction z, and faces the first direction x or the second direction y. The side surface 823x of each of the connecting conductors 823A, 823B is entirely covered with a sealing resin 840.

[0287] A lower surface 823r of each of the connecting conductors 823A and 823B is a surface that contacts the wiring main surface 821s of the main surface wiring 821. This lower surface 823r is flat.

[0288] Each of the connecting conductors 823A, 823B extends from the wiring principal surface 821s to the resin principal surface 840s in the thickness direction z. Therefore, the upper surface 823s of each of the connecting conductors 823A, 823B is exposed from the resin principal surface 840s. In this embodiment, as shown in Fig. 58, the upper surface 823s of the first connecting conductor 823A is formed to be concave in a curved shape. Although not shown, the upper surface 823s of the second connecting conductor 823B is also formed to be concave in a curved shape.

[0289] As shown in FIG. 53, the first connection conductor 823A is electrically connected to a first upper surface electrode 871 of the upper surface wiring 870. Specifically, an upper surface 823s of the first connection conductor 823A overlaps with the first upper surface electrode 871 of the upper surface wiring 870 when viewed from the thickness direction z, and is in contact with the first upper surface electrode 871. The second connection conductor 823B is electrically connected to a second upper surface electrode 872 of the upper surface wiring 870. Specifically, an upper surface 823s of the second connection conductor 823B overlaps with the second upper surface electrode 872 of the upper surface wiring 870 when viewed from the thickness direction z, and is in contact with the second upper surface electrode 872. In this manner, the upper surface wiring 870 is electrically connected to the connection conductor 823.

[0290] 56, the first connecting conductor 823A is made of a seed layer 823a and a plating layer 823b stacked on top of each other. The seed layer 823a is made of a first layer in contact with an upper surface 821bs (the wiring main surface 821s of the main surface wiring 821) of the conductive layer 821b, and a second layer in contact with the first layer. The first layer is mainly composed of Ti, for example, and the second layer is mainly composed of Cu, for example. The thickness of the seed layer 823a (the dimension in the thickness direction z of the seed layer 823a) is about 200 nm or more and 8800 nm or less. The plating layer 823b is mainly composed of Cu.

[0291] The seed layer 823a has an upper surface 823as and a lower surface 823ar that face in opposite directions in the thickness direction z. The upper surface 823as faces in the same direction as the substrate main surface 810s, and the lower surface 823ar faces in the same direction as the substrate back surface 810r. The lower surface 823ar of the seed layer 823a constitutes the lower surface 823r of the connection conductor 823.

[0292] The plating layer 823b has an upper surface 823bs and a lower surface 823br facing opposite to each other in the thickness direction z. The upper surface 823bs faces the same direction as the substrate main surface 810s, and the lower surface 823br faces the same direction as the substrate back surface 810r. The lower surface 823br of the plating layer 823b is in contact with an upper surface 823as of the seed layer 823a. The upper surface 823bs of the plating layer 823b forms the upper surface 823s of the connecting conductor 823. The second connecting conductor 823B has the same configuration as the first connecting conductor 823A shown in FIG.

[0293] As shown in Fig. 49 and Fig. 52, the first functional element 830 is a flat chip component. The first functional element 830 includes a semiconductor element. In this embodiment, the first functional element 830 is an integrated circuit (IC) such as an LSI (Large Scale Integration). More specifically, the first functional element 830 is a switching power supply LSI. The first functional element 830 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a discrete semiconductor element such as a diode or various sensors.

[0294] As shown in FIG. 49 and FIG. 55, the size of the first functional element 830 is smaller than the size of the second functional element 860. Specifically, the dimension of the first functional element 830 in the thickness direction z is smaller than the dimension of the second functional element 860 in the thickness direction z. The dimension of the first functional element 830 in the thickness direction z is 100 μm or more and 300 μm or less. When the first functional element 830 is an LSI, the dimension of the LSI in the thickness direction z is, for example, about 100 μm. The dimension of the first functional element 830 in the first direction x is smaller than the dimension of the second functional element 860 in the first direction x. The dimension of the first functional element 830 in the second direction y is smaller than the dimension of the second functional element 860 in the second direction y.

[0295] The shape of the first functional element 830 as viewed in the thickness direction z is substantially square. As shown in Fig. 55, the first functional element 830 has an element main surface 830s and an element back surface 830r that face opposite each other in the thickness direction z. The element main surface 830s is a surface on which components for the function of the first functional element 830 are formed. The element main surface 830s faces in the same direction as the substrate back surface 810r of the substrate 810. The element back surface 830r faces in the same direction as the substrate main surface 810s of the substrate 810.

[0296] The first functional element 830 has an element substrate 831, a plurality of electrode pads 832, wiring 833, an insulating film 834A, and a protective film 834B.

[0297] 57, recesses 831b in which electrodes 831a of the element substrate 831 are exposed are formed in the element substrate 831. A plurality of electrodes 831a and a plurality of recesses 831b are provided.

[0298] The insulating film 834A covers the surface (element principal surface 830s) of the element substrate 831. The insulating film 834A penetrates in the thickness direction z to form a recess 831b. In this embodiment, the insulating film 834A is made of an electrically insulating material, for example, SiO 2 (silicon oxide). The insulating film 834A covers a part of the electrode pad 832, and a part of the surface of the electrode pad 832 is exposed as a connection terminal. The insulating film 834A may be made of SiN (silicon nitride).

[0299] A plurality of wirings 833 are formed on the element main surface 830s so as to be individually connected to each electrode 831a. Each wiring 833 is formed on the surface of the insulating film 834A. Each wiring 833 is also formed in the recess 831b, thereby being connected to each electrode 831a. Each wiring 833 is made of, for example, Cu.

[0300] Protective film 834B covers the surface of insulating film 834A and also covers the surfaces of each wiring 833. Protective film 834B also covers the periphery of electrode pad 832. That is, each electrode pad 832 protrudes downward from protective film 834B. Protective film 834B is made of an electrically insulating material, such as polyimide resin.

[0301] Each electrode pad 832 is a terminal for electrically connecting to the main surface wiring 821, and is connected to each wiring 833. In this manner, each electrode 831a of the element substrate 831 is electrically connected to the main surface wiring 821 via each electrode pad 832 and each wiring 833.

[0302] Each electrode pad 832 is disposed at a position different from each recess 831b in a direction perpendicular to the thickness direction z (plane direction of the element principal surface 830s). Each electrode pad 832 has a conductive part 832a and a barrier layer 832b stacked on each other in the thickness direction z. The conductive part 832a is made of, for example, Cu. The barrier layer 832b is made of a Ni layer. The barrier layer 832b is stacked so as to cover the tip surface of the conductive part 832a. A solder layer 835 is stacked on the end surface of the barrier layer 832b opposite to the end surface on the conductive part 832a side among both end surfaces in the thickness direction z. By providing the barrier layer 832b in each electrode pad 832, it is possible to suppress the conductive part 832a made of Cu from penetrating into the solder layer 835. The barrier layer 832b may be composed of a Ni layer, a Pd (palladium) layer, and an Au (gold) layer stacked on each other. The barrier layer 832b may be omitted.

[0303] As shown in FIG. 57, a barrier layer 881 is formed on a portion of the wiring main surface 821s of the main surface wiring 821 facing the solder layer 835 in the thickness direction z. The barrier layer 881 is made of a Ni layer. This barrier layer 881 can suppress the solder layer 835 from spreading. The barrier layer 881 may be made of a Ni layer, a Pd layer, and an Au layer stacked on top of each other. In this manner, the solder layer 835 and the barrier layer 881 form a joint 880 that joins the main surface wiring 821 and the electrode pad 832 of the first functional element 830.

[0304] 55, the first functional element 830 is connected to the main surface wiring 821 via a solder layer 835. The solder layer 835 is made of an alloy containing Su (tin) or Sn. This alloy is, for example, an Sn-Ag based alloy, an Sn-Sb (antimony) based alloy, or the like. In this manner, the electrode pad 832 is joined to the main surface wiring 821 via the solder layer 835, whereby the first functional element 830 is mounted on the main surface wiring 821.

[0305] 50, 52, and 54, external electrode 850 serves as an external connection terminal for connecting electronic component 801A to a wiring board. External electrode 850 is made of, for example, a plurality of metal layers stacked on top of each other. The metal layers are, for example, Ni layers, Pd layers, and Au layers.

[0306] The external electrodes 850 are provided in accordance with the through wirings 822. More specifically, as shown in FIG. 52, the external electrodes 850 are provided on each of the four through wirings 822 that are provided close to the substrate side surface 811 and arranged at a distance from each other in the first direction x. In this case, the four external electrodes 850 are arranged at a distance from each other in the first direction x. The external electrodes 850 are provided on each of the four through wirings 822 that are provided close to the substrate side surface 812 and arranged at a distance from each other in the first direction x. In this case, the four external electrodes 850 are arranged at a distance from each other in the first direction x. The external electrodes 850 are provided on each of the four through wirings 822 that are provided close to the substrate side surface 813 and arranged at a distance from each other in the second direction y. In this case, the four external electrodes 850 are arranged at a distance from each other in the second direction y. An external electrode 850 is provided on each of the four through-wires 822 provided close to the substrate side surface 814 and arranged at a distance from one another in the second direction y. In this case, the four external electrodes 850 are arranged at a distance from one another in the second direction y. An external electrode 850 is provided on the through-wire 822 provided at the center of the substrate back surface 810r in the first direction x and the second direction y. Each external electrode 850 covers the back surface 822r of each through-wire 822.

[0307] As shown in FIG. 55, the second functional element 860 is an element having a relatively large dimension in the thickness direction z, such as a resistor, a capacitor, an inductor, or a diode. In this embodiment, the second functional element 860 is an inductor used in a power supply circuit, a so-called power supply inductor. In the illustrated example, the second functional element 860 is configured such that a winding metal alloy capable of handling a large current is sealed with a sealing resin. The second functional element 860 has a first electrode 861 and a second electrode 862. In the illustrated example, the second functional element 860 is a surface mount type package. The dimension of the second functional element 860 in the first direction x is about 6.6 mm, the dimension of the second functional element 860 in the second direction y is about 7.0 mm, and the dimension of the second functional element 860 in the thickness direction z is about 3.0 mm.

[0308] When an inductor is used for the second functional element 860, the configuration of the inductor is not limited to this. For example, a wound ferrite or multilayer ferrite inductor may be used. The external shape of the inductor is not limited to the example shown in the figure, and may be a rectangular plate shape or a box shape that is square when viewed from the thickness direction z.

[0309] As shown in FIG. 51 and FIG. 55, the second functional element 860 is connected to the upper surface wiring 870. More specifically, the first electrode 861 of the second functional element 860 is joined to the first upper surface electrode 871 of the upper surface wiring 870 by solder SD, and the second electrode 862 of the second functional element 860 is joined to the second upper surface electrode 872 of the upper surface wiring 870 by solder SD. In this way, the second functional element 860 is electrically connected to the first functional element 830. As shown in FIG. 55, the internal electrode 820 and the upper surface wiring 870 form a conductive path that electrically connects the first functional element 830 and the second functional element 860. In addition, the second functional element 860 is electrically connected to the external electrode 850 via the upper surface wiring 870 and the internal electrode 820.

[0310] In this embodiment, electronic component 801A is a power supply module in which an inductor, which is a second functional element 860, is electrically connected to a switching power supply LSI, which is a first functional element 830. Therefore, electronic component 801A is applied to a power supply circuit. In this way, the switching power supply LSI and the inductor are modularized by electronic component 801A, so that the power supply circuit can be made smaller.

[0311] (Electronic component manufacturing method) A manufacturing method for an electronic component 801A according to the seventh embodiment of the present disclosure will be described with reference to Figures 59 to 78. In Figures 59 to 62, 64, 65, 67, and 69 to 73, two adjacent dashed lines indicate an area in which one electronic component 801A is formed. The definitions of the directions shown in Figures 59 to 78 are the same as those shown in Figures 49 to 58.

[0312] 59, the manufacturing method of electronic component 801A includes a step of preparing support substrate 1600. Support substrate 1600 is made of, for example, a single crystal intrinsic semiconductor. Support substrate 1600 is made of, for example, a single crystal material such as Si. Support substrate 1600 has upper surface 1601 and lower surface 1602 facing opposite sides in thickness direction z. Note that support substrate 1600 may be made of a substrate made of a composite resin material such as epoxy resin.

[0313] The method for manufacturing electronic component 801A includes a step of forming terminal pillars 1622 on upper surface 1601 of support substrate 1600. Terminal pillars 1622 are made of, for example, Cu or a Cu alloy, and are formed by electrolytic plating.

[0314] More specifically, the terminal pillar 1622 is formed through, for example, a step of forming a seed layer, a step of forming a mask on the seed layer by photolithography, and a step of forming the terminal pillar 1622 in contact with the seed layer. Specifically, a seed layer is formed on the upper surface 1601 of the support substrate 1600 by, for example, a sputtering method. Next, the seed layer is covered with, for example, a photosensitive resist layer, and the resist layer is exposed to light and developed to form a mask having an opening. Next, a plating metal is deposited on the surface of the seed layer exposed from the mask by an electrolytic plating method using the seed layer as a conductive path, to form the terminal pillar 1622. After the terminal pillar 1622 is formed, the mask is removed. The terminal pillar 1622 may be formed of a Cu columnar material.

[0315] The manufacturing method of electronic component 801A includes a step of forming substrate 1610, which is an example of an insulating layer. More specifically, as shown in FIG. 60, substrate 1610 is formed in contact with upper surface 1601 of support substrate 1600 and covering terminal pillar 1622. Substrate 1610 is formed so as to cover the upper surface of terminal pillar 1622. The material of substrate 1610 may be the material constituting substrate 810 shown in FIG. 49. In this embodiment, synthetic resin containing epoxy resin or the like as a main component is used as the material of substrate 1610. In this manner, the manufacturing method of electronic component 801A may be said to include an insulating layer forming step.

[0316] The manufacturing method of electronic component 801A includes a step of grinding substrate 1610 and terminal pillar 1622. More specifically, by grinding a part of substrate 1610 and terminal pillar 1622, terminal pillar 1622 is exposed on upper surface 1611 of substrate 1610. In this step, upper surface 1622s of terminal pillar 1622 constitutes main surface 822s of through wiring 822. Also in this step, substrate 1610 has upper surface 1611 constituting an insulating main surface and lower surface 1612 constituting an insulating back surface. Substrate 1610 is to become substrate 810 shown in FIG. 55. In grinding substrate 1610, substrate 1610 is made to have the same thickness as substrate 810. Terminal pillar 1622 is made to have the same thickness as through wiring 822. 60, some of the terminal pillars 1622 (terminal pillars 1622 arranged between adjacent dashed lines in the second direction y) form through wirings 822. In this manner, the manufacturing method for electronic component 801A can be said to include a step of forming a plurality of through wirings 822.

[0317] The manufacturing method of electronic component 801A includes a step of forming main surface wiring 1621. More specifically, as shown in Fig. 62, main surface wiring 1621 is formed on upper surface 1611 of substrate 1610 and upper surface 1622s of terminal pillar 1622 (main surface 822s of through wiring 822). As shown in Fig. 63, main surface wiring 1621 includes metal layer 1621a and conductive layer 1621b. Main surface wiring 1621 is formed through a step of forming metal layer 1621a, a step of forming a mask on metal layer 1621a by photolithography, and a step of forming conductive layer 1621b in contact with metal layer 1621a.

[0318] More specifically, first, metal layer 1621a is formed by, for example, a sputtering method. For example, metal layer 1621a including a Ti layer and a Cu layer is formed by forming a Ti layer on upper surface 1611 of base material 1610 and main surface 822s of through wiring 822, and forming a Cu layer in contact with the Ti layer. Next, metal layer 1621a is covered with, for example, a photosensitive resist layer, and the resist layer is exposed and developed to form a mask having an opening. Next, plating metal is deposited on the surface of metal layer 1621a exposed from the mask by, for example, an electrolytic plating method using metal layer 1621a as a conductive path, to form conductive layer 1621b. Through these steps, main surface wiring 1621 is formed. After main surface wiring 1621 is formed, the mask is removed. In this way, the manufacturing method of electronic component 801A can be said to include a main surface wiring forming step.

[0319] 64 to 66, the method for manufacturing electronic component 801A includes a step of forming connecting conductor 1623. More specifically, connecting conductor 1623 is formed on upper surface 1621s of main surface wiring 1621, as shown in FIGS.

[0320] The connecting conductor 1623 is formed, for example, through a step of forming a seed layer, a step of forming a mask on the seed layer by photolithography, and a step of forming a plating layer in contact with the seed layer.

[0321] 64, a seed layer 1623a is formed on an upper surface 1621s of the main surface wiring 1621 and an upper surface 1611 of the base material 1610 by, for example, a sputtering method. Next, the seed layer 1623a is covered with, for example, a photosensitive resist layer, and the resist layer is exposed to light and developed to form a mask having an opening.

[0322] Next, as shown in Fig. 66, a plating metal is deposited on the surface of the seed layer 1623a exposed from the mask by electrolytic plating using the seed layer 1623a as a conductive path, forming a plating layer 1623b. This forms a connecting conductor 1623 made of a laminate of the seed layer 1623a and the plating layer 1623b. After the connecting conductor 1623 is formed, the mask is removed. The connecting conductor 1623 may be formed of a Cu columnar material.

[0323] Next, as shown in FIG. 66, the unnecessary seed layer 1623a is removed. Specifically, the seed layer 1623a is removed except for the portion of the seed layer 1623a covered with the plating layer 1623b. The unnecessary seed layer 1623a is removed by, for example, H 2 SO 4 In this way, the method for producing electronic component 801A can be said to include a conductor forming step.

[0324] As shown in FIG. 67 and FIG. 68, the manufacturing method of electronic component 801A includes a step of forming joint 880. More specifically, as shown in FIG. 67, joint 880 is formed on upper surface 1621s of main surface wiring 1621. As shown in FIG. 68, joint 880 includes barrier layer 881 and solder layer 1682. First, barrier layer 881 is formed on upper surface 1621s of main surface wiring 1621. Barrier layer 881 can be formed by, for example, electrolytic plating using main surface wiring 1621 as a conductive path. Next, solder layer 1682 is formed by precipitating an alloy containing Sn as a plating metal on upper surface 881s of barrier layer 881 by electrolytic plating. Thereafter, solder layer 1682 is melted by reflow processing to smooth the surface of solder layer 1682 having roughness. This smoothing makes it possible to prevent the occurrence of voids when solder layer 1682 is joined to a solder layer (not shown) of first functional element 830. Note that solder layer 1682 shown in Figures 67 and 68 shows the state after reflow treatment.

[0325] The manufacturing method of electronic component 801A includes a step of mounting first functional element 830. More specifically, as shown in Fig. 69, first functional element 830 is mounted on main surface wiring 1621. Mounting of first functional element 830 is performed by flip chip bonding (FCB).

[0326] Specifically, first, a solder layer (not shown) is formed by depositing an alloy containing Sn as a plating metal on the barrier layer 832b of the electrode pad 832 of the first functional element 830, for example, by electrolytic plating. This solder layer is made of the same material as the solder layer 1682 (see FIG. 68) of the joint 880. The surface of the solder layer of the first functional element 830 is also smoothed by a reflow process, similar to the above-mentioned solder layer 1682.

[0327] Next, for example, flux is applied to the joint 880, and then the first functional element 830 is mounted on the joint 880 using, for example, a flip chip bonder. As a result, the first functional element 830 is temporarily attached to the joint 880. Thereafter, the solder layer 1682 of the joint 880 and the solder layer of the first functional element 830 are each put into a liquid phase state by a reflow process, and then the solder layer 1682 of the joint 880 and the solder layer of the first functional element 830 are solidified by cooling, thereby connecting the first functional element 830 to the joint 880. Therefore, the solder layer 835 shown in FIG. 57 is composed of the solder layer 1682 of the joint 880 and the solder layer of the first functional element 830. In this way, it can be said that the manufacturing method of the electronic component 801A includes a first element mounting process.

[0328] The manufacturing method of electronic component 801A includes a step of forming resin layer 1640. More specifically, as shown in FIG. 70, resin layer 1640 is formed so as to cover upper surface 1611 of substrate 1610, main surface wiring 1621, connecting conductor 1623, and first functional element 830. Resin layer 1640 is a member that becomes sealing resin 840 shown in FIG. 49. Resin layer 1640 is, for example, a synthetic resin whose main component is epoxy resin. For example, resin layer 1640 is formed by transfer molding. In this way, it can be said that the manufacturing method of electronic component 801A includes a resin layer forming step.

[0329] The manufacturing method of electronic component 801A includes a step of cutting resin layer 1640 and connecting conductor 1623 so as to reduce the thickness of resin layer 1640 and connecting conductor 1623. More specifically, as shown in FIG. 71, resin main surface 1640s of resin layer 1640 is ground by, for example, a chemical mechanical polishing (CMP) method using an abrasive (abrasive grains) until connecting conductor 1623 is exposed from resin layer 1640. In this step, resin main surface 1640s of resin layer 1640 and upper surface of connecting conductor 1623 are ground until the dimension of connecting conductor 1623 in thickness direction z becomes a predetermined dimension. Thus, connecting conductor 823 is formed. FIG. 71 shows the state after grinding. As shown in FIG. 71, upper surface 823s of connecting conductor 823 is exposed from resin main surface 1640s of resin layer 1640. In this step, the shape of upper surface 823s of connecting conductor 823 becomes the same as the shape of upper surface 823s of connecting conductor 823 shown in FIG. 58. Furthermore, the shape of resin main surface 1640s of resin layer 1640 becomes the same as the shape of resin main surface 40s of sealing resin 840 shown in FIG. 58. That is, grinding marks are formed on resin main surface 1640s due to grinding. Therefore, resin main surface 1640s corresponds to the cut surface of resin layer 1640. In this way, it can be said that the manufacturing method of electronic component 801A includes a resin layer cutting step.

[0330] The manufacturing method of electronic component 801A includes a step of forming upper surface wiring 870 and insulating film 873. More specifically, as shown in FIG. 72, upper surface wiring 870 is formed on resin main surface 1640s of resin layer 1640 and upper surface 823s of connecting conductor 823. This step can also be said to form upper surface wiring 870 on the cut surface of resin layer 1640. The method of forming upper surface wiring 870 is, for example, the same as the method of forming main surface wiring 1621. An insulating film 873 is formed on a portion of resin main surface 1640s of resin layer 1640 other than first upper surface electrode 871 and second upper surface electrode 872 of upper surface wiring 870. In the step of forming insulating film 873, for example, a spin coater (spin coating device) is used to apply insulating film 873 to resin main surface 1640s of resin layer 1640. Note that a film-like photosensitive resin material may be attached. Then, the photosensitive resin material is exposed to light and developed to perform patterning. This causes first upper surface electrode 871 and second upper surface electrode 872 of upper surface wiring 870 to be exposed from insulating film 873. In this way, it can be said that the method for manufacturing electronic component 801A includes an upper surface wiring forming step and an insulating film forming step.

[0331] The manufacturing method of electronic component 801A includes a step of removing support substrate 1600. In this embodiment, as shown in FIG. 73, support substrate 1600 is removed by grinding. Note that FIG. 73 is shown upside down with respect to FIG. 72. As another method of this step, base material 1610 may be made thicker than substrate 810 shown in FIG. 55, and in the grinding step of support substrate 1600, after grinding support substrate 1600, base material 1610 and terminal pillar 1622 may be ground to make the thickness of base material 1610 equal to the thickness of substrate 810. Alternatively, a peeling film may be formed in advance, and support substrate 1600 may be removed by a peeling method.

[0332] The manufacturing method of electronic component 801A includes a step of cutting base material 1610 and half-cutting resin layer 1640. More specifically, as shown in FIG. 74, first, dicing tape DT is attached to the lower surface of resin layer 1640. Next, base material 1610 is cut and a part of resin layer 1640 in thickness direction z is cut (half-cut). When cutting base material 1610 and half-cutting resin layer 1640, a dicing blade is used to make a cut from base material 1610 toward dicing tape DT along a cutting line (broken line) shown in FIG. 73. By half-cutting resin layer 1640 in this way, separation groove 1645 is formed in resin layer 1640 as shown in FIG. 74. In this step, substrate 810, through-hole wiring 822, and main surface wiring 821 are formed by cutting base material 1610. In this way, the manufacturing method of electronic component 801A can be said to include a cutting step. Also, it can be said that the manufacturing method of electronic component 801A includes a first cutting step.

[0333] The manufacturing method of electronic component 801A includes a step of forming external electrode 850. More specifically, as shown in Fig. 75, external electrode 850 is formed on back surface 822r of each through-wire 822 exposed from base material 1610. External electrode 850 is made of a plating metal. For example, external electrode 850 is formed by precipitating plating metals, such as Ni, Pd, and Au, in this order, by electroless plating.

[0334] The manufacturing method of electronic component 801A includes a step of dividing first functional element 830 into individual pieces each having a unit. More specifically, as shown in FIG. 76, a dicing blade narrower than the dicing blade that half-cuts resin layer 1640 is used to cut from separation groove 1645 of resin layer 1640 to dicing tape DT, and resin layer 1640 is cut. In this case, resin layer 1640 is cut along a cutting line (broken line) shown in FIG. 73. As a result, sealing resin 840 having a step 845 is formed. The individual piece is an electronic component including substrate 810, sealing resin 840, and first functional element 830. In this way, the manufacturing method of electronic component 801A can also be said to include a cutting step. In addition, the manufacturing method of electronic component 801A can also be said to include a second cutting step.

[0335] The manufacturing method of electronic component 801A includes a step of mounting second functional element 860. More specifically, as shown in Fig. 77, solder SD is applied to each of first upper surface electrode 871 and second upper surface electrode 872 of upper surface wiring 870. As a method of forming solder SD, the solder SD may be formed by precipitating an alloy containing Sn as a plating metal on first upper surface electrode 871 and second upper surface electrode 872.

[0336] Next, second functional element 860 is mounted on the solder SD formed on first upper surface electrode 871 and second upper surface electrode 872. As a result, second functional element 860 is temporarily attached to first upper surface electrode 871 and second upper surface electrode 872. Thereafter, solder SD is melted by a reflow process, and then solidified by cooling. As a result, second functional element 860 is connected to solder SD. In this way, the manufacturing method of electronic component 801A can be said to include a second element mounting step. Through the above steps, electronic component 801A can be manufactured.

[0337] (action) Next, the operation of this embodiment will be described.

[0338] Each connecting conductor 823 that is electrically connected to the main surface wiring 821 is electrically connected to an upper surface wiring 870 formed on the resin main surface 840s of the sealing resin 840. That is, the main surface wiring 821 and the upper surface wiring 870 are electrically connected via each connecting conductor 823.

[0339] The first functional element 830 is disposed inside the sealing resin 840 so as to be electrically connected to the main surface wiring 821, and the second functional element 860 is disposed on the resin main surface 840s of the sealing resin 840 so as to be electrically connected to the upper surface wiring 870. In this manner, the first functional element 830 and the second functional element 860 are disposed such that the position of the first functional element 830 in the thickness direction z is different from the position of the second functional element 860 in the thickness direction z, and the first functional element 830 and the second functional element 860 overlap when viewed from the thickness direction z. In this manner, in the electronic component 801A of this embodiment, the first functional element 830 and the second functional element 860 electrically connected to each other are mounted three-dimensionally (3D mounted) rather than planarly (2D mounted). This makes it possible to reduce the arrangement space for the first functional element 830 and the second functional element 860 in a direction perpendicular to the thickness direction z, compared to a configuration in which the first functional element 830 and the second functional element 860 are arranged on the same plane in a direction perpendicular to the thickness direction z.

[0340] (effect) According to this embodiment, the following effects can be obtained.

[0341] (1-1) The electronic component 801A includes a first functional element 830 disposed so as to be electrically connected to a main surface wiring 821 formed on a substrate 810, a sealing resin 840 that seals the main surface wiring 821 and the first functional element 830, a second functional element 860 mounted on a resin main surface 840s of the sealing resin 840, and a connecting conductor 823 that electrically connects the main surface wiring 821 and the second functional element 860. The connecting conductor 823 is exposed from the resin main surface 840s of the sealing resin 840. According to this configuration, the first functional element 830 and the second functional element 860 are disposed so as to overlap each other as viewed from the thickness direction z. This makes it possible to reduce the size of the electronic component 801A in the direction perpendicular to the thickness direction z, as compared to a configuration in which the first functional element 830 and the second functional element 860 are disposed side by side on the same plane in the direction perpendicular to the thickness direction z.

[0342] (1-2) The dimension of the second functional element 860 in the thickness direction z is larger than the dimension of the first functional element 830 in the thickness direction z. With this configuration, even if the dimension of the second functional element 860 arranged outside the sealing resin 840 in the thickness direction z is large, it is not necessary to increase the dimension of the sealing resin 840 in the thickness direction z. In other words, since the dimension of the first functional element 830 sealed by the sealing resin 840 in the thickness direction z is small, the dimension of the sealing resin 840 in the thickness direction z can be reduced. Therefore, in the manufacturing process of the electronic component 801A, the dimension of the resin layer 1640 in the thickness direction z can be reduced, thereby reducing warping of the base material 1610 caused by the influence of thermal contraction of the resin layer 1640.

[0343] (1-3) Top surface wiring 870 is formed on the resin main surface 840s of the sealing resin 840. The top surface wiring 870 is electrically connected to the connecting conductor 823. With this configuration, the top surface wiring 870 can form wiring suitable for mounting the second functional element 860. Therefore, the second functional element 860 can be suitably mounted on the resin main surface 840s.

[0344] (1-4) The dimension of the second functional element 860 in the second direction y is larger than the dimension of the first functional element 830 in the second direction y. With this configuration, a functional element larger than the first functional element 830 in the second direction y can be mounted on the resin principal surface 840s. Therefore, the number of types of second functional elements 860 that can be mounted on the resin principal surface 840s increases.

[0345] (1-5) Each main surface wiring 821 has an inner portion 821p that extends further inwardly into the substrate main surface 810s than each through wiring 822. The first functional element 830 is mounted on the inner portion 821p. According to this configuration, the plurality of through wirings 822 are arranged further outwardly from the first functional element 830 onto the substrate main surface 810s. This makes it possible to ensure space for changing the pitch of the plurality of through wirings 822 in the arrangement direction. Therefore, for example, the pitch of the plurality of through wirings 822 in the arrangement direction can be made larger than the pitch of the inner portions 821p of the plurality of main surface wirings 821 in the arrangement direction.

[0346] (1-6) The connecting conductor 823 is disposed between the first functional element 830 and the through wiring 822 in the extension direction of the inner portion 821p of the main surface wiring 821. With this configuration, the influence of deformation of the through wiring 822 is less likely to be transmitted to the connecting conductor 823.

[0347] (1-7) The first connecting conductor 823A and the second connecting conductor 823B are distributed and disposed on both sides of the first functional element 830 when viewed from the thickness direction z. With this configuration, it is possible to shorten the distance between the first upper surface electrode 871 of the upper surface wiring 870 and the first connecting conductor 823A, and the distance between the second upper surface electrode 872 of the upper surface wiring 870 and the second connecting conductor 823B. Therefore, the length of the upper surface wiring 870 can be shortened.

[0348] (1-8) Through wiring 822 is exposed on each of substrate side surfaces 811-814 of substrate 810. With this configuration, when electronic component 801A is mounted on a wiring substrate, for example, by soldering, the solder also comes into contact with the surfaces of through wiring 822 exposed from substrate side surfaces 811-814 to form a fillet. This makes it possible to visually confirm the state of bonding of electronic component 801A by soldering when electronic component 801A is mounted on the wiring substrate.

[0349] (1-9) Main surface wiring 821 is exposed on each of resin side surfaces 841-844 of sealing resin 840. With this configuration, when electronic component 801A is mounted, for example, on a wiring board by soldering, the solder also comes into contact with the surfaces of main surface wiring 821 exposed from resin side surfaces 841-844 to form a fillet. This makes it possible to visually confirm the state of bonding of electronic component 801A by solder when electronic component 801A is mounted on a wiring board.

[0350] (1-10) The main surface wiring 821, the through wiring 822, and the connection conductor 823 are each formed by electrolytic plating. In other words, the internal electrode 820 is formed by electrolytic plating. Moreover, the external electrode 850 is each formed by electroless plating. Therefore, the electronic component 801A is wired by plating, and does not use a lead frame formed from a metal plate. Wiring by plating can be made thinner than when a lead frame structure is adopted. Therefore, the electronic component 801A can be made thinner. In addition, when an LSI is used for the first functional element 830, the number of terminals increases with the high integration of the LSI, and it is necessary to miniaturize the internal electrodes, etc., but when a lead frame is used, there is a limit to miniaturization because a metal plate is processed. On the other hand, the electronic component 801A of this embodiment can also accommodate miniaturization because the internal electrode 820 is formed by plating. Therefore, an electronic component having more terminals can be manufactured.

[0351] [Eighth embodiment] 79 to 100, an electronic component 801B according to an eighth embodiment of the present disclosure will be described. Electronic component 801B of this embodiment differs from electronic component 801A of the seventh embodiment mainly in that it includes an insulating member 890 instead of substrate 810 and in the configuration of internal electrodes 820. In the following description, components common to those of electronic component 801A of the seventh embodiment are denoted by the same reference numerals, and description thereof may be omitted.

[0352] (Electronic component configuration) As shown in FIG. 79, the insulating member 890 is made of a material having electrical insulation properties, such as polyimide resin or phenol resin. The insulating member 890 is provided on the lower surface side (rear surface side) of the electronic component 801B. In this embodiment, the insulating member 890 is disposed below the sealing resin 840 in the thickness direction z. In addition, in this embodiment, the shape of the insulating member 890 viewed from the thickness direction z is the same as the shape of the substrate 810 viewed from the thickness direction z (see FIGS. 50 and 52). The insulating member 890 has an insulating main surface 890s and an insulating rear surface 890r facing in opposite directions to each other in the thickness direction z, and four insulating side surfaces 890x provided between the insulating main surface 890s and the insulating rear surface 890r in the thickness direction z. Each insulating side surface 890x faces the first direction x or the second direction y.

[0353] The insulating main surface 890s of the insulating member 890 faces the same direction as the element back surface 830r of the first functional element 830 in the thickness direction z, and faces the element main surface 830s of the first functional element 830. The insulating back surface 890r of the insulating member 890 faces the same direction as the element main surface 830s of the first functional element 830 in the thickness direction z. The insulating member 890 has a plurality of recesses 891 and through holes 892 formed therein. In this embodiment, the arrangement of the plurality of recesses 891 is the same as the arrangement of the plurality of recesses 815 (see FIG. 52) in the seventh embodiment. That is, the plurality of recesses 891 are provided four on each side of the insulating member 890. The shape of each recess 891 as viewed from the thickness direction z is a rectangular recess. The shape of each recess 891 as viewed from the thickness direction z is the same as the shape of the recess 815 as viewed from the thickness direction z in the seventh embodiment.

[0354] The through hole 892 penetrates the substrate 810 in the thickness direction z. The through hole 892 is provided in the center of the insulating member 890 in the first direction x and the second direction y. The shape of the through hole 892 as viewed from the thickness direction z is rectangular.

[0355] The shape of each recess 891 as viewed from the thickness direction z can be changed arbitrarily. The shape of each recess 891 as viewed from the thickness direction z can be a square concave shape, an arc shape, or the like, or a polygonal shape other than a rectangle. The shape of the through hole 892 as viewed from the thickness direction z can be changed arbitrarily. The shape of the through hole 892 as viewed from the thickness direction z can be a square, a circle, an ellipse, or the like, or a polygonal shape other than a rectangle.

[0356] The internal electrode 820 has a plurality of (16 in this embodiment) wiring layers 824 and a plurality of (two in this embodiment) connecting conductors 823. The arrangement of the wiring layers 824 is the same as the arrangement of the main surface wiring 821 and the through wiring 822 in the seventh embodiment (see FIG. 52). As in the seventh embodiment, the two connecting conductors 823 in this embodiment are a first connecting conductor 823A and a second connecting conductor 823B. The first connecting conductor 823A is electrically connected to one wiring layer 824 among the multiple wiring layers 824. The second connecting conductor 823B is electrically connected to another wiring layer 824 among the multiple wiring layers 824. The arrangement of the connecting conductors 823A and 823B is the same as the arrangement of the connecting conductors 823A and 823B in the seventh embodiment.

[0357] As shown in FIG. 79, each wiring layer 824 has a wiring main surface 824s and a wiring back surface 824r that face opposite to each other in the thickness direction z. The wiring main surface 824s faces the same direction as the insulating main surface 890s of the insulating member 890, and the wiring back surface 824r faces the same direction as the insulating back surface 890r of the insulating member 890. Each wiring layer 824 is made of a material having electrical conductivity. For example, Cu, Cu alloy, or the like can be used as the material of each wiring layer 824. In this embodiment, each wiring layer 824 includes a plating layer.

[0358] Each wiring layer 824 includes a main surface wiring 825 and a through wiring 826. In this embodiment, each wiring layer 824 has the main surface wiring 825 and the through wiring 826 integrally formed therewith. Therefore, the wiring main surface 824s constitutes the wiring main surface of the main surface wiring 825, and the wiring back surface 824r constitutes the back surface of the main surface wiring 825 and the back surface of the through wiring 826. Since the back surface of the through wiring 826 is exposed from the insulating member 890 in the thickness direction z, it can be said that the wiring back surface 824r constitutes an exposed back surface of the through wiring 826 exposed from the insulating back surface 890r.

[0359] The main surface wiring 825 is formed on an insulating main surface 890s of the insulating member 890. The through wirings 826 are formed in the recesses 891 and through holes 892 of the insulating member 890. The shape of each through wiring 826 as viewed from the thickness direction z is determined according to the shape of each recess 891 and through hole 892 as viewed from the thickness direction z. In this embodiment, the shape of each through wiring 826 as viewed from the thickness direction z is rectangular.

[0360] As shown in FIG. 80, each wiring layer 824 is composed of a seed layer 824a and a plating layer 824b stacked on top of each other. The seed layer 824a is composed of, for example, a first layer whose main component is Ti and a second layer whose main component is Cu. The seed layer 824a has a thickness of about 200 nm or more and 8800 nm or less. The plating layer 824b has a main component of Cu. The plating layer 824b has a thickness of about 20 μm or more and 50 μm or less. The thicknesses of the seed layer 824a and the plating layer 824b are not limited to those described above.

[0361] Each of the connecting conductors 823A, 823B extends upward from a wiring main surface 824s of the wiring layer 824 in the thickness direction z. More specifically, each of the connecting conductors 823A, 823B extends upward from an upper surface 825s of the main surface wiring 825 in the thickness direction z. The configuration of each of the connecting conductors 823A, 823B is similar to the configuration of each of the connecting conductors 823A, 823B in the seventh embodiment. Furthermore, the upper surface 823s of each of the connecting conductors 823A, 823B is exposed from a resin main surface 840s of the sealing resin 840, similar to the seventh embodiment.

[0362] An upper surface wiring 870 and an insulating film 873 are formed on a resin main surface 840s of the sealing resin 840, similarly to the seventh embodiment. A second functional element 860 is connected to the upper surface wiring 870, similarly to the seventh embodiment. The mounting position of the second functional element 860 on the resin main surface 840s is the same as the mounting position of the second functional element 860 on the resin main surface 840s in the seventh embodiment. Therefore, the positional relationship between the first functional element 830 and the second functional element 860 is also the same as the positional relationship between the first functional element 830 and the second functional element 860 in the seventh embodiment.

[0363] (Electronic component manufacturing method) A manufacturing method for an electronic component 801B according to the eighth embodiment of the present disclosure will be described with reference to Figures 81 to 100. The definitions of the directions shown in these figures are the same as those shown in Figures 49 to 58.

[0364] The manufacturing method of electronic component 801B includes a step of preparing support substrate 1700. More specifically, as shown in FIG. 81, support substrate 1700 is prepared having upper surface 1701 and lower surface 1702 facing opposite sides in thickness direction z. Support substrate 1700 is, for example, a glass substrate or a Si substrate. In this embodiment, a light-transmitting glass substrate is used as support substrate 1700. The thickness of support substrate 1700 is about 0.5 μm.

[0365] The method for manufacturing electronic component 801B includes a step of forming temporary fixing material 1710 on upper surface 1701 of supporting substrate 1700. More specifically, temporary fixing material 1710 is formed so as to cover the entire upper surface 1701 of supporting substrate 1700, as shown in FIG.

[0366] The manufacturing method of electronic component 801B includes a step of forming a sputtered film 1720 on temporary fixing material 1710. More specifically, as shown in Fig. 81, sputtered film 1720 is formed so as to cover the entire surface of temporary fixing material 1710. Sputtered film 1720 is a metal film whose main component is Ti.

[0367] The manufacturing method of electronic component 801B includes a step of forming insulating layer 1790 shown in FIG. 82. This insulating layer 1790 corresponds to insulating member 890 (see FIG. 79) of electronic component 801B. More specifically, insulating layer 1790 is an insulating film made of a photosensitive resin material such as polyimide resin or phenol resin. Insulating layer 1790 has insulating main surface 1790s and insulating back surface 1790r facing opposite sides in thickness direction z. In this step, insulating layer 1790 is applied onto sputtered film 1720 using, for example, a spin coater (spin coating device). Note that a film-like photosensitive resin material may be attached. Then, the photosensitive resin material is exposed to light and developed to perform patterning. As a result, insulating layer 1790 is formed. In this way, it can be said that the manufacturing method of electronic component 801B includes an insulating layer forming step.

[0368] The method for manufacturing electronic component 801B includes a step of forming wiring layer 1724 shown in FIG.

[0369] More specifically, as shown in FIG. 84, first, a seed layer 1724a is formed. A part of the seed layer 1724a later corresponds to a part of the internal electrode 820 of the electronic component 801B (specifically, the seed layer 824a of the wiring layer 824). The seed layer 1724a is formed by a sputtering method. The seed layer 1724a is formed over the entire surface of each of the insulating layer 1790 and the sputtered film 1720 exposed to the insulating layer 1790. The seed layer 1724a of this embodiment is composed of a Ti layer and a Cu layer stacked on each other. In the step of forming the seed layer 1724a, a Ti layer is formed in contact with the insulating layer 1790 and the sputtered film 1720 exposed to the insulating layer 1790, and then a Cu layer is formed in contact with the Ti layer.

[0370] Next, a plating layer 1724b is formed as shown in Fig. 85. Fig. 85 shows a plating layer 1724b formed on a part of a seed layer 1724a. Each wiring layer 1724 shown in Fig. 85 has a laminated structure of a seed layer 1724a and a plating layer 1724b.

[0371] As shown in FIG. 85, the plating layer 1724b corresponds to a part of the internal electrode 820 of the electronic component 801B (specifically, the plating layer 824b of the wiring layer 824). The plating layer 824b is formed by pattern formation using photolithography and electrolytic plating. In the process of forming the plating layer 1724b, a resist layer (not shown) for forming the plating layer 1724b is first formed by photolithography. In forming this resist layer, a photosensitive resist is applied so as to cover the entire surface of the seed layer 1724a, and the photosensitive resist is exposed and developed to perform patterning. This patterning exposes a part of the seed layer 1724a (a part where the plating layer 1724b is to be formed). Then, the plating layer 1724b is formed on the exposed seed layer 1724a by electrolytic plating using the seed layer 1724a as a conductive path. Thereafter, the resist layer is removed to form the plating layer 1724b shown in FIG. 85.

[0372] Next, as shown in FIG. 85, all of the unnecessary seed layer 1724a that is not covered with the plating layer 1724b is removed. The unnecessary seed layer 1724a is removed by wet etching. In this wet etching, for example, H 2 SO 4 and H 2 O 2 (hydrogen peroxide) is used. By the step of removing unnecessary seed layer 1724a, insulating layer 1790 is exposed from the portion from which seed layer 1724a has been removed. Furthermore, by removing unnecessary seed layer 1724a, wiring layer 1724 made of seed layer 1724a and plating layer 1724b is formed. This wiring layer 1724 corresponds to wiring layer 824 of internal electrode 820 of electronic component 801B (see FIG. 61). In this way, it can be said that the manufacturing method of electronic component 801B includes a first internal electrode formation step.

[0373] The method of manufacturing electronic component 801B includes a step of forming a plurality of (two in this embodiment) connecting conductors 1723 shown in FIG.

[0374] More specifically, as shown in FIG. 87, first, a seed layer 1723a is formed. A part of the seed layer 1723a later corresponds to a part of the internal electrode 820 of the electronic component 801B (specifically, the seed layer 823a of the connection conductor 823). The seed layer 1723a is formed by a sputtering method. The seed layer 1723a is formed over the entirety of each of the wiring layer 1724 and the insulating layer 1790, which are exposed to the wiring layer 1724. In this embodiment, the seed layer 1723a is composed of a Ti layer and a Cu layer stacked on each other. In the step of forming the seed layer 1723a, a Ti layer is formed in contact with the parts of the wiring layer 1724 and the insulating layer 1790, which are exposed to the wiring layer 1724, and then a Cu layer is formed in contact with the Ti layer.

[0375] Next, a plating layer 1723b is formed as shown in Fig. 88. Fig. 88 shows a plating layer 1723b formed on a part of a seed layer 1723a. Each connecting conductor 1723 shown in Fig. 88 has a laminated structure of a seed layer 1723a and a plating layer 1723b.

[0376] As shown in FIG. 88, the plating layer 1723b corresponds to a part of the internal electrode 820 of the electronic component 801B (specifically, the plating layer 823b of the connection conductor 1723). The plating layer 1723b is formed by pattern formation using photolithography and electrolytic plating. In the process of forming the plating layer 1723b, a resist layer (not shown) for forming the plating layer 1723b is first formed by photolithography. In forming this resist layer, a photosensitive resist is applied so as to cover the entire surface of the seed layer 1723a, and the photosensitive resist is exposed and developed to perform patterning. This patterning exposes a part of the seed layer 1723a (a part for forming the plating layer 1723b). Then, the plating layer 1723b is formed on the exposed seed layer 1723a by electrolytic plating using the seed layer 1723a as a conductive path.

[0377] The method for manufacturing electronic component 801B includes a step of removing unnecessary seed layer 1723a. More specifically, all unnecessary seed layer 1723a that is not covered by plating layer 1723b and bonding portion 880 is removed. This unnecessary seed layer 1723a is removed in the same manner as the above-mentioned unnecessary seed layer 1724a is removed. That is, for example, H 2 SO 4 and H 2 O 2This is performed by wet etching using a mixed solution of the above. As a result, the wiring layer 1724, the insulating layer 1790, and the sputtered film 1720 are exposed from the portion from which the seed layer 1723a has been removed. Furthermore, by removing unnecessary seed layer 1723a, a connecting conductor 1723 made of seed layer 1723a and plating layer 1723b is formed. The connecting conductor 1723 corresponds to the connecting conductor 823 (see FIG. 79) of the internal electrode 820 of electronic component 801B. In this way, it can be said that the manufacturing method for electronic component 801B includes a second internal electrode forming step.

[0378] The method for manufacturing electronic component 801B includes a step of forming bonding portion 880 shown in Fig. 89. The step of forming bonding portion 880 of this embodiment is similar to the step of forming bonding portion 880 of the seventh embodiment.

[0379] The manufacturing method of electronic component 801B includes a step of mounting first functional element 830 shown in Fig. 90. The method of mounting first functional element 830 in this embodiment is similar to the method of mounting first functional element 830 in the seventh embodiment. In other words, it can be said that the manufacturing method of electronic component 801B includes a first element mounting step.

[0380] As shown in FIG. 91, the method for manufacturing electronic component 801B includes a step of forming resin layer 1740 that covers first functional elements 830. This resin layer 1740 corresponds to sealing resin 840 (see FIG. 79) of electronic component 801B. In the method for forming resin layer 1740 in this embodiment, resin layer 1740 that collectively seals all of first functional elements 830 is formed. Resin layer 1740 is, for example, a synthetic resin whose main component is epoxy resin. Resin layer 1740 is formed by transfer molding, for example. In this way, it can be said that the method for manufacturing electronic component 801B includes a resin layer formation step.

[0381] The manufacturing method of electronic component 801B includes a step of cutting resin layer 1740 and connecting conductor 1723 to reduce the thickness of resin layer 1740 and connecting conductor 1723 shown in FIG. 92. The step of cutting resin layer 1740 and connecting conductor 1723 in this embodiment to reduce their thickness is similar to the step of cutting resin layer 1640 and connecting conductor 1623 in the seventh embodiment to reduce their thickness (see FIG. 71 for both). This forms connecting conductor 823. Upper surface 823s of connecting conductor 823 is exposed from resin main surface 1740s, which is the end surface of resin layer 1740 on the opposite side to support substrate 1700 in thickness direction z. In this way, it can be said that the manufacturing method of electronic component 801B includes a resin layer cutting step.

[0382] The method for manufacturing electronic component 801B includes a step of forming upper surface wiring 870 and insulating film 873 shown in Fig. 93. The step of forming upper surface wiring 870 and insulating film 873 of this embodiment is similar to the step of forming upper surface wiring 870 and insulating film 873 of the seventh embodiment. In other words, it can be said that the method for manufacturing electronic component 801B includes an upper surface wiring formation step and an insulating film formation step.

[0383] As shown in FIG. 94, the manufacturing method of electronic component 801B includes a step of peeling support substrate 1700 (see FIG. 93) from sputtered film 1720. In the step of peeling support substrate 1700, first, dicing tape DT is attached to resin main surface 1740s (insulating film 873) of resin layer 1740. Then, for example, laser is irradiated from lower surface 1702 (see FIG. 93) of support substrate 1700. At this time, the laser light is transmitted through support substrate 1700 and irradiated to temporary fixing material 1710 (see FIG. 93). This reduces the adhesion of temporary fixing material 1710, and support substrate 1700 can be peeled off from sputtered film 1720. If temporary fixing material 1710 remains partially (for example, remains as soot) after peeling support substrate 1700 from sputtered film 1720, this partially remaining temporary fixing material 1710 is removed by, for example, plasma. Through the above processing, the support substrate 1700 and the temporary fixing material 1710 are removed.

[0384] The method of peeling off the support substrate 1700 is not limited to the method using laser irradiation. For example, the support substrate 1700 and the like may be peeled off from the sputtered film 1720 by blowing air from a direction (first direction x or second direction y) perpendicular to the thickness direction z, or the temporary fixing material 1710 may be softened by heating, and then the support substrate 1700 and the like may be peeled off from the sputtered film 1720. Here, in the case of peeling off by laser irradiation, the support substrate 1700 needs to be made of a material having appropriate translucency in order to transmit laser light. On the other hand, in the case of peeling off by blowing air or peeling off by heating, for example, a Si substrate or the like may be used as the support substrate 1700 instead of a glass substrate.

[0385] 95, the method for manufacturing electronic component 801B includes a step of removing sputtered film 1720 (see FIG. 94). By removing this sputtered film 1720, insulating back surface 1790r of insulating layer 1790 and back surface 1724r of wiring layer 1724 are exposed.

[0386] The manufacturing method of electronic component 801B includes a step of cutting insulating layer 1790 and wiring layer 1724 and half-cutting resin layer 1740. More specifically, as shown in FIG. 96, dicing tape DT is attached to the lower surface of resin layer 1740, and insulating layer 1790 and wiring layer 1724 are cut and a part of resin layer 1740 in thickness direction z is cut (half-cut). When cutting insulating layer 1790 and wiring layer 1724 and half-cutting resin layer 1740, a cut is made from insulating layer 1790 toward dicing tape DT along cutting line CL (dotted chain line) shown in FIG. 95, for example, by a dicing blade. Note that the width in the short side direction of cutting line CL shown in FIG. 95 is the thickness (width) of the dicing blade. In this manner, wiring layer 824 and insulating member 890 are formed by cutting insulating layer 1790 and wiring layer 1724. Then, by half-cutting resin layer 1740, separation groove 1745 is formed in resin layer 1740. In this way, the manufacturing method of electronic component 801B can be said to include a cutting step. Also, the manufacturing method of electronic component 801B can be said to include a first cutting step.

[0387] 97, the method for manufacturing electronic component 801B includes a step of forming external electrodes 850. The step of forming external electrodes 850 of this embodiment is similar to the step of forming external electrodes 850 of the seventh embodiment.

[0388] The manufacturing method of electronic component 801B includes a step of dividing first functional element 830 into individual pieces each having one unit, as shown in Fig. 98. The step of dividing first functional element 830 of the present embodiment into individual pieces each having one unit is similar to the step of dividing first functional element 830 of the seventh embodiment into individual pieces each having one unit. That is, the manufacturing method of electronic component 801B can also be said to include a cutting step. Also, the manufacturing method of electronic component 801B can also be said to include a second cutting step.

[0389] The manufacturing method of electronic component 801B includes a step of mounting second functional element 860, as shown in FIGS. 99 and 100. The step of mounting second functional element 860 in this embodiment is similar to the step of mounting second functional element 860 in the seventh embodiment. That is, as shown in FIG. 99, solder SD is formed on each of first upper surface electrode 871 and second upper surface electrode 872 of upper surface wiring 870, and then, as shown in FIG. 100, second functional element 860 is fixed to the solder SD. In this way, it can be said that the manufacturing method of electronic component 801B includes a second functional element mounting step. Through the above steps, electronic component 801B can be manufactured.

[0390] (effect) According to this embodiment, in addition to the same effects as those of the seventh embodiment, the following effects can be obtained.

[0391] (2-1) The main surface wiring 825 and the through wiring 826 are integrally formed as the wiring layer 824. According to this configuration, the process of forming the wiring layer 824 can be simplified compared to the case where the main surface wiring 825 and the through wiring 826 are formed separately.

[0392] (2-2) The through wiring 826 and the main surface wiring 825 are formed to the same thickness. With this configuration, the thickness of the insulating member 890 can be made thinner than when the through wiring 826 is formed by a terminal pillar.

[0393] [Ninth embodiment] An electronic component 801C according to a ninth embodiment of the present disclosure will be described with reference to Figs. 101 to 105. The electronic component 801C of this embodiment differs from the electronic component 801A of the seventh embodiment mainly in the type and number of second functional elements 860 and the number and arrangement of connecting conductors 823. In the following description, components common to the components of the electronic component 801A of the seventh embodiment are denoted by the same reference numerals, and description thereof may be omitted. Also, in Fig. 101, the second functional element 860 is indicated by a two-dot chain line for convenience.

[0394] 101, an electronic component 801C of this embodiment configures an audio output device by a first functional element 830 and a plurality (four in this embodiment) of second functional elements 860. The audio output device is a device for amplifying a weak audio signal and driving an electroacoustic conversion element 1000 (see FIG. 105) such as a speaker or a headphone.

[0395] The multiple second functional elements 860 are arranged at intervals in the first direction x and the second direction y. In this embodiment, two second functional elements 860 spaced apart from each other in the first direction x are arranged near the resin side surface 841 of the resin principal surface 840s, and two second functional elements 860 spaced apart from each other in the first direction x are arranged near the resin side surface 842 of the resin principal surface 840s.

[0396] 102, the top surface wiring 900 formed on the resin main surface 840s has top surface electrodes 901 for electrically connecting to the second functional element 860. In this embodiment, four top surface electrodes 901 are formed per second functional element 860. The four top surface electrodes 901 are arranged at a distance from each other in the first direction x and the second direction y. Thus, in this embodiment, the top surface wiring 900 has 16 top surface electrodes 901.

[0397] 102 and 103, 16 connecting conductors 823 are provided to individually and electrically connect the 16 upper surface electrodes 901 to the 16 main surface wirings 821. In other words, a connecting conductor 823 is connected to each of the main surface wirings 821.

[0398] 102, the four connecting conductors 823 overlap with the top surface electrode 901 in the thickness direction z. That is, the connecting conductors 823 are in contact with the top surface electrode 901. Therefore, the top surface wiring 900 has twelve connecting wirings 902 that individually connect the twelve connecting conductors 823 and the twelve top surface electrodes 901 that do not overlap with each other in the thickness direction z. In this manner, the first functional element 830 and the four second functional elements 860 are electrically connected to each other.

[0399] 104, a connection wiring 902 is formed on an upper surface 823s of the connection conductor 823 that does not overlap with the upper surface electrode 901 in the thickness direction z. That is, the connection wiring 902 covers the upper surface 823s of the connection conductor 823. The connection wiring 902 is covered with an insulating film 873.

[0400] FIG. 105 shows a simplified circuit configuration of an electronic component 801C as an audio output device. In this embodiment, each second functional element 860 is electrically connected to an electroacoustic conversion element 1000, and outputs an audio signal to the electroacoustic conversion element 1000 after amplifying the audio signal. Each second functional element 860 has a full-bridge type output stage 863 that amplifies and outputs the audio signal, and an LC filter 864 that removes noise from the audio signal output from the output stage 863. In this embodiment, each second functional element 860 uses a BTL (Balanced Transformer Less) method, and therefore has an output stage 863 and two LC filters 864 connected to the output stage 863. By using this BLT method, an output coupling capacitor is not required, and the output of the electroacoustic conversion element 1000 is doubled.

[0401] 105, each second functional element 860 is configured to be packaged by sealing an output stage 863 and two LC filters 864 with sealing resin, and has four external electrodes 865. Two of the four external electrodes 865 constitute an input electrode electrically connected to the input side of one half-bridge circuit in the output stage 863, and an output electrode electrically connected to the output side of one of the two LC filters 864. The remaining two external electrodes 865 constitute an input electrode electrically connected to the input side of another half-bridge circuit in the output stage 863, and an output electrode electrically connected to the output side of the other of the two LC filters 864.

[0402] The output stage 863 is configured such that two pairs of transistors connected in series are connected in parallel. An example of a transistor is an N-type MOSFET. The output stage 863 has two arms connected in parallel, each arm having a source electrode of a MOSFET in an upper arm and a drain electrode of a MOSFET in a lower arm connected to each other.

[0403] Each LC filter 864 has a configuration in which an inductor 864a and a capacitor 864b are connected in series. A first end of the inductor 864a is connected to a node between a source electrode of the MOSFET of the upper arm and a drain electrode of the MOSFET of the lower arm. A second end of the inductor 864a is connected to a first end of the capacitor 864b. A second end of the capacitor 864b is grounded. In addition, the second end of the inductor 864a and the first end of the capacitor 864b are connected to the electroacoustic conversion element 1000 via an external electrode 865.

[0404] The first functional element 830 is a control circuit element that controls each second functional element 860, and is configured, for example, by an LSI. The first functional element 830 controls the on-off switching of each MOSFET in the output stage 863 of each second functional element 860. The first functional element 830 has an upper arm drive circuit that controls the switching of the upper arm MOSFET, a lower arm drive circuit that controls the switching of the lower arm MOSFET, and a signal generation circuit that outputs a PWM signal to the upper arm drive circuit and the lower arm drive circuit to control each MOSFET. In this way, the electronic component 801C of this embodiment can be said to be an audio output device equipped with a class D amplifier circuit.

[0405] The operation of this embodiment will be described.

[0406] Since the second functional element 860 is not sealed by the sealing resin 840 like the first functional element 830, in other words, since the second functional element 860 is mounted on the resin main surface 840s which is outside the sealing resin 840, the number of second functional elements 860 mounted on the resin main surface 840s can be easily changed. Therefore, the number of second functional elements 860 mounted on the resin main surface 840s can be adjusted according to the number of electroacoustic conversion elements 1000 electrically connected to the electronic component 801C.

[0407] According to this embodiment, in addition to the effects of the seventh embodiment, the following effects can be obtained.

[0408] (3-1) The second functional element 860 has a transistor as the output stage 863. According to this configuration, the second functional element 860 is provided outside the sealing resin 840, and heat generated by driving the transistor is easily dissipated to the outside of the electronic component 801C. Therefore, the heat of the transistor is less likely to interfere with the heat generated by driving the first functional element 830, and the occurrence of heat concentration due to the transistor and the first functional element 830 can be suppressed.

[0409] Furthermore, since the second functional element 860 includes the output stage 863, wiring of a transistor through which a large current flows is provided inside the second functional element 860, so that the current supplied from the first functional element 830 to the output stage 863 of the second functional element 860 is reduced. Therefore, EMI noise in the internal electrode 820 connecting the first functional element 830 and the second functional element 860 can be reduced.

[0410] [Example of change] The above-mentioned embodiments are examples of possible forms of the electronic components and the manufacturing method of the electronic components according to the present disclosure, and are not intended to limit the forms. The electronic components and the manufacturing method of the electronic components according to the present disclosure may take forms different from those exemplified in the above-mentioned embodiments. One example is a form in which a part of the configuration of each of the above-mentioned embodiments is replaced, changed, or omitted, or a form in which a new configuration is added to each of the above-mentioned embodiments. The following modified examples can be combined with each other as long as no technical contradiction occurs. For convenience of explanation, the following modified examples are basically explained using the seventh embodiment, but can also be applied to other embodiments as long as no technical contradiction occurs.

[0411] In the seventh and ninth embodiments, the configuration of the main surface wiring 821 can be changed arbitrarily. In one example, the main surface wiring 821 may have a laminated structure of a seed layer 824a and a plating layer 824b, like the wiring layer 824 in the eighth embodiment. Note that the wiring layer 824 in the eighth embodiment may have a laminated structure of a metal layer 821a and a conductive layer 821b, like the main surface wiring 821 in the seventh embodiment.

[0412] In the seventh and ninth embodiments, the main surface wiring 821 and the through wiring 822 may be formed integrally, like the main surface wiring 825 and the through wiring 826 in the eighth embodiment.

[0413] In the eighth embodiment, like the main surface wiring 821 and the through wiring 822 in the seventh embodiment, the main surface wiring 825 and the through wiring 826 may be formed separately.

[0414] In the seventh and ninth embodiments, the width dimension of the main surface wiring 821 (the dimension in the direction perpendicular to the extension direction of the main surface wiring 821 as viewed from the thickness direction z) and the width dimension of the through wiring 822 (the dimension in the direction perpendicular to the extension direction of the through wiring 822 as viewed from the thickness direction z) can be changed arbitrarily. In one example, the width dimension of the main surface wiring 821 may be larger than the width dimension of the through wiring 822. Also, the width dimension of the main surface wiring 821 may be smaller than the width dimension of the through wiring 822.

[0415] In the ninth embodiment, the electronic component 801C may include the insulating member 890 of the electronic component 801B, instead of the substrate 810. In this case, instead of the main surface wiring 821 and the through wiring 822, a wiring layer 824 is used.

[0416] In the ninth embodiment, the configuration of the first functional element 830 and the configuration of the second functional element 860 can be changed arbitrarily. In one example, as shown in FIG. 106, the first functional element 830 may have an output stage 863 of each of the second functional elements 860 of the ninth embodiment. The first functional element 830 has a control circuit 836 that controls the output stage 863 of each of the second functional elements 860. The control circuit 836 is made of, for example, an LSI. Since the first functional element 830 has the output stage 863, the output stage 863 is omitted from each of the second functional elements 860. Each of the second functional elements 860 has an LC filter 864.

[0417] Here, since electronic component 801C electrically connects first functional element 830 and second functional element 860 via internal electrode 820 and top surface wiring 870, the conductive path between first functional element 830 and second functional element 860 is shorter than in a configuration in which second functional element 860 is disposed away from sealing resin 840 of electronic component 801C. Therefore, as shown in Fig. 106, since first functional element 830 has output stage 863, even if a large current flows from output stage 863 of first functional element 830 to second functional element 860, an increase in EMI noise can be suppressed because the conductive path between first functional element 830 and second functional element 860 is short.

[0418] In each embodiment, the shapes of electronic components 801A, 801B, and 801C may be changed as appropriate. In one example, electronic component 801A is configured such that step 845 is omitted from sealing resin 840. That is, sealing resin 840 is configured such that sealing resin 840 is not partitioned into first resin portion 846 and second resin portion 847. In the manufacturing method of such electronic component 801A, a step of cutting base material 1610 and half-cutting resin layer 1640 is replaced with a step of singulating. That is, a step of forming external electrodes 850 is performed after the step of singulating. Note that step 845 may be omitted from electronic component 801B of the eighth embodiment and electronic component 801C of the ninth embodiment.

[0419] In the seventh and ninth embodiments, the shape of the back surface 822r of the through wiring 822 exposed from the substrate 810 as viewed from the thickness direction z can be arbitrarily changed. The shape of the back surface 822r of the through wiring 822 arranged at a distance from each other in the first direction x as viewed from the thickness direction z may be a rectangle whose long side is the second direction y and whose short side is the first direction x. The shape of the back surface 822r of the through wiring 822 arranged at a distance from each other in the second direction y as viewed from the thickness direction z may be a rectangle whose long side is the first direction x and whose short side is the second direction y. Note that the shape of the back surface 822r of the through wiring 822 as viewed from the thickness direction z is not limited to a rectangular shape, and may be a circular shape, an ellipse, or the like.

[0420] In the eighth embodiment, the shape of the back surface 826r of the through wiring 826 exposed from the insulating member 890 as viewed from the thickness direction z can be arbitrarily changed. The shape of the back surface 826r of the through wiring 826 arranged at a distance from each other in the first direction x as viewed from the thickness direction z may be a rectangle whose long side is the second direction y and whose short side is the first direction x. The shape of the back surface 826r of the through wiring 826 arranged at a distance from each other in the second direction y as viewed from the thickness direction z may be a rectangle whose long side is the first direction x and whose short side is the second direction y. Note that the shape of the back surface 826r of the through wiring 826 as viewed from the thickness direction z is not limited to a rectangular shape, and may be a circular shape, an ellipse, or the like.

[0421] In each embodiment, the shape of the through holes 816, 892 as viewed from the thickness direction z and the shape of the through wirings 822, 826 arranged in the through holes 816, 892 as viewed from the thickness direction z (the shape of the external electrode 850 as viewed from the thickness direction z) can be changed arbitrarily. In one example, as shown in FIG. 107, the shape of the through hole 816 as viewed from the thickness direction z and the shape of the through wiring 822 arranged in the through hole 816 as viewed from the thickness direction z (the shape of the external electrode 850 as viewed from the thickness direction z) are each square. In the illustrated example, the dimension of the through hole 816 in the second direction y and the dimension of the through wiring 822 arranged in the through hole 816 in the second direction y (the dimension of the external electrode 850 in the second direction y) are larger than the dimension of the through hole 816 in the second direction y and the dimension of the through wiring 822 arranged in the through hole 816 in the second direction y (the dimension of the external electrode 850 in the second direction y) of the seventh embodiment. This configuration makes it easier for heat to be dissipated from the first functional element 830 to the outside of the electronic component 801A.

[0422] In each embodiment, the through wirings 822, 826 arranged in the through holes 816, 892 may not be electrically connected to the electrode pad 832 of the first functional element 830 via the main surface wiring 821. In this case, the external electrode 850 covering the through wirings 822, 826 arranged in the through holes 816, 892 may be omitted.

[0423] In each embodiment, the through holes 816, 892 and the through wirings 822, 826 arranged in the through holes 816, 892 may be omitted. Accordingly, the external electrode 850 covering the through wirings 822, 826 arranged in the through holes 816, 892 is also omitted.

[0424] In each embodiment, the internal electrode 820 is formed by electrolytic plating, but this is not limited to the above. For example, the main surface wiring 821 of the internal electrode 820 may be formed by a lead frame, and the connecting conductor 823 may be formed by a metal pillar. In this case, the connecting conductor 823 may be joined to the wiring main surface 821s of the main surface wiring 821 by a conductive bonding material, or may be joined to the main surface wiring 821 by welding such as ultrasonic welding.

[0425] In each embodiment, the external electrode 850 covers the rear surfaces 822r, 826r of the through wirings 822, 826, but this is not limited thereto. For example, in the seventh and ninth embodiments, the external electrode 850 may be configured to cover the exposed side surface 822xa of the side surface 822x of the through wiring 822 that is exposed from the substrate side surfaces 811 to 814 of the substrate 810. The external electrode 850 may also be configured to cover the wiring side surface 821xa of the main surface wiring 821 that is exposed from the resin side surfaces 841 to 844 of the sealing resin 840. In the eighth embodiment, the external electrode 850 may also be configured to cover the side surface of the through wiring 826 that is exposed from the insulating side surface 890x of the insulating member 890. The external electrode 850 may also be configured to cover the side surface of the main surface wiring 825 that is exposed from the resin side surfaces 841 to 844 of the sealing resin 840.

[0426] In the seventh and ninth embodiments, it is possible to arbitrarily change the position of the connection conductor 823 relative to the main surface wiring 821. In one example, the connection conductor 823 is disposed in a portion of the main surface wiring 821 that overlaps with the through wiring 822 in the thickness direction z.

[0427] In the eighth embodiment, the position of the connection conductor 823 relative to the wiring layer 824 can be changed arbitrarily. In one example, the first connection conductor 823A is connected to the through wiring 826 in the wiring layer 824. The second connection conductor 823B is connected to the through wiring 826 in the wiring layer 824.

[0428] In the seventh and eighth embodiments, the positional relationship between the first connecting conductor 823A and the second connecting conductor 823B and the first functional element 830 can be changed as desired. In one example, the first connecting conductor 823A and the second connecting conductor 823B may each be arranged closer to one side in the second direction y than the first functional element 830. Also, the first connecting conductor 823A and the second connecting conductor 823B may be arranged dispersedly in the first direction x than the first functional element 830. Also, the first connecting conductor 823A and the second connecting conductor 823B may each be arranged closer to one side in the first direction x than the first functional element 830.

[0429] In each embodiment, the dimensions of the connecting conductor 823 in the first direction x and the second direction y can be changed as desired. For example, in the seventh embodiment, the dimension of the first connecting conductor 823A in the first direction x is larger than the dimension of the main surface wiring 821 extending in the second direction y in the first direction x. Furthermore, the dimension of the second connecting conductor 823B in the first direction x is larger than the dimension of the main surface wiring 821 extending in the second direction y in the first direction x.

[0430] In each embodiment, the numbers of the main surface wiring 821, the through wiring 822, and the connecting conductor 823 can be changed as desired. The numbers of the main surface wiring 821, the through wiring 822, and the connecting conductor 823 may be sufficient as long as they allow electrical connection between the first functional element 830 and the second functional element 860. For this reason, for example, the number of each of the main surface wiring 821, the through wiring 822, and the connecting conductor 823 may be one.

[0431] In each embodiment, the configuration of the terminal of the first functional element 830 can be changed as desired. In one example, as shown in Fig. 108, the wiring 833 may be omitted, and an electrode pad 832 may be provided in a recess 831b of an element substrate 831. In this case, the electrode pad 832 is directly connected to the electrode 831a.

[0432] In each embodiment, the main surface wiring 821 and the first functional element 830 are electrically connected by flip-chip bonding, but this is not limited to this. For example, the main surface wiring 821 and the first functional element 830 may be electrically connected by a wire formed by wire bonding.

[0433] In each embodiment, the main surface wiring 821 extends along the first direction x or the second direction y, but is not limited thereto. For example, as shown in Fig. 109, in an electronic component 801A, the pitch of the through wirings 822 (external electrodes 850) arranged in the first direction x may be larger than the pitch of the electrode pads 832 arranged in the first direction x, and the pitch of the through wirings 822 (external electrodes 850) arranged in the second direction y may be larger than the pitch of the electrode pads 832 arranged in the second direction y. In this case, as shown in Fig. 110, the first connecting conductor 823A and the second connecting conductor 823B do not overlap with the first upper surface electrode 871 and the second upper surface electrode 872 of the upper surface wiring 870 when viewed from the thickness direction z. For this reason, in the illustrated example, the top surface wiring 870 includes a connection wiring 874 that connects the first top surface electrode 871 and the first connecting conductor 823A, and a connection wiring 874 that connects the second top surface electrode 872 and the second connecting conductor 823B. In the illustrated example, the first top surface electrode 871 and the connection wiring 874 are integrally formed, and the second top surface electrode 872 and the connection wiring 875 are integrally formed. The connection wiring 874 is provided so as to cover the top surface 823s of the first connecting conductor 823A. The connection wiring 875 is provided so as to cover the top surface 823s of the second connecting conductor 823B. The electronic component 801B of the eighth embodiment can also be modified in a similar manner.

[0434] In each embodiment, the main surface wiring 821 does not have to have the inner portion 821p. In this case, the connection conductor 823 is connected to a portion of the main surface wiring 821 that overlaps with the through wiring 822 in the thickness direction z.

[0435] In each embodiment, the top surface wiring 870 and the second functional element 860 are electrically connected by solder SD, but this is not limited to this. For example, the top surface wiring 870 and the second functional element 860 may be electrically connected by a wire formed by wire bonding.

[0436] In each embodiment, the top surface wirings 870, 900 may be omitted from the electronic components 801A to 801C. In this case, the connecting conductor 823 and the second functional element 860 are directly electrically connected. In one example, the top surface 823s of the first connecting conductor 823A exposed from the resin main surface 840s is connected to the first electrode 861 of the second functional element 860 by solder SD, and the top surface 823s of the second connecting conductor 823B exposed from the resin main surface 840s is connected to the second electrode 862 of the second functional element 860 by solder SD.

[0437] In each embodiment, the insulating film 873 may be omitted from the electronic components 801A to 801C.

[0438] In each embodiment, the relationship between the first functional element 830 and the second functional element 860 can be changed arbitrarily. In one example, the second functional element 860 may be a driving element, and the first functional element 830 may be a control element that controls the driving of the second functional element 860. Also, the second functional element 860 may be an optical element, and the first functional element 830 may be a control element that controls the light-emitting mode of the second functional element 860. For example, a light-emitting diode may be used as the optical element. In this case, the first functional element 830 as a control element controls the supply of power to the optical element (the second functional element 860). In one example, as shown in FIG. 111, the second functional element 860 has a substrate 910 having a substrate main surface 910s and a substrate back surface 910r that face opposite each other in the thickness direction z, a light-emitting diode 920 mounted on the substrate main surface 910s, and a light-transmitting sealing resin 930 that seals the light-emitting diode 920. The substrate 910 is formed in a rectangular flat plate shape with the long side direction being the second direction y and the short side direction being the first direction x. A first electrode 911 and a second electrode 912 are provided at both ends of the substrate 910 in the second direction y. The first electrode 911 constitutes an anode electrode, and the second electrode 912 constitutes a cathode electrode. The first electrode 911 is connected to the first upper surface electrode 871, and the second electrode 912 is connected to the second upper surface electrode 872. This electrically connects the light emitting diode 920 and the LSI as the first functional element 830. In addition, a VCSEL (Vertical Cavity Surface Emitting LASER) may be used as the optical element.

[0439] In each embodiment, the electronic components 801A, 801B, and 801C may include a plurality of first functional elements 830. In this case, the types (LSI, IC, etc.) of the plurality of first functional elements 830 may be different from one another.

[0440] In the seventh and eighth embodiments, the size of the second functional element 860 can be changed arbitrarily. In one example, the size of the second functional element 860 may be smaller than the size of the first functional element 830. In addition, in the seventh and eighth embodiments, a plurality of second functional elements 860 may be mounted on the resin main surface 840s.

[0441] In each embodiment, the second functional element may be omitted from the electronic components 801A, 801B, and 801C. That is, the electronic components 801A, 801B, and 801C may be configured to include a substrate 810 (insulating member 890), a main surface wiring 821 (825), a first functional element 830 that is conductive to the main surface wiring 821 (825) and is arranged on the opposite side of the substrate 810 (insulating member 890) from the main surface wiring 821 (825) in the thickness direction z, a connecting conductor 823 that is conductive to the main surface wiring 821 (825) and extends toward the opposite side of the substrate 810 (insulating member 890) in the thickness direction z, a through wiring 822 (826) that is conductive to the main surface wiring 821 (825) and extends toward the opposite side of the first functional element 830 in the thickness direction z, and a sealing resin 840 that seals the main surface wiring 821 (825), the first functional element 830, and the connecting conductor 823. In this case, the connecting conductor 823 is exposed from a resin main surface 840s of the sealing resin 840 so as to be electrically connected to the second functional element 860. The electronic components 801A, 801B, and 801C may also include upper surface wiring 870 on the resin main surface 840s of the sealing resin 840.

[0442] 112, electronic component 801A does not include second functional element 860. Upper surface wiring 870 is formed on resin main surface 840s of sealing resin 840. With this configuration, the type of second functional element 860 can be appropriately changed depending on the circuit to which electronic component 801A is applied. In addition, after electronic component 801A is mounted on a wiring board (not shown), an appropriate type of second functional element 860 can be mounted on upper surface wiring 870 depending on the circuit of the wiring board. Electronic components 801B and 801C can also be changed in a similar manner.

[0443] A manufacturing method for electronic components 801A and 801C not including such a second functional element 860 includes the same steps as the manufacturing method for electronic component 801A of the seventh embodiment, from the step of forming terminal pillars 1622 on upper surface 1601 of support substrate 1600 in Fig. 59 to the step of dividing into individual pieces with first functional element 830 as one unit in Fig. 76. That is, the manufacturing method for electronic components 801A and 801C not including second functional element 860 includes a step of forming a plurality of through wirings 822, an insulating layer forming step of forming an insulating layer (substrate 1610), a main surface wiring forming step of forming main surface wiring 1621, a conductor forming step of forming connecting conductor 1623, a first element mounting step of mounting first functional element 830, a resin layer forming step of forming resin layer 1640, and a cutting step of cutting resin layer 1640 etc.

[0444] Furthermore, the manufacturing method of electronic component 801B not including second functional element 860 has the same steps as the manufacturing method of electronic component 801B of the eighth embodiment, from the step of preparing support substrate 1700 in Fig. 81 to the step of dividing first functional element 830 in Fig. 98 into individual pieces as one unit. That is, the manufacturing method of electronic component 801B not including second functional element 860 includes an insulating layer forming step of forming insulating layer 1790, a first internal electrode forming step of forming wiring layer 1724 consisting of main surface wiring and through wiring, a second internal electrode forming step of forming connecting conductor 1723, a first element mounting step of mounting first functional element 830, a resin layer forming step of forming resin layer 1740, and a cutting step of cutting resin layer 1740 etc.

[0445] (Additional Note) The technical ideas that can be understood from the above-described embodiments and modifications will be described below.

[0446] (Appendix 1-1) a substrate having a substrate main surface and a substrate back surface facing in opposite directions; A wiring portion having a conductive layer formed on the main surface of the substrate; a joint portion having a first plating layer formed on an upper surface of the wiring portion and a first solder layer formed on an upper surface of the first plating layer; a semiconductor element having a main surface facing the substrate main surface, an element electrode formed on the main surface, and a second solder layer formed on a lower surface of the element electrode and joined to the first solder layer; A sealing resin that covers the semiconductor element; Equipped with the bonding portion is larger than the element electrode when viewed in a thickness direction perpendicular to the main surface of the substrate; Semiconductor device.

[0447] (Appendix 1-2) The semiconductor device according to claim 1-1, wherein the aspect ratio of the first solder layer in a cross section perpendicular to the main surface of the substrate is 40 or more and 80 or less.

[0448] (Appendix 1-3) The semiconductor device according to claim 1-1 or 1-2, wherein a distance from the element electrode to an end of the joint is 4 μm or more and 10 μm or less.

[0449] (Appendix 1-4) The semiconductor device according to any one of claims 1-1 to 1-3, wherein a distance between an end of the conductive layer and an end of the joint is 1 μm or less.

[0450] (Appendix 1-5) the element electrode and the second solder layer are disposed on both ends of the mounting surface along a first direction parallel to the mounting surface, The wiring portion is formed so as to extend toward the outside of the semiconductor element. The semiconductor device according to any one of Supplementary Notes 1-1 to 1-4.

[0451] (Appendix 1-6) The semiconductor device according to claim 1-5, wherein the distance from the element electrode to the end of the joint is a second distance in a direction toward the outside of the semiconductor element that is greater than a first distance in a direction toward the inside of the semiconductor element.

[0452] (Appendix 1-7) The semiconductor device according to any one of claims 1-1 to 1-6, wherein the thickness of the solder layer is equal to or less than the thickness of the first plating layer.

[0453] (Appendix 1-8) The semiconductor device according to any one of claims 1-1 to 1-7, wherein the thickness of the first solder layer is 1 μm or more and 5 μm or less, and the thickness of the first plating layer is 3 μm or more and 5 μm or less.

[0454] (Appendix 1-9) The semiconductor device according to any one of claims 1-1 to 1-8, wherein the conductive layer has a thickness of 15 μm or more and 20 μm or less.

[0455] (Appendix 1-10) The semiconductor device according to any one of claims 1-1 to 1-9, wherein a thickness of the solder layer consisting of the first solder layer and the second solder layer is 10 μm or more and 15 μm or less.

[0456] (Appendix 1-11) The semiconductor device according to any one of claims 1-1 to 1-10, wherein the conductive layer is made of Cu and the first plating layer is made of Ni.

[0457] (Appendix 1-12) The semiconductor device according to any one of claims 1-1 to 1-11, wherein the element electrode has a second plating layer, and the second solder layer is formed on a lower surface of the second plating layer.

[0458] (Appendix 1-13) The semiconductor device according to claim 1-12, wherein the second plating layer is made of Ni.

[0459] (Appendix 1-14) The semiconductor device according to any one of claims 1-1 to 1-13, further comprising a metal layer formed on a lower surface of the conductive layer.

[0460] (Appendix 1-15) The semiconductor device according to any one of claims 1 to 14, wherein the metal layer contains Ti.

[0461] (Appendix 1-16) The substrate is made of resin, the wiring portion includes a main surface wiring including the conductive layer, and a through-wire that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the substrate in the thickness direction. The semiconductor device according to any one of claims 1-1 to 1-15,

[0462] (Appendix 1-17) The semiconductor device according to claim 1-16, further comprising an external connection terminal that covers the through-wiring exposed on the rear surface of the substrate.

[0463] (Appendix 1-18) The semiconductor device according to claim 1-17, wherein the main surface wiring and the through wiring are exposed at a side surface of the substrate.

[0464] (Appendix 1-19) The semiconductor device according to claim 1-18, wherein the external connection terminal covers the main surface wiring and the through wiring exposed at a side surface of the substrate.

[0465] (Appendix 1-20) the wiring portion has a columnar wiring provided on an opposite side of the main surface wiring from the through wiring, The pillar-shaped wiring extends in the thickness direction and has a side surface exposed from a side surface of the resin. The semiconductor device according to claim 1-16.

[0466] (Appendix 1-21) The semiconductor device described in Appendix 1-20, wherein the sealing resin has a first resin portion on the substrate side and a second resin portion on the resin top surface side, and when viewed from the thickness direction, the second resin portion is larger than the first resin portion.

[0467] (Appendix 1-22) The semiconductor device according to claim 1-20 or 1-21, further comprising an external connection terminal that covers the wiring portion exposed from the substrate and the sealing resin.

[0468] (Appendix 1-23) The substrate is made of resin, the wiring portion includes a main surface wiring including the conductive layer, and a through-wire that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the sealing resin in the thickness direction. The semiconductor device according to any one of claims 1-1 to 1-15,

[0469] (Appendix 1-24) The semiconductor device according to claim 1-23, further comprising an external connection terminal covering the through wiring exposed on an upper surface of the sealing resin.

[0470] (Appendix 1-25) the substrate is made of a semiconductor material; the wiring portion includes a main surface wiring including the conductive layer, and a through-wire that is disposed outside the semiconductor element when viewed from the thickness direction, is connected to the main surface wiring, and penetrates the substrate in the thickness direction. The semiconductor device according to any one of claims 1-1 to 1-15,

[0471] (Appendix 1-26) The semiconductor device described in Appendix 1-25, wherein the substrate has a first insulating layer interposed between the substrate main surface and the conductive layer, and a second insulating layer interposed between the inner wall of a through hole in which the through wiring is arranged and the through wiring.

[0472] (Appendix 1-27) The semiconductor device according to claim 1-25 or 1-26, wherein the through wiring has an upper surface facing the conductive layer, and the upper surface is concave toward the inside of the through wiring.

[0473] (Appendix 1-28) The semiconductor device according to any one of claims 1-23 to 1-27, further comprising an external connection terminal that covers the through-wiring exposed on a rear surface of the substrate.

[0474] (Appendix 2-1) a sealing resin including a first layer having a first main surface and a first back surface facing opposite sides to each other in a thickness direction, and a second layer having a second back surface in contact with the first main surface, and a second main surface facing the side opposite to the second back surface in the thickness direction; a wiring in contact with the first main surface and partly covered with the second layer; A semiconductor device comprising: a lower surface opposite to the first main surface; and a plurality of pads provided on the lower surface, at least one of the plurality of pads being joined to the wiring; and a semiconductor element covered by the second layer.

[0475] (Appendix 2-2) The semiconductor device according to claim 2-1, wherein a distance between the first main surface and the first back surface is smaller than a distance between the second main surface and the second back surface.

[0476] (Appendix 2-3) The semiconductor device according to claim 2-2, wherein the first layer contains a filler including an inorganic compound.

[0477] (Appendix 2-4) Further comprising a plurality of interconnections connected to the interconnections, each of the plurality of interconnections extends from the interconnection to the first back surface and is partially covered by the first layer; The semiconductor device according to claim 2-2 or 2-3, wherein each of the plurality of interconnections has a bottom surface exposed at the first back surface.

[0478] (Appendix 2-5) Further comprising a plurality of terminals; The semiconductor device according to claim 2-4, wherein the plurality of terminals individually cover the bottom surfaces of the plurality of interconnections.

[0479] (Appendix 2-6) The semiconductor device according to claim 2-5, wherein each of the plurality of terminals includes a plurality of metal layers stacked in the thickness direction.

[0480] (Appendix 2-7) The semiconductor device described in Appendix 2-6, wherein a composition of the multiple metal layers includes nickel and gold.

[0481] (Appendix 2-8) The semiconductor device according to claim 2-5, wherein each of the plurality of terminals includes a solder ball.

[0482] (Appendix 2-9) the first layer has a side surface that faces a direction perpendicular to the thickness direction and is connected to a first main surface and a first back surface; The semiconductor device according to claim 2-6 or 2-7, wherein each of the plurality of interconnections has an end face exposed at the side surface.

[0483] (Appendix 2-10) Each of the plurality of terminals has a bottom and a side connected to the bottom, the bottom portion covers the bottom surface of any of the plurality of interconnections; The semiconductor device according to claim 2-9, wherein the side portion covers the end face of any one of the plurality of interconnections.

[0484] (Appendix 2-11) Further comprising a heat sink; the heat sink includes a portion embedded in the first layer and in contact with the second back surface, The semiconductor device according to claim 2-6, wherein at least a portion of the heat sink overlaps with the semiconductor element when viewed along the thickness direction.

[0485] (Appendix 2-12) the heat sink has a base portion embedded in the first layer and a covering portion laminated on the base portion and exposed at the first back surface, a thickness of the base portion is equal to a distance between the first main surface and the first back surface, The semiconductor device described in Appendix 2-11, wherein the covering portion includes the multiple metal layers.

[0486] (Appendix 2-13) the heat sink has a bump portion protruding from the base portion toward the lower surface in the thickness direction, 13. The semiconductor device according to claim 12, wherein any one of the plurality of pads is bonded to the bump portion.

[0487] (Appendix 2-14) Further comprising a plurality of first interconnections and a plurality of second interconnections connected to the interconnections; each of the plurality of first interconnections extends from the interconnection to the first back surface and is partially covered by the first layer; each of the plurality of first interconnections has a bottom surface exposed on the first back surface; each of the plurality of second interconnections extends from the interconnection to the second main surface and is partially covered by the second layer; The semiconductor device according to claim 2-2 or 2-3, wherein each of the plurality of second interconnections has a top surface exposed at the second main surface.

[0488] (Appendix 2-15) The semiconductor device described in Appendix 2-14, wherein, when viewed along the thickness direction, the shortest distance from the center of the semiconductor element to any one of the plurality of second interconnections is shorter than the shortest distance from the center of the semiconductor element to any one of the plurality of first interconnections.

[0489] (Appendix 2-16) Further comprising a plurality of first terminals and a plurality of second terminals; the first terminals cover the bottom surfaces...

Claims

1. forming a plurality of through-hole wirings on an electrically insulating supporting substrate; an insulating layer forming step of forming an insulating layer on the support substrate so as to fill spaces between the through-hole wirings and expose the through-hole wirings from both an insulating main surface and an insulating back surface facing opposite sides in a thickness direction; a main surface wiring forming step of forming a main surface wiring on the insulating main surface, the main surface wiring having a main surface and a back surface of the wiring facing opposite sides in the thickness direction, the back surface of the wiring being electrically connected to the through wiring; a conductor forming step of forming a connection conductor on the wiring main surface; a first element mounting step of mounting a first functional element on the wiring main surface; a resin layer forming step of forming a resin layer that covers the main surface wiring, the connecting conductor, and the first functional element; a cutting process for cutting the insulating layer, the resin layer, the main surface wiring, and the through wiring in the thickness direction to form an insulating member provided with the through wiring and a sealing resin covering the main surface wiring, the connecting conductor, and the first functional element; Equipped with In the resin layer forming step, the resin layer is formed such that the connecting conductor is exposed from a surface of the resin layer opposite to the insulating member, a second element mounting step of mounting a second functional element on a surface of the sealing resin opposite to the insulating member so as to be electrically connected to the connecting conductor. A method for manufacturing electronic components.

2. an insulating layer forming step of forming an insulating layer having an insulating main surface and an insulating back surface facing opposite sides in a thickness direction; a first internal electrode forming process for forming a through-hole wiring exposed from the insulating back surface, and a main surface wiring having a wiring main surface and a wiring back surface facing opposite sides in the thickness direction, the main surface being laminated on the insulating main surface so as to be conductive with the through-hole wiring on the wiring back surface; a second internal electrode forming step of forming a connecting conductor to be laminated on the wiring main surface; a first element mounting step of mounting a first functional element on the wiring main surface; a resin layer forming step of forming a resin layer that covers the main surface wiring, the connecting conductor, and the first functional element; a cutting process for cutting the insulating layer, the through wiring, the wiring main surface, and the resin layer in the thickness direction to form an insulating member provided with the through wiring and a sealing resin covering the main surface wiring, the connecting conductor, and the first functional element; Equipped with In the resin layer forming step, the resin layer is formed such that the connecting conductor is exposed from a surface of the resin layer opposite to the insulating member, a second element mounting step of mounting a second functional element on a surface of the sealing resin opposite to the insulating member so as to be electrically connected to the connecting conductor. A method for manufacturing electronic components.

3. forming a plurality of through-wires on a support substrate; an insulating layer forming step of forming an insulating layer on the support substrate so as to fill spaces between the through-hole wirings and expose the through-hole wirings from both an insulating main surface and an insulating back surface facing opposite sides in a thickness direction; a main surface wiring forming step of forming a main surface wiring on the insulating main surface, the main surface wiring having a main surface and a back surface of the wiring facing opposite sides in the thickness direction, the back surface of the wiring being electrically connected to the through wiring; a conductor forming step of forming a connection conductor on the wiring main surface; a first element mounting step of mounting a first functional element on the wiring main surface; a resin layer forming step of forming a resin layer that covers the main surface wiring, the connecting conductor, and the first functional element; a cutting process for cutting the insulating layer, the resin layer, the main surface wiring, and the through wiring in the thickness direction to form an insulating member provided with the through wiring and a sealing resin covering the main surface wiring, the connecting conductor, and the first functional element; Equipped with In the resin layer forming step, the resin layer is formed such that the connecting conductor is exposed from a surface of the resin layer opposite to the insulating member, the sealing resin has an element mounting surface on which a second functional element electrically connected to the connecting conductor is mounted, The element mounting surface is formed on the surface of the sealing resin opposite to the insulating layer in the thickness direction. A method for manufacturing electronic components.

4. an insulating layer forming step of forming an insulating layer having an insulating main surface and an insulating back surface facing opposite sides in a thickness direction; a first internal electrode forming process for forming a through-hole wiring exposed from the insulating back surface, and a main surface wiring having a wiring main surface and a wiring back surface facing opposite sides in the thickness direction, the main surface being laminated on the insulating main surface so as to be conductive with the through-hole wiring on the wiring back surface; a second internal electrode forming step of forming a connecting conductor to be laminated on the wiring main surface; a first element mounting step of mounting a first functional element on the wiring main surface; a resin layer forming step of forming a resin layer that covers the main surface wiring, the connecting conductor, and the first functional element; a cutting process for cutting the insulating layer, the through wiring, the wiring main surface, and the resin layer in the thickness direction to form an insulating member provided with the through wiring and a sealing resin covering the main surface wiring, the connecting conductor, and the first functional element; Equipped with In the resin layer forming step, the resin layer is formed such that the connecting conductor is exposed from a surface of the resin layer opposite to the insulating member, the sealing resin has an element mounting surface on which a second functional element electrically connected to the connecting conductor is mounted, The element mounting surface is formed on the surface of the sealing resin opposite to the insulating layer in the thickness direction. A method for manufacturing electronic components.

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