Clock Driver for Time-Interleaved Digital-to-Analog Converter

Abstract

In some aspects, a method for providing a first driving clock signal and a second driving clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal with the first divided clock signal to generate the first driving clock signal and inputting the first driving clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal with the second divided clock signal to generate a second driving clock signal and inputting the second driving clock signal to a clock input of the second sub-DAC.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to and the benefit of nonprovisional patent application Ser. No. 17 / 654,916, filed with the U.S. Patent and Trademark Office on March 15, 2022, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes. [Background technology]

[0002] Aspects of the present disclosure relate generally to digital-to-analog converters (DACs), and more specifically to time-interleaved DACs.

[0003] Background technology

[0003] High-bandwidth communication systems require high-speed digital-to-analog conversion. One technique for achieving high-speed digital-to-analog conversion is to time-interleave two or more digital-to-analog converters (DACs), where the two or more interleaved DACs alternately convert a digital signal to an analog signal. Summary of the Invention

[0004]

[0004] In the following, a simplified summary of one or more implementations is presented to provide a basic understanding of such implementations. This "Summary" is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the "Description of the Preferred Embodiments" presented later.

[0005]

[0005] A first aspect relates to a system. The system includes a clock divider circuit having an input, a first output, and a second output, the input of the clock divider circuit configured to receive an input clock signal. The system also includes a first clock gating circuit having a first input, a second input, and an output, the first input of the first clock gating circuit configured to receive the input clock signal, and the second input of the first clock gating circuit coupled to the first output of the clock divider circuit. The system also includes a second clock gating circuit having a first input, a second input, and an output, the first input of the second clock gating circuit configured to receive the input clock signal, and the second input of the second clock gating circuit coupled to the second output of the clock divider circuit. The system also includes a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit, and a second sub-DAC having a clock input coupled to the output of the second clock gating circuit.

[0006]

[0006] A second aspect relates to a system. The system includes a clock divider circuit having an input, a first output, and a second output, the input of the clock divider circuit configured to receive an input clock signal. The system also includes a first clock gating circuit having a first input, a second input, and an output, the first input of the first clock gating circuit configured to receive the input clock signal, and the second input of the first clock gating circuit coupled to the first output of the clock divider circuit. The system also includes a multiplexer having a first input, a second input, and an output, the first input of the multiplexer coupled to the first output of the clock divider circuit, and the second input of the multiplexer coupled to the second output of the clock divider circuit. The system also includes a second clock gating circuit having a first input, a second input, and an output, the first input of the second clock gating circuit configured to receive the input clock signal, and the second input of the second clock gating circuit coupled to the output of the multiplexer. The system also includes a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit, and a second sub-DAC having a clock input coupled to the output of the second clock gating circuit.

[0007]

[0007] A third aspect relates to a method for providing a first driving clock signal and a second driving clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC. The method includes receiving an input clock signal and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal with the first divided clock signal to generate the first driving clock signal and inputting the first driving clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal with the second divided clock signal to generate a second driving clock signal and inputting the second driving clock signal to a clock input of the second sub-DAC. [Brief description of the drawings]

[0008] [Figure 1] 1 illustrates an example of a time-interleaved digital-to-analog converter (DAC) in accordance with certain aspects of the present disclosure. [Diagram 2]

[0009] 1 illustrates an example of a clock circuit coupled to a time-interleaved DAC circuit in accordance with certain aspects of the present disclosure. [Diagram 3]

[0010] FIG. 2 is a timing diagram illustrating an example of a clock signal input to a time-interleaved DAC circuit in accordance with certain aspects of the present disclosure. [Figure 4]

[0011] 1 illustrates an example of a clock circuit including a clock gating circuit in accordance with certain aspects of the present disclosure. [Diagram 5]

[0012] 5 is a timing diagram illustrating an example of clock signals in the clock circuit of FIG. 4 in accordance with certain aspects of the present disclosure. [Figure 6A]

[0013] 1 illustrates an example implementation of a clock gating circuit in accordance with certain aspects of the present disclosure. [Figure 6B]

[0014] 1 illustrates another exemplary implementation of a clock gating circuit in accordance with certain aspects of the present disclosure. [Figure 7A]

[0015] FIG. 6B is a timing diagram illustrating an example of signals in a first clock gating circuit and a second clock gating circuit, each of which is implemented using the example clock gating circuit of FIG. 6A, in accordance with certain aspects of the present disclosure. [Figure 7B]

[0016] FIG. 6B is a timing diagram illustrating an example of signals in a first clock gating circuit and a second clock gating circuit, each of which is implemented using the example clock gating circuit of FIG. 6B, in accordance with certain aspects of the present disclosure. [Figure 8]

[0017] 1 illustrates an example of a wireless device including a clock circuit and a DAC circuit in accordance with certain aspects of the present disclosure. [Figure 9]

[0018] 1 illustrates an example implementation of a transmitter in accordance with certain aspects of the present disclosure. [Figure 10]

[0019] 1 illustrates an example of a clock circuit for driving clock inputs of multiple sub-DACs in accordance with certain aspects of the present disclosure. [Figure 11]

[0020] 1 illustrates an example implementation of a transmitter including an in-phase path and a quadrature path in accordance with certain aspects of the present disclosure. [Figure 12]

[0021] 1 illustrates an example of a clock circuit including multiple clock gating circuits in accordance with certain aspects of the present disclosure. [Figure 13A]

[0022] 1 illustrates an example of a programmable clock circuit and a programmable DAC circuit in accordance with certain aspects of the present disclosure. [Figure 13B]

[0023] 13B illustrates an example of the programmable clock circuit in FIG. 13A including a second multiplexer, according to certain embodiments of the present disclosure. [Figure 13C]

[0024] 1 illustrates an example of a transmitter coupled to a programmable DAC circuit in accordance with certain aspects of the present disclosure. [Figure 14]

[0025] 1 illustrates an example of a clock multiplexer coupled to a clock circuit in accordance with certain aspects of the present disclosure. [Figure 15]

[0026] 1 illustrates an example of a clock circuit including a bypass switch and a shorting switch in accordance with certain aspects of the present disclosure. [Figure 16]

[0027] 1 illustrates an example implementation of a clock divider circuit in accordance with certain aspects of the present disclosure. [Figure 17]

[0028] 5 is a flowchart illustrating an example method of providing a first driving clock signal and a second driving clock signal to a first sub-DAC and a second sub-DAC in accordance with certain aspects of the present disclosure. [Figure 18]

[0029] 11 is a flowchart illustrating another exemplary method of providing a first driving clock signal and a second driving clock signal to a first sub-DAC and a second sub-DAC in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0030] The following detailed description, taken in conjunction with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0010]

[0031] High-bandwidth communication systems require high-speed digital-to-analog conversion. One technique for achieving high-speed digital-to-analog conversion is to time-interleave two or more digital-to-analog converters (DACs), where the two or more interleaved DACs alternately convert a digital signal to an analog signal. As used herein, a "DAC circuit" is a circuit that includes two or more DACs. Each of the two or more DACs in a DAC circuit may be referred to as a "sub-DAC."

[0011]

[0032] 1 shows an example of a DAC circuit 110 including a first sub-DAC 120, a second sub-DAC 130, and a combiner 140 according to a particular embodiment. The DAC circuit 110 has an input 112 and an output 114 configured to receive a digital signal. The first sub-DAC 120 has a data input 122, a clock input 124, and an output 126. The second sub-DAC 130 has a data input 132, a clock input 134, and an output 136. The data input 122 of the first sub-DAC 120 and the data input 132 of the second sub-DAC 130 are coupled to an input 112 of the DAC circuit 110. The combiner 140 has a first input 142 coupled to the output 126 of the first sub-DAC 120, a second input 144 coupled to the output 136 of the second sub-DAC 130, and an output 146 coupled to the output 114 of the DAC circuit 110. Although the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130 are each shown as single-ended outputs in FIG. 1, it should be understood that the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130 may each be a differential output in some implementations.

[0012]

[0033] The first sub-DAC 120 receives a digital signal at a data input 122 and a clock signal clk1 at a clock input 124. The first sub-DAC 120 is configured to convert the digital signal at the data input 122 to a first analog signal at an output 126. The first sub-DAC 120 is also configured to perform a digital-to-analog conversion of the digital signal based on the clock signal clk1. For example, the first sub-DAC 120 may be configured to sample a digital value of the digital signal on an edge (e.g., a rising edge) of the clock signal clk1 and convert the sampled digital value to a first analog signal at the output 126. The clock signal clk1 may be referred to as a first driving clock signal because it drives the clock input 124 of the first sub-DAC 120.

[0013]

[0034] The second sub-DAC 130 receives a digital signal at a data input 132 and a clock signal clk2 at a clock input 134. The second sub-DAC 130 is configured to convert the digital signal at the data input 132 to a second analog signal at an output 136. The second sub-DAC 130 is also configured to perform digital-to-analog conversion of the digital signal based on the clock signal clk2. For example, the second sub-DAC 130 may be configured to sample a digital value of the digital signal on an edge (e.g., a rising edge) of the clock signal clk2 and convert the sampled digital value to a second analog signal at the output 136. The clock signal clk2 may also be referred to as a second driving clock signal because it drives the clock input 134 of the second sub-DAC 130.

[0014]

[0035] The combiner 140 is configured to receive a first analog signal from the first sub-DAC 120 at a first input 142, receive a second analog signal from the second sub-DAC 130 at a second input 144, and combine the first and second analog signals into a combined analog signal at an output 146. The combined analog signal is output at an output 114 of the DAC circuit 110. In some implementations, the combiner 140 may be implemented by shorting the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130. Thus, the DAC circuit 110 converts the digital signal at the input 112 into a combined analog signal at the output 114.

[0015]

[0036] As described above, the first sub-DAC 120 performs digital-to-analog conversion of a digital signal based on the clock signal clk1, and the second sub-DAC 130 performs digital-to-analog conversion of a digital signal based on the clock signal clk2. In a specific embodiment, the clock signal clk2 is phase-shifted by 180 degrees (i.e., half a clock period) with respect to the clock signal clk1. This allows the first sub-DAC 120 and the second sub-DAC 130 to alternately perform digital-to-analog conversion. In a specific embodiment, each of the clock signals clk1 and clk2 is F s As a result, each of the first sub-DAC 120 and the second sub-DAC 130 has a frequency of F s Because the first sub-DAC 120 and the second sub-DAC alternately perform digital-to-analog conversion, the DAC circuit 110 converts the digital signal at the input 112 to a signal at a frequency (i.e., rate) of 2F. s (i.e., twice the frequency of each of the sub-DACs 120 and 130) to an analog signal (i.e., a composite analog signal at output 114). Thus, DAC circuit 110 achieves a digital-to-analog conversion rate that is twice the digital-to-analog conversion rate of each of the sub-DACs 120 and 130.

[0016]

[0037] A challenge with using the DAC circuit 110 is the time skew between the sub-DACs 120 and 130, which degrades image attenuation and interleaving operation. For example, the time skew can be caused by a phase imbalance where the clock signal clk2 is not exactly 180 degrees out of phase with the clock signal clk1. To address this, calibration techniques have been developed that measure the image power due to the time skew and reduce the time skew based on the measurement using delay control circuits. However, the calibration techniques are complex, require long calibration times, and can consume large amounts of power and area.

[0017]

[0038] FIG. 2 shows an existing clock circuit 200 for generating clock signals clk1 and clk2. The clock circuit 200 includes a clock divider 210 (also called a divider), a duty cycle correction (DCC) block 220, and serially coupled clock buffers 230 and 240. The clock circuit 200 is configured to output a clock signal clk1 that is input to the clock input 124 of the first sub-DAC 120. In this example, the second sub-DAC 130 has an inverted clock input 134 (indicated by a circle at the clock input 134), which means that the clock signal clk1 is inverted to provide the clock signal clk2 to the second sub-DAC 130. It should be noted that the data inputs and outputs of the sub-DACs 120 and 130 are not shown in FIG. 2 for ease of explanation.

[0018]

[0039] In this example, clock circuit 200 has a 2F s The clock divider 210 divides the frequency of the input clock clk_in by two to produce F s DCC block 220 provides a divided clock signal having a frequency of about 100 kHz. DCC block 220 adjusts the duty cycle of the divided clock signal such that clock signal clk1 at output 204 has a duty cycle of about 50%. This helps to ensure that clock signals clk1 and clk2 are about 180 degrees out of phase, as explained further below. However, DCC block 220 adds complexity, area, and power consumption to clock circuit 200.

[0019]

[0040] 3 is a timing diagram illustrating the case where the duty cycle of the clock signal clk1 is not corrected by the DCC block 220. Ideally, when the duty cycle of the clock signal clk1 is 50%, the rising edge 310 and the falling edge 315 are aligned at half the clock period (i.e., 0.5 / F), which corresponds to a phase of 180 degrees. s) in the example shown in FIG. 3, however, clock signal clk1 has a duty cycle of less than 50%, which causes the separation between rising edge 310 and falling edge 315 to be less than half a clock period. When clock signal clk1 is inverted to become clock signal clk2, falling edge 315 becomes rising edge 320 of clock signal clk2. As shown in FIG. 3, a duty cycle of less than 50% causes the phase difference between rising edge 310 of clock signal clk1 and rising edge 320 of clock signal clk2 to be less than 180 degrees out of phase, resulting in time skew. Assuming that each of sub-DACs 120 and 130 performs digital-to-analog conversion on the rising edge of the respective clock signal, the time skew degrades the time interleaved operation of DAC circuit 110.

[0020]

[0041] Aspects of the present disclosure provide a clock gating circuit for generating clock signals for sub-DACs with low time skew without requiring a DCC block or calibration, as described further below. In addition, aspects of the present disclosure provide output switches, multiplexers, and internal bypass switches that can be used with the clock gating circuit to handle different phase requirements for different modes (e.g., 4G and 5G modes in a transceiver).

[0021]

[0042] 4 illustrates an example of a clock circuit 400 (also referred to as a clock driver) according to certain aspects of the present disclosure. The clock circuit 400 includes a clock divider circuit 410 (also referred to as a divider), a first clock gating circuit (CGC) 420, and a second CGC 430. The clock circuit 400 has an input 402, a first output 404, and a second output 406. The input 402 is configured to receive an input clock signal clk_in from a clock source (e.g., a phase locked loop (PLL)). The first output 404 is coupled to the first clock input 124 of the first sub-DAC 120, and the second output 406 is coupled to the clock input 134 of the second sub-DAC 130.

[0022]

[0043] The clock divider circuit 410 has an input 412, a first output 414, and a second output 416. The input 412 is coupled to the input 402 of the clock circuit 400 and is configured to receive an input clock signal clk_in. In one example, the input clock signal clk_in is 2F s The clock divider circuit 410 is configured to divide the frequency of the input clock signal clk_in to generate a first divided clock signal and a second divided clock signal. In some aspects, the second divided clock signal is approximately 180 degrees out of phase with the first divided clock signal, as described further below. In one example, the clock divider circuit 410 is configured to divide the frequency of the input clock signal clk_in by two, and the first divided clock signal and the second divided clock signal each have a frequency of F. s It should be understood, however, that the disclosure is not limited to this example and that the clock divider circuit 410 may divide the frequency of the input clock signal clk_in by another divisor to generate the first and second divided clock signals. The clock divider circuit 410 outputs the first divided clock signal at a first output 414 and the second divided clock signal at a second output 416.

[0023]

[0044] The first CGC 420 has a first input 422, a second input 424, and an output 426. The first input 422 is coupled to the input 402 of the clock circuit 400 to receive the input clock signal clk_in, and the second input 424 is coupled to the first output 414 of the clock divider circuit 410 to receive the first divided clock signal. The output 426 is coupled to the first output 404 of the clock circuit 400, which is coupled to the clock input 124 of the first sub-DAC 120. In operation, the first CGC 420 is configured to gate the input clock signal clk_in using the first divided clock signal to generate the clock signal clk1 for the first sub-DAC 120.

[0024]

[0045] The second CGC 430 has a first input 432, a second input 434, and an output 436. The first input 432 is coupled to the input 402 of the clock circuit 400 to receive the input clock signal clk_in, and the second input 434 is coupled to the second output 416 of the clock divider circuit 410 to receive the second divided clock signal. The output 436 is coupled to the second output 406 of the clock circuit 400, which is coupled to the clock input 134 of the second sub-DAC 130. In operation, the second CGC 430 is configured to gate the input clock signal clk2 using the second divided clock signal to generate the clock signal clk2 for the second sub-DAC 130.

[0025]

[0046] The first CGC 420 and the second CGC 430 may gate alternating pulses of the input clock signal clk_in to generate clock signals clk1 and clk2 that are 180 degrees out of phase. For example, the first CGC 420 may gate even pulses of the input clock signal clk_in using a first divided clock signal to generate clock signal clk1, and the second CGC 430 may gate odd pulses of the input clock signal clk_in using a second divided clock signal to generate clock signal clk2, or vice versa.

[0026]

[0047] An example of clock gating is shown in Figure 5, which shows an example timing diagram of input clock signal clk, clock signal clk1, and clock signal clk2. In this example, a first CGC 420 gates even pulses of the input clock signal clk_in to generate clock signal clk1, and a second CGC 430 gates odd pulses of the input clock signal clk_in to generate clock signal clk2. As shown in Figure 5, this results in rising edges 510 and 515 of clock signals clk1 and clk2 being spaced apart by one period of the input clock signal clk_in, which is the case when the input clock signal clk_in is 2F s Since it has a frequency of 1 / 2F s Equal to the input clock period 1 / 2F s is the clock frequency F, which is the frequency of each of the clock signals clk1 and clk2. s 0.5 / F, which is exactly 180 degrees away from s Thus, the rising edges 510 and 515 of the clock signals clk1 and clk2 are 180 degrees apart. Assuming that each of the sub-DACs 120 and 130 performs a digital-to-analog conversion on the rising edge of its respective clock signal, the clock signals clk1 and clk2 cause the sub-DACs 120 and 130 to perform digital-to-analog conversions 180 degrees out of phase with each other. This allows the first sub-DAC 120 and the second sub-DAC 130 to operate in a time-interleaved manner (e.g., in the DAC circuit 110 shown in FIG. 1).

[0027]

[0048] The rising edges 510 and 515 of the clock signals clk1 and clk2 are 180 degrees apart even when the duty cycle of the input clock signal clk_in is not 50%. This is because, unlike the example shown in FIG. 3, the clock circuit 400 does not generate the rising edge of the clock signal clk2 by inverting the falling edge of the clock signal clk1, which is sensitive to the duty cycle of the clock signal clk1. For example, FIG. 5 shows an example in which the input clock signal clk_in has a duty cycle of less than 50%. As shown in FIG. 5, the rising edges 510 and 515 of the clock signals clk1 and clk2 are 180 degrees apart even when the input clock signal clk_in has a duty cycle of less than 50%. The same applies when the input clock signal clk_in has a duty cycle of more than 50%. Therefore, clock circuit 400 can generate clock signals clk1 and clk2 that are 180 degrees apart without the need for duty cycle correction by DCC block 220 of FIG.

[0028]

[0049] 5, note that the falling edges 520 and 525 of the clock signals clk1 and clk2 are also 180 degrees apart. As a result, the clock signals clk1 and clk2 cause the sub-DACs 120 and 130 to perform digital-to-analog conversions that are 180 degrees out of phase with each other when each of the sub-DACs 120 and 130 performs digital-to-analog conversions on the falling edges of their respective clock signals. Thus, the clock circuit 400 can be used when each of the sub-DACs 120 and 130 performs digital-to-analog conversions on the rising edges of their respective clock signals, or when each of the sub-DACs 120 and 130 performs digital-to-analog conversions on the falling edges of their respective clock signals.

[0029]

[0050] 6A illustrates an example implementation of a CGC 610 according to certain aspects. The example CGC 610 may be used to implement each of the first CGC 420 and the second CGC 430 of FIG. 4 (i.e., each of the first CGC 420 and the second CGC 430 may be a separate instance of the CGC 610).

[0030]

[0051] In this example, the CGC 610 has a first input 612, a second input 614, and an output 616. In an example where the CGC 610 implements the first CGC 420, the first input 612 corresponds to the first input 422, the second input 614 corresponds to the second input 424, and the output 616 corresponds to the output 426. In this example, the first input 612 receives the input clock signal clk_in and the second input 614 receives the first divided clock signal from the clock divider circuit 410. In an example where the CGC 610 implements the second CGC 430, the first input 612 corresponds to the first input 432, the second input 614 corresponds to the second input 434, and the output 616 corresponds to the output 436. In this example, the first input 612 receives the input clock signal clk_in and the second input 614 receives the second divided clock signal from the clock divider circuit 410. As explained above, the second divided clock signal is 180 degrees out of phase with the first divided clock signal according to a particular embodiment.

[0031]

[0052] In this example, the CGC 610 includes a NOR gate 620, a delay circuit 630, and an AND gate 640. The NOR gate 620 has a first input 622 coupled to a first input 612 of the CGC 610, a second input 624 coupled to a second input 614 of the CGC 610, and an output 626. The AND gate 640 has a first input 642, a second input 644 coupled to the first input 612 of the CGC 610, and an output 646 coupled to an output 616 of the CGC 610. The delay circuit 630 is coupled between the output 626 of the NOR 620 and the first input 642 of the AND gate 640. It should be understood that each of the NOR gate 620 and the AND gate 640 may be implemented using a combination of logic gates in some implementations. For example, the AND gate 640 may be implemented using a NAND gate and an inverter in some implementations.

[0032]

[0053] In an example where CGC 610 implements the first CGC 420, NOR gate 620 receives the input clock signal clk_in and the first divided clock signal from clock divider circuit 410. NOR gate 620 then generates an internal clock gating signal (labeled "gate_en") by performing a NOR operation on the first divided clock signal and the input clock signal clk_in. Delay circuit 630 delays the clock gating signal by a time delay that may be programmable. As explained further below, the time delay controls the pulse width of clock signal clk1. In FIG. 6A, the delayed clock gating signal is labeled "gate_en_delayed."

[0033]

[0054] AND gate 640 receives the delayed clock gating signal and the input clock signal clk_in. AND gate 640 then gates the input clock signal clk_in with the delayed clock gating signal to generate clock signal clk1. In this example, AND gate 640 gates the input clock signal clk_in by performing an AND operation on the input clock signal clk_in and the delayed clock gating signal.

[0034]

[0055] 7A is a timing diagram illustrating example signals 710 in a first CGC 420 for an example where the first CGC 420 is implemented with a CGC 610, according to certain aspects. In the example of FIG. 7A, the signals 710 include an input clock signal clk_in, a first divided clock signal (labeled "clk_div1"), a clock gating signal (labeled "gate_en1"), a delayed clock gating signal (labeled "gate_en_delayed1"), and a clock signal clk1. The pulse width of the clock signal clk1 can be adjusted by adjusting the delay of the delay circuit 630. The longer the delay, the wider the pulse width.

[0035]

[0056] In an example where CGC 610 implements the second CGC 430, NOR gate 620 receives the input clock signal clk_in and the second divided clock signal from clock divider circuit 410. NOR gate 620 then generates an internal clock gating signal (labeled "gate_en") by performing a NOR operation on the second divided clock signal and the input clock signal clk_in. Delay circuit 630 delays the clock gating signal by a time delay that may be programmable.

[0036]

[0057] AND gate 640 receives the delayed clock gating signal (labeled "gate_en_delayed") and the input clock signal clk_in. AND gate 640 then gates the input clock signal clk_in with the delayed clock gating signal to generate clock signal clk2. In this example, AND gate 640 gates the input clock signal clk_in by performing an AND operation on the input clock signal clk_in and the delayed clock gating signal.

[0037]

[0058] FIG. 7A also illustrates exemplary signals 720 in the second CGC 430 for an example where the second CGC 430 is implemented with the CGC 610, according to certain aspects. In the example of FIG. 7A, the signals 720 include an input clock signal clk_in, a second divided clock signal (labeled "clk_div2"), a clock gating signal (labeled "gate_en2"), a delayed clock gating signal (labeled "gate_en_delayed2"), and a clock signal clk2. In the example of FIG. 7A, the second divided clock signal is 180 degrees out of phase with the first divided clock signal (i.e., the rising edge of the second divided clock signal is shifted 180 degrees from the rising edge of the first divided clock signal). In this example, the second divided clock signal may be generated by inverting the first divided clock signal or by another technique.

[0038]

[0059] As shown in FIG. 7A, the clock signal clk1 and the clock signal clk2 are in "). One clock period of input clock signal clk_in corresponds to 180 degrees with respect to clock signals clk1 and clk2, in this example, because input clock signal clk_in has a frequency equal to twice the frequency of each of clock signals clk1 and clk2. Thus, in this example, clock signals clk1 and clk2 are 180 degrees out of phase.

[0039]

[0060] It should be understood that the first CGC 420 and the second CGC 430 are not limited to the exemplary implementation shown in FIG. 6A, and each of the first CGC 420 and the second CGC 430 may be implemented using various logic gates and various configurations of logic gates. In this regard, FIG. 6B illustrates another exemplary implementation of the CGC 610 in which the configuration of the NOR gate 620 and the delay circuit 630 has been modified relative to FIG. 6A. In this example, the delay circuit 630 is coupled between the first input 612 of the CGC 610 and the first input 622 of the NOR gate 620, the second input 624 of the NOR gate 620 is coupled to the first input 612 of the CGC 610, and the output 626 of the NOR gate 620 is coupled to the first input 642 of the AND gate 640. The second input 644 of the AND gate 640 is coupled to the second input 614 of the CGC 610.

[0040]

[0061] In this example, delay circuit 630 delays the input clock signal clk_in to generate a delayed input clock signal (labeled "clk_in_delayed"). NOR gate 620 performs a NOR operation on the input clock signal and the delayed input clock signal to generate a clock pulse whose width is controlled by the time delay of delay circuit 630. In an example where CGC 610 implements a first CGC 420, AND gate 640 gates the clock pulse with the first divided clock signal to generate clock signal clk1. In an example where CGC 610 implements a second CGC 430, AND gate 640 gates the clock pulse with the second divided clock signal to generate clock signal clk2. It should be understood that the operations of NOR gate 620 and AND gate 640 may be performed by other combinations of logic gates.

[0041]

[0062] FIG. 7B is a timing diagram illustrating example signals 750 for an example in which the CGC 610 of FIG. 6B implements the first CGC 420. FIG. 7B also illustrates example signals 760 for an example in which the CGC 610 of FIG. 6B implements the second CGC 430. As shown in FIG. 7B, the resulting clock signals clk1 and clk2 are synchronized with each other ("T in "), which corresponds to a 180 degree phase shift of clock signals clk1 and clk2. The pulse width of each of clock signals clk1 and clk2 is controlled by the time delay of a respective delay circuit.

[0042]

[0063] In general, it should be understood that each of the first CGC 420 and the second CGC 430 may include a logic gate for gating the input clock signal clk_in using the first divided clock signal or the second divided clock signal, and may include a delay circuit for adjusting the pulse width of a respective one of the clock signals clk1 and clk2.

[0043]

[0064] 8 illustrates an example of a wireless device 805 including a clock circuit 400 and a DAC circuit 110 in accordance with some aspects. In this example, the wireless device 805 also includes a phase-locked loop (PLL) 820, a baseband processor 810, a transmitter 830, and an antenna 840.

[0044]

[0065] The PLL 820 has an output 822 coupled to the input 402 of the clock circuit 400. In this example, the PLL 820 is configured to generate an input clock signal clk_in and output the input clock signal clk_in at the output 822. The clock circuit 400 receives the generated input clock signal clk_in via the input 402.

[0045]

[0066] The clock circuit 400 outputs a clock signal clk1 to the clock input 124 of the first sub-DAC 120 and a clock signal clk2 to the clock input 134 of the second sub-DAC 130. As explained above, the clock signals clk1 and clk2 may be out of phase by 180 degrees to operate the sub-DACs 120 and 130 in a time interleaved manner. This allows the DAC circuit 110 to adjust the frequency of each of the clock signals clk1 and clk2 to F. s In this case, 2F s The digital-to-analog conversion can be performed at a frequency (ie, rate) of 10 MHz.

[0046]

[0067] An input 112 of the DAC circuit 110 is coupled to an output 812 of a baseband processor 810 (also called a modem). The baseband processor 810 is configured to receive data to be transmitted (e.g., from another processor), generate a digital baseband signal including the data, and output the digital baseband signal at an output 812. The DAC circuit 110 receives the digital baseband signal via the input 112 and converts the digital baseband signal to an analog baseband signal at an output 114.

[0047]

[0068] The transmitter 830 has an input 832 coupled to the output 114 of the DAC circuit 110 and an output 834 coupled to an antenna 840. The transmitter 830 is configured to receive an analog baseband signal, process the analog baseband signal into a radio frequency (RF) signal, and output the RF signal at output 834 to the antenna 840 for transmission.

[0048]

[0069] In one example, the processing performed by the transmitter 830 may include frequency up-conversion, filtering, power amplification, and / or other processing. In this regard, FIG. 9 illustrates an example implementation of the transmitter 830, where the transmitter 830 may include a filter 910, a mixer 920, and a power amplifier 930 coupled in a chain. The filter 910 may include a baseband filter and / or a low pass filter. The mixer 920 may be configured to mix the baseband signal with a local oscillator signal (labeled "LO") to frequency up-convert the baseband signal to an RF signal. The power amplifier 930 is configured to amplify the RF signal for transmission via the antenna 840. It should be understood that the transmitter 830 may include one or more additional components not shown in FIG. 9. Although one antenna 840 is shown in FIG. 8, it should be understood that the wireless device 805 may include multiple antennas coupled to the transmitter 830 (e.g., arranged in an array).

[0049]

[0070] It should be understood that the clock circuit 400 is not limited to two sub-DACs 120 and 130, and the clock circuit 400 may be used to drive the clock inputs of more than two sub-DACs. In this regard, FIG. 10 illustrates an example in which a DAC circuit 110 includes a third sub-DAC 1020, a fourth sub-DAC 1030, and a second synthesizer 1040 according to a particular embodiment. In this example, the DAC circuit 110 has a second input 1012 configured to receive a digital signal, and a second output 1014. The third sub-DAC 1020 has a data input 1022 coupled to the second input 1012, a clock input 1024 coupled to the first output 404 of the clock circuit 400, and an output 1026. The fourth sub-DAC 1030 has a data input 1032 coupled to the second input 1012, a clock input 1034 coupled to the second output 406 of the clock circuit 400, and an output 1036. The combiner 1040 has a first input 1042 coupled to the output 1026 of the third sub-DAC 1020, a second input 1044 coupled to the output 1036 of the fourth sub-DAC 1030, and an output 1046 coupled to the second output 1014.

[0050]

[0071] The third sub-DAC 1020 receives a digital signal at a data input 1022 and a clock signal clk1 from the clock circuit 400 at a clock input 1024. The third sub-DAC 1020 is configured to convert the digital signal at the data input 1022 to a first analog signal at an output 1026. The third sub-DAC 1020 is also configured to perform digital-to-analog conversion of the digital signal based on the clock signal clk1.

[0051]

[0072] The fourth sub-DAC 1030 receives a digital signal at a data input 1032 and a clock signal clk2 from the clock circuit 400 at a clock input 1034. The fourth sub-DAC 1030 is configured to convert the digital signal at the data input 1032 to a second analog signal at an output 1036. The fourth sub-DAC 1030 is also configured to perform digital-to-analog conversion of the digital signal based on the clock signal clk2.

[0052]

[0073] The combiner 1040 is configured to receive a first analog signal from the third sub-DAC 1020 at a first input 1042, receive a second analog signal from the fourth sub-DAC 1030 at a second input 1044, and combine the first analog signal and the second analog signal into a combined analog signal at an output 1046. The combined analog signal is output at an output 1014 of the DAC circuit 110. In some implementations, the combiner 1040 may be implemented by shorting the output 1026 of the third sub-DAC 1020 and the output 1036 of the fourth sub-DAC 1030.

[0053]

[0074] As described above, the clock signal clk2 is phase-shifted by 180 degrees (i.e., half a clock period) with respect to the clock signal clk1. This allows the third sub-DAC 1020 and the fourth sub-DAC 1030 to adjust the frequency of each of the clock signals clk1 and clk2 to F. s So, 2F s The digital-to-analog conversion is performed alternately to provide an effective digital-to-analog conversion rate of .

[0054]

[0075] In certain aspects, the exemplary DAC circuit 110 shown in FIG. 10 may be used in a wireless device employing in-phase (I) and quadrature (Q) modulation. In this example, the first sub-DAC 120 and the second sub-DAC 130 may be used to generate an analog in-phase (I) signal, and the third sub-DAC 1020 and the fourth sub-DAC 1030 may be used to generate an analog quadrature (Q) signal. In this regard, FIG. 11 illustrates an exemplary implementation of a transmitter 830 configured to receive analog I and Q signals and convert the analog I and Q signals to RF signals for transmission.

[0055]

[0076] 11, the transmitter 830 includes an in-phase (I) path including a first filter 1110 and a first mixer 1120 coupled in a chain. The I path is coupled to the output 114 of the DAC circuit 110 via a first input 832-1. The first filter 1110 may include a baseband filter, a low pass filter, etc. The first mixer 1120 is configured to mix the analog I signal with a first local oscillator signal (labeled "LO_I") to frequency upconvert the analog I signal to a first RF signal.

[0056]

[0077] The transmitter 830 also includes a quadrature (Q) path including a second filter 1130 and a second mixer 1140 coupled in a chain. The Q path is coupled to a second output 1014 of the DAC circuit 110 via a second input 832-2. The second filter 1130 may include a baseband filter, a low pass filter, etc. The second mixer 1140 is configured to mix the analog Q signal with a second local oscillator signal (labeled "LO_Q") to frequency upconvert the analog Q signal to a second RF signal. The second local oscillator signal may be 90 degrees out of phase with the first local oscillator signal.

[0057]

[0078] The transmitter 830 also includes a combiner 1150 coupled to the first mixer 1120 and the second mixer 1140, and a power amplifier 1160 coupled to the combiner 1150. The combiner 1150 is configured to combine the first RF signal and the second RF signal into a combined RF signal and output the combined RF signal to the power amplifier 1160. The power amplifier 1160 amplifies the combined RF signal and outputs the resulting amplified RF signal at the output 834. It should be understood that the transmitter 830 may include one or more additional components not shown in FIG.

[0058]

[0079] In some aspects, the clock circuit 400 may include one or more additional CGCs for driving the clock inputs 1024 and 1034 of the third sub-DAC 1020 and the fourth sub-DAC 1030 instead of using the CGCs 420 and 430. In this regard, FIG. 12 illustrates an example in which the clock circuit 400 further includes a third CGC 1240 and a fourth CGC 1250 for driving the clock inputs 1024 and 1034 of the third sub-DAC 1020 and the fourth sub-DAC 1030.

[0059]

[0080] The third CGC 1240 has a first input 1242, a second input 1244, and an output 1246. The first input 1242 is coupled to the input 402 of the clock circuit 400 to receive the input clock signal clk_in, and the second input 1244 is coupled to the first output 414 of the clock divider circuit 410 to receive the first divided clock signal. The output 1246 is coupled to the third output 1204 of the clock circuit 400, which is coupled to the clock input 1024 of the third sub-DAC 1020. In one example, the third CGC 1240 can be implemented using the exemplary CGC 610 shown in FIG. 6A or FIG. 6B. In operation, the third CGC 1240 is configured to gate the input clock signal clk_in using the first divided clock signal to generate the clock signal clk3 for the third sub-DAC 1020.

[0060]

[0081] The fourth CGC 1250 has a first input 1252, a second input 1254, and an output 1256. The first input 1252 is coupled to the input 402 of the clock circuit 400 to receive the input clock signal clk_in, and the second input 1254 is coupled to the second output 416 of the clock divider circuit 410 to receive the second divided clock signal. The output 1256 is coupled to the fourth output 1206 of the clock circuit 400, which is coupled to the clock input 1034 of the fourth sub-DAC 1030. In one example, the fourth CGC 1250 can be implemented using the exemplary CGC 610 shown in FIG. 6A or FIG. 6B. In operation, the fourth CGC 1250 is configured to gate the input clock signal clk_in using the second divided clock signal to generate the clock signal clk4 for the fourth sub-DAC 1030.

[0061]

[0082] In some aspects, the clock signals clk3 and clk4 that are 180 degrees out of phase with each other may be configured to have a frequency of F s So, 2F s DAC1020 and DAC1030 alternately perform digital-to-analog conversion to provide an effective digital-to-analog conversion rate of .

[0062]

[0083] In certain aspects, the clock circuit 400 and the DAC circuit 110 may be programmable to handle two or more modes. In this regard, FIG. 13A shows an example in which the clock circuit 400 and the DAC circuit 110 may switch between a first mode and a second mode. In the first mode, the first sub-DAC 120 and the second sub-DAC 130 operate in a time-interleaved manner, as described above with reference to FIG. 4. In the second mode, the first sub-DAC 120 and the second sub-DAC 130 perform digital-to-analog conversion on separate channels. In other words, the first sub-DAC 120 and the second sub-DAC 130 are not time-interleaved in the second mode, as will be further described below.

[0063]

[0084] In this example, the clock circuit 400 includes a multiplexer 1310 having a first input 1312, a second input 1314, a selection input 1318, and an output 1316. The first input 1312 is coupled to a first output 414 of the clock divider circuit 410, the second input 1314 is coupled to a second output 416 of the clock divider circuit 410, and the output 1316 is coupled to a second input 434 of the second CGC 430. In operation, the multiplexer 1310 is configured to receive a selection signal from the controller 1365 via the selection input 1318, select the first input 1312 or the second input 1314 based on the selection signal, and couple the selected one of the first input 1312 and the second input 1314 to the output 1316 of the multiplexer 1310. In this example, the first input 1312 receives the first divided clock signal and the second input 1314 receives the second divided clock signal. Thus, when the first input 1312 is selected, the multiplexer 1310 inputs the first divided clock signal to the second input 434 of the second CGC 430, and when the second input 1314 is selected, the multiplexer 1310 inputs the second divided clock signal to the second input 434 of the second CGC 430.

[0064]

[0085] In this example, the DAC circuit 110 has a first input 112-1 coupled to a data input 122 of the first sub-DAC 120, a second input 112-2 coupled to a data input 132 of the second sub-DAC 130, and a first output 114-1 coupled to an output 146 of the combiner 140. The DAC circuit 110 also includes a second output 114-2 and a third output 114-3 for a second mode, as described further below.

[0065]

[0086] In this example, the DAC circuit 110 includes a first output switch 1330, a second output switch 1340, a third output switch 1350, and a fourth output switch 1360. The first output switch 1330 is coupled between the output 126 of the first sub-DAC 120 and the first input 142 of the combiner 140. The second output switch 1340 is coupled between the output 136 of the second sub-DAC 130 and the second input 144 of the combiner 140. The third output switch 1350 is coupled between the output 126 of the first sub-DAC 120 and the second output 114-2. The fourth output switch 1360 is coupled between the output 136 of the second sub-DAC 130 and the third output 114-3. The output switches 1330, 1340, 1350, and 1360 are controlled by a controller 1365. For ease of illustration, the individual connections between the controller 1365 and the output switches 1330, 1340, 1350, and 1360 are not explicitly shown in Figure 13A. The first output 114-1, the second output 114-2, and the third output 114-3 may also be referred to as the first DAC output, the second DAC output, and the third DAC output, respectively.

[0066]

[0087] In the first mode, the controller 1365 causes the multiplexer 1310 to select the second input 1314. Thus, in the first mode, the multiplexer 1310 inputs the second divided clock signal to the second input 434 of the second CGC 430. As a result, the clock signal clk2 is 180 degrees out of phase with the clock signal clk1, which causes the sub-DACs 120 and 130 to perform digital-to-analog conversion alternately in a time-interleaved manner. In this mode, the same digital signal may be input to the first input 112-1 and the second input 112-2.

[0067]

[0088] Also, in the first mode, the controller 1365 closes (i.e., turns on) the first output switch 1330 and the second output switch 1340, and opens (i.e., turns off) the third output switch 1350 and the fourth output switch 1360. As a result, the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130 are coupled to the combiner 140, which combines the analog signals from the sub-DACs 120 into a composite analog signal and outputs the composite analog signal at the first output 114-1. In the first mode, the DAC circuit 110 converts the composite analog signal into a 2F s The digital-to-analog conversion rate (also called the sampling rate) is 100 kHz.

[0068]

[0089] In the second mode, the controller 1365 causes the multiplexer 1310 to select the first input 1312. Thus, in the second mode, the multiplexer 1310 inputs the first divided clock signal to the second input 434 of the second CGC 430. As a result, the clock signal clk2 is approximately in phase with the clock signal clk1 because both CGCs 420 and 430 use the first divided clock signal to gate the input clock signal clk_in. In this mode, a first digital signal may be input to the first input 112-1 and a second digital signal may be input to the second input 112-2. The first sub-DAC 120 converts the first digital signal to a first analog signal, and the second sub-DAC 130 converts the second digital signal to a second analog signal.

[0069]

[0090] Also, in the second mode, the controller 1365 opens (i.e., turns off) the first output switch 1330 and the second output switch 1340, and closes (i.e., turns on) the third output switch 1350 and the fourth output switch 1360. As a result, the output 126 of the first sub-DAC 120 is coupled to the second output 114-2, and the output 136 of the second sub-DAC 130 is coupled to the third output 114-3. As a result, the first analog signal from the first sub-DAC 120 is output at the second output 114-2, and the second analog signal from the second sub-DAC 130 is output at the third output 114-3. Thus, in the second mode, the sub-DACs 120 and 130 perform digital-to-analog conversion in parallel on their respective digital signals. In the second mode, the first analog signal and the second analog signal are each output at F s The digital-to-analog conversion rate is

[0070]

[0091] It should be understood that the clock circuit 400 is not limited to one multiplexer 1310. In this regard, FIG. 13B illustrates an example in which the clock circuit 400 includes a second multiplexer 1320 between the clock divider circuit 410 and the first CGC 420 to provide additional programmability. In this example, the second multiplexer 1320 has a first input 1322 coupled to the first output 414 of the clock divider circuit 410, a second input 1324 coupled to the second output 416 of the clock divider circuit 410, a select input 1328 coupled to the controller 1365, and an output 1326 coupled to the second input 424 of the first CGC 420. In this example, the second multiplexer 1320 allows the controller 1365 to selectively input the first divided clock signal or the second divided clock signal to the second input 424 of the first CGC 420 (e.g., to support one or more additional operating modes). The second multiplexer 1320 may also be used to provide propagation delay matching with the multiplexer 1310. In the first and second modes described above, the controller 1365 causes the second multiplexer 1320 to select the first input 1322 coupled to the first output 414 of the clock divider circuit 410. Thus, in the first and second modes, the second multiplexer 1320 couples the second input 424 of the first CGC 420 to the first output 414 of the clock divider circuit 410 to receive the first divided clock signal described above.

[0071]

[0092] In an example where the clock circuit 400 and the DAC circuit 110 are used in a wireless device, the first input 112-1 and the second input 112-2 of the DAC circuit 110 may be coupled to the baseband processor 810 or another processor. Also, each of the outputs 114-1, 114-3, and 114-3 of the DAC circuit 110 may be coupled to a respective transmitter. In this regard, FIG. 13C illustrates an example where a wireless device includes a first transmitter 1370 having an input 1372 coupled to the first output 114-1, a second transmitter 1380 having an input 1382 coupled to the second output 114-2, and a third transmitter 1390 having an input 1392 coupled to the third output 114-3. Each of the transmitters 1370, 1380, and 1390 may be implemented using a separate instance of the example transmitter 830 shown in FIG. 9 or FIG. 11. In a first mode, the combined output of the first sub-DAC 120 and the second sub-DAC 130 is coupled to a first transmitter 1370. In a second mode, the output 126 of the first sub-DAC 120 is coupled to a second transmitter 1380 and the output 136 of the second sub-DAC 130 is coupled to a third transmitter 1390. The output 1374 of the first transmitter 1370, the output 1384 of the second transmitter 1380, and the output 1394 of the third transmitter 1390 may be coupled to separate antennas or to a common antenna.

[0072]

[0093] In some implementations, in the second mode, the first sub-DAC 120 may be used to generate an in-phase (I) signal, and the second sub-DAC 130 may be used to generate a quadrature (Q) signal. In this example, the second transmitter 1380 may be implemented using the I signal path of the transmitter 830 shown in FIG. 11, and the third transmitter 1390 may be implemented using the Q signal path of the example transmitter 830 shown in FIG. 11, with the input 1382 of the second transmitter 1380 corresponding to the first input 832-1 shown in FIG. 11, and the input 1392 of the third transmitter 1390 corresponding to the second input 832-2 shown in FIG. 11. In this example, one instance of the transmitter 830 shown in FIG. 11 may be used to implement the second transmitter 1380 and the third transmitter 1390.

[0073]

[0094] In certain aspects, the clock circuit 400 may use different sources of the input clock signal clk_in for different modes. In this regard, FIG. 14 illustrates an example of a system including the clock circuit 400, a clock multiplexer 1410, a first phase-locked loop (PLL) 1420, and a second PLL 1430. In this example, the first PLL 1420 outputs a first root clock signal having a first frequency, and the second PLL 1430 outputs a second root clock signal having a second frequency.

[0074]

[0095] The clock multiplexer 1410 has a first input 1412 coupled to an output 1422 of the first PLL 1420, a second input 1414 coupled to an output 1432 of the second PLL 1430, a selection input 1418 coupled to the controller 1365, and an output 1416 coupled to an input 402 of the clock circuit 400. The clock multiplexer 1410 is configured under the control of the controller 1365 to selectively input the first root clock signal from the first PLL 1420 or the second root clock signal from the second PLL 1430 to the input 402 of the clock circuit 400. In this example, the selected one of the first root clock signal and the second root clock signal becomes the input clock signal clk_in described above.

[0075]

[0096] The controller 1365 may select the first root clock signal or the second root clock signal based on the operating mode of the clock circuit 400 and the DAC circuit 110. For example, the controller 1365 may select the first root clock signal in the first mode described above and the second root clock signal in the second mode described above. This feature allows the sub-DACs 120 and 130 to operate at different digital-to-analog conversion rates for different modes.

[0076]

[0097] 15 illustrates another example of a clock circuit 400, in accordance with certain aspects. In this example, the clock circuit 400 may be coupled to the example DAC circuit 110 illustrated in FIGS. 13A and 13B.

[0077]

[0098] In this example, the clock circuit 400 may include a shorting switch 1530 coupled between the output 426 of the first CGC 420 and the output 436 of the second CGC 430. The shorting switch 1530 is controlled by a controller 1365 (shown in FIGS. 13A and 13B ). In this example, the controller 1365 may selectively close (i.e., turn on) the shorting switch 1530 to short the first output 404 and the second output 406 of the clock circuit 400.

[0078]

[0099] For example, in the second mode described above, the clock signals clk1 and clk2 may be approximately in phase because both CGCs 420 and 430 receive the first divided clock signal in the second mode. In this mode, the controller 1365 may close the shorting switch 1530 to reduce any time skew between the clock signals clk1 and clk2. The skew may be caused by small variations between the CGCs 420 and 430 (e.g., due to process variations) and / or small variations in the clock paths of the clock signals clk1 and clk2. In the example of FIG. 15, closing the shorting switch 1530 in the second mode shorts the clock input 124 of the first sub-DAC 120 and the clock input 134 of the second sub-DAC 130. The controller 1365 can open (i.e., turn off) the shorting switch 1530 in the first mode because the clock signals clk1 and clk2 are 180 degrees out of phase with each other to operate the sub-DACs 120 and 130 in a time-interleaved manner in the first mode.

[0079]

[0100] In this example, the clock circuit 400 may include a first bypass switch 1520 and a second bypass switch 1526. The first bypass switch 1520 is coupled between a first input 422 of the first CGC 420 and an output 426 of the first CGC 420. The second bypass switch 1525 is coupled between a first input 432 of the second CGC 430 and an output 436 of the second CGC 430. In this example, the controller 1365 can selectively close (i.e., turn on) the bypass switches 1520 and 1525 to bypass the CGCs 420 and 430. The controller 1365 can disable the CGCs 420 and 430 when the bypass switches 1520 and 1525 are turned on. In the first and second modes described above, the controller 1365 opens (ie, turns off) the bypass switches 1520 and 1525 since the CGCs 420 and 430 are used in these modes.

[0080]

[0101] For example, in the third mode, the controller 1365 can close (i.e., turn on) the bypass switches 1520 and 1525 to bypass the CGCs 420 and 430. In this mode, the clock inputs 124 and 134 of each of the sub-DACs 120 and 130 (shown in FIGS. 13A and 13B) are driven by the input clock signal clk_in. When the input clock signal clk_in is 2F s , so that each of the sub-DACs 120 and 130 has a frequency of 2F in the third mode. sIn the third mode, the controller 1365 closes (i.e., turns on) the first output switch 1330 and the second output switch 1340 and opens (i.e., turns off) the third output switch 1350 and the fourth output switch 1360. As a result, the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130 are coupled to the combiner 140, which combines the analog signals from the sub-DACs 120 into a combined analog signal and outputs the combined analog signal at the first output 114-1. In the third mode, the same digital signal is input to the sub-DACs 120 and 130, which convert the digital signal into a 2F s The digital-to-analog conversion can be performed in parallel and in phase with each other at a rate of

[0081]

[0102] The third mode may provide higher performance compared to the time-interleaved type at the expense of more power consumption since each sub-DAC 120 and 130 operates at twice the frequency in the third mode. The third mode may be used, for example, for use cases requiring high performance. In the third mode, the controller 1365 may also close the shorting switch 1530 since both sub-DACs 120 and 130 are driven by the input clock signal clk_in in this mode.

[0082]

[0103] In another example, in the fourth mode, the controller 1365 can close (i.e., turn on) the bypass switches 1520 and 1525 to drive the clock inputs 124 and 134 of the sub-DACs 120 and 130 (shown in FIGS. 13A and 13B) respectively with the input clock signal clk_in. s , so that each of the sub-DACs 120 and 130 has a frequency of 2F in the fourth mode. sIn the fourth mode, the controller 1365 opens the first output switch 1330 and the second output switch 1340 and closes the third output switch 1350 and the fourth output switch 1360. In this mode, a first digital signal may be input to the first input 112-1 and a second digital signal may be input to the second input 112-2. The first sub-DAC 120 converts the first digital signal to a first analog signal, and the second sub-DAC 130 converts the second digital signal to a second analog signal. The first analog signal is output from the second output 114-2 and the second analog signal is output from the third output 114-3. Since the clock inputs 124 and 134 of each of the sub-DACs 120 and 130 are driven by the input clock signal clk_in, each of the sub-DACs 120 and 130 performs a digital-to-analog conversion at a rate of 2F in the fourth mode. s It performs digital-to-analog conversion at a rate of

[0083]

[0104] It should be understood that clock circuit 400 and DAC circuit 110 are not limited to the exemplary modes described above, for example, in some implementations clock circuit 400 and DAC circuit 110 may use only a subset of the modes described above and / or may support one or more additional modes not described above.

[0084]

[0105] 16 illustrates an exemplary implementation of a clock divider circuit 410 according to certain aspects of the disclosure. In this example, the clock divider circuit 410 includes a divider 1610 and a flop 1620 (e.g., a D flip-flop). The divider 1610 has an input 1612 coupled to the input 412 of the clock divider circuit 410 and an output 1614. The flop 1620 has a latch input 1622 (labeled “D”) coupled to the output 1614 of the divider 1610, a clock input 1624 coupled to the input 412 of the clock divider circuit 410, a first output 1626 (labeled “Q”) coupled to the first output 414 of the clock divider circuit 410, and a second output 1628 (labeled “Qb”) coupled to the second output 416 of the clock divider circuit 410. The first output 1626 and the second output 1628 may be complementary outputs.

[0085]

[0106] The divider 1610 is configured to receive an input clock signal clk_in, divide the frequency of the input clock signal clk_in (e.g., by 2), and output the resulting divided clock signal at the output 1614. The flop 1620 is configured to receive the divided clock signal from the divider 1610 at a latch input 1622 and receive the input clock signal clk_in at a clock input 1624. The flop 1620 is configured to resample the divided clock signal using the input clock signal clk_in. The flop 1620 may do this by latching a logic state of the divided clock signal at the latch input 1622 on each trigger edge of the input clock signal clk_in, outputting the latched logic state at a first output 1626, and outputting an inverse of the latched logic state at a second output 1628. In one example, each trigger edge is a rising edge (also referred to as a positive edge). In another example, each trigger edge is a falling edge (also referred to as a negative edge). Resampling the divided clock signal using the input clock signal clk_in helps to synchronize the divided clock signal with the input clock signal clk_in to avoid glitches.

[0086]

[0107] In this example, the resampled divided clock signal at the first output 1626 is used for the first divided clock signal, and the inversion of the resampled divided clock signal at the second output 1628 is used for the second divided clock signal. In this example, the inversion of the resampled divided clock signal corresponds to the resampled divided clock signal shifted by only 180 degrees in phase.

[0087]

[0108] FIG. 17 shows an exemplary method 1700 for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC. The first sub-DAC may correspond to the first sub-DAC 120, and the second sub-DAC may correspond to the second sub-DAC 130.

[0088]

[0109] In block 1710, an input clock signal is received. The input clock signal may correspond to the input clock signal clk_in.

[0089]

[0110] In block 1720, the input clock signal is divided to generate a first divided clock signal and a second divided clock signal. For example, the input clock signal may be divided by a clock dividing circuit 410. In certain embodiments, the second divided clock signal is phase-shifted by approximately 180 degrees relative to the first divided clock signal. In certain embodiments, dividing the input clock signal includes dividing the frequency of the input clock signal (e.g., by 2 or another divisor) to generate the first divided clock signal and the second divided clock signal.

[0090]

[0111] In block 1730, the input clock signal is gated using the first divided clock signal to generate a first driving clock signal. For example, the input clock signal may be gated using the first divided clock signal by the first clock gating circuit 420. The first driving clock signal may correspond to the clock signal clk1.

[0091]

[0112] In block 1740, a first driving clock signal is input to a clock input of the first sub-DAC. For example, the clock input of the first sub-DAC may correspond to the clock input 124.

[0092]

[0113] In block 1750, the input clock signal is gated using the second divided clock signal to generate a second driving clock signal. For example, the input clock signal may be gated using the second divided clock signal by the second clock gating circuit 430. The second driving clock signal may correspond to the clock signal clk2.

[0093]

[0114] In block 1760, the second driving clock signal is input to a clock input of the second sub-DAC. For example, the clock input of the second sub-DAC may correspond to the clock input 134.

[0094]

[0115] In certain aspects, the method 1700 may also include combining the output of the first sub-DAC and the output of the second sub-DAC. For example, the output of the first sub-DAC and the output of the second sub-DAC may be combined by the combiner 140.

[0095]

[0116] It should be understood that method 1700 is not limited to a particular order of blocks 1710-1760. For example, it should be understood that blocks 1710 and 1760 may be performed in various orders without departing from the scope of the present disclosure. It should also be understood that two or more of blocks 1710 and 1760 may be performed simultaneously.

[0096]

[0117] 18 shows an example method 1800 for providing a first driving clock signal and a second driving clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC. The first sub-DAC may correspond to the first sub-DAC 120, and the second sub-DAC may correspond to the second sub-DAC 130.

[0097]

[0118] At block 1810, an input clock signal is received. The input clock signal may correspond to the input clock signal clk_in.

[0098]

[0119] At block 1820, the input clock signal is divided to generate a first divided clock signal and a second divided clock signal. For example, the input clock signal may be divided by the clock divider circuit 410. In a particular aspect, the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal. In a particular aspect, dividing the input clock signal includes dividing the frequency of the input clock signal (e.g., by 2 or another divisor) to generate the first divided clock signal and the second divided clock signal.

[0099]

[0120] In block 1830, the input clock signal is gated using the first divided clock signal to generate a first driving clock signal. For example, the input clock signal may be gated using the first divided clock signal by the first clock gating circuit 420. The first driving clock signal may correspond to the clock signal clk1.

[0100]

[0121] In block 1840, a first driving clock signal is input to a clock input of the first sub-DAC. For example, the clock input of the first sub-DAC may correspond to the clock input 124.

[0101]

[0122] In a first mode, in block 1850, the input clock signal is gated using the second divided clock signal to generate a second driving clock signal. For example, the input clock signal may be gated using the second divided clock signal by the second clock gating circuit 430. The second driving clock signal may correspond to the clock signal clk2.

[0102]

[0123] In the second mode, the input clock signal is gated using the first divided clock signal to generate the second driving clock signal in block 1860. For example, the multiplexer 1310 may select the second input 1314 in the first mode and the first input 1312 in the second mode.

[0103]

[0124] In block 1870, the second driving clock signal is input to a clock input of the second sub-DAC. For example, the clock input of the second sub-DAC may correspond to the clock input 134.

[0104]

[0125] It should be understood that the method 1800 is not limited to a particular order of blocks 1810-1870, and that two or more of the blocks may be performed simultaneously.

[0105]

[0126] The method 1800 may also include combining the output of the first sub-DAC with the output of the second sub-DAC in the first mode. For example, to combine the output 126 of the first sub-DAC 120 and the output 136 of the second sub-DAC 130, the output switches 1330 and 1340 may be closed and the output switches 1350 and 1360 may be opened.

[0106]

[0127] The method 1800 may also include shorting the clock input of the first sub-DAC to the clock input of the second sub-DAC in the second mode. For example, the shorting switch 1530 may be closed in the second mode to short the clock input 124 of the first sub-DAC 120 to the clock input 134 of the second sub-DAC 130.

[0107]

[0128] The method 1800 may also include coupling, in the first mode, an output of the first sub-DAC and an output of the second sub-DAC to a first transmitter.

[0108]

[0129] The method 1800 may also include, in the second mode, coupling an output of the first sub-DAC to the second transmitter and coupling an output of the second sub-DAC to the third transmitter. For example, the output switches 1350 and 1360 may be closed to couple the output 126 of the first sub-DAC 120 to the second transmitter 1380 and the output 136 of the second sub-DAC 130 to the third transmitter 1390.

[0109]

[0130] Although not explicitly shown, it should be understood that any one or more of the clock paths shown in FIG. 4, FIG. 8, and FIG. 10-FIG. 15 may include one or more clock buffers. For example, it should be understood that the clock path between the output 426 of the first CGC 420 and the clock input 124 of the first sub-DAC 120 may include one or more buffers. In this example, the output 426 of the first CGC 420 is coupled to the clock input 124 of the first sub-DAC 120 via one or more clock buffers. Similarly, the clock path between the output 436 of the second CGC 430 and the clock input 134 of the second sub-DAC 130 may include one or more buffers. In this example, the output 436 of the second CGC 430 is coupled to the clock input 134 of the second sub-DAC 130 via one or more clock buffers. Additionally, the clock path between each of the PLLs 1420 and 1430 and the clock circuit 400 may include one or more clock buffers.

[0110]

[0131] The following numbered clauses describe example implementations.

[0111]

[0132] 1. A system comprising:

[0133] a clock divider circuit having an input, a first output, and a second output, the input of the clock divider circuit configured to receive an input clock signal;

[0134] a first clock gating circuit having a first input, a second input, and an output, the first input of the first clock gating circuit configured to receive an input clock signal, and the second input of the first clock gating circuit coupled to a first output of the clock divider circuit;

[0135] a second clock gating circuit having a first input, a second input, and an output, the first input of the second clock gating circuit configured to receive an input clock signal, and the second input of the second clock gating circuit coupled to the second output of the clock divider circuit;

[0136] a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to an output of the first clock gating circuit;

[0137] a second sub-DAC having a clock input coupled to the output of the second clock gating circuit; Including, the system.

[0112]

[0138] 2. The clock divider circuit is

[0139] dividing an input clock signal to generate a first divided clock signal and a second divided clock signal;

[0140] outputting a first divided clock signal at a first output of the clock divider circuit;

[0141] outputting a second divided clock signal at a second output of the clock divider circuit; 2. The system of claim 1, configured to:

[0113]

[0142] 3. The system of claim 2, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

[0114]

[0143] 4. The system of claim 3, wherein the clock divider circuit is configured to invert the first divided clock signal to generate the second divided clock signal.

[0115]

[0144] 5. A system described in any one of clauses 2 to 4, wherein the clock divider circuit is configured to divide the frequency of an input clock signal to generate a first divided clock signal and a second divided clock signal.

[0116]

[0145] 6. The system of claim 5, wherein the frequency of the input clock signal is divided by two.

[0117]

[0146] 7. A first clock gating circuit comprising:

[0147] gating the input clock signal with the first divided clock signal to generate a first driving clock signal;

[0148] outputting a first driving clock signal at an output of the first clock gating circuit; The system according to any one of clauses 2 to 6, configured as follows:

[0118]

[0149] 8. The system of clause 7, wherein the first clock gating circuit includes a delay circuit having a time delay, and the first clock gating circuit is configured to control a pulse width of the first driving clock signal based on the time delay.

[0119]

[0150] 9. A second clock gating circuit comprising:

[0151] gating the input clock signal with the second divided clock signal to generate a second driving clock signal;

[0152] outputting a second driving clock signal at an output of the second clock gating circuit; 9. The system according to claim 7 or 8, configured to:

[0120]

[0153] 10. The system of claim 9, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

[0121]

[0154] 11.

[0155] a first clock gating circuit configured to gate even pulses of the input clock signal using the first divided clock signal to generate a first driving clock signal;

[0156] a second clock gating circuit for gating odd pulses of the input clock signal using the second divided clock signal to generate a second driving clock signal; 11. The system according to claim 9 or 10, configured to:

[0122]

[0157] 12.

[0158] a first clock gating circuit configured to gate odd pulses of the input clock signal using the first divided clock signal to generate a first driving clock signal;

[0159] a second clock gating circuit configured to gate even pulses of the input clock signal using the second divided clock signal to generate a second driving clock signal; 11. A system according to clause 9 or 10.

[0123]

[0160] 13. The system of any one of clauses 1-12, further comprising a combiner coupled to an output of the first sub-DAC and an output of the second sub-DAC.

[0124]

[0161] 14. The system of claim 13, wherein the combiner is coupled to the transmitter.

[0125]

[0162] 15. A system comprising:

[0163] A clock divider circuit having an input, a first output, and a second output, wherein the input of the clock divider circuit is configured to receive an input clock signal, the clock divider circuit;

[0164] A first clock gating circuit having a first input, a second input, and an output, wherein the first input of the first clock gating circuit is configured to receive an input clock signal, and the second input of the first clock gating circuit is coupled to the first output of the clock divider circuit, the first clock gating circuit;

[0165] A multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the first output of the clock divider circuit, and the second input of the multiplexer is coupled to the second output of the clock divider circuit, the multiplexer;

[0166] A second clock gating circuit having a first input, a second input, and an output, wherein the first input of the second clock gating circuit is configured to receive an input clock signal, and the second input of the second clock gating circuit is coupled to the output of the multiplexer, the second clock gating circuit;

[0167] A first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit;

[0168] A second sub-DAC having a clock input coupled to the output of the second clock gating circuit; A system comprising.

[0126]

[0169] 16. The clock divider circuit is

[0170] To generate a first divided clock signal and a second divided clock signal, divide the input clock signal,

[0171] Output the first divided clock signal at the first output of the clock divider circuit,

[0172] Output the second divided clock signal at the second output of the clock divider circuit. 16. The system of claim 15, configured to:

[0127]

[0173] 17. The system of clause 16, wherein the clock divider circuit is configured to divide a frequency of an input clock signal to generate the first divided clock signal and the second divided clock signal.

[0128]

[0174] 18. The system of claim 17, wherein the frequency of the input clock signal is divided by two.

[0129]

[0175] 19. The system of any one of clauses 16-18, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

[0130]

[0176] 20. The system of claim 19, wherein the clock divider circuit is configured to invert the first divided clock signal to generate the second divided clock signal.

[0131]

[0177] twenty one.

[0178] causing the multiplexer to select a second input of the multiplexer in the first mode;

[0179] causing the multiplexer to select the first input of the multiplexer in the second mode; 21. The system of any one of clauses 16 to 20, further comprising a controller configured to:

[0132]

[0180] twenty two.

[0181] a first output switch coupled between the output of the first sub-DAC and the combiner;

[0182] a second output switch coupled between the output of the second sub-DAC and the combiner;

[0183] The controller

[0184] In a first mode, the first output switch and the second output switch are closed;

[0185] In the second mode, the first output switch and the second output switch are opened, The system according to clause 21, configured as such.

[0133]

[0186] 23. Further includes a short - circuit switch coupled between the output of the first clock gating circuit and the output of the second clock gating circuit, and the controller is configured to open the short - circuit switch in the first mode and close the short - circuit switch in the second mode. The system according to clause 22.

[0134]

[0187] 24. The output of the synthesizer is coupled to the first DAC output, and the system

[0188] Further includes a third output switch coupled between the output of the first sub - DAC and the second DAC output, and

[0189] a fourth output switch coupled between the output of the second sub - DAC and the third DAC output, and

[0190] The controller

[0191] In the first mode, opens the third output switch and the fourth output switch,

[0192] In the second mode, closes the third output switch and the fourth output switch. The system according to clause 22 or 23, configured as such.

[0135]

[0193] 25.

[0194] A first bypass switch coupled between the first input of the first clock gating circuit and the output of the first clock gating circuit, and

[0195] a second bypass switch coupled between the first input of the second clock gating circuit and the output of the second clock gating circuit, and

[0196] The controller

[0197] In the first mode and the second mode, the first bypass switch and the second bypass switch are opened;

[0198] In a third mode, the first bypass switch and the second bypass switch are closed. The system according to any one of clauses 21 to 24, configured as follows:

[0136]

[0199] 26. A method for providing a first driving clock signal and a second driving clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC, comprising:

[0200] Receiving an input clock signal;

[0201] dividing an input clock signal to generate a first divided clock signal and a second divided clock signal;

[0202] gating an input clock signal with a first divided clock signal to generate a first driving clock signal;

[0203] inputting a first driving clock signal to a clock input of a first sub-DAC;

[0204] gating the input clock signal with the second divided clock signal to generate a second driving clock signal;

[0205] inputting a second driving clock signal to a clock input of a second sub-DAC; A method comprising:

[0137]

[0206] 27. The method of claim 26, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

[0138]

[0207] 28.

[0208] gating the input clock signal with the first divided clock signal includes gating even pulses of the input clock signal with the first divided clock signal;

[0209] gating the input clock signal with the second divided clock signal includes gating odd pulses of the input clock signal with the second divided clock signal. 28. The method according to clause 26 or 27.

[0139]

[0210] 29.

[0211] gating the input clock signal with the first divided clock signal includes gating odd pulses of the input clock signal with the first divided clock signal;

[0212] gating the input clock signal with the second divided clock signal includes gating even pulses of the input clock signal with the second divided clock signal. 28. The method according to clause 26 or 27.

[0140]

[0213] 30. The method of any one of clauses 26 to 29, wherein dividing the input clock signal to generate the first and second divided clock signals comprises dividing a frequency of the input clock signal to generate the first and second divided clock signals.

[0141]

[0214] 31. The method of clause 30, wherein dividing the frequency of the input clock signal includes dividing the frequency of the input clock signal by two.

[0142]

[0215] 32. The method of any one of clauses 26-31, further comprising combining an output of the first sub-DAC and an output of the second sub-DAC.

[0143]

[0216] 33. A method for providing a first driving clock signal and a second driving clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC, comprising:

[0217] Receiving an input clock signal;

[0218] dividing an input clock signal to generate a first divided clock signal and a second divided clock signal;

[0219] gating an input clock signal with a first divided clock signal to generate a first driving clock signal;

[0220] inputting a first driving clock signal to a clock input of a first sub-DAC;

[0221] in a first mode, gating the input clock signal using the second divided clock signal to generate a second driving clock signal;

[0222] in a second mode, gating the input clock signal using the first divided clock signal to generate a second driving clock signal;

[0223] inputting a second driving clock signal to a clock input of a second sub-DAC; A method comprising:

[0144]

[0224] 34. The method of claim 33, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

[0145]

[0225] 35.

[0226] gating the input clock signal with the first divided clock signal includes gating even pulses of the input clock signal with the first divided clock signal;

[0227] gating the input clock signal with the second divided clock signal includes gating odd pulses of the input clock signal with the second divided clock signal. 35. The method according to clause 33 or 34.

[0146]

[0228] 36.

[0229] gating the input clock signal with the first divided clock signal includes gating odd pulses of the input clock signal with the first divided clock signal;

[0230] gating the input clock signal with the second divided clock signal includes gating even pulses of the input clock signal with the second divided clock signal. 35. The method according to clause 33 or 34.

[0147]

[0231] 37. The method of any one of clauses 33-36, wherein dividing the input clock signal to generate the first and second divided clock signals comprises dividing a frequency of the input clock signal to generate the first and second divided clock signals.

[0148]

[0232] 38. The method of clause 37, wherein dividing the frequency of the input clock signal includes dividing the frequency of the input clock signal by two.

[0149]

[0233] 39. The method of any one of clauses 33-38, further comprising, in the first mode, combining an output of the first sub-DAC and an output of the second sub-DAC.

[0150]

[0234] 40. The method of clause 39, further comprising, in the second mode, shorting a clock input of the first sub-DAC to a clock input of the second sub-DAC.

[0151]

[0235] 41. The method of any one of clauses 39 and 40, further comprising, in the first mode, coupling an output of the first sub-DAC and an output of the second sub-DAC to a first transmitter.

[0152]

[0236] 42. In the second mode,

[0237] coupling an output of the first sub-DAC to a second transmitter;

[0238] coupling an output of the second sub-DAC to a third transmitter; 42. The method of claim 41, further comprising:

[0153]

[0239] Within the scope of the present disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration". None of the implementations or aspects described herein as "exemplary" should necessarily be construed as being more preferred or advantageous than other aspects of the present disclosure. Similarly, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages, or modes of operation being described. The term "about" as used herein with respect to a stated value or property is intended to indicate within 10% of the stated value or property.

[0154]

[0240] The foregoing description of the present disclosure has been provided so that any person skilled in the art can make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein. The invention as described in the claims of the original application is set forth below. [C1] A system comprising: a clock divider circuit having an input, a first output, and a second output, the input of the clock divider circuit configured to receive an input clock signal; a first clock gating circuit having a first input, a second input, and an output, the first input of the first clock gating circuit configured to receive the input clock signal and the second input of the first clock gating circuit coupled to the first output of the clock divider circuit; a second clock gating circuit having a first input, a second input, and an output, the first input of the second clock gating circuit configured to receive the input clock signal and the second input of the second clock gating circuit coupled to the second output of the clock divider circuit; a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit; a second sub-DAC having a clock input coupled to the output of the second clock gating circuit; Including, the system. [C2] The clock divider circuit, dividing the input clock signal to generate a first divided clock signal and a second divided clock signal; outputting the first divided clock signal at the first output of the clock divider circuit; outputting the second divided clock signal at the second output of the clock divider circuit; The system according to claim 1, configured as follows: [C3] The system of C2, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal. [C4] The system of C3, wherein the clock divider circuit is configured to invert the first divided clock signal to generate the second divided clock signal. [C5] The system of C2, wherein the clock divider circuit is configured to divide a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal. [C6] The system of C5, wherein the frequency of the input clock signal is divided by two. [C7] The first clock gating circuit, gating the input clock signal using the first divided clock signal to generate a first driving clock signal; outputting the first driving clock signal at the output of the first clock gating circuit; The system of claim 2, configured as follows: [C8] The system of C7, wherein the first clock gating circuit includes a delay circuit having a time delay, and the first clock gating circuit is configured to control a pulse width of the first driving clock signal based on the time delay. [C9] The second clock gating circuit, gating the input clock signal using the second divided clock signal to generate a second driving clock signal; outputting the second driving clock signal at the output of the second clock gating circuit; The system according to C7, configured as follows: [C10] The system of C9, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal. [C11] the first clock gating circuit is configured to gate even pulses of the input clock signal using the first divided clock signal to generate the first driving clock signal; the second clock gating circuit gates odd pulses of the input clock signal using the second divided clock signal to generate the second driving clock signal. The system according to C9, configured as follows: [C12] the first clock gating circuit is configured to gate odd pulses of the input clock signal using the first divided clock signal to generate the first driving clock signal; the second clock gating circuit is configured to gate even pulses of the input clock signal using the second divided clock signal to generate the second driving clock signal. The system described in C9. [C13] The system of C1, further comprising a combiner coupled to an output of the first sub-DAC and an output of the second sub-DAC. [C14] The system of C13, wherein the combiner is coupled to a transmitter. [C15] A system comprising: a clock divider circuit having an input, a first output, and a second output, the input of the clock divider circuit configured to receive an input clock signal; a first clock gating circuit having a first input, a second input, and an output, the first input of the first clock gating circuit configured to receive the input clock signal and the second input of the first clock gating circuit coupled to the first output of the clock divider circuit; a multiplexer having a first input, a second input, and an output, the first input of the multiplexer coupled to the first output of the clock divider circuit and the second input of the multiplexer coupled to the second output of the clock divider circuit; a second clock gating circuit having a first input, a second input, and an output, the first input of the second clock gating circuit configured to receive the input clock signal, and the second input of the second clock gating circuit coupled to the output of the multiplexer; a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit; a second sub-DAC having a clock input coupled to the output of the second clock gating circuit; Including, the system. [C16] The clock divider circuit, dividing the input clock signal to generate a first divided clock signal and a second divided clock signal; outputting the first divided clock signal at the first output of the clock divider circuit; outputting the second divided clock signal at the second output of the clock divider circuit; The system according to C15, configured as follows: [C17] The system of C16, wherein the clock divider circuit is configured to divide a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal. [C18] The system of C17, wherein the frequency of the input clock signal is divided by two. [C19] The system of C16, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal. [C20] The system of C19, wherein the clock divider circuit is configured to invert the first divided clock signal to generate the second divided clock signal. [C21] causing the multiplexer to select the second input of the multiplexer in a first mode; causing the multiplexer to select the first input of the multiplexer in a second mode; The system of claim 16, further comprising a controller configured to: [C22] A first output switch coupled between the output of the first sub-DAC and a combiner; a second output switch coupled between the output of the second sub-DAC and the combiner; The controller: 23. The system of claim 21, configured to: in the first mode, close the first output switch and the second output switch; and in the second mode, open the first output switch and the second output switch. [C23] The system of C22, further comprising a shorting switch coupled between the output of the first clock gating circuit and the output of the second clock gating circuit, the controller configured to open the shorting switch in the first mode and close the shorting switch in the second mode. [C24] The output of the synthesizer is coupled to a first DAC output, and the system comprises: a third output switch coupled between the output of the first sub-DAC and a second DAC output; a fourth output switch coupled between the output of the second sub-DAC and a third DAC output; The controller: In the first mode, the third output switch and the fourth output switch are opened; and in the second mode, the third output switch and the fourth output switch are closed. The system according to C22, configured as follows: [C25] a first bypass switch coupled between the first input of the first clock gating circuit and the output of the first clock gating circuit; a second bypass switch coupled between the first input of the second clock gating circuit and the output of the second clock gating circuit; The controller: In the first mode and the second mode, the first bypass switch and the second bypass switch are opened; in a third mode, closing the first bypass switch and the second bypass switch; The system according to C21, configured as follows: [C26] A method for providing a first driving clock signal and a second driving clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC, comprising: Receiving an input clock signal; dividing the input clock signal to generate a first divided clock signal and a second divided clock signal; gating the input clock signal using the first divided clock signal to generate the first driving clock signal; inputting the first driving clock signal to a clock input of the first sub-DAC; gating the input clock signal with the second divided clock signal to generate the second driving clock signal; inputting the second driving clock signal to a clock input of the second sub-DAC; A method comprising: [C27] The method of C26, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal. [C28] Gating the input clock signal with the first divided clock signal includes gating even pulses of the input clock signal with the first divided clock signal; gating the input clock signal with the second divided clock signal includes gating odd pulses of the input clock signal with the second divided clock signal. The method described in C26. [C29] Gating the input clock signal with the first divided clock signal includes gating odd pulses of the input clock signal with the first divided clock signal; gating the input clock signal with the second divided clock signal includes gating even pulses of the input clock signal with the second divided clock signal. The method described in C26. [C30] The method of C26, wherein dividing the input clock signal to generate the first divided clock signal and the second divided clock signal includes dividing a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal. [C31] The method of C30, wherein dividing the frequency of the input clock signal includes dividing the frequency of the input clock signal by two. [C32] The method of C26, further comprising combining an output of the first sub-DAC and an output of the second sub-DAC.

Claims

1. 1. A system comprising: a clock divider circuit having an input, a first output, and a second output, the input of the clock divider circuit configured to receive an input clock signal; a first clock gating circuit having a first input, a second input, and an output, the first input of the first clock gating circuit configured to receive the input clock signal, and the second input of the first clock gating circuit coupled to the first output of the clock divider circuit; a second clock gating circuit having a first input, a second input, and an output, the first input of the second clock gating circuit configured to receive the input clock signal, and the second input of the second clock gating circuit coupled to the second output of the clock divider circuit; a first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit; a second sub-DAC having a clock input coupled to the output of the second clock gating circuit; Including, The clock divider circuit comprises: dividing the input clock signal to generate a first divided clock signal and a second divided clock signal; outputting the first divided clock signal at the first output of the clock divider circuit; outputting the second divided clock signal at the second output of the clock divider circuit; It is configured as follows: The first clock gating circuit comprises: gating the input clock signal using the first divided clock signal to generate a first driving clock signal; outputting the first driving clock signal at the output of the first clock gating circuit; It is configured as follows: the first clock gating circuit includes a delay circuit having a time delay, the first clock gating circuit being configured to control a pulse width of the first driving clock signal based on the time delay. system.

2. 2. The system of claim 1, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

3. 3. The system of claim 2, wherein the clock divider circuit is configured to invert the first divided clock signal to generate the second divided clock signal.

4. 2. The system of claim 1, wherein the clock divider circuit is configured to divide a frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal.

5. 5. The system of claim 4, wherein the frequency of the input clock signal is divided by two.

6. The second clock gating circuit comprises: gating the input clock signal using the second divided clock signal to generate a second driving clock signal; outputting the second driving clock signal at the output of the second clock gating circuit; The system of claim 1 configured to:

7. 7. The system of claim 6, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

8. the first clock gating circuit is configured to gate even pulses of the input clock signal using the first divided clock signal to generate the first driving clock signal; the second clock gating circuit gates odd pulses of the input clock signal using the second divided clock signal to generate the second driving clock signal; The system of claim 6 , configured to:

9. the first clock gating circuit is configured to gate odd pulses of the input clock signal using the first divided clock signal to generate the first driving clock signal; the second clock gating circuit is configured to gate even pulses of the input clock signal using the second divided clock signal to generate the second driving clock signal. The system of claim 6.

10. The system of claim 1 , further comprising a combiner coupled to an output of the first sub-DAC and an output of the second sub-DAC.

11. The system of claim 10 , wherein the combiner is coupled to a transmitter.

12. 1. A system comprising: A clock divider circuit having an input, a first output, and a second output, wherein the input of the clock divider circuit is configured to receive an input clock signal. A first clock gating circuit having a first input, a second input, and an output, wherein the first input of the first clock gating circuit is configured to receive the input clock signal, and the second input of the first clock gating circuit is coupled to the first output of the clock divider circuit. A multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the first output of the clock divider circuit, and the second input of the multiplexer is coupled to the second output of the clock divider circuit. A second clock gating circuit having a first input, a second input, and an output, wherein the first input of the second clock gating circuit is configured to receive the input clock signal, and the second input of the second clock gating circuit is coupled to the output of the multiplexer. A first sub-digital-to-analog converter (sub-DAC) having a clock input coupled to the output of the first clock gating circuit. A second sub-DAC having a clock input coupled to the output of the second clock gating circuit. A system comprising the above.

13. The clock divider circuit is configured to divide the input clock signal to generate a first divided clock signal and a second divided clock signal, output the first divided clock signal at the first output of the clock divider circuit, output the second divided clock signal at the second output of the clock divider circuit. The system according to claim 12, wherein the system is configured as described above.

14. The system according to claim 13, wherein the clock divider circuit is configured to divide the frequency of the input clock signal to generate the first divided clock signal and the second divided clock signal.

15. The system according to claim 14, wherein the frequency of the input clock signal is divided by 2.

16. 14. The system of claim 13, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

17. 17. The system of claim 16, wherein the clock divider circuit is configured to invert the first divided clock signal to generate the second divided clock signal.

18. causing the multiplexer to select the second input of the multiplexer in a first mode; causing the multiplexer to select the first input of the multiplexer in a second mode; The system of claim 13 , further comprising a controller configured to:

19. a first output switch coupled between an output of the first sub-DAC and a combiner; a second output switch coupled between the output of the second sub-DAC and the combiner; The controller: in the first mode, closing the first output switch and the second output switch; in the second mode, the first output switch and the second output switch are opened; The system of claim 18 configured to:

20. 20. The system of claim 19, further comprising a shorting switch coupled between the output of the first clock gating circuit and the output of the second clock gating circuit, the controller configured to open the shorting switch in the first mode and close the shorting switch in the second mode.

21. an output of the synthesizer coupled to a first DAC output, the system comprising: a third output switch coupled between the output of the first sub-DAC and a second DAC output; a fourth output switch coupled between the output of the second sub-DAC and a third DAC output; The controller: in the first mode, the third output switch and the fourth output switch are open; in the second mode, closing the third output switch and the fourth output switch; The system of claim 19 configured to:

22. a first bypass switch coupled between the first input of the first clock gating circuit and the output of the first clock gating circuit; a second bypass switch coupled between the first input of the second clock gating circuit and the output of the second clock gating circuit; The controller: in the first mode and in the second mode, the first bypass switch and the second bypass switch are opened; in a third mode, closing the first bypass switch and the second bypass switch; The system of claim 18 configured to:

23. 1. A method for providing a first driving clock signal and a second driving clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC, comprising: Receiving an input clock signal; dividing the input clock signal to generate a first divided clock signal and a second divided clock signal; gating the input clock signal using the first divided clock signal to generate the first driving clock signal; and gating the input clock signal using the first divided clock signal to generate the first driving clock signal includes controlling a pulse width of the first driving clock signal based on time-delaying the first divided clock signal or the input clock signal. inputting the first driving clock signal to a clock input of the first sub-DAC; gating the input clock signal with the second divided clock signal to generate the second driving clock signal; inputting the second driving clock signal to a clock input of the second sub-DAC; Including, method.

24. 24. The method of claim 23, wherein the second divided clock signal is phase shifted by approximately 180 degrees relative to the first divided clock signal.

25. gating the input clock signal with the first divided clock signal includes gating even pulses of the input clock signal with the first divided clock signal; gating the input clock signal with the second divided clock signal includes gating odd pulses of the input clock signal with the second divided clock signal.

24. The method of claim 23.

26. gating the input clock signal with the first divided clock signal includes gating odd pulses of the input clock signal with the first divided clock signal; gating the input clock signal with the second divided clock signal includes gating even pulses of the input clock signal with the second divided clock signal.

24. The method of claim 23.

27. 24. The method of claim 23, wherein dividing the input clock signal to generate the first and second divided clock signals comprises dividing a frequency of the input clock signal to generate the first and second divided clock signals.

28. 28. The method of claim 27, wherein dividing the frequency of the input clock signal comprises dividing the frequency of the input clock signal by two.

29. 24. The method of claim 23, further comprising combining an output of the first sub-DAC and an output of the second sub-DAC.

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