Surface-emitting laser array, light source module, and distance measuring device

The surface-emitting laser array is miniaturized by connecting VCSEL elements in parallel within sub-arrays and series connecting these sub-arrays, addressing the challenge of miniaturization in conventional VCSEL arrays and enhancing performance for LiDAR applications.

JP7683252B2Active Publication Date: 2025-05-27RICOH CO LTD
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Patent Information

Application Number
JP2021040536
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2021-03-12
Publication Date
2025-05-27
Estimated Expiration
2041-03-12

AI Technical Summary

Technical Problem

Conventional VCSEL arrays face challenges in miniaturization, which is essential for advanced applications such as LiDAR systems.

Method used

The proposed surface-emitting laser array consists of multiple sub-arrays with VCSEL elements connected in parallel within each sub-array, and these sub-arrays are connected in series. This configuration allows for reduced drive current and enables miniaturization by optimizing the layout and electrical connections.

Benefits of technology

The solution achieves miniaturization of the VCSEL array, reduces drive current, and minimizes light emission unevenness, making it suitable for compact distance measuring devices like LiDAR systems.

✦ Generated by Eureka AI based on patent content.

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Patent Text Reader

Abstract

To provide a surface light emitting laser array, a light source module, and a distance measuring device that can be reduced in size.SOLUTION: A surface light emitting laser array has a substrate, and a plurality of sub-arrays including a plurality of surface light emitting laser elements that are provided on the substrate, emit light through the substrate, and are electrically connected in parallel to each other. The surface light emitting laser elements each have a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a resonator provided between the first semiconductor layer and the second semiconductor layer. The adjacent sub-arrays have electrodes for commonly connecting the first semiconductor layers in the plurality of surface light emitting laser elements included in one of the sub-arrays and the second semiconductor layers in the plurality of surface light emitting laser elements included in the other of the sub-arrays with each other. The plurality of sub-arrays are electrically connected in series to each other.SELECTED DRAWING: Figure 1
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Description

Technical Field

[0001] The present invention relates to a surface-emitting laser array, a light source module, and a distance measuring device.

Background Art

[0002] In recent years, the spread of distance measuring sensors utilizing TOF (Time Of Flight) technology such as LiDAR has been rapidly progressing. As a key device for such distance measuring sensors, a vertical cavity surface emitting laser (VCSEL) array that enables two-dimensional arraying, has an easy light source layout design, and has small temperature fluctuations in wavelength is expected.

[0003] Conventionally, a configuration in which surface-emitting laser elements are connected in series has been proposed for the purpose of reducing the drive current of a VCSEL array.

Summary of the Invention

Problems to be Solved by the Invention

[0004] There is room for improvement in miniaturization in conventional VCSEL arrays.

[0005] An object of the present invention is to provide a surface-emitting laser array, a light source module, and a distance measuring device that can be miniaturized.

Means for Solving the Problems

[0006] According to one aspect of the disclosed technology, a surface-emitting laser array includes a semiconductor substrate, a plurality of sub-arrays provided on the semiconductor substrate, emitting light through the semiconductor substrate, and including a plurality of surface-emitting laser elements electrically connected in parallel to each other, and the surface-emitting laser elements each have, in order from the semiconductor substrate side, a first semiconductor layer of a first conductivity type, a resonator, and a second semiconductor layer of a second conductivity type. Adjacent sub-arrays have an electrode that commonly connects the first semiconductor layer in the plurality of surface-emitting laser elements included in one sub-array and the second semiconductor layer in the plurality of surface-emitting laser elements included in the other sub-array. The plurality of sub-arrays are electrically connected in series, and in the arrangement direction in which the plurality of sub-arrays are arranged, two or more of the surface-emitting laser elements are arranged in the arrangement direction within one of the plurality of sub-arrays, and a region electrically connected to the second semiconductor layer of each of the two or more surface-emitting laser elements is disposed on the one sub-array and the electrode is electrically connected to the second semiconductor layer of each of the two or more surface-emitting laser elements, and includes a dielectric layer that covers the electrode and is provided with an opening that exposes a part of the electrode on the subarray and.

Advantages of the Invention

[0007] According to the disclosed technology, miniaturization can be achieved.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and duplicate explanations may be omitted.

[0010] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a vertical cavity surface emitting laser (VCSEL) array. FIG. 1 is a cross-sectional view showing a surface-emitting laser array according to the first embodiment. FIG. 2 is an equivalent circuit diagram showing the surface-emitting laser array according to the first embodiment. FIG. 3 is a plan view showing the surface-emitting laser array according to the first embodiment.

[0011] As shown in FIG. 1, the VCSEL array 100 according to the first embodiment includes a substrate 101, a first sub-array 121 and a second sub-array 122 on the substrate 101, and a cathode pad portion 129. As shown in FIG. 2, the first sub-array 121 and the second sub-array 122 are connected in series with each other. The first sub-array 121 and the second sub-array 122 each include two VCSEL elements 124 that emit light L through the substrate 101. In the first sub-array 121, the two VCSEL elements 124 are electrically connected in parallel with each other, and in the second sub-array 122, the two VCSEL elements 124 are electrically connected in parallel with each other. The cathode pad portion 129 includes a pseudo-VCSEL element 125. As shown in FIGS. 1 and 3, the second sub-array 122 is between the first sub-array 121 and the cathode pad portion 129. The substrate 101 is, for example, a non-doped semi-insulating GaAs substrate.

[0012] The VCSEL element 124 includes a first contact layer 102 having a first conductivity type, a first multilayer mirror 103 having a first conductivity type, a resonator 104, a second multilayer mirror 106 having a second conductivity type, and a second contact layer 107 having a second conductivity type.

[0013] The first contact layer 102 is on the substrate 101. The first contact layer 102 is, for example, a highly doped GaAs layer. The two VCSEL elements 124 included in the first subarray 121 share one first contact layer 102, and the two VCSEL elements 124 included in the second subarray 122 share one first contact layer. The first contact layer 102 is an example of a first semiconductor layer.

[0014] The first multilayer mirror 103 is on the first contact layer 102. The first multilayer mirror 103 alternately includes two types of layers with different refractive indices. For example, one layer (high refractive index layer) is an Al 0.2 Ga 0.8 As layer, and the other layer (low refractive index layer) is an Al 0.9 Ga 0.1 As layer. Although not shown, the first multilayer mirror 103 includes a composition gradient layer with a continuously changing composition between the high refractive index layer and the low refractive index layer, and the optical thickness of each layer including up to the center of the composition gradient layer is λ / 4 with the oscillation wavelength of the laser being λ.

[0015] The resonator 104 is on the first multilayer mirror 103. The resonator 104 includes a lower spacer layer, an active layer on the lower spacer layer, and an upper spacer layer on the active layer. The optical length of the resonator 104 is λ. For example, the oscillation wavelength λ is 940 nm.

[0016] The second multilayer mirror 106 is on the resonator 104. The second multilayer mirror 106 alternately includes two types of layers with different refractive indices. For example, one layer (high refractive index layer) is an Al 0.2 Ga 0.8 As layer, and the other layer (low refractive index layer) is an Al 0.9 Ga 0.1It is the As layer. Although not shown, the second multilayer mirror 106 includes a composition gradient layer with a continuously changing composition between the high refractive index layer and the low refractive index layer. The optical thickness of each layer including up to the center of the composition gradient layer is λ / 4, where λ is the oscillation wavelength of the laser. The number of pairs of the high refractive index layer and the low refractive index layer in the second multilayer mirror 106 is larger than the number of pairs of the high refractive index layer and the low refractive index layer in the first multilayer mirror 103. Thereby, the VCSEL element 124 can emit the light L through the substrate 101.

[0017] The second multilayer mirror 106 includes a selective oxidation layer 105. The selective oxidation layer 105 includes an oxidized region 105a and a non-oxidized region 105b. The Al composition of the selective oxidation layer 105 is higher than that of the surrounding layers. For example, the selective oxidation layer 105 is an AlAs layer.

[0018] The second contact layer 107 is on the second multilayer mirror 106. The second contact layer 107 is, for example, a highly doped GaAs layer. The second contact layer 107 is an example of a second semiconductor layer.

[0019] The pseudo-VCSEL element 125 has a laminated structure similar to that of the VCSEL element 124.

[0020] The VCSEL array 100 has an insulating layer 108 covering the VCSEL element 124 and the pseudo-VCSEL element 125. The insulating layer 108 is, for example, a SiN layer or a SiO 2 layer or the like. The insulating layer 108 has an opening 108a that exposes the second contact layer 107 of the two VCSEL elements 124 included in the first subarray 121, and an opening 108b that exposes the second contact layer 107 of the two VCSEL elements 124 included in the second subarray 122. The insulating layer 108 does not have an opening that exposes the second contact layer 107 of the pseudo-VCSEL element 125. The insulating layer 108 has an opening 108s that exposes the first contact layer 102 included in the first subarray 121, and an opening 108t that exposes the first contact layer 102 included in the second subarray 122.

[0021] The VCSEL array 100 has an electrode 109a, an electrode 109b, and an electrode 109x on an insulating layer 108. The electrode 109a contacts the second contact layer 107 of two VCSEL elements 124 included in the first sub-array 121 through an opening 108a. The electrode 109b contacts the second contact layer 107 of two VCSEL elements 124 included in the second sub-array 122 through an opening 108b. The electrode 109b also contacts the first contact layer 102 included in the first sub-array 121 in a contact region 126 (see FIG. 3). The electrode 109x is on the insulating layer 108 at a cathode pad portion 129 but does not contact the second contact layer 107 of the pseudo-VCSEL element 125. The electrode 109x contacts the first contact layer 102 included in the second sub-array 122 in a contact region 127 (see FIG. 3). The contact region 126 corresponds to an opening 108s, and the contact region 127 corresponds to an opening 108t. The electrodes 109a, 109b, and 109x are, for example, a laminate including a Ti film, a Pt film on the Ti film, and an Au film on the Pt film. Note that the underlayer for ohmic connection with the first contact layer 102 and the underlayer for ohmic connection with the second contact layer 107 may be different.

[0022] The VCSEL array 100 has an antireflection film 110 on the emitting side surface (back surface) of the substrate 101. The optical thickness of the antireflection film 110 is λ / 4.

[0023] In the VCSEL array 100 according to the first embodiment, the first contact layer 102 in the first sub-array 121 and the second contact layer 107 in the second sub-array 122 are not electrically connected through the substrate 101. The electrode 109b connects the first contact layer 102 in the first sub-array 121 and the second contact layer 107 in the second sub-array 122. Therefore, the first sub-array 121 and the second sub-array 122 are connected in series. For this reason, according to the first embodiment, the drive current can be reduced to approximately half compared with the case where all the VCSEL elements 124 are connected in parallel.

[0024] In addition, if a potential difference is applied between the electrode 109a and the electrode 109x, the VCSEL array 100 can be driven. Therefore, it is not necessary to provide anode pads and cathode pads for mounting on each of the first sub-array 121 and the second sub-array 122. For this reason, it is suitable for miniaturization. Also, the interval between the light-emitting portions between the VCSEL elements 124 can be reduced, and light emission unevenness can be suppressed.

[0025] Next, a light source module including the VCSEL array 100 will be described. FIG. 4 is a cross-sectional view showing a first example of a light source module including the VCSEL array 100. FIG. 5 is a cross-sectional view showing a second example of a light source module including the VCSEL array 100.

[0026] As shown in FIG. 4, the first example of the light source module has a submount 150 on which the VCSEL array 100 is mounted. The submount 150 has an insulating substrate 151 made of AlN, and electrodes 152 and 153 on the insulating substrate 151. The electrode 152 faces the electrode 109a, and the electrode 153 faces the electrode 109x. The light source module has bonding materials 154 between the electrode 152 and the electrode 109a, and between the electrode 153 and the electrode 109x. The submount 150 is an example of a mounting substrate.

[0027] When manufacturing the light source module, the VCSEL array 100 is junctioned and bonded in an aligned state. The bonding material 154 is formed using, for example, a conductive paste, a solder material, or the like. A bonding surface may be formed without using a bonding material by metal bonding using heat or ultrasonic waves.

[0028] In such a first example, a potential difference is applied from the electrodes 152 and 153 between the electrode 109a and the electrode 109x of the VCSEL array 100.

[0029] In the second example of the light source module, as shown in FIG. 5, in addition to the configuration of the first example, the submount 150 has an electrode 155. The electrode 155 faces the electrode 109b. The light source module also has a bonding material 154 between the electrode 155 and the electrode 109b. Other configurations are the same as those of the first example.

[0030] Even in such a second example, a potential difference is applied between the electrodes 152 and 153 between the electrodes 109a and 109x of the VCSEL array 100. Although the electrode 155 is not included in the current path, the heat generated in the VCSEL element 124 included in the second subarray 122 is efficiently released to the submount 150 through the electrode 155 and the bonding material 154 thereon.

[0031] In both the first example and the second example, it is important to prevent a short circuit between the bonding materials 154 during the manufacture of the light source module. In the present embodiment, since one electrode 109a or 109b corresponds to two VCSEL elements 124, the interval between the bonding materials 154 can be made relatively large, and it is easy to prevent a short circuit.

[0032] (Modification of the First Embodiment) Here, a modification of the first embodiment will be described. FIG. 6 is a plan view showing a modification of the surface-emitting laser array according to the first embodiment.

[0033] In this modification, the contact region 126 is not between the first subarray 121 and the second subarray 122, but is on the side of the first subarray 121 in a direction perpendicular to the direction in which the first subarray 121 and the second subarray 122 are arranged. Therefore, compared with the first embodiment, the distance between the VCSEL elements 124 in the first subarray 121 and the VCSEL elements 124 in the second subarray 122 is small. For this reason, the variation in the interval between the VCSEL elements 124 in the VCSEL array 100 is reduced, and the light emission unevenness can be further suppressed. Also, further miniaturization is possible.

[0034] (Second Embodiment) Next, the second embodiment will be described. The second embodiment relates to a VCSEL array. FIG. 7 is a cross-sectional view showing a surface-emitting laser array according to the second embodiment. FIG. 8 is an equivalent circuit diagram showing the surface-emitting laser array according to the second embodiment.

[0035] In the VCSEL array 200 according to the second embodiment, as shown in FIG. 7, the first sub-array 121 and the second sub-array 122 each include three VCSEL elements 124 that emit light L through the substrate 101. As shown in FIG. 8, the three VCSEL elements 124 within the first sub-array 121 are electrically connected in parallel to each other, and the three VCSEL elements 124 within the second sub-array 122 are electrically connected in parallel to each other.

[0036] The VCSEL array 200 has a dielectric layer 111 that covers the electrodes 109a, 109b, and 109x. The dielectric layer 111 has an opening 111a that exposes the electrode 109a within the first sub-array 121, an opening 111b that exposes the electrode 109b within the second sub-array 122, and an opening 111x that exposes the electrode 109x within the cathode pad portion 129. The opening 111a is approximately above the one located in the center among the three VCSEL elements 124 within the first sub-array 121. The opening 111b is approximately above the one located in the center among the three VCSEL elements 124 within the second sub-array 122. The opening 111x is above the pseudo-VCSEL element 125. The portions of the electrode 109a exposed from the opening 111a, the portions of the electrode 109b exposed from the opening 111b, and the portions of the electrode 109x exposed from the opening 111x function as mounting pads. The dielectric layer 111 is, for example, a SiN layer or a SiO 2 layer or the like.

[0037] Other configurations are the same as those in the first embodiment.

[0038] In the second embodiment, the designer can design the position of the mounting pads independently from the light-emitting points of the VCSEL elements 124. For example, the distance between the light-emitting points of the VCSEL elements 124 between the adjacent first sub-array 121 and the second sub-array 122 is smaller than the distance between the adjacent mounting pads. Therefore, the light emission unevenness is further suppressed.

[0039] Next, a light source module including the VCSEL array 200 will be described. FIG. 9 is a cross-sectional view showing the light source module including the VCSEL array 200.

[0040] As shown in FIG. 9, the light source module has a submount 150 on which the VCSEL array 200 is mounted. The submount 150 has an insulating substrate 151, electrodes 152, 153, and 155 on the insulating substrate 151, and a dielectric layer 156. The portions of the electrodes 152, 153, and 155 exposed from the dielectric layer 156 function as second mounting pads. For example, the mounting pad of the first sub-array 121 and the second mounting pad of the electrode 152 have the same planar shape. For example, the mounting pad of the second sub-array 122 and the second mounting pad of the electrode 155 have the same planar shape. For example, the mounting pad of the cathode pad portion 129 and the second mounting pad of the electrode 153 have the same planar shape. The bonding material 154 is solder such as Sn-Ag-Cu, for example.

[0041] In such a light source module, the bonding region where the VCSEL array 200 and the submount 150 are bonded depends on the dielectric layers 111 and 156, and the light-emitting portion of the VCSEL element 124 is not affected by the bonding region. As described above, for example, the distance between the light-emitting points of the VCSEL elements 124 between the adjacent first sub-array 121 and the second sub-array 122 is smaller than the distance between the adjacent mounting pads. In this case, a short circuit between the bonding materials 154 can be prevented, and the distance between the light-emitting points can be narrowed. Therefore, the light emission unevenness is further suppressed. Also, similar to the second example described above, good heat dissipation characteristics can be obtained.

[0042] Generally, the VCSEL element 124 is formed by lithography technology and semiconductor processes, and the interval of the bonding material 154 is likely to be larger than that of the VCSEL element 124. According to this embodiment, the light-emitting part of the VCSEL element 124 can be arranged without being restricted by the interval of the mounting pads.

[0043] (Third Embodiment) Next, the third embodiment will be described. The third embodiment relates to a VCSEL array. FIG. 10 is a cross-sectional view showing a surface-emitting laser array according to the third embodiment.

[0044] As shown in FIG. 10, the VCSEL array 300 according to the third embodiment has solder films 112 in the opening 111a, the opening 111b, and the opening 111x. The solder film 112 is formed by, for example, vapor deposition or sputtering. In the third embodiment, the solder film 112 functions as a mounting pad.

[0045] Other configurations are the same as those in the second embodiment.

[0046] The third embodiment can also obtain the same effects as those in the second embodiment. In addition, the mounting to the submount 150 is simplified.

[0047] Next, a manufacturing method of the VCSEL array 300 according to the third embodiment will be described. FIGS. 11 to 18 are cross-sectional views showing a manufacturing method of a surface-emitting laser array according to the third embodiment. FIGS. 19 to 20 are plan views showing a manufacturing method of a surface-emitting laser array according to the third embodiment. FIG. 12 corresponds to a cross-sectional view taken along the line XII-XII in FIG. 19, and FIG. 14 corresponds to a cross-sectional view taken along the line XIV-XIV in FIG. 20.

[0048] First, as shown in FIG. 11, a first contact layer 102, a first multilayer mirror 103, a resonator 104, a second multilayer mirror 106, and a second contact layer 107 are sequentially grown on a substrate 101. The semiconductor stacked structure of the first contact layer 102, the first multilayer mirror 103, the resonator 104, the second multilayer mirror 106, and the second contact layer 107 is fabricated, for example, by crystal growth using a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. Here, an example using the MOCVD method is shown. As an example, trimethylaluminum (TMA), trimethylgallium (TMG), trimethylindium (TMI), etc. are used as group III raw materials, and arsine (AsH 3 ), phosphine (PH 3 ) are used as group V raw materials. As an example, carbon tetrabromide (CBr 4 ) is used as a raw material for a p-type dopant, and monosilane (SiH 4 ) is used as a raw material for an n-type dopant.

[0049] As the substrate 101, for example, a semi-insulating GaAs substrate is used.

[0050] The first contact layer 102 is, for example, an n-type GaAs layer with a thickness of 3 μm. In order to prevent overetching of the first contact layer 102, an etch stop layer such as an AlGaInP layer or a GaInP layer may be formed between the first contact layer 102 and the first multilayer mirror 103.

[0051] The first multilayer mirror 103 includes 24.5 pairs of high refractive index layers and low refractive index layers. For example, the high refractive index layer is an n-type Al 0.2 Ga 0.8 As layer, and the low refractive index layer is an n-type Al 0.9 Ga 0.1It is an As layer. A composition gradient layer with a thickness of 20 nm is formed between the high refractive index layer and the low refractive index layer to reduce the electrical resistance. When the oscillation wavelength is λ, the optical thickness of the high refractive index layer and the low refractive index layer is λ / 4 including half of the adjacent composition gradient layer. When the optical thickness is λ / 4, the actual thickness D of the layer is D = λ / 4n (where n is the refractive index of the medium of the layer).

[0052] The resonator 104 includes a lower spacer layer, an active layer above the lower spacer layer, and an upper spacer layer above the active layer. The optical length of the resonator 104 is λ. For example, the oscillation wavelength λ is 940 nm. The lower spacer layer and the upper spacer layer are, for example, Al 0.4 Ga 0.6 As layers. The active layer has a three quantum well structure. Each quantum well layer is an InGaAs layer, and each barrier layer is an Al 0.1 GaAs layer. The active layer is formed at the center of the resonator 104. For example, the oscillation wavelength λ is 940 nm.

[0053] The second multilayer mirror 106 includes 38 pairs of high refractive index layers and low refractive index layers. For example, the high refractive index layer is a p-type Al 0.2 Ga 0.8 As layer, and the low refractive index layer is a p-type Al 0.9 Ga 0.1 As layer. A composition gradient layer with a thickness of 20 nm is formed between the high refractive index layer and the low refractive index layer to reduce the electrical resistance. When the oscillation wavelength is λ, the optical thickness of the high refractive index layer and the low refractive index layer is λ / 4 including half of the adjacent composition gradient layer.

[0054] The second multilayer mirror 106 includes, for example, a selective oxidation layer 105 (not shown) made of p-AlAs. The position of the selective oxidation layer 105 is at an optical distance of λ / 4 from the interface between the second multilayer mirror 106 and the resonator 104. The selective oxidation layer 105 may include composition gradient layers, intermediate layers, etc. up and down.

[0055] The second contact layer 107 is, for example, a p-type GaAs layer.

[0056] After the formation of the semiconductor stack structure, using photolithography technology, for example, a square resist pattern with a side length of 30 μm and a rectangular resist pattern of 80 μm × 200 μm are formed on the second contact layer 107. The square resist pattern is formed in the planned formation area of the VCSEL element 124, and the rectangular resist pattern is formed in the planned formation area of the pseudo-VCSEL element 125. Next, using these resist patterns as masks, Cl 2 Using the electron cyclotron resonance (ECR) etching method with Cl gas, as shown in FIGS. 12 and 19, the semiconductor stack structure is etched so that the first contact layer 102 is exposed as the bottom surface. As a result, a mesa structure is formed. The mesa structure is formed such that at least the selective oxidation layer 105 (not shown) is exposed. After etching, the resist pattern is removed.

[0057] Next, using the semiconductor stack structure with the mesa structure formed as the object to be oxidized, heat treatment (oxidation treatment) is performed in water vapor. As a result, Al in the selective oxidation layer 105 is selectively oxidized from the outer peripheral portion of the mesa structure. Then, as shown in FIG. 13, in the central portion of the mesa structure, an unoxidized non-oxidation region 105b surrounded by the Al oxidation region 101a remains. Thereby, an oxidation constriction structure is formed that restricts the path of the drive current of the light-emitting portion to only the central portion of the mesa structure. The non-oxidation region 105b is the current passage region (current injection region). In this way, for example, a square current passage region with a side length of 10 μm is formed.

[0058] Next, using photolithography technology, a resist pattern is formed on the first contact layer 102 and the second contact layer 107. The resist pattern has openings between the planned formation area of the first sub-array 121 and the planned formation area of the second sub-array 122, and between the planned formation area of the second sub-array 122 and the planned formation area of the cathode pad portion 129. The width of the opening is, for example, 20 μm. Next, using these resist patterns as masks, Cl 2By using the ECR etching method with gas, as shown in FIGS. 14 and 20, the first contact layer 102 is etched so that the substrate 101 is exposed as the bottom surface. As a result, grooves with a width of 20 μm are formed in the first contact layer 102. Due to the grooves, the first contact layer 102 in the first sub-array 121, the first contact layer 102 in the second sub-array 122, and the first contact layer 102 in the cathode pad portion 129 are electrically insulated. The grooves may be formed by a wet etching method using a solvent.

[0059] Next, as shown in FIG. 15, an optically transparent insulating layer 108 covering the mesa structure is formed, for example, by using a plasma chemical vapor deposition (CVD) method. The insulating layer 108 is, for example, a SiN layer. Next, using photolithography technology, openings 108a and 108b, and openings 108s and 108t are formed in the insulating layer 108 by etching using BHF (buffered hydrofluoric acid) or the like.

[0060] Next, formation of a resist pattern, formation of a metal film, and lift-off are performed by photolithography technology, and electrodes 109a, 109b, and 109x are formed as shown in FIG. 16. The metal film is, for example, a laminate including a Ti film, a Pt film on the Ti film, and an Au film on the Pt film. The underlayer for ohmic connection with the first contact layer 102 and the underlayer for ohmic connection with the second contact layer 107 may be different. In this case, evaporation and lift-off may be performed in two or three steps.

[0061] Next, as shown in FIG. 17, an optically transparent dielectric layer 111 covering the electrodes 109a, 109b, and 109x is formed, for example, by using a plasma CVD method. The dielectric layer 111 is, for example, a SiN layer. Next, using photolithography technology, openings 111a, 111b, and 111x are formed in the dielectric layer 111 by etching using BHF (buffered hydrofluoric acid) or the like.

[0062] Next, as shown in FIG. 18, a solder film 112 is then formed. In forming the solder film 112, first, a seed layer (not shown) is formed by a sputtering method or the like. The seed layer includes, for example, a Ti film and a Cu film on the Ti film. Next, a resist pattern is formed on the seed layer using photolithography technology. The resist pattern opens only the mounting area used for mounting with the submount 150. The distance between adjacent openings is, for example, 200 μm. This distance is desirably set in consideration of subsequent mounting processes so that no short circuit occurs between adjacent mounting pads. Next, the solder film 112 is selectively formed in the openings by an electroplating method. The material of the solder film 112 is, for example, SnAg, SnAgCu, SuAu, etc. An adhesion layer such as a Ni layer or a Cr layer may be formed between the seed layer and the solder film 112. After the formation of the solder film 112, the resist pattern is removed, and etch-back by reverse sputtering or the like over the entire surface is performed to remove the exposed seed layer.

[0063] Next, the emitting side surface (back surface) of the substrate 101 is polished to a mirror finish by a Chemical Mechanical Polishing (CMP) method or the like. Next, an antireflection film 110 is formed on the emitting side surface of the substrate 101. The antireflection film 110 is formed, for example, by a plasma CVD method. The antireflection film 110 is, for example, a SiN film with an optical thickness of λ / 4.

[0064] In this way, the VCSEL array 300 according to the third embodiment is manufactured.

[0065] (Fourth Embodiment) Next, the fourth embodiment will be described. The fourth embodiment relates to a VCSEL array. FIG. 21 is a cross-sectional view showing a surface-emitting laser array according to the fourth embodiment. FIG. 22 is an equivalent circuit diagram showing a surface-emitting laser array according to the fourth embodiment.

[0066] As shown in FIG. 21, the VCSEL array 400 according to the fourth embodiment includes a substrate 101, a first sub-array 121, a second sub-array 122, a third sub-array 123, and a cathode pad portion 129 on the substrate 101. As shown in FIG. 22, the first sub-array 121, the second sub-array 122, and the third sub-array 123 are connected in series with each other. The first sub-array 121, the second sub-array 122, and the third sub-array 123 each include two VCSEL elements 124 that emit light L through the substrate 101. In the first sub-array 121, the two VCSEL elements 124 are electrically connected in parallel with each other, in the second sub-array 122, the two VCSEL elements 124 are electrically connected in parallel with each other, and in the third sub-array 123, the two VCSEL elements 124 are electrically connected in parallel with each other. As shown in FIG. 21, the third sub-array 123 is between the second sub-array 122 and the cathode pad portion 129.

[0067] In addition to the openings 108a and 108b, the insulating layer 108 has an opening 108c that exposes the second contact layer 107 of the two VCSEL elements 124 included in the third sub-array 123. In addition to the openings 108s and 108t, the insulating layer 108 has an opening 108u that exposes the first contact layer 102 included in the third sub-array 123.

[0068] In addition to the electrodes 109a, 109b, and 109x, the VCSEL array 100 has an electrode 109c on the insulating layer 108. The electrode 109c contacts the second contact layer 107 of the two VCSEL elements 124 included in the third sub-array 123 through the opening 108c.

[0069] The dielectric layer 111 has openings 111a and 111x, but does not have an opening 111b. Accordingly, the dielectric layer 111 covers the entire electrodes 109b and 109c. The VCSEL array 400 has solder films 112 in the opening 111a and in the opening 111x. The VCSEL array 400 further has a solder film 112c that extends across the second sub-array 122 and the third sub-array 123. The solder film 112c may enter inside the gap of the dielectric layer 111 between the second sub-array 122 and the third sub-array 123. In the fourth embodiment, the solder films 112 and 112c function as mounting pads.

[0070] Other configurations are the same as those in the third embodiment.

[0071] Next, a light source module including the VCSEL array 400 will be described. FIG. 23 is a cross-sectional view showing the light source module including the VCSEL array 400.

[0072] As shown in FIG. 23, the light source module has a submount 150 on which the VCSEL array 400 is mounted. The submount 150 has an insulating substrate 151, electrodes 152, 153, and 155 on the insulating substrate 151, and a dielectric layer 156. The portions of the electrodes 152, 153, and 155 exposed from the dielectric layer 156 function as second mounting pads. For example, the mounting pad of the first sub-array 121 and the second mounting pad of the electrode 152 have the same planar shape. For example, the mounting pads (solder films 112c) of the second sub-array 122 and the third sub-array 123 and the second mounting pad of the electrode 155 have the same planar shape. For example, the mounting pad of the cathode pad portion 129 and the second mounting pad of the electrode 153 have the same planar shape.

[0073] The fourth embodiment also provides the same effects as the third embodiment. Further, the mounting pads can be combined into one without electrically short-circuiting the second subarray 122 and the third subarray 123. Therefore, the number of subarrays is equal to the number of mounting pads. Although the electrode 155 is not included in the current path, the heat generated in the VCSEL element 124 included in the second subarray 122 and the heat generated in the VCSEL element 124 included in the third subarray 123 are efficiently released to the submount 150 through the electrode 155 and the bonding material 154 thereon. In the fourth embodiment, no gap for the mounting pad is required between the second subarray 122 and the third subarray 123, a bonding region with a large area can be obtained, and more excellent heat dissipation characteristics can be obtained.

[0074] Note that the VCSEL array 400 according to the fourth embodiment has three subarrays. However, even if the number of subarrays is four or more, the number of mounting pads can be three. For example, even if the number of subarrays is four or five, the VCSEL array may have the mounting pad of the first subarray 121, the mounting pad of the cathode pad portion 129, and the mounting pad for heat dissipation not included in the current path. In such a case, the number of mounting pads is less than the number of subarrays. Further, for example, when the number of subarrays is five, the mounting pads that are not included in the current path and are not electrically connected may be divided into two regions, and the number of mounting pads may be four.

[0075] Note that the insulation separation between adjacent first contact layers 102 may be performed by ion implantation of hydrogen or the like instead of forming a groove by etching.

[0076] Also, in the above embodiment, the substrate 101 is a semi-insulating GaAs substrate in order to electrically insulate the semiconductor laminate structure and the substrate 101. However, the substrate 101 is not limited to the semi-insulating GaAs substrate. For example, if there is a non-doped GaAs layer between the substrate 101 and the first contact layer 102, the substrate 101 may be an n-type GaAs substrate.

[0077] (Fifth Embodiment) Next, the fifth embodiment will be described. The fifth embodiment relates to a distance measuring device. The distance measuring device is an example of an optical device. FIG. 24 is a diagram showing the distance measuring device according to the fifth embodiment.

[0078] The distance measuring device 500 according to the fifth embodiment includes a light projecting unit 510, a light receiving unit 520, a time measurement circuit 530, and a control circuit 540.

[0079] The light projecting unit 510 includes, for example, a light source 511, a light source driving circuit 512, an optical scanner 513, an optical scanner driving circuit 514, a scanning angle monitor 515, and a projection lens 516. The light source 511 includes a light source module having a VCSEL array according to the first to fourth embodiments. The light source driving circuit 512 drives the light source 511 based on a driving signal output from the control circuit 540. The optical scanner 513 includes a MEMS (Micro Electro Mechanical System) mirror, a polygon mirror, or the like. The optical scanner driving circuit 514 drives the optical scanner 513 based on a driving signal output from the control circuit 540. The light source module of the light source 511 has a plurality of sub-arrays. Each sub-array includes one or more VCSEL elements, and the VCSEL elements within each sub-array are electrically connected in parallel. Also, each sub-array is arranged one-dimensionally in the scanning direction (in the sub-scanning direction) of the optical scanner 513. The light source module of the light source 511 is driven by the light source driving circuit 512 with a pulse current on the order of nanoseconds, for example. Then, the laser light emitted from the VCSEL element is converted into a desired beam profile by a projection lens 516 or the like as necessary, and then the irradiation direction is determined by the optical scanner 513 and irradiated to the outside of the distance measuring device 500. The scanning angle of the optical scanner 513 is measured by the scanning angle monitor 515, and this result is output to the control circuit 540. The optical scanner 513 and the projection lens 516 are examples of optical elements.

[0080] The laser light irradiated to the outside of the distance measuring device 500 is reflected by an object and returns to the distance measuring device 500, reaching the light receiving unit 520.

[0081] The light-receiving unit 520 includes, for example, a light-receiving element 521, a light-receiving lens 522, and a band-pass filter 523. The light-receiving element 521 includes a silicon APD (Avalanche Photo Diode) element. The light-receiving lens 522 converges the light that has reached the light-receiving unit 520 onto the light-receiving element 521. The band-pass filter 523 includes a dielectric multilayer film and is designed to transmit only the light in the region of the oscillation wavelength of the light source 511. The signal-to-noise ratio of the signal can be improved by the band-pass filter 523.

[0082] The light that has reached the light-receiving element 521 is converted into an electrical signal by the light-receiving element 521 and input into the time measurement circuit 530 through an amplifier 531 and a comparator 532 as required.

[0083] The time measurement circuit 530 receives the drive signal of the light source 511 output by the control circuit 540 and the signal from the light-receiving element 521. The time measurement circuit 530 measures the delay time between these two signals and outputs the result to the control circuit 540.

[0084] The control circuit 540 converts the delay time from the time measurement circuit 530 into a light wavelength.

[0085] According to such a distance measurement device 500, the distance to an object is measured, and two-dimensional distance information can be obtained by sequentially irradiating the sub-light-emitting region of the light source module and the spatial region decomposed by the optical scanner 513 with laser light. This distance measurement device 500 can be used, for example, in LiDAR (Light Detection and Ranging).

[0086] The light source module of the present disclosure can be used not only as the light source of a distance measuring device but also as the excitation light source of a solid-state laser. Further, a surface-emitting laser module can be combined with an optical element such as a phosphor that performs wavelength conversion of the emitted light from the surface-emitting laser module and used as a light source device such as a projector. A surface-emitting laser module can also be combined with an optical element such as a lens, a mirror, or a diffraction grating that diverges or converges the emitted light from the surface-emitting laser module and used as a light source device for sensing.

[0087] As described above in detail regarding the preferred embodiments, etc., it is not limited to the above-described embodiments, etc., and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

Description of Reference Numerals

[0088] 100, 200, 300, 400, surface-emitting laser array (VCSEL array) 101 substrate 102, 107 contact layer 103, 106 multilayer mirror 104 resonator 105 selective oxidation layer 109a, 109b, 109c, 109x electrode 121, 122, 123 sub-array 124 VCSEL element 125 pseudo-VCSEL element 129 cathode pad portion 150 submount 500 distance measuring device

Prior Art Documents

Patent Documents

[0089]

Patent Document 1

Patent Document 2

Patent Document 3

Claims

1. A semiconductor substrate, a plurality of sub-arrays provided on the semiconductor substrate, each sub-array including a plurality of surface-emitting laser elements that emit light through the semiconductor substrate and are electrically connected in parallel to each other, having, each of the surface-emitting laser elements including, in order from the semiconductor substrate side, a first semiconductor layer of a first conductivity type, a resonator, a second semiconductor layer of a second conductivity type, having, adjacent sub-arrays having an electrode that commonly connects the first semiconductor layer in the plurality of surface-emitting laser elements included in one of the sub-arrays and the second semiconductor layer in the plurality of surface-emitting laser elements included in the other sub-array, the plurality of sub-arrays being electrically connected in series, in the arrangement direction in which the plurality of sub-arrays are arranged, two or more of the surface-emitting laser elements are arranged in the arrangement direction within one of the plurality of sub-arrays, and a region electrically connected to the second semiconductor layer of each of the two or more surface-emitting laser elements is disposed on the one sub-array, the electrode being electrically connected to the second semiconductor layer of each of the two or more surface-emitting laser elements, a surface-emitting laser array, characterized in that it includes a dielectric layer that covers the electrode and is provided with an opening that exposes a part of the electrode on the sub-array.

2. One or more of the plurality of sub-arrays are provided with mounting pads mounted on a mounting substrate, the mounting pads including a conduction pad that is a region electrically connected to the second semiconductor layer and a non-conduction pad that is not electrically connected to the second semiconductor layer, the conduction pad being a part exposed from the opening of the electrode or a solder film provided in the opening, the non-conduction pad being a solder film on the dielectric layer, the surface-emitting laser array according to claim 1.

3. In the arrangement direction, the size of the mounting pad is smaller than the size of the sub-array on which the mounting pad is provided, the surface-emitting laser array according to claim 2.

4. Two or more of the plurality of sub-arrays are provided with the mounting pads, the distance between the emission points of the surface-emitting laser elements between adjacent sub-arrays being smaller than the distance between adjacent mounting pads, the surface-emitting laser array according to claim 2 or 3.

5. The surface-emitting laser array according to any one of claims 2 to 4, wherein the number of the mounting pads is less than or equal to the number of the sub-arrays.

6. The surface-emitting laser array according to any one of claims 1 to 5, wherein a distance between emission points of the surface-emitting laser elements between adjacent sub-arrays is equal to a distance between emission points of the surface-emitting laser elements within the sub-arrays.

7. A surface-emitting laser array, a mounting substrate on which the surface-emitting laser array is mounted, and having, wherein the surface-emitting laser array includes a semiconductor substrate, a plurality of sub-arrays provided on the semiconductor substrate, emitting light through the semiconductor substrate, and including a plurality of surface-emitting laser elements electrically connected in parallel to each other, and having, each of the surface-emitting laser elements includes, in order from the semiconductor substrate side, a first semiconductor layer of a first conductivity type, a resonator, a second semiconductor layer of a second conductivity type, and having, adjacent sub-arrays have an electrode that commonly connects the first semiconductor layer in the plurality of surface-emitting laser elements included in one of the sub-arrays and the second semiconductor layer in the plurality of surface-emitting laser elements included in the other sub-array, the plurality of sub-arrays are electrically connected in series, in an array direction in which the plurality of sub-arrays are arranged, two or more of the surface-emitting laser elements are arranged in the array direction within one of the plurality of sub-arrays, and a region electrically connected to the second semiconductor layer of each of the two or more surface-emitting laser elements is disposed on the one sub-array, the electrode is electrically connected to the second semiconductor layer of each of the two or more surface-emitting laser elements, and includes a dielectric layer that covers the electrode and has an opening that exposes a part of the electrode on the sub-array, a light source module, characterized in that a region electrically connected to the second semiconductor layer on the sub-array and an electrode of the mounting substrate are joined by a bonding material.

8. One or more of the plurality of sub-arrays are provided with mounting pads mounted on the mounting substrate, the mounting pads include a conduction pad that is a region electrically connected to the second semiconductor layer and a non-conduction pad that is not electrically connected to the second semiconductor layer, the conduction pad is a part exposed from the opening of the dielectric layer of the electrode or a solder film provided in the opening. The non-conductive pad is a solder film on the dielectric layer, The light source module according to claim 7, wherein the mounting substrate has a second mounting pad having the same planar shape as the mounting pad.

9. The light source module according to claim 7 or 8, An optical element into which the light emitted from the light source module is incident, A distance measuring device characterized by comprising the same.

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