Chip resistor

Abstract

The purpose of the present invention is to provide a chip resistor that can handle high power. A chip resistor according to the present disclosure comprises an insulation substrate (11), a pair of electrodes (12), and a resistor (13). The pair of electrodes (12) are provided at the respective ends of the upper surface of the insulation substrate (11). The resistor (13) is provided on the insulation substrate (11) and is connected to the pair of electrodes (12). The insulation substrate (11) has a first region (11a) in the center thereof and a second region (11b) at each end of the first region (11a). A recess (20) is provided in the first region (11a) of the insulation substrate (11). The resistor (13) formed on the first region (11a) has a serpentine shape in plan view. At least part of the resistor (13) is embedded in the recess (20). A trimming groove (14) is provided in the resistor (13) formed on a second region (11b).

Description

Technical Field

[0001] The present disclosure relates to a chip resistor formed of a thick film resistor used in various electronic devices, and particularly to a chip resistor used in electronic devices that require high power.

Background Art

[0002] As shown in FIGS. 20 and 21, a conventional chip resistor includes a substrate 1 made of an insulator, a pair of electrodes 2, a layer 3 made of a resistor, protective films 4a and 4b, electrodes 5 provided on a pair of end faces, and a metal layer 6 formed by plating. The pair of electrodes 2 are respectively provided at both ends of the upper surface of the substrate 1. The layer 3 made of a resistor is provided on the upper surface of the substrate 1 and between the pair of electrodes 2. The protective films 4a and 4b are provided so as to cover at least the layer 3 made of a resistor. The pair of electrodes 5 are respectively provided on both end faces of the substrate 1 so as to be electrically connected to the pair of electrodes 2. The metal layer 6 is provided on a part of the surfaces of the pair of electrodes 2 and the surfaces of the pair of electrodes 5. The layer 3 made of a resistor is formed in a meandering shape. Note that FIG. 20 is a top view of a conventional chip resistor. FIG. 21 is a cross-sectional view of the chip resistor shown in FIG. 20 cut along line XXI-XXI.

[0003] Note that the conventional chip resistors shown in FIGS. 20 and 21 are disclosed in, for example, Patent Document 1.

[0004] Further, as shown in FIG. 22, another conventional chip resistor includes a substrate 1 made of an insulator, a pair of electrodes 2, a layer 3 made of a resistor, a protective film 4, and a glass layer 8. A recess is formed in the substrate 1, and the glass layer 8 is provided at the bottom of the recess. The layer 3 made of a resistor is provided on the recess of the substrate 1 and on the glass layer 8. The pair of electrodes 2 are provided on the substrate 1 so as to be in contact with the layer 3 made of a resistor. The protective film 4 is provided on the layer 3 made of a resistor. The conventional chip resistor shown in FIG. 22 is disclosed in, for example, Patent Document 2.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

[0006] In the conventional chip resistor disclosed in Patent Document 1, when trying to cope with high power, the heat generation of the layer 3 made of the resistor body becomes large. Therefore, the temperature of the layer 3 made of the resistor body becomes high, and there is a problem that it cannot cope with high power.

[0007] Also, in the conventional chip resistor disclosed in Patent Document 2, since all of the layer 3 made of the resistor body is embedded in the concave portion, there is a problem that heat is dissipated only at the portion in contact with the substrate 1 made of the insulator.

[0008] The present disclosure aims to solve the above-mentioned conventional problems and provide a chip resistor capable of coping with high power.

[0009] To solve the above problems, the chip resistor of the present disclosure includes an insulating substrate, a pair of electrodes, and a resistor body. The insulating substrate has a first region at the central portion when viewed from its upper surface, and second regions at both ends of the first region. A concave portion is provided in the first region of the insulating substrate. The pair of electrodes are respectively provided at both ends of the upper surface of the insulating substrate. The resistor body is provided at least in the concave portion of the insulating substrate. The resistor body is connected to each of the pair of electrodes. Further, the resistor body has a trimming groove in the second region of the insulating substrate.

[0010] It is preferable that the concave portion of the chip resistor of the present disclosure is in a meandering shape.

[0011] It is preferable that a resistor body is further provided on the upper surface of the insulating substrate in the chip resistor of the present disclosure.

[0012] The chip resistor of the present disclosure has a resistor embedded in a recess provided in an insulating substrate, particularly a meandering recess. Therefore, the contact area between the resistor and the insulating substrate is increased. As a result, the heat generated in the resistor can be effectively dissipated to the insulating substrate. Consequently, the temperature of the resistor can be lowered. Therefore, the chip resistor exhibits an excellent effect of being capable of handling high power.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the embodiments shown below are merely embodiments of the invention according to the present disclosure, and the invention according to the present disclosure is not limited to the embodiments shown below.

[0015] (First Embodiment) The chip resistor in the first embodiment of the present disclosure will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of the chip resistor in the first embodiment of the present disclosure, and FIG. 2 is a top view of the chip resistor. FIG. 1 is a cross-sectional view when the chip resistor shown in FIG. 2 is cut along the line I-I in a plane perpendicular to the paper surface.

[0016] As shown in FIGS. 1 and 2, the chip resistor in the first embodiment of the present disclosure includes an insulating substrate 11, a pair of upper surface electrodes 12, a resistor 13, a trimming groove 14, a first protective film 15, and a second protective film 16. The pair of upper surface electrodes 12 are respectively provided at both ends of the upper surface of the insulating substrate 11. The resistor 13 is on a part of the pair of upper surface electrodes 12 and on the upper surface of the insulating substrate 11, and is formed between the pair of upper surface electrodes 12. The trimming groove 14 is provided in the resistor 13. The first protective film 15 covers the resistor 13. The second protective film 16 covers the first protective film 15.

[0017] In addition, a pair of end surface electrodes 17 are respectively provided on both end surfaces of the insulating substrate 11. The pair of end surface electrodes 17 are electrically connected to the pair of upper surface electrodes 12 respectively. Also, on each of both end surfaces of the insulating substrate 11, a plating layer 18 is formed on each part of each of the pair of upper surface electrodes 12 and on the surface of each of the pair of end surface electrodes 17.

[0018] Note that, to avoid complexity, in FIG. 2, the illustration of the first protective film 15, the second protective film 16, the pair of end surface electrodes 17, and the plating layer 18 is omitted.

[0019] Note that, taking the thickness direction of the insulating substrate 11 as the Z axis, the plane parallel to the upper surface of the insulating substrate 11 as the XY plane, the direction from one of the pair of upper surface electrodes 12 to the other as the X axis, and the direction perpendicular to the X axis as the Y axis, an XYZ orthogonal coordinate system is defined. The cross-sectional view shown in FIG. 1 is a cross-sectional view when cut along the line I-I shown in FIG. 2 and in a plane parallel to the XZ plane. Note that, in all the drawings described below, the XYZ orthogonal coordinate system is defined as described above.

[0020] In the above configuration, the insulating substrate 11 is Al 2 O 3It is composed of alumina containing 96%. The shape of the insulating substrate 11 is rectangular (rectangular in top view). This insulating substrate 11 is divided into a first region 11a in the central part and second regions 11b at both ends of the first region 11a. Further, in the first region 11a, a meandering recess 20 is provided in top view. Here, "top view" means looking from the direction in which the upper surface of the insulating substrate 11 faces.

[0021] The insulating substrate 11 with the meandering recess 20 formed will be described. The thickness of the insulating substrate 11 is 0.4 mm, the length in the X-axis direction is 1.95 mm, and the length in the Y-axis direction is 1.2 mm. FIG. 3 is a cross-sectional view of the insulating substrate with the recess 20 formed. FIG. 4 is a top view of the insulating substrate with the recess 20 formed. FIG. 3 is a cross-sectional view when cut along the line III-III of the insulating substrate 11 shown in FIG. 4 and in a plane perpendicular to the paper surface.

[0022] The width Xa of the first region 11a in the X-axis direction is Xa = 1.02 mm. Regarding the width of the second region 11b in the X-axis direction, if the width of the second region 11b on the left side in FIG. 4 is Xb1 and the width of the second region 11b on the right side is Xb2, then Xb1 = 0.63 mm and Xb2 = 0.3 mm.

[0023] Regarding the recess 20, it is formed within the region of the width Ya in the Y-axis direction between the left boundary and the right boundary of the first region 11a in FIG. 4. The width of the recess 20 is Xa1. The recess 20 extends in the Y-axis direction along the left boundary of the first region 11a, and when the length of the recess 20 becomes Ya1, it extends in the X-axis direction. Then, with a gap Xv from the recess 20 that extended in the Y-axis direction (negative Y-axis direction) just now, the recess 20 extends in the Y-axis direction (positive Y-axis direction) again. And when the recess 20 makes a round trip and the length of the recess 20 becomes Ya1, it extends in the X-axis direction again. Repeating such a process, the recess 20 reaches from the left boundary to the right boundary of the first region 11a in FIG. 4.

[0024] In the first embodiment, the depth of the recess 20 is 0.01 mm. For the recess 20, Xa1 = 0.15 mm, Ya = 0.8 mm, Ya1 = 0.68 mm, and Xv = 0.14 mm. Xa2 = 0.44 mm. Hereinafter, the X-axis direction may be referred to as the longitudinal direction of the insulating substrate.

[0025] Also, each of the pair of upper surface electrodes 12 is provided at both ends on the upper surface of the second region 11b of the insulating substrate 11.

[0026] The pair of upper surface electrodes 12 are formed by printing and baking a thick film material containing a metal such as silver. Note that a pair of back surface electrodes (not shown) may be provided at both ends on the back surface of the insulating substrate 11.

[0027] The resistor 13 is provided between the pair of upper surface electrodes 12 on the upper surface of the insulating substrate 11. For the resistor 13, the thickness is 0.02 mm, the length in the X-axis direction is 1.35 mm, and the length in the Y-axis direction is 0.8 mm.

[0028] The resistor 13 is formed by printing a thick film material made of copper nickel, silver palladium, or ruthenium oxide and then baking it. The resistor 13 partially overlaps and is connected to each of the pair of upper surface electrodes 12. Two overlapping portions of the resistor 13 with the pair of upper surface electrodes 12 are formed. In FIGS. 1 and 2, both ends of the resistor 13 are formed on the upper surfaces of both ends of the pair of upper surface electrodes 12, but they may be formed on the lower surfaces of both ends of the pair of upper surface electrodes 12. A current flows through the resistor 13 between the pair of upper surface electrodes 12.

[0029] This resistor 13 is embedded in the recess 20 in the first region 11a. Therefore, the resistor 13 is formed in a meandering shape, whereby the effective length of the resistor 13 becomes longer and the potential difference per unit length becomes smaller, so the surge resistance is improved. Also, since the resistor 13 is buried in the recess 20, the resistors 13 do not face each other in the planar direction, and the surge resistance is further improved.

[0030] Further, the resistor 13 is formed on the upper surface of the insulating substrate 11 in the second region 11b. The resistor 13 embedded in the recess 20 is connected to the resistor 13 formed on the upper surface of the insulating substrate 11.

[0031] Next, the insulating substrate 11 when the resistor 13 is provided on the insulating substrate 11 in which the recess 20 is formed will be described below. FIG. 5 is a top view of the insulating substrate 11 when the resistor 13 is provided on the insulating substrate 11 in which the recess 20 is formed. In the first region 11a of the insulating substrate 11, the resistor 13 is embedded in the recess 20. Regarding the second region 11b of the insulating substrate 11, let the length of the resistor 13 extending in the X-axis direction from the second region 11b on the left side of FIG. 5 be X13b1, and the length of the resistor 13 extending in the X-axis direction from the second region 11b on the right side of FIG. 5 be X13b2.

[0032] Let the value in the X-axis direction of the overlapping width in the X-axis direction between the resistor 13 extending in the X-axis direction from the second region 11b on the left side of FIG. 5 and the region where the resistor 13 is embedded in the recess 20 in the first region 11a be X13a1. Also, let the value in the X-axis direction of the overlapping width in the X-axis direction between the resistor 13 extending in the X-axis direction from the second region 11b on the right side of FIG. 5 and the region where the resistor 13 is embedded in the recess 20 in the first region 11a be X13a2. Further, let the size of the entire resistor 13 in the X-axis direction be X13, and the size in the Y-axis direction be Y13. In the first embodiment, X13 = 1.35 mm, Y13 = 0.8 mm, X13a1 = 0.08 mm, X13a2 = 0.08 mm, X13b1 = 0.33 mm, and X13b2 = 0.25 mm.

[0033] Next, the relationship between the resistor 13 formed on the insulating substrate 11 and the pair of upper surface electrodes 12 will be described with reference to FIG. 6. FIG. 6 is a top view showing the arrangement relationship between the resistor 13 formed on the insulating substrate 11 and the pair of upper surface electrodes 12. The resistor 13 partially overlaps and is connected to each of the pair of upper surface electrodes 12. Each of the pair of upper surface electrodes 12 is made of a metal such as silver with a thickness of 0.01 mm. That is, the thickness of each of the pair of electrodes 12 is 0.01 mm. Also, each of the pair of upper surface electrodes 12 has a rectangular shape with sides in the X-axis direction and the Y-axis direction. The lengths of the sides in the Y-axis direction of the pair of upper surface electrodes 12 are the same. Let the length of each of the pair of upper surface electrodes 12 in the Y-axis direction be Y12. Also, for the pair of upper surface electrodes 12, let the length of one side in the X-axis direction of the upper surface electrode 12 on the left side of the paper surface of FIG. 6 be X121, and the length of one side in the X-axis direction of the upper surface electrode 12 on the right side of the paper surface of FIG. 6 be X122. In the first embodiment, X121 = 0.35 mm, X122 = 0.2 mm, X12b1 = 0.1 mm, X12b2 = 0.1 mm, and Y12 = 0.9 mm.

[0034] Furthermore, as shown in FIG. 2, trimming grooves 14 are provided in the resistor 13 formed in the second region 11b. It is difficult to form trimming grooves 14 in the resistor 13 embedded in the recess 20. However, it is easy to form trimming grooves 14 in the resistor 13 formed on the upper surface of the insulating substrate 11 in the second region 11b.

[0035] The trimming grooves 14 are formed by irradiating the resistor 13 formed on the upper surface of the insulating substrate 11 in the second region 11b with laser light. In FIG. 2, the shape of the trimming grooves 14 is L-shaped, but it is not limited to this. Also, it is preferable that the resistor 13 has a meandering shape as a whole with the resistor 13 embedded in the recess 20 in the first region 11a and the resistor 13 provided with the trimming grooves 14 in the second region 11b.

[0036] The first protective film 15 covers the resistor 13 and is made of an insulator mainly composed of glass. The first protective film 15 can mitigate the impact caused by the irradiation of laser light when forming the trimming groove 14 in the resistor 13. After forming the first protective film 15 on the resistor 13, laser light is irradiated onto the first protective film 15 to form the trimming groove 14.

[0037] The second protective film 16 covers the entire first protective film 15 and a part of the pair of upper surface electrodes 12 and is made of an epoxy resin.

[0038] A pair of end surface electrodes 17 are respectively provided on both end surfaces of the insulating substrate 11, and are formed by printing a material composed of Ag and resin so as to be electrically connected to the upper surfaces of the pair of upper surface electrodes 12 exposed from the second protective film 16. Note that the end surface electrodes 17 may be formed by sputtering a metal material.

[0039] Furthermore, a plating layer 18 composed of a Ni plating layer and a Sn plating layer is formed on a part of the pair of upper surface electrodes 12 and the surfaces of the pair of end surface electrodes 17. At this time, the plating layer 18 is in contact with the second protective film 16. Note that a Cu plating layer may be provided under the Ni plating layer.

[0040] Next, the trimming groove 14 will be described with reference to FIGS. 7 and 8. FIG. 7 is an enlarged view of a portion surrounded by the region α of the chip resistor shown in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII of the chip resistor shown in FIG. 7.

[0041] The trimming groove 14 penetrates the first protective film 15 and the resistor 13 from the surface of the first protective film 15 and reaches the surface of the insulating substrate 11. The inside of the trimming groove 14 is filled with the second protective film 16.

[0042] The trimming groove 14 is formed in the second region 11b on the left side of FIG. 2, extends in the X-axis direction, and has an L shape extending in the Y-axis direction. Let the length of the trimming groove 14 extending in the X-axis direction be X14, and the length extending in the Y-axis direction be Y14. Also, let the width of the trimming groove 14 be W14 and the depth be D14. Let the distance of the trimming groove 14 from the boundary between the first region 11a and the second region 11b on the left side of FIG. 2 be Xb14. Further, the trimming groove 14 extends beyond the resistor 13 along the Y-axis direction. Let the length of the trimming groove 14 extending beyond this resistor 13 be Yb14. In the first embodiment, W14 = 0.03 mm, D14 = 0.02 mm, Xb14 = 0.6 mm, and Yb14 = 0.05 mm.

[0043] As described above, in the first embodiment, since the meandering recess 20 provided in the insulating substrate 11 is embedded with the resistor 13, the contact area between the resistor 13 and the insulating substrate 11 increases. As a result, the heat generated in the resistor 13 can be effectively dissipated to the insulating substrate 11. As a result, the temperature of the resistor 13 can be lowered, and thus an effect of being able to handle high power is obtained. That is, a high-power type chip resistor can be obtained.

[0044] (Second Embodiment) The chip resistor according to the second embodiment of the present disclosure will be described below with reference to the drawings. FIG. 9 is a cross-sectional view of the chip resistor according to the second embodiment, and FIG. 10 is a top view of the same chip resistor. FIG. 9 is a cross-sectional view when the chip resistor shown in FIG. 10 is cut along the IX-IX line by a plane perpendicular to the paper surface. In FIG. 10, the illustration of the first protective film 15, the second protective film 16, the pair of end face electrodes 17, and the plating layer 18 is omitted to avoid complexity. As shown in FIG. 9, the chip resistor according to the second embodiment further provides a resistor 13 on the upper surface of the insulating substrate 11 and on the upper surface of the resistor 13 embedded in the recess 20 with respect to the chip resistor according to the first embodiment. At this time, the resistor 13 embedded in the recess 20 and the upper resistor 13 are integrally formed. Note that the dimensions and materials of each element in the chip resistor according to the second embodiment are the same as those of the chip resistor according to the first embodiment.

[0045] With this configuration, the contact area between the resistor 13 and the insulating substrate 11 becomes even larger. As a result, the heat generated in the resistor 13 can be effectively dissipated by the insulating substrate 11.

[0046] Note that the recess 20 does not necessarily have to be meandering in a top view. It is sufficient that the recess 20 exists in a part of the first region 11a and a part of the meandering resistor 13 is buried in the recess 20. Also in this case, the contact area between the resistor 13 and the insulating substrate 11 becomes large.

[0047] (Third Embodiment) Hereinafter, the chip resistor in the third embodiment of the present disclosure will be described with reference to FIGS. 11 and 12.

[0048] FIG. 11 is a cross-sectional view of the chip resistor in the third embodiment of the present disclosure, and FIG. 12 is a top view of the same chip resistor. FIG. 11 is a cross-sectional view taken along a plane parallel to the XZ plane passing through the line XI-XI of the chip resistor shown in FIG. 12. In FIG. 12, the illustration of the first protective film 15, the second protective film 16, the end face electrode 17, and the plating layer 18 is omitted for the sake of simplicity.

[0049] In FIGS. 11 and 12, a recess 20 is provided in the central portion of the upper surface of the insulating substrate 11. In the insulating substrate 11, the region where the recess 20 is provided is the first region 11a, and the regions on both sides of the recess 20 are the second regions 11b. That is, the edge of the recess 20 is the boundary between the first region 11a and the second region 11b. A pair of upper surface electrodes 12 are provided at both ends of the upper surface of the insulating substrate 11. Also, a resistor 13 is provided on the upper surface of the insulating substrate 11 between the pair of upper surface electrodes 12. A first trimming groove 14a is provided on the first region 11a of this resistor 13. Also, a second trimming groove 14b is provided on the second region 11b. Also, a first protective film 15 is provided so as to cover the resistor 13. Further, a second protective film 16 is provided so as to cover the first protective film 15.

[0050] Further, the chip resistor includes a pair of end face electrodes 17 provided on both end faces of the insulating substrate 11 so as to be electrically connected to a pair of upper surface electrodes 12, and a plating layer 18 formed on a part of the pair of upper surface electrodes 12 and the surfaces of the pair of end face electrodes 17.

[0051] In the above configuration, the insulating substrate 11 is made of alumina containing 96% of Al 2 O 3 and has a rectangular shape (rectangular in top view). A recess 20 is provided in the insulating substrate 11.

[0052] Also, the pair of upper surface electrodes 12 are provided at both ends of the upper surface of the insulating substrate 11 and are formed by printing and baking a thick film material containing a metal such as silver. A pair of lower surface electrodes 17b are provided at both ends of the lower surface of the insulating substrate 11.

[0053] Furthermore, the resistor 13 is formed on the upper surface of the insulating substrate 11 between the pair of upper surface electrodes 12 by printing a thick film material made of copper nickel, silver palladium, or ruthenium oxide and then baking it, and is connected to the pair of upper surface electrodes 12. In FIG. 11, both ends of the resistor 13 are formed on the upper surfaces of both ends of the pair of upper surface electrodes 12, but may also be formed on the lower surfaces of both ends of the pair of upper surface electrodes 12. A current flows through the resistor 13 between the pair of upper surface electrodes 12.

[0054] This resistor 13 is partially embedded in the recess 20.

[0055] Next, the first trimming grooves 14a and 14b will be described with reference to FIG. 13. FIG. 13 is an enlarged view of a portion surrounded by the region β of the chip resistor shown in FIG. 12.

[0056] The first trimming groove 14a reaches the surface of the insulating substrate 11 in which the recess 20 is formed by penetrating the first protective film 15 and the resistor 13 from the surface of the first protective film 15 in the first region 11a. The second protective film 16 is filled inside the first trimming groove 14a.

[0057] The second trimming groove 14b penetrates the first protective film 15 and the resistor 13 from the surface of the first protective film 15 and reaches the surface of the insulating substrate 11 in the second region 11b on the left side of FIG. 12. The second protective film 16 is filled inside the second trimming groove 14b.

[0058] The first trimming groove 14a is formed in the first region 11a shown in FIG. 11, extends in the X-axis direction, and has an L shape extending in the Y-axis direction. Let the length of the first trimming groove 14a extending in the X-axis direction be X14a, and the length extending in the Y-axis direction be Y14a. Also, let the width of the first trimming groove 14a be W14a and the depth be D14a. Let the distance of the first trimming groove 14a from the boundary between the first region 11a and the second region 11b on the right side of FIG. 12 be Xa14a. Further, the first trimming groove 14a extends beyond the resistor 13 along the Y-axis direction. Let the length of the trimming groove 14 extending beyond this resistor 13 be Ya14a. In the third embodiment, W14a = 0.03 mm, D14a = 0.02 mm, X14a = 0.05 mm, Y14a = 0.4 mm, Xb14a = 0.3 mm, and Yb14a = 0.05 mm.

[0059] The second trimming groove 14b is formed in the second region 11b on the left side of FIG. 12, extends in the X-axis direction, and has an L shape extending in the Y-axis direction. Let the length of the second trimming groove 14b extending in the X-axis direction be X14b, and the length extending in the Y-axis direction be Y14b. Also, let the width of the second trimming groove 14b be W14b and the depth be D14b. Let the distance of the second trimming groove 14b from the boundary between the first region 11a and the second region 11b on the left side of FIG. 12 be Xb14b. Further, the second trimming groove 14b extends beyond the resistor 13 along the Y-axis direction. Let the length of the trimming groove 14 extending beyond this resistor 13 be Yb14b. In the third embodiment, W14b = 0.03 mm, D14b = 0.01 mm, X14b = 0.05 mm, Y14b = 0.3 mm, Xb14b = 0.05 mm, and Yb14b = 0.05 mm. Also, the length of the first trimming groove 14a provided in the meandering resistor portion 13b in the short side direction of the insulating substrate 11 is larger than the length of the second trimming groove 14b provided in the rectangular parallelepiped resistor portion 13c on the upper surface of the insulating substrate 11 in the short side direction of the insulating substrate 11. With this configuration, since current concentrates on the meandering resistor portion 13b with high heat dissipation, it has the effect of being able to handle high power.

[0060] The first trimming groove 14a and the second trimming groove 14b are formed by irradiating the resistor 13 formed on the upper surface of the insulating substrate 11 with a laser. In FIG. 12, the shapes of the first trimming groove 14a and the second trimming groove 14b are L-shaped, but it is not limited thereto.

[0061] The first protective film 15 covers the resistor 13. The first protective film 15 is composed of an insulator mainly containing glass. The first protective film 15 can relieve the impact caused by the irradiation of laser light when forming the first trimming groove 14a and the second trimming groove 14b. After forming the first protective film 15 on the resistor 13, the first protective film 15 is irradiated with laser light to form the first trimming groove 14a and the second trimming groove 14b.

[0062] The second protective film 16 is made of an epoxy resin so as to cover the entire first protective film 15 and a part of the pair of upper surface electrodes 12. The pair of end surface electrodes 17 are provided on both end surfaces of the insulating substrate 11, and are formed by printing a material made of Ag and resin so as to be electrically connected to the upper surfaces of the pair of upper surface electrodes 12 exposed from the second protective film 16. Note that the end surface electrodes 17 may be formed by sputtering a metal material.

[0063] Furthermore, a plating layer 18 composed of a Ni plating layer and a Sn plating layer is formed on a part of the pair of upper surface electrodes 12 and the surfaces of the pair of end surface electrodes 17. At this time, the plating layer 18 is in contact with the second protective film 16. Note that a Cu plating layer may be provided under the Ni plating layer.

[0064] As described above, in the third embodiment, the resistor 13 is partially embedded in the recess 20 provided in the insulating substrate 11, the first trimming groove 14a is formed in the meandering resistor portion 13b, and the second trimming groove 14b is formed in the rectangular parallelepiped resistor portion 13c provided on the upper surface of the insulating substrate 11. Therefore, after significantly changing the resistance value by the first trimming groove 14a, the resistance value can be adjusted with high precision by the second trimming groove 14b, and as a result, there is an effect of improving the resistance value accuracy.

[0065] (Fourth Embodiment) The chip resistor according to the fourth embodiment of the present disclosure will be described below with reference to the drawings. A cross-sectional view of the chip resistor according to the fourth embodiment of the present disclosure is shown in FIG. 14, and a top view of the chip resistor is shown in FIG. 15. FIG. 14 is a cross-sectional view when the chip resistor shown in FIG. 15 is cut along the line XIV-XIV by a plane perpendicular to the paper surface. Note that in FIG. 15, the illustration of the first protective film 15, the second protective film 16, the pair of end surface electrodes 17, and the plating layer 18 is omitted to avoid complexity.

[0066] The chip resistor according to the fourth embodiment includes an insulating substrate 11, a pair of upper surface electrodes 12, a resistor 13, a first protective film 15, a second protective film 16, a pair of end surface electrodes 17, and a plating layer 18. The pair of upper surface electrodes 12 are respectively provided at both ends of the upper surface of the insulating substrate 11. A plurality of strip-shaped recesses 20 are provided on the upper surface of the insulating substrate 11. The resistor 13 is embedded in the recess 20 of the insulating substrate 11 and is provided so as to cover the recess 20. The resistor 13 is in contact with each of the pair of upper surface electrodes 12 and is electrically connected to the pair of upper surface electrodes 12. The first protective film 15 and the second protective film 16 are provided on the resistor 13. A trimming groove 14 reaching from the surface of the first protective film 15 to the insulating substrate 11 is provided between the recesses 20. The second protective film 16 is filled in the trimming groove 14. The pair of end surface electrodes 17 are provided on the outer surfaces in the longitudinal direction of the insulating substrate 11. The pair of end surface electrodes 17 are respectively in contact with and electrically connected to the pair of upper surface electrodes 12. A plating layer 18 is provided on the surface of each of the pair of end surface electrodes 17. Note that the dimensions and materials of the elements in the chip resistor according to the fourth embodiment are the same as those in the chip resistor according to the first embodiment.

[0067] The chip resistor according to this embodiment improves heat dissipation by increasing the contact area between the substrate with good heat dissipation and the resistor. Thereby, the chip resistor can be made to handle higher power.

[0068] (Fifth Embodiment) The chip resistor in the fifth embodiment of the present disclosure will be described below with reference to the drawings. A cross-sectional view of the chip resistor in the fifth embodiment of the present disclosure is shown in FIG. 16, and a top view of the chip resistor is shown in FIG. 17. FIG. 16 is a cross-sectional view when the chip resistor shown in FIG. 17 is cut along the line XVI-XVI by a plane perpendicular to the paper surface. In FIG. 17, illustration of the first protective film 15, the second protective film 16, the pair of end surface electrodes 17, and the plating layer 18 is omitted to avoid complexity.

[0069] The chip resistor according to the fifth embodiment includes an insulating substrate 11, a resistor 13, a pair of upper surface electrodes 12, a first protective film 15, a second protective film 16, a pair of end face electrodes 17, and a plating layer 18. The resistor 13 is provided on the upper surface of the insulating substrate 11. The pair of upper surface electrodes 12 are respectively provided at both ends of the upper surface of the insulating substrate 11 and are electrically connected to the resistor 13. The insulating substrate 11 has a first region 11a at the central portion thereof and second regions 11b at both ends of the first region 11a. A meandering recess 20 is provided in the first region 11a of the insulating substrate 11 in a top view. The resistor 13 is embedded in the recess 20. The resistor 13 has substantially the same shape as the recess 20 formed in the first region 11a. A trimming groove 14 is provided in the resistor 13 formed in the second region 11b. The trimming groove 14 is filled with the second protective film 16. Also, the pair of end face electrodes 17 are provided on the outer surfaces in the longitudinal direction of the insulating substrate 11. The pair of end face electrodes 17 are respectively in contact with and electrically connected to the pair of upper surface electrodes 12. A plating layer 18 is provided on the surface of each of the pair of end face electrodes 17. Note that the dimensions and materials of the elements in the chip resistor according to the fifth embodiment are the same as those in the chip resistor according to the first embodiment.

[0070] According to the chip resistor of this fifth embodiment, since the contact area with a substrate having good heat dissipation performance is improved, the heat dissipation performance of the chip resistor is improved. Therefore, it is possible to increase the power of the chip resistor.

[0071] (Sixth Embodiment) The chip resistor in the sixth embodiment of the present disclosure will be described below with reference to the drawings. A cross-sectional view of the chip resistor in the sixth embodiment of the present disclosure is shown in FIG. 18, and a top view of the chip resistor is shown in FIG. 19. FIG. 18 is a cross-sectional view when the chip resistor shown in FIG. 19 is cut along the line XVIII-XVIII by a plane perpendicular to the paper surface. In FIG. 19, illustration of the first protective film 15, the second protective film 16, the pair of end face electrodes 17, and the plating layer 18 is omitted to avoid complexity.

[0072] The chip resistor according to the sixth embodiment includes an insulating substrate 11, a pair of upper surface electrodes 12, a resistor 13, a first protective film 15, a second protective film 16, a pair of end face electrodes 17, and a plating layer 18. The pair of upper surface electrodes 12 are respectively provided at both ends of the upper surface of the insulating substrate 11. The resistor 13 is in contact with the pair of upper surface electrodes 12 and is electrically connected to the upper surface electrodes 12. Further, the resistor 13 has a trimming groove 14. The first protective film 15 and the second protective film 16 are formed on the upper surface of the insulating substrate 11 so as to cover at least the resistor 13. The pair of end face electrodes 17 are provided on the outer surfaces in the longitudinal direction of the first protective film 15 and the insulating substrate 11. A plating layer 18 is provided on the surface of each of the pair of end face electrodes 17.

[0073] Further, a recess 20 is provided on the upper surface of the insulating substrate 11, and a hot spot portion 19 is provided in the recess 20. The hot spot portion 19 is a portion (current concentration portion) where current concentrates in the resistor 13. Note that the dimensions and materials of each element in the chip resistor according to the sixth embodiment are the same as those of the chip resistor according to the first embodiment.

[0074] According to the sixth embodiment, the contact area with a substrate having high heat dissipation properties for the hot spot portion 19 can be increased, thereby enabling the chip resistor to have higher power.

[0075] (Embodiment) An embodiment of the chip resistor of the present disclosure will be described below.

[0076] (First Aspect) The chip resistor according to the first aspect of the present disclosure includes an insulating substrate (11), a pair of electrodes (12), and a resistor body (13). The insulating substrate (11) has a first region (11a) in the central portion when viewed from its upper surface, and second regions (11b) at both ends of the first region (11a). A recess (20) is provided in the first region (11a) of the insulating substrate (11). The pair of electrodes are respectively provided at both ends of the upper surface of the insulating substrate (11). The resistor body (13) is provided at least in the recess (20) of the insulating substrate (11). The resistor body (13) is connected to each of the pair of electrodes (12). Further, the resistor body (13) has trimming grooves (14) in the second region (11b) of the insulating substrate (11).

[0077] (Second aspect) The chip resistor according to the second aspect of the present disclosure is, in the first aspect, such that the recess (20) is serpentine.

[0078] (Third aspect) The chip resistor according to the third aspect of the present disclosure is, in the first aspect, such that a further resistor body (13) is provided on the upper surface of the insulating substrate (11).

[0079] (Fourth aspect) The chip resistor according to the fourth aspect of the present disclosure includes an insulating substrate (11), a pair of upper surface electrodes (12), a resistor body (13), a protective layer, an end face electrode (17), and a lower surface electrode. The insulating substrate (11) has a rectangular shape. The insulating substrate (11) is provided with a recess (20) on its upper surface. The pair of upper surface electrodes (12) are provided on the upper surface of the insulating substrate (11). The resistor body (13) is provided on the upper surface of the insulating substrate (11) and within the recess (20). The resistor body (13) is electrically connected to the pair of upper surface electrodes (12). Further, the resistor body (13) has one or a plurality of trimming grooves (14). The protective layer is provided on the upper surface of the insulating substrate (11) and covers at least the resistor body (13). The end face electrode (17) is provided on the outer surface in the longitudinal direction of the insulating substrate (11). Also, the end face electrode (17) is electrically connected to one of the upper surface electrodes (12). The lower surface electrode (17b) is provided on the lower surface of the insulating substrate (11). Also, the lower surface electrode (17b) is electrically connected to the end face electrode (17).

[0080] (Fifth Aspect) The chip resistor according to the fifth aspect of the present disclosure is, in the fourth aspect, the plurality of trimming grooves (14) are composed of a first trimming groove (14a) and a second trimming groove (14b). The first trimming groove (14a) is disposed on the recess (20). The second trimming groove (14b) is disposed on a position different from the recess (20) on the insulating substrate (11). The length of the first trimming groove (14a) in the short side direction of the insulating substrate (11) is larger than the length of the second trimming groove (14b) in the short side direction of the insulating substrate (11).

[0081] (Sixth Aspect) The chip resistor according to the sixth aspect of the present disclosure includes an insulating substrate (11), a pair of upper surface electrodes (12), a resistor (13), a first protective film (15), a second protective film (16), and end face electrodes (17). The insulating substrate (11) has a rectangular shape. The insulating substrate (11) is provided with a plurality of strip-shaped recesses (20) on its upper surface. The pair of upper surface electrodes (12) are respectively provided at both ends of the upper surface of the insulating substrate (11). The resistor (13) is provided on at least the recess (20) of the insulating substrate (11). The resistor (13) is electrically connected to each of the pair of upper surface electrodes (12). The first protective film (15) is provided on the upper surface of the resistor (13). The end face electrodes (17) are provided from the outer surface in the longitudinal direction of the insulating substrate (11) to the lower surface. Also, the end face electrodes (17) are electrically connected to the upper surface electrodes (12). Trimming grooves (14) are formed in the resistor (13) and the first protective film (15). The trimming grooves (14) are formed so as to reach the strip-shaped recess (20) in the insulating substrate (11) from the upper surface of the first protective film (15). The second protective film (16) is provided on the first protective film (15). The trimming grooves (14) are filled with the second protective film (16).

[0082] (Seventh Aspect) The chip resistor according to the seventh aspect of the present disclosure includes an insulating substrate (11), a pair of upper surface electrodes (12), a resistor (13), a first protective film (15), a second protective film (16), and end face electrodes (17). The insulating substrate (11) is provided with a meandering concave portion (20) on its upper surface. The pair of upper surface electrodes (12) are respectively provided at both ends of the upper surface of the insulating substrate (11). The resistor (13) is embedded in at least the meandering concave portion (20) of the insulating substrate (11). The resistor (13) has a meandering resistor portion (13b) and a pair of rectangular parallelepiped resistor portions (13c). The meandering resistor portion (13b) is embedded in the meandering concave portion (20). The pair of rectangular parallelepiped resistor portions (13c) are provided on the upper surface of the insulating substrate (11). The pair of rectangular parallelepiped resistor portions (13c) are respectively arranged at both ends of the meandering resistor portion (13b). The pair of rectangular parallelepiped resistor portions (13c) are respectively electrically connected to the pair of upper surface electrodes (12). The first protective film (15) is provided on the upper surface of the resistor (13). The end face electrodes (17) are provided from the outer side surface in the longitudinal direction of the insulating substrate (11) to the lower surface. Further, the end face electrodes (17) are electrically connected to one of the upper surface electrodes (12). Trimming grooves (14) are formed in the resistor (13) and the first protective film (15). The trimming grooves (14) are formed so as to reach the concave portion (20) in the insulating substrate (11) from the upper surface of the first protective film (15) through the rectangular parallelepiped resistor portion (13c). The second protective film (16) is provided on the first protective film (15). The trimming grooves (14) are filled with the second protective film (16).

[0083] (Eighth Aspect) The chip resistor according to the eighth aspect of the present disclosure includes an insulating substrate (11), a pair of upper surface electrodes (12), a resistor (13), protective films (15, 16), and end face electrodes (17). A recess (20) is provided on the upper surface of the insulating substrate (11). The resistor (13) is provided on the upper surface of the insulating substrate (11). The pair of upper surface electrodes (12) are respectively provided at both ends of the upper surface of the insulating substrate (11). The resistor (13) is provided on the insulating substrate (11). The resistor (13) is electrically connected to each of the pair of upper surface electrodes (12). Further, the resistor (13) has a trimming groove (14). The protective films (15, 16) are provided on the upper surface of the insulating substrate (11) so as to cover at least the resistor (13). The recess (20) provided on the upper surface of the insulating substrate (11) is disposed at a current concentration portion (19) in the vicinity of the trimming groove (14).

Industrial Applicability

[0084] The chip resistor according to the present disclosure has an effect of being able to cope with high power, and is particularly useful in high-power type chip resistors formed of a thick film resistor used in various electronic devices and the like.

[0085] Further, the chip resistor of the present disclosure has an effect of being able to provide a chip resistor capable of adjusting the resistance value with high precision and coping with high power, and is particularly useful in chip resistors formed of a thick film resistor used in various electronic devices and the like.

Explanation of Reference Numerals

[0086] 11 Insulating substrate 11a First region 11b Second region 12 Upper surface electrode 13 Resistor 13b Meandering resistor portion 13c Cuboid resistor portion 14 Trimming groove 14a First trimming groove 14b Second trimming groove 15 First protective film 16 Second protective film 17 End face electrode 17b Bottom surface electrode 18 Plating layer 19 Hot spot part 20 Recess

Claims

【Claim 1】 A rectangular insulating substrate having a recess on its upper surface, a pair of upper surface electrodes provided on the upper surface of the insulating substrate, a resistor provided on the insulating substrate and electrically connected to the pair of upper surface electrodes and having a trimming groove, a protective layer provided on the upper surface of the insulating substrate so as to cover at least the resistor, an end face electrode provided on an outer surface in the longitudinal direction of the insulating substrate and electrically connected to the upper surface electrode, a lower surface electrode provided on the lower surface of the insulating substrate and electrically connected to the end face electrode, the resistor is provided on both the upper surface of the insulating substrate and the embedded portion embedded in the recess, A chip resistor in which the length in the short side direction of the insulating substrate of the first trimming groove provided in the resistor provided in the embedded portion is larger than the length in the short side direction of the insulating substrate of the second trimming groove provided in the resistor provided on the upper surface of the insulating substrate.

Images