Wiring Substrate, Semiconductor Device, and Method for Manufacturing Wiring Substrate

Abstract

To suppress deterioration of an electric characteristic.SOLUTION: A wiring board includes: an insulation layer; and a wiring layer laminated in the insulation layer and a wiring pattern. The wiring pattern includes: a base part risen from a front surface of the insulation layer; and a top part which is connected to one end on the side opposite to the insulation layer of the base part via a step of a width direction, and has a width wider than that of the base part.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board.

Background Art

[0002] Conventionally, for example, a wiring pattern may be formed on a wiring board on which a semiconductor chip is mounted by using, for example, a semi-additive method. Specifically, a seed layer is formed by electroless copper plating on an insulating layer of the wiring board, a pattern of a dry film resist (DFR) is formed on the seed layer, and then a wiring pattern is formed by electrolytic copper plating using the DFR pattern as a mask. Then, after a metal film is formed by plating such as tin (Sn) or solder on the upper surface of the wiring pattern, the DFR is peeled off.

[0003] The metal film formed on the upper surface of the wiring pattern functions as an etching resist. That is, after the DFR is peeled off, the upper surface of the wiring pattern is protected while the seed layer exposed between the wiring patterns is removed by etching. Then, the metal film formed on the upper surface of the wiring pattern is removed by selective etching.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, conventional wiring boards have a problem in that the width of the wiring pattern becomes narrower, resulting in a decrease in electrical characteristics. Specifically, in the etching process of the seed layer described above, the wiring pattern, which is formed using copper in the same way as the seed layer, is etched, and the width of the wiring pattern becomes narrower. At this time, the top surface of the wiring pattern is protected by a metal film such as tin or solder, while the sides of the wiring pattern are exposed and are exposed to the etching solution at the same time as the seed layer, thus narrowing the width of the wiring pattern.

[0006] Furthermore, when the width of the wiring pattern becomes narrower, the cross-sectional area and surface area of ​​the wiring pattern decrease, leading to increased resistance loss. As a result, the speed of electrical signals transmitted through the wiring pattern is hindered, and the electrical characteristics deteriorate.

[0007] The disclosed technology has been made in view of the above, and aims to provide a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can suppress the deterioration of electrical characteristics. [Means for solving the problem]

[0008] In one embodiment, the wiring board disclosed herein comprises an insulating layer and a wiring layer laminated on the insulating layer and having a wiring pattern, wherein the wiring pattern has a base portion rising from the surface of the insulating layer and a top portion wider than the base portion, connected to one end of the base portion opposite to the insulating layer via a step in the width direction. [Effects of the Invention]

[0009] According to one embodiment of the wiring board, semiconductor device, and method for manufacturing the wiring board disclosed herein, the effect is achieved that a decrease in electrical characteristics can be suppressed. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows the configuration of a wiring board according to one embodiment. [Figure 2]FIG. 2 is a diagram showing an enlarged structure of a wiring layer. [Figure 3] FIG. 3 is a diagram showing a specific example of the shape of a wiring layer. [Figure 4] FIG. 4 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 5] FIG. 5 is a diagram showing a specific example of a core substrate formation process. [Figure 6] FIG. 6 is a diagram showing a specific example of a build-up process. [Figure 7] FIG. 7 is a diagram showing a specific example of a solder resist layer formation process. [Figure 8] FIG. 8 is a diagram showing a specific example of a terminal formation process. [Figure 9] FIG. 9 is a diagram showing a specific example of a semiconductor chip mounting process. [Figure 10] FIG. 10 is a flowchart showing a wiring layer formation process. [Figure 11] FIG. 11 is a diagram showing a specific example of a seed layer formation process. [Figure 12] FIG. 12 is a diagram showing a specific example of a development process. [Figure 13] FIG. 13 is a diagram showing a specific example of a plating process. [Figure 14] FIG. 14 is a diagram for explaining an example of a protective film formation method. [Figure 15] FIG. 15 is a diagram for explaining an example of a protective film formation method. [Figure 16] FIG. 16 is a diagram showing a specific example of a protective film formation process. [Figure 17] FIG. 17 is a diagram showing a specific example of an etching process. [Figure 18] FIG. 18 is a diagram for explaining another example of a protective film formation method.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, an embodiment of a wiring board, a semiconductor device, and a method for manufacturing a wiring board disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited by this embodiment.

[0012] FIG. 1 is a diagram showing the configuration of a wiring board 100 according to an embodiment. In FIG. 1, a cross-section of the wiring board 100 is schematically shown. The wiring board 100 shown in FIG. 1 can be used, for example, as a substrate of a semiconductor device on which a semiconductor chip is mounted.

[0013] The wiring board 100 has a laminated structure and includes a core substrate 110, a multilayer wiring structure 120, and solder resist layers 130 and 140. Hereinafter, as shown in FIG. 1, the solder resist layer 140 is described as the lowermost layer and the solder resist layer 130 is described as the uppermost layer. However, the wiring board 100 may be used, for example, upside down, and may be used in any orientation.

[0014] The core substrate 110 is formed by forming wiring layers 113 on both sides of a base material 111 which is a plate-like insulator by metal plating. The wiring layers 113 on both sides are connected by vias 112 as necessary.

[0015] The multilayer wiring structure 120 is formed by laminating layers including an insulating insulating layer 121 and a conductive wiring layer 122. The insulating layer 121 is formed using an insulating resin such as an epoxy resin and a polyimide resin. The wiring layer 122 is formed using a metal such as copper. In FIG. 1, two layers are laminated in the multilayer wiring structure 120 above the core substrate 110, and two layers are laminated in the multilayer wiring structure 120 below the core substrate 110. However, the number of laminated layers may be one layer or three or more layers. As will be described later, the wiring pattern included in the wiring layer 122 has a wider width at the top farther from the core substrate 110 than at the base closer to the core substrate 110.

[0016] The solder resist layer 130 is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 130 is a layer made of an insulating photosensitive resin such as acrylic resin and polyimide resin, and is one of the insulating layers. The solder resist layer 130 may also be formed using an insulating non-photosensitive resin such as epoxy resin.

[0017] The solder resist layer 130 side of the wiring board 100 is the side on which electronic components such as semiconductor chips are mounted. At the location where the semiconductor chip is mounted, an opening 131 is drilled in the solder resist layer 130. If the solder resist layer 130 is formed using a photosensitive resin, the opening 131 can be formed by exposure and development. If the solder resist layer 130 is formed using a non-photosensitive resin, the opening 131 can be formed by laser processing. A connection terminal 150 is then formed in the opening 131 to connect the wiring layer 122 of the multilayer wiring structure 120 to the electrodes of the semiconductor chip.

[0018] The solder resist layer 140, like the solder resist layer 130, is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 140 is a layer made of an insulating photosensitive resin such as acrylic resin and polyimide resin, and is one of the insulating layers. The solder resist layer 140 may also be formed using an insulating non-photosensitive resin such as epoxy resin.

[0019] The solder resist layer 140 side of the wiring board 100 is the side that connects to external components and equipment. At the locations where external connection terminals that electrically connect to external components and equipment are formed, openings 141 are drilled in the solder resist layer 140, and the wiring layers 122 of the multilayer wiring structure 120 are exposed through the openings 141. External connection terminals, such as solder balls, are formed in the openings 141. If the solder resist layer 140 is formed using a photosensitive resin, the openings 141 can be formed by exposure and development. If the solder resist layer 140 is formed using a non-photosensitive resin, the openings 141 can be formed by laser processing.

[0020] Figure 2 is an enlarged view showing the structure of the wiring layer 122 in the multilayer wiring structure 120. In Figure 2, wiring patterns 210a and 210b formed on the upper surface of the insulating layer 121 are shown. Wiring pattern 210b is a wider wiring pattern than wiring pattern 210a.

[0021] The wiring pattern 210a has a seed layer 211a formed on the upper surface of the insulating layer 121, a base portion 212a connected to the upper surface of the seed layer 211a, and a top portion 213a connected above the base portion 212a. The height of the wiring pattern 210a from the upper surface of the insulating layer 121 to the upper surface of the top portion 213a is, for example, 15 μm and falls within the range of 10 to 30 μm.

[0022] In this diagram, the multilayer wiring structure 120 above the core substrate 110 is shown, with the base 212a connected to the upper surface of the seed layer 211a and the top 213a connected above the base 212a. However, in the multilayer wiring structure 120 below the core substrate 110, the base 212a is connected to the lower surface of the seed layer 211a, and the top 213a is connected below the base 212a. In other words, the part of the wiring pattern 210a closer to the core substrate 110 is the base 212a, and the part further away from the core substrate 110 is the top 213a. To put it another way, the base 212a rises from the surface of the insulating layer 121 via the seed layer 211a, and the top 213a is connected to one end of the base 212a opposite to the insulating layer 121.

[0023] Comparing the width A of the top portion 213a with the width B of the base portion 212a, width A is, for example, about 5 μm wider than width B. That is, the top portion 213a is connected to the base portion 212a via a step in the width direction. Specifically, for example, while the width B of the base portion 212a is 3 to 10 μm, the width A of the top portion 213a is 8 to 15 μm. Also, comparing the height C of the top portion 213a itself with the height D to the top portion 213a, height D is greater than height C. Specifically, for example, while the height C of the top portion 213a itself is 2 to 10 μm, the height D from the top surface of the insulating layer 121 to the top portion 213a is 8 to 20 μm. Of the height D from the top surface of the insulating layer 121 to the top portion 213a, the thickness of the seed layer 211a is, for example, 1 μm, and falls within the range of 0.5 to 1.5 μm.

[0024] On the other hand, the wiring pattern 210b has a seed layer 211b formed on the upper surface of the insulating layer 121, a base 212b connected to the upper surface of the seed layer 211b, and a top 213b connected above the base 212b. The height of the wiring pattern 210b from the upper surface of the insulating layer 121 to the upper surface of the top 213b is, for example, 15 μm, similar to the wiring pattern 210a, and falls within the range of 10 to 30 μm.

[0025] In this diagram, the multilayer wiring structure 120 above the core substrate 110 is shown, with the base 212b connected to the upper surface of the seed layer 211b and the top 213b connected above the base 212b. However, in the multilayer wiring structure 120 below the core substrate 110, the base 212b is connected to the lower surface of the seed layer 211b, and the top 213b is connected below the base 212b. In other words, the part of the wiring pattern 210b closer to the core substrate 110 is the base 212b, and the part further away from the core substrate 110 is the top 213b. To put it another way, the base 212b rises from the surface of the insulating layer 121 via the seed layer 211b, and the top 213b is connected to one end of the base 212b opposite to the insulating layer 121.

[0026] Comparing the width A' of the top portion 213b with the width B' of the base portion 212b, width A' is, for example, about 5 μm wider than width B'. That is, the top portion 213b is connected to the base portion 212b via a step in the width direction. Specifically, for example, while the width B' of the base portion 212b is 25 to 95 μm, the width A' of the top portion 213b is 30 to 100 μm. Also, comparing the height C' of the top portion 213b itself with the height D' to the top portion 213b, height D' is greater than height C'. Specifically, for example, while the height C' of the top portion 213b itself is 1 to 5 μm, the height D' from the top surface of the insulating layer 121 to the top portion 213b is 9 to 25 μm. Furthermore, of the height D' from the top surface to the top 213b of the insulating layer 121, the thickness of the seed layer 211b is, for example, 1 μm, similar to the seed layer 211a, and falls within the range of 0.5 to 1.5 μm.

[0027] Thus, both wiring patterns 210a and 210b have tops 213a and 213b that are wider than their bases 212a and 212b. Furthermore, in the wiring pattern 210b, which is wider overall, the height C' of the top 213b itself is lower than the height C of the top 213a of the wiring pattern 210a. Because the width of the tops 213a and 213b of the wiring patterns 210a and 210b is increased, the cross-sectional area and surface area of ​​the wiring patterns 210a and 210b are increased, which reduces resistance loss and suppresses the deterioration of electrical characteristics.

[0028] Furthermore, focusing on the surface roughness of the wiring patterns 210a and 210b, the arithmetic mean roughness Ra of the top and side surfaces of the apex portions 213a and 213b is, for example, 50 nm, which falls within the range of 40 to 60 nm, while the arithmetic mean roughness Ra of the side surfaces of the base portions 212a and 212b is, for example, 150 nm, which falls within the range of 100 to 200 nm. In other words, the top and side surfaces of the apex portions 213a and 213b are smoother than the side surfaces of the base portions 212a and 212b. In this way, by forming smooth areas with low roughness on the surface of the wiring patterns 210a and 210b, the resistance loss can be reduced when considering the skin effect on the wiring patterns 210a and 210b.

[0029] The cross-sectional shapes of the wiring patterns 210a and 210b can be of various shapes, as long as the width of the top portions 213a and 213b is wider than the width of the base portions 212a and 212b. For example, as shown in Figure 3(a), the width of the top portion 213 may be wider than the width of the base portion 212, and the sides of the base portion 212 and seed layer 211 may have a straight cross-sectional shape. Also, for example, as shown in Figure 3(b), the width of the top portion 213 may be wider than the width of the base portion 212, and the sides of the base portion 212 and seed layer 211 may have a curved cross-sectional shape. Furthermore, for example, as shown in Figure 3(c), the width of the top portion 213 may be wider than the width of the base portion 212, and the sides of the base portion 212 and seed layer 211 may have a tapered cross-sectional shape.

[0030] Next, a method for manufacturing a semiconductor device having the wiring board 100 configured as described above will be explained with reference to the flowchart in Figure 4, using a specific example.

[0031] First, a core substrate 110, which will serve as a support member for the wiring board 100, is formed (step S101). Specifically, as shown in Figure 5, for example, vias 112 penetrating the substrate 111 are formed on a base material 111, which is a plate-shaped insulator, and wiring layers 113 made of a metal such as copper are formed on both sides of the base material 111, for example, by copper foil or copper plating. The wiring layers 113 on both sides of the base material 111 are connected by vias 112 formed by metal plating such as copper, as needed. As the base material 111, for example, a reinforcing material such as glass woven fabric impregnated with an insulating resin such as epoxy resin can be used. In addition to glass woven fabric, glass nonwoven fabric, aramid woven fabric, or aramid nonwoven fabric can be used as the reinforcing material. In addition to epoxy resin, polyimide resin or cyanate resin can be used as the insulating resin.

[0032] Then, a multilayer wiring structure 120 is formed on the upper and lower surfaces of the core substrate 110 by a build-up method (step S102). Specifically, as shown in Figure 6, for example, an insulating layer 121 is formed on the upper and lower surfaces of the core substrate 110, and a wiring layer 122 is formed on the surface of the insulating layer 121. The insulating layer 121 is formed using an insulating resin such as epoxy resin or polyimide resin. The wiring layer 122 is formed by plating a metal such as copper.

[0033] The wiring layers 113 and 122 of the core substrate 110, or the wiring layers 122 of adjacent layers, are connected by vias 123 formed by metal plating, such as copper, as needed. Multiple insulating layers 121 and wiring layers 122 may be laminated on the upper and lower surfaces of the core substrate 110, respectively. The process for forming the wiring layers 122 that constitute the multilayer wiring structure 120 will be described in detail later.

[0034] Once the multilayer wiring structure 120 is formed, the wiring layers 122 on the surface of the multilayer wiring structure 120 are covered with solder resist layers 130 and 140 (step S103). Specifically, the wiring layers 122 on the surface of the multilayer wiring structure 120 laminated on the upper surface of the core substrate 110 are covered with solder resist layer 130, and the wiring layers 122 on the surface of the multilayer wiring structure 120 laminated on the lower surface of the core substrate 110 are covered with solder resist layer 140.

[0035] Then, as shown in Figure 7, for example, an opening 131 is drilled in the solder resist layer 130 on the side on which the semiconductor chip is mounted, at the location where connection terminals to the semiconductor chip are provided. The wiring layer 122 on the surface of the multilayer wiring structure 120 is exposed at the bottom of the opening 131. On the other hand, an opening 141 is drilled in the solder resist layer 140 on the side that is connected to external components or equipment, at the location where external connection terminals are provided. The wiring layer 122 on the surface of the multilayer wiring structure 120 is exposed at the bottom of the opening 141.

[0036] When photosensitive resins are used as solder resist layers 130 and 140, the openings 131 and 141 can be formed by exposure and development. When non-photosensitive resins are used as solder resist layers 130 and 140, the openings 131 and 141 can be formed by laser processing.

[0037] Then, connection terminals for connecting a semiconductor chip are formed in the opening 131 of the solder resist layer 130 (step S104). That is, as shown in Figure 8, for example, connection terminals 150 are formed in the opening 131 by, for example, copper plating. Once the connection terminals 150 are formed on the solder resist layer 130 side, external connection terminals are formed on the solder resist layer 140 side (step S105). Then, a semiconductor chip is mounted on the solder resist layer 130 side (step S106), and the connection terminals 150 and the electrodes of the semiconductor chip are connected. Specifically, as shown in Figure 9, for example, external connection terminals such as solder balls 170 are formed in the opening 141 of the solder resist layer 140. Also, a semiconductor chip 180 is mounted above the connection terminals 150, and the electrodes 181 of the semiconductor chip 180 are joined to the connection terminals 150 by, for example, solder.

[0038] The joint between the electrode 181 and the connection terminal 150 is then sealed with underfill resin 182, resulting in a semiconductor device on which the semiconductor chip 180 is mounted on the wiring board 100. Note that the order of the process of forming the external connection terminals and the process of mounting the semiconductor chip may be reversed. That is, after the semiconductor chip 180 is mounted on the wiring board 100, external connection terminals such as solder balls 170 may be formed in the openings 141 of the solder resist layer 140.

[0039] Next, the process of forming the wiring layer 122 that constitutes the multilayer wiring structure 120 will be explained in more detail with reference to the flow chart shown in Figure 10. Here, we will explain the case in which the wiring layer 122 is formed on the upper surface of the insulating layer 121 above the core substrate 110.

[0040] Once the insulating layer 121 is formed, a seed layer is formed on the insulating layer 121 (step S201). Specifically, as shown in Figure 11, for example, a seed layer 211 is formed on the upper surface of the insulating layer 121, for example by electroless copper plating. The thickness of the seed layer 211 is, for example, 1 μm and falls within the range of 0.5 to 1.5 μm.

[0041] Then, a dry film resist (DFR) is laminated on the seed layer 211 (step S202), and exposure and development are performed according to the position of the wiring pattern (step S203). As a result, as shown in Figure 12, for example, openings 220a and 220b are formed in the DFR 220 laminated on the seed layer 211 at the positions where the wiring pattern is formed. The thickness of the DFR 220 is, for example, about 30 to 40 μm. In this case, it is assumed that a relatively narrow opening 220a and a relatively wide opening 220b are formed in the DFR 220.

[0042] Then, by electrolytic copper plating using, for example, a copper sulfate plating solution (step S204), copper is deposited in the openings 220a and 220b, and a wiring pattern is formed. Specifically, as shown in Figure 13, for example, a relatively narrow wiring pattern 210a and a relatively wide wiring pattern 210b are formed in the opening of the DFR220.

[0043] Once the wiring patterns 210a and 210b are formed, the DFR 220 is peeled off (step S205). For peeling off the DFR 220, for example, caustic soda or an amine-based alkaline peeling solution is used. Peeling off the DFR 220 yields a wiring layer 122 in which the wiring patterns 210a and 210b are formed on the seed layer 211. At this stage, the seed layer 211 remains over the entire surface, and the wiring patterns 210a and 210b are short-circuited, so it is necessary to remove the seed layer 211 between the wiring patterns 210a and 210b.

[0044] Therefore, a protective film is formed to protect the upper surface and upper side of the wiring patterns 210a and 210b (step S206). Specifically, a protective film is formed by thermally transferring an insulating resin ink, such as epoxy resin, to the upper surface and upper side of the wiring patterns 210a and 210b. At this time, for example, as shown in Figure 14, ink 320 may be attached to the transfer surface of the heating plate 310, and the heating plate 310 may be lowered from above the wiring patterns 210 on the wiring board 100 and pressurized to thermally transfer the ink 320 to the upper surface and upper side of the wiring patterns 210.

[0045] If the transfer surface of the heating plate 310 is formed from an elastically deformable material such as rubber, the range of the sides to which the ink 320 is transferred is adjusted according to the width of the wiring pattern 210. Specifically, for example, as shown in Figure 15, if the transfer surface 310a of the heating plate 310 is formed from an elastically deformable material, the ink 320 penetrates to a relatively deep position around the sides of a narrow wiring pattern 210a, and the ink 320 is heat-transferred over a range from the upper edge of the sides of the wiring pattern 210a to a relatively deep position. On the other hand, around the sides of a wide wiring pattern 210b, the ink 320 only penetrates to a relatively shallow position, and the ink 320 is heat-transferred over a range from the upper edge of the sides of the wiring pattern 210b to a relatively shallow position.

[0046] As a result of the thermal transfer of the ink 320, a protective film made of ink 320 is formed on the upper surface and upper side of the wiring patterns 210a and 210b. That is, as shown in Figure 16 for example, a protective film 230a is formed covering the upper surface and upper side of the wiring pattern 210a, and a protective film 230b is formed covering the upper surface and upper side of the wiring pattern 210b. Here, since the wiring pattern 210a is narrower than the wiring pattern 210b, the protective film 230a of the wiring pattern 210a extends further downward than the protective film 230b of the wiring pattern 210b. That is, the area where the side of the wiring pattern 210a is covered by the protective film 230a extends further downward than the area where the side of the wiring pattern 210b is covered by the protective film 230b.

[0047] Once the protective films 230a and 230b are formed, the seed layer 211 is etched (step S207). Specifically, the seed layer 211 and wiring patterns 210a and 210b formed on the upper surface of the insulating layer 121 are immersed in an etching solution that selectively dissolves, for example, copper, and the seed layer 211 exposed between the wiring patterns 210a and 210b is removed. At this time, since the wiring patterns 210a and 210b are formed from the same metal (for example, copper) as the seed layer 211, the wiring patterns 210a and 210b are dissolved at the same time as the seed layer 211 is dissolved. That is, the lower sides of the wiring patterns 210a and 210b that are not protected by the protective films 230a and 230b are dissolved. As a result, the wiring patterns 210a and 210b are formed that are narrower in the lower part that is not protected by the protective films 230a and 230b than in the upper part that is protected by the protective films 230a and 230b. In other words, a step in the width direction is formed on the sides of the wiring patterns 210a and 210b.

[0048] Specifically, as shown in Figure 17, for example, wider top portions 213a and 213b are formed above the protective films 230a and 230b, while narrower base portions 212a and 212b are formed below the protective films 230a and 230b. A step in the width direction is formed between the top portions 213a and 213b and the base portions 212a and 212b. Furthermore, since the seed layer 211 is removed between the wiring patterns 210a and 210b, the seed layer 211a remains below the base portion 212a in wiring pattern 210a, and the seed layer 211b remains below the base portion 212b in wiring pattern 210b. As a result, wiring patterns 210a and 210b are formed with a shape in which the top portions 213a and 213b are wider than the base portions 212a and 212b.

[0049] Then, the protective films 230a and 230b are peeled off from the wiring patterns 210a and 210b (step S208). For peeling off the protective films 230a and 230b, a caustic soda or amine-based alkaline stripping solution is used, similar to the stripping of DFR220. As the protective films 230a and 230b are peeled off, the top and side surfaces of the top portions 213a and 213b are exposed.

[0050] The top and side surfaces of the vertices 213a and 213b are protected by the protective films 230a and 230b and are not etched, so they have a lower roughness and are smoother compared to the side surfaces of the bases 212a and 212b which are etched. Also, because the top and side surfaces of the vertices 213a and 213b are protected by the protective films 230a and 230b and are not etched, the width of the vertices 213a and 213b is constant from the top to the bottom. That is, the cross-sectional shape of the vertices 213a and 213b is a straight cross-sectional shape on the side. In contrast, the side surfaces of the bases 212a and 212b are etched, so the width of the bases 212a and 212b is not constant, and the cross-sectional shape of the bases 212a and 212b is a curved cross-sectional shape on the side or a tapered cross-sectional shape on the side.

[0051] As described above, according to this embodiment, a protective film is formed on the upper surface and upper side of the wiring pattern formed by plating on the seed layer, for example by thermal transfer of ink, and then the seed layer between the wiring patterns is removed by etching. As a result, the lower side of the wiring pattern that is not protected by the protective film is etched, while the upper surface and upper side of the wiring pattern that is protected by the protective film are not etched, resulting in a wiring pattern having a top that is wider than the base. As a result, the reduction in the cross-sectional area and surface area of ​​the wiring pattern is suppressed, reducing resistance loss and suppressing the deterioration of electrical characteristics.

[0052] In the above embodiment, protective films 230a and 230b are formed on the wiring patterns 210a and 210b by thermal transfer of ink 320. However, protective films that protect the wiring patterns 210a and 210b from etching can also be formed by other methods. For example, a dry film resist (DFR) can be laminated and pressed onto the upper surface of the wiring patterns 210a and 210b formed by electrolytic copper plating, so that the upper sides of the wiring patterns 210a and 210b are covered by the DFR. As the DFR, for example, a film-like photosensitive resin using epoxy resin can be used.

[0053] Specifically, as shown in Figure 18, for example, the upper parts of the wiring patterns 210a and 210b are embedded in the DFR240 which is laminated on the upper surface of the wiring patterns 210a and 210b. In this state, exposure and development of the DFR240 are performed so that the DFR240 remains in an area that is wider than the width of the wiring patterns 210a and 210b by a predetermined width. This makes it possible to form protective films 230a and 230b on the upper surface and upper sides of the wiring patterns 210a and 210b. The protective films 230a and 230b formed by the DFR240 are peeled off after the etching of the seed layer 211 is completed, similar to the protective films 230a and 230b formed by the ink 320.

[0054] In the above embodiment, the wiring layer 122 of the wiring board 100 having a core substrate 110 was described, but the above-described wiring patterns 210a and 210b can also be applied to wiring boards without a core substrate (coreless build-up wiring boards). [Explanation of Symbols]

[0055] 110 Core board 120 Multilayer wiring structure 121 Insulating layer 122 wiring layer 123 Beer 130, 140 solder resist layers 150 connection terminals 170 solder balls 180 semiconductor chips 210, 210a, 210b wiring patterns Seed layers 211, 211a, 211b 212, 212a, 212b base 213, 213a, 213b top 230a, 230b Protective film 240 DFR

Claims

1. an insulating layer; a wiring layer laminated on the insulating layer and having a wiring pattern; The wiring pattern is a base portion rising from the surface of the insulating layer; a top portion that is connected to one end of the base portion opposite to the insulating layer via a step in the width direction and that is wider than the base portion; A wiring board characterized by:

2. The top portion is The base has a side surface whose surface roughness is lower than that of the side surface of the base.

2. The wiring board according to claim 1.

3. The top portion is The end surface has a surface roughness lower than that of the side surface of the base.

2. The wiring board according to claim 1.

4. The wiring pattern is a seed layer formed on the surface of the insulating layer; The base portion is The seed layer is formed on the surface of the insulating layer.

2. The wiring board according to claim 1.

5. The base portion is 2. The wiring board according to claim 1, wherein the side surface is linear in cross section.

6. The base portion is 2. The wiring board according to claim 1, wherein the side surface of the cross section is curved.

7. The base portion is 2. The wiring board according to claim 1, wherein the side surface of the wiring board is tapered in cross section.

8. The wiring layer is a first wiring pattern and a second wiring pattern that is wider than the first wiring pattern; The second wiring pattern is The top of the first wiring pattern is lower in height than the top of the first wiring pattern.

2. The wiring board according to claim 1.

9. A wiring board; a semiconductor chip mounted on the wiring substrate; The wiring board is an insulating layer; a wiring layer laminated on the insulating layer and having a wiring pattern; The wiring pattern is a base portion rising from the surface of the insulating layer; a top portion that is connected to one end of the base portion opposite to the insulating layer via a step in the width direction and that is wider than the base portion; A semiconductor device characterized by:

10. forming a seed layer made of a metal material on the surface of the insulating layer; forming a wiring pattern made of the same metal as the seed layer on the surface of the seed layer; forming a protective film that covers an end face of the wiring pattern opposite to a face that contacts the seed layer and that covers a part of a side face adjacent to the end face; removing a portion of the seed layer exposed from the wiring pattern by etching; The protective film covering the end faces and part of the side faces of the wiring pattern is removed.

1. A method for manufacturing a wiring board, comprising the steps of:

11. The step of forming the protective film includes: An ink made of insulating resin is transferred onto the end face of the wiring pattern and a part of the side face adjacent to the end face.

11. The method for manufacturing a wiring board according to claim 10.

12. The step of forming the protective film includes: a dry film resist is laminated and pressed on an end surface of the wiring pattern opposite to the surface that contacts the seed layer; The dry film resist is left on the end face of the wiring pattern and a part of the side face adjacent to the end face.

11. The method for manufacturing a wiring board according to claim 10.

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