Element

Abstract

To realize efficient generation or detection of terahertz waves in an element of an antenna array structure.SOLUTION: An element comprises an antenna array in which a plurality of antennas are provided, each of the antennas including a first conductor layer, a semiconductor layer that is electrically connected to the first conductor layer and that generates or detects a terahertz wave, a second conductor layer that is electrically connected to the semiconductor layer and that faces the first conductor layer via the semiconductor layer, and a dielectric layer. The element includes a coupling line in which a substrate, the first conductor layer, the dielectric layer, and the second conductor layer are laminated in this order, and which is connected to the second conductor layer in order to mutually synchronize a plurality of antennas at a frequency of a terahertz wave, and a bias line for connecting a power supply that supplies a bias signal to the semiconductor layer and the second conductor layer. Wiring layers in which parts of the coupling line extending in the in-plane direction of the substrate are formed and a wiring layer in which a part of the bias line extending in the in-plane direction of the substrate is formed are different layers.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a device and a method for manufacturing the device. [Background technology]

[0002] As a current injection type light source that generates electromagnetic waves in the frequency range of 30 GHz to 30 THz (hereinafter referred to as "Terahertz waves"), oscillators that integrate a semiconductor element with electromagnetic gain for Terahertz waves and a resonator are known. Among these, oscillators that integrate a resonant tunneling diode (RTD) and an antenna are expected to operate at room temperature in the frequency range around 1 THz.

[0003] Patent Document 1 discloses a terahertz wave antenna array in which a plurality of oscillators, each of which integrates an RTD and an antenna, are arranged on the same substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-200065 A [Non-patent literature]

[0005] [Non-Patent Document 1] Jpn.J.Appl.Phys.,Vol.47,No.6(2008), pp.4375-4384 Summary of the Invention [Problem to be solved by the invention]

[0006] In the antenna array disclosed in Patent Document 1, an increase in antenna gain can be expected by increasing the number of antennas and synchronizing each antenna. On the other hand, a coupling line that couples adjacent antennas to synchronize each oscillator and a bias line that supplies a bias signal to each RTD are required. Therefore, as the number of antennas increases, the risk of electrical and mechanical interference between the coupling line and bias line of each antenna increases. Therefore, there is a limit to the number of antennas that can be arranged, and the effect of enhancing power and gain by the antenna array is limited, making it impossible to efficiently generate and detect terahertz waves.

[0007] In view of the above problems, an object of the present invention is to realize efficient generation or detection of terahertz waves in an element having an antenna array structure. [Means for solving the problem]

[0008] The first aspect of the present invention is A substrate; A first conductor layer laminated on the substrate; a semiconductor layer that generates or detects terahertz waves and is electrically connected to the first conductor layer; a second conductor layer electrically connected to the semiconductor layer and facing the first conductor layer with the semiconductor layer interposed therebetween; A dielectric layer; An antenna array including a plurality of antennas, the substrate, the first conductor layer, the dielectric layer, and the second conductor layer are laminated in this order; a coupling line connected to the second conductor layer in order to synchronize the plurality of antennas with each other at a frequency of the terahertz wave; a bias line connecting a power source for supplying a bias signal to the semiconductor layer and the second conductor layer; having a wiring layer in which a portion of the coupling line extending in the in-plane direction of the substrate is provided and a wiring layer in which a portion of the bias line extending in the in-plane direction of the substrate are provided are different layers; The device is characterized in that

[0009] A second aspect of the present invention is A substrate; A first conductor layer laminated on the substrate; a semiconductor layer that generates or detects terahertz waves and is electrically connected to the first conductor layer; a second conductor layer electrically connected to the semiconductor layer and facing the first conductor layer with the semiconductor layer interposed therebetween; A dielectric layer; An antenna array including a plurality of antennas, the substrate, the first conductor layer, the dielectric layer, and the second conductor layer are laminated in this order; a lead wire connected to the second conductor layer of the antenna and narrower than the width of the antenna; a bias line connected to a power supply that supplies a bias signal to the semiconductor layer; having the bias line is a common bias line disposed between adjacent antennas in the antenna array; a bias signal is supplied to the semiconductor layer of each antenna by connecting the common bias line and a lead line drawn from each of the adjacent antennas; The device is characterized in that

[0010] A third aspect of the present invention is A method for manufacturing an element having an antenna array in which a plurality of antennas are provided, comprising the steps of: forming a semiconductor layer on a substrate for generating or detecting terahertz waves; forming a first conductor layer on the substrate; forming a dielectric layer; forming a bias line connecting a power supply that supplies a bias signal to the semiconductor layer and a second conductor layer; forming the second conductor layer and the third conductor layer; a step of forming a coupling line connected to the second conductor layer, the coupling line having a structure in which the dielectric layer is sandwiched between the first conductor layer and the third conductor layer, for mutually synchronizing the plurality of antennas at a frequency of the terahertz wave; having a wiring layer in which a portion of the coupling line extending in the in-plane direction of the substrate is provided and a wiring layer in which a portion of the bias line extending in the in-plane direction of the substrate are provided are different layers; The present invention relates to a method for producing an element. Effect of the Invention

[0011] According to the present invention, efficient generation or detection of terahertz waves can be realized in an element having an antenna array structure. [Brief description of the drawings]

[0012] [Figure 1] 1 is a diagram showing a semiconductor element according to a first embodiment. [Diagram 2] 1 is a top view of a semiconductor element according to a first embodiment. [Diagram 3] 1 is a graph showing the relationship between dielectric layer thickness and conductor loss. [Figure 4] FIG. 4 is a diagram showing a semiconductor element according to a second embodiment. [Diagram 5] FIG. 11 is a diagram showing a semiconductor element according to a third embodiment. [Figure 6] FIG. 11 is a diagram showing a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 11 is a diagram showing a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 11 is a diagram showing a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 13 is a diagram showing an oscillation element according to a fifth embodiment. [Figure 10] FIG. 11 is a diagram illustrating an oscillation element according to a second embodiment. [Figure 11] FIG. 11 is a diagram illustrating an oscillation element according to a second embodiment. [Figure 12]13 is a graph showing the relationship between a third conductor layer and an oscillation frequency. [Figure 13] 13 is a graph showing the influence of an oscillation element on an oscillation output. [Figure 14] 13 is a graph showing the oscillation output of the oscillation element and a single antenna according to Example 2. [Figure 15] 10 is a flowchart showing a method for manufacturing an oscillation element according to a second embodiment. [Figure 16] 6A to 6C are diagrams illustrating a manufacturing process of an oscillation element according to Example 2. [Figure 17] 11 is a diagram showing an oscillation element according to Examples 3 and 4. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] <Embodiment 1> The semiconductor device 100 according to this embodiment will be described with reference to FIGS. 1(a) to 2(c). The semiconductor device 100 has a frequency f THz 1 is a semiconductor element that oscillates or detects terahertz waves. FIG. 1(a) is a perspective view showing the appearance of the semiconductor element 100, FIG. 1(b) is an A-A' cross-sectional view of the semiconductor element 100, and FIG. 1(c) is a B-B' cross-sectional view of the semiconductor element 100. FIG. 2 is a top view of the semiconductor element 100 as seen from the stacking direction (upper part) of the semiconductor element. In the following description, an example in which the semiconductor element 100 is used as an oscillator will be described. Here, terahertz waves are electromagnetic waves in a frequency range of 30 GHz or more and 30 THz or less. In addition, the length of each component in the stacking direction of each component, such as the substrate 113, the dielectric layer 104, and the semiconductor layer 115, of the semiconductor element 100 is called the "thickness" or "height". In addition, the direction in which the dielectric layer 104 and the semiconductor layer 115 exist with respect to the substrate 113 is called the "upper".

[0014] The semiconductor element 100 is provided with a plurality of antennas. In this embodiment, the semiconductor element 100 includes an antenna array in which nine antennas 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, and 100i are arranged in a 3×3 matrix. The antenna 100a serves both as a resonator that resonates with terahertz waves and a radiator that transmits or receives terahertz waves. The antenna 100a includes a semiconductor layer 115a for oscillating or detecting electromagnetic waves of terahertz waves. The other eight antennas 100b to 100i have the same configuration as the antenna 100a. In addition, each antenna can be arranged at a pitch equal to or less than the wavelength of the terahertz waves to be detected or generated, or at an integer multiple of the wavelength.

[0015] The configuration of the antenna 100a will be described in detail below, and detailed description of components of the other antennas 100b to 100i similar to those of the antenna 100a will be omitted. In addition, in the description, the reference numbers of the components of each of the antennas 100a to 100i are followed by alphabets corresponding to each antenna. For example, the components of the second conductor layer 103 that are included in the antenna 100a are referred to as the second conductor layer 103a.

[0016] [About antennas] The antenna 100a is made up of two conductor layers, a first conductor layer 106 and a second conductor layer 103a. The dielectric layer 104 is sandwiched between the dielectric layers 102 and 104a and 104b. Such a configuration is called a microstrip antenna using a microstrip line of a finite length. In this embodiment, an example using a patch antenna, which is a microstrip resonator, will be described.

[0017] The second conductor layer 103a is a patch conductor of the antenna 100a, which is disposed so as to face the first conductor layer 106 via the dielectric layer 104 (semiconductor layer 115a). The second conductor layer 103a is electrically connected to the semiconductor layer 115a. The antenna 100a has a width of λ in the A-A' direction (resonance direction) of the second conductor layer 103a. THzThe first conductor layer 106 is a ground conductor that is electrically grounded. THz is the effective wavelength in the dielectric layer 104 of the terahertz wave resonating in the antenna 100a, and the wavelength of the terahertz wave in a vacuum is λ0, and the effective relative dielectric constant of the dielectric layer 104 is ε r Then, λ THz =λ0×ε r -1 / 2 It is expressed as:

[0018] The semiconductor layer 115a includes an active layer 101a made of a semiconductor layer having electromagnetic wave gain or nonlinearity for terahertz waves. A typical semiconductor layer having electromagnetic wave gain in the frequency band of terahertz waves is a resonant tunneling diode (RTD). In this embodiment, an example in which an RTD is used as the active layer 101a will be described. Hereinafter, the active layer 101a will be referred to as an RTD 101a.

[0019] The RTD 101a has a resonant tunneling structure layer including a plurality of tunnel barrier layers, a quantum well layer is provided between the plurality of tunnel barriers, and has a multiple quantum well structure that generates terahertz waves by intersubband transition of carriers. The RTD 101a has electromagnetic wave gain in the frequency region of terahertz waves based on the photon-assisted tunneling phenomenon in the negative differential resistance region of the current-voltage characteristics, and self-oscillates in the negative differential resistance region.

[0020] The antenna 100a is an active antenna in which a semiconductor layer 115a including an RTD 101a and a patch antenna are integrated. The frequency f of the terahertz wave oscillated from the antenna 100a alone is THz is determined by the resonant frequency of the total parallel resonant circuit that combines the patch antenna and the reactance of the semiconductor layer 115a. Specifically, from the equivalent circuit of the oscillator described in Non-Patent Document 1, the admittance (Y RTD and Y aa), the frequency that satisfies the amplitude condition of equation (1) and the phase condition of equation (2) is the oscillation frequency f THz is determined as: Re[Y RTD ]+Re[Y aa ]≦0 (1) Im[Y RTD ]+Im[Y aa ]=0 (2)

[0021] Here, Y RTD is the admittance of the semiconductor layer 115a, where Re is the real part and Im is the imaginary part. Since the semiconductor layer 115a includes the RTD 101a, which is a negative resistance element, as an active layer, Re[Y RTD ] has a negative value. Also, Y aa 1 shows the admittance of the entire structure of patch antenna 100a as seen from semiconductor layer 115a.

[0022] The active layer 101a may be a quantum cascade laser (QCL) structure having a multilayer structure of several hundreds to several thousands of semiconductor layers. In this case, the semiconductor layer 115a is a semiconductor layer including a QCL structure. The active layer 101a may be a negative resistance element such as a Gunn diode or an IMPATT diode, which are often used in the millimeter wave band. The active layer 101a may be a high-frequency element such as a transistor terminated at one terminal. As the transistor, a heterojunction bipolar transistor (HBT), a compound semiconductor layer-based FET, a high electron mobility transistor (HEMT), or the like is preferable. The active layer 101a may be a Josephson element using a superconductor layer. A negative differential resistance of the resistor may be used.

[0023] The dielectric layer 104 is composed of two layers, a first dielectric layer 1041 and a second dielectric layer 1042. In a microstrip type resonator such as a patch antenna, the conductor loss is reduced and the radiation efficiency is improved by making the dielectric layer 104 thick. The dielectric layer 104 is required to be able to form a thick film (typically 3 μm or more), to have low loss and low dielectric constant in the terahertz band, and to have good micro-machining properties (flattening and etching). Here, the thicker the dielectric layer 104 is, the higher the radiation efficiency is, but if it is too thick, multi-mode resonance may occur. For this reason, it is preferable to design the thickness of the dielectric layer 104 within a range of 1 / 10 or less of the oscillation wavelength as the upper limit. On the other hand, since the miniaturization and high current density of the diode are required for the high frequency and high output of the oscillator, the dielectric layer 104 is also required to suppress leakage current and countermeasures against migration as an insulating structure of the diode. In this embodiment, in order to achieve the above two objectives, the first dielectric layer 1041 and the second dielectric layer 1042 are made of two different materials.

[0024] The first dielectric layer 1041 is made of, for example, BCB (benzocyclobutene, manufactured by Dow Chemical Company, ε r1 =2), polytetrafluoroethylene, polyimide, and other organic dielectric materials are preferably used. r1 is the relative dielectric constant of the first dielectric layer 1041. In addition, it is possible to form a relatively thick film, and an inorganic dielectric material such as a TEOS oxide film or spin-on glass having a low dielectric constant may be used for the first dielectric layer 1041.

[0025] The second dielectric layer 1042 is required to have insulating properties (the ability to act as an insulator and high resistance body that does not conduct electricity against DC voltage), barrier properties (the ability to prevent the diffusion of metal materials used in the electrodes), and processability (the ability to be processed with submicron precision). Specific examples of materials that satisfy these requirements include silicon oxide (ε r2 =4), silicon nitride (ε r2 =7), inorganic insulating materials such as aluminum oxide and aluminum nitride are preferably used. r2 is the relative dielectric constant of the second dielectric layer 1042.

[0026] In this embodiment, when the dielectric layer 104 has a two-layer structure, the relative dielectric constant of the dielectric layer 104 is ε r is the thickness and relative dielectric constant ε of the first dielectric layer 1041. r1 and the thickness and relative dielectric constant ε of the second dielectric layer 1042 r2 From the viewpoint of impedance matching between the antenna and space, it is preferable that the difference in dielectric constant between the antenna and air is small. Therefore, the first dielectric layer 1041 is made of a material different from that of the second dielectric layer 1042 and has a low dielectric constant (ε r1 <ε r2 In the semiconductor device 100, the dielectric layer 104 does not need to have a two-layer structure, and may have a structure made of only one layer of the above-mentioned materials.

[0027] The semiconductor layer 115a is disposed on the first conductor layer 106 formed on the substrate 113. The semiconductor layer 115a and the first conductor layer 106 are electrically connected. In order to reduce ohmic loss, the semiconductor layer 115a and the first conductor layer 106 are preferably connected with low resistance. An electrode 116a is disposed on the side of the semiconductor layer 115a opposite to the side on which the first conductor layer 106 is disposed, and the electrode 116a and the semiconductor layer 115a are electrically connected. The semiconductor layer 115a and the electrode 116a are embedded in the second dielectric layer 1042, and are surrounded by the second dielectric layer 1042.

[0028] If the electrode 116a is a conductor that is ohmically connected to the semiconductor layer 115a, it is suitable for reducing ohmic loss and RC delay due to series resistance. When the electrode 116a is used as an ohmic electrode, for example, Ti / Pd / Au, Ti / Pt / Au, AuGe / Ni / Au, TiW, Mo, ErAs, etc. are preferably used as the material. If the region of the semiconductor layer 115a in contact with the electrode 116a is a semiconductor doped with a high concentration of impurities, the contact resistance will be lower, making it suitable for higher output and higher frequencies. Since the absolute value of the negative resistance, which indicates the magnitude of the gain of the RTD 101a used in the terahertz wave band, is approximately on the order of 1 to 100 Ω, it is preferable to suppress the loss of the electromagnetic wave to 1% or less of that. Therefore, the contact resistance in the ohmic electrode should be suppressed to 1 Ω or less as a guideline. Furthermore, in order to operate in the terahertz wave band, the width of the semiconductor layer 115a (≈ electrode 116a) is typically about 0.1 to 5 μm. For this reason, the contact resistance should be set to a resistivity of 10 Ω·μm 2 It is preferable to suppress it to a range of 0.001 to several Ω or less.

[0029] Also, a configuration using a metal that has a Schottky contact rather than an ohmic contact with the electrode 116a is conceivable. In this case, the contact interface between the electrode 116a and the semiconductor layer 115a exhibits rectification, and the antenna 100a is a suitable configuration for a terahertz wave detector. In the following, in this embodiment, a configuration using an ohmic electrode as the electrode 116a will be described.

[0030] Inside the antenna 100a disposed above and below the RTD 101a, as shown in FIG. 1(b), a substrate 113, a first conductor layer 106, a semiconductor layer 115a, an electrode 116a, a conductor 117a, and a second conductor layer 103a are laminated in this order.

[0031] The conductor 117a is formed inside the dielectric layer 104, and the second conductor layer 103a and the electrode 116a are electrically connected via the conductor 117a. If the width of the conductor 117a is too large, the resonance characteristics of the patch antenna 100a will deteriorate and the radiation efficiency will decrease due to an increase in parasitic capacitance. For this reason, the width of the conductor 117a is preferably a size that does not interfere with the resonant electric field, and typically, the width of the conductor 117a is set to a size that is large enough to minimize interference with the resonant electric field and the oscillation frequency f that exists in the antenna 100a. THzThe width of the conductor 117a is preferably 1 / 10 or less of the effective wavelength λ of the terahertz wave. The width of the conductor 117a may be small enough not to increase the series resistance, and can be reduced to about twice the skin depth as a guideline. In order to reduce the series resistance to a level not exceeding 1 Ω, the width of the conductor 117a is typically in the range of 0.1 μm to 20 μm.

[0032] The second conductor layer 103a is electrically connected to the line 108a1 and the line 108a2 via the conductor 107a1 and the conductor 107a2. The lines 108a1 and 108a2 are also drawn out lines electrically connected to the bias circuit 120 via the bias line 111, which is a common wiring formed in the chip. The line 108 is drawn out from each of the antennas. The bias circuit 120 is a power source for supplying a bias signal to the RTD 101a of the antenna 100a. Therefore, the bias line 111 is connected to the line 108, which is a drawn out line drawn out from each of the adjacent antennas, so that a bias signal is supplied to the semiconductor layer 115 of each antenna. Since the bias line 111 is common, the operating voltage variation between the antennas can be reduced, and therefore the synchronization is stabilized even if the number of arrays is increased. In addition, it is possible to make the structure around the antennas symmetrical, and the radiation pattern does not collapse.

[0033] Conductors 107a1 and 107a2 are connection parts for electrically and mechanically connecting lines 108a1 and 108a2 to second conductor layer 103a. A structure that electrically connects upper and lower layers, such as conductor 117a and conductors 107a1 and 107a2, is called a via. In addition to serving as members that constitute the patch antenna, first conductor layer 106 and second conductor layer 103a also serve as electrodes for injecting current into RTD 101a by being connected to these vias. Conductor 117a and conductors 107a1 and 107a2, which are vias, have a resistivity of 1×10 -6 Materials with a resistance of Ω·m or less are preferable. Specifically, metals and metal compounds such as Ag, Au, Cu, W, Ni, Cr, Ti, Al, AuIn alloys, and TiN are preferably used as materials.

[0034] The width of conductors 107a1 and 107a2 is smaller than the width of second conductor layer 103a. The width shown here is the width in the electromagnetic wave resonance direction (=A-A' direction) in antenna 100a. Also, the width of a portion (connection portion) of line 108a1 (line 108a2) connected to conductor 107a1 (conductor 107a2) is smaller (thinner) than the width of second conductor layer 103a (antenna 100a). Also, these widths are set according to the oscillation frequency f THz The effective wavelength λ of the terahertz wave is preferably 1 / 10 or less (λ / 10 or less). This is because, in order to improve radiation efficiency, it is preferable that the conductors 107a1 and 107a2 and the lines 108a1 and 108a2 are arranged in dimensions and positions that do not interfere with the resonant electric field in the antenna 100a.

[0035] The positions of the conductors 107a1 and 107a2 are determined based on the oscillation frequency f THz In this case, the conductors 107a1 and 107a2 and the lines 108a1 and 108a2 are preferably arranged at nodes of the electric field of the terahertz wave having an oscillation frequency f THz In other words, the lines 108a1 and 108a2 are configured such that the impedance is sufficiently higher than the absolute value of the negative differential resistance of the RTD 101a in a frequency band around the oscillation frequency f THz In this case, the other antennas and the antenna 100a are connected to each other so that the RTD has high impedance at frequency f THz In this case, the path via the bias line 111 is isolated. As a result, the oscillation frequency f induced in each antenna is THz The current of the antenna 100a does not affect the adjacent antennas. THz The other antennas 100b to 100i in the semiconductor device 100 are similar to the antenna 100a.

[0036] The bias line 111 is a common bias wiring (wiring layer) for the antennas 100a to 100i. The antennas 100a to 100i are connected to the bias line 111 via the lines 108a1, 108a2 to lines 108i1, 108i2 connected to the antennas 100a to 100i, respectively. Of the bias line 111, the lines in the A-A' direction (resonance direction) are shown as 111x1 to 111x4, and the lines in the B-B' direction are shown as 111y1 to 111y4 in FIG. 1(b) and FIG. 1(c). In this description, the bias common wiring of the semiconductor element 100 is generally referred to as the bias line 111.

[0037] [[About the bias circuit]] The bias circuit 120 is a power supply arranged outside the chip to supply a bias signal to the RTDs 101a to 101i. The bias circuit 120 includes shunt resistors 121 connected in parallel to each of the RTDs 101a to 101i, wiring 122, a power supply 123, and a capacitance 124 connected in parallel to the shunt resistor 121.

[0038] The wiring 122 is shown as an inductance in FIG. 1(a) because it necessarily has a parasitic inductance component. The power supply 123 supplies a current required to drive each of the RTDs 101a to 101i and adjusts the bias voltage applied to each of the RTDs 101a to 101i. The bias voltage is typically selected from the voltage in the negative differential resistance region of the RTD used for the RTDs 101a to 101i. The bias circuit 120 is connected to a bias line 111, which is an internal chip wiring. In the case of the antenna 100a, the bias voltage from the bias circuit 120 is supplied to the RTD 101a in the antenna 100a via the line 108a1 and the line 108a2. The same applies to the other antennas 100b to 100i.

[0039] The shunt resistor 121 and the capacitor 124 have a role of suppressing parasitic oscillation of a relatively low-frequency resonant frequency (typically a frequency band from DC (Direct Current) to 10 GHz) caused by the bias circuit 120. A value equal to or slightly smaller than the absolute value of the combined negative differential resistance of the RTDs 101a to 101i connected in parallel is selected. The capacitance 124 is also set to be equal to or slightly lower than the absolute value of the combined negative differential resistance of the RTDs 101a to 101i connected in parallel, as with the shunt resistor 121. That is, the bias circuit 120 is set to have a lower impedance than the absolute value of the combined negative resistance corresponding to the gain in the frequency band from DC to 10 GHz due to these shunt structures. In general, the capacitance 124 is preferably larger within the above-mentioned range, and in the example of this embodiment, the capacitance is about several tens of pF. The capacitance 124 is a decoupling capacitance, and may be, for example, a MIM (Metal-insulator-Metal) structure in which the antenna 100a and the substrate are shared.

[0040] [About the antenna array] The semiconductor device 100 is an antenna array having nine antennas 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, and 100i arranged in a 3×3 matrix. Each of the antennas 100a to 100i transmits a frequency f THz Adjacent antennas are coupled to each other by a coupling line 109, and the terahertz wave oscillation frequency f THz They are mutually injection locked (mutually synchronized) at

[0041] Here, mutual injection locking means that a plurality of self-excited oscillators oscillate in synchronization with each other through mutual interaction. For example, antennas 100a and 100b are mutually coupled by a coupling line 109ab, and antennas 100a and 100d are mutually coupled by a coupling line 109ad. The same applies to other adjacent antennas. Note that "mutually coupled" refers to a phenomenon in which a current induced in one antenna acts on another adjacent antenna to change the transmission and reception characteristics of the other antennas. By synchronizing mutually coupled antennas in the same phase or in opposite phase, the mutual injection locking phenomenon causes mutual strengthening or weakening of the electromagnetic fields between the antennas. This makes it possible to adjust the increase or decrease of the antenna gain. Note that in this description, the entire coupling line that couples the antennas of the semiconductor element 100 is written as a coupling line 109. Also, the coupling lines that couple each antenna that constitute the coupling line 109 are written using the alphabet corresponding to each antenna. For example, the coupling line that couples the antenna 100a and the antenna 100b is represented as a coupling line 109ab.

[0042] The oscillation conditions of the semiconductor device 100 are determined by the conditions of mutual injection locking in a configuration in which two or more individual RTD oscillators are coupled, as disclosed in J. Appl. Phys., Vol. 103, 124514 (2008) (Non-Patent Document 2). Specifically, consider the oscillation conditions of an antenna array in which an antenna 100a and an antenna 100b are coupled by a coupling line 109ab. At this time, two oscillation modes occur: positive-phase mutual injection locking and anti-phase mutual injection locking. The oscillation conditions of the positive-phase mutual injection locking oscillation mode (even mode) are expressed by equations (4) and (5), and the oscillation conditions of the anti-phase mutual injection locking oscillation mode (odd mode) are expressed by equations (6) and (7). Positive phase (even mode): Frequency f = f even Y even =Yaa+Yab+Y RTD Re(Y even )≦0 (4) Im(Y even )=0 (5) Out of phase (odd mode): Frequency f = f odd Y odd =Yaa+Yab+Y RTD Re(Y odd )≦0 (6) Im(Y odd )=0 (7)

[0043] Here, Y ab is the mutual admittance between antenna 100a and antenna 100b. Y ab is proportional to the coupling constant that represents the strength of coupling between antennas, and ideally, -Y ab It is preferable that the real part of f is large and the imaginary part is zero. The semiconductor device 100 of this embodiment is coupled under the condition of mutual injection locking in positive phase, and the oscillation frequency f THz ≒f even Similarly, the other antennas are coupled to each other via coupling lines 109 so as to satisfy the above-mentioned positive phase mutual injection locking condition.

[0044] The coupling line 109 is a microstrip line in which the dielectric layer 104 is sandwiched between the third conductor layer 110 and the first conductor layer 106. For example, as shown in FIG. 1(b), the coupling line 109ab has a structure in which the dielectric layer 104 is sandwiched between the third conductor layer 110ab and the first conductor layer 106. Similarly, the coupling line 109bc sandwiches the dielectric layer 104 between the third conductor layer 110bc, the coupling line 109ad sandwiches the dielectric layer 104 between the third conductor layer 110ad, and the coupling line 109cf sandwiches the dielectric layer 104 between the first conductor layer 106 and the third conductor layer 110cf.

[0045] In the semiconductor device 100, the antennas are coupled to each other by DC coupling. The third conductor layer 110ab, which is an upper conductor layer of the coupling line 109ab that couples the antenna 100a and the antenna 100b, is directly connected to the second conductor layers 103a and 103b. In the semiconductor device 100, the third conductor layer 110ab and the second conductor layers 103a and 103b are formed in the same layer. Similarly, the third conductor layer 110ae, which is an upper conductor layer of the coupling line 109ae that couples the antenna 100a and the antenna 100e, is directly connected to the second conductor layers 103a and 103e. The third conductor layer 110ae and the second conductor layers 103a and 103e are formed in the same layer.

[0046] With this structure, the antennas 100b and 100e are mutually coupled to the antenna 100a, and the terahertz wave frequency f THz In an antenna array synchronized by DC coupling, adjacent antennas can be synchronized with strong coupling, making it easier to achieve synchronous operation by pulling in, and is tolerant to variations in frequency and phase of each antenna.

[0047] In the semiconductor element 100, the coupling line 109 and the bias line 111 are arranged on different layers. For example, as shown in FIG. 1B, the third conductor layer 110ab constituting the coupling line 109ab that couples the antenna 100a and the antenna 100b and the fourth conductor layer 111x2 constituting the bias line 111 are arranged on different layers. Also, the third conductor layer 110ad constituting the coupling line 109ad that couples the antenna 100a and the antenna 100d and the fourth conductor layer 111x1 constituting the bias line 111 are arranged on different layers. In other words, the wiring layer in which the coupling line 109 is provided with a portion extending in the in-plane direction of the substrate 113 (direction perpendicular to the stacking direction) and the wiring layer in which the bias line 111 is provided with a portion extending in the in-plane direction of the substrate 113 are arranged on different layers. Here, the wiring layer in which the coupling line 109 has a portion extending in the in-plane direction is the third conductor layer 110 and the first conductor layer 106. On the other hand, the wiring layer in which the bias line 111 has a portion extending in the in-plane direction is the fourth conductor layer 111. In this embodiment, all of the third conductor layers 110 and the first conductor layers 106 in all of the antennas are disposed in a layer different from any of the fourth conductor layers 111.

[0048] Thus, at high frequencies (f THz The coupling line 109 that transmits the high frequency (DC to several tens of GHz) and the bias line 111 that transmits the low frequency (DC to several tens of GHz) are arranged on different layers. This allows the layout of the width, length, routing, etc. of the transmission line to be freely set within each layer. It is possible.

[0049] In the semiconductor element 100, the substrate 113, the first conductor layer 106, and the second conductor layer 103a are laminated in this order from the substrate 113 side. At least one of the coupling line 109 and the bias line 111 is disposed in a layer between the first conductor layer 106 and the second conductor layer 103. For example, as shown in FIG. 1(b), the fourth conductor layers 111x2 and 111x1 are disposed in a layer between the first conductor layer 106 and the second conductor layer 103.

[0050] 2, the coupling line 109 and the bias line 111 cross each other when viewed from above (in a plan view). For example, as shown in FIG. 1(b) and FIG. 1(c), the third conductor layer 110ab and the fourth conductor layer 111x2 cross each other, and the third conductor layer 110ad and the fourth conductor layer 111y3 cross each other in a plan view.

[0051] In this way, by laying the lines so that the coupling line 109 and the bias line 111 cross each other, a more layout-saving configuration can be realized. Therefore, by adopting such a configuration, the number of antennas to be arranged can be increased even in an antenna array in which antennas are arranged in a matrix of m×n (m≧2, n≧2). According to this embodiment, even if the number of antennas is increased, physical interference between the coupling line (coupling line 109) for synchronizing the antennas and the feed line (bias line 111) for supplying bias to each RTD 101 can be suppressed. Therefore, in the semiconductor element 100, the upper limit of the number of antennas that can be arranged is suppressed, and a significant improvement in directivity and front intensity can be expected with an increase in the number of arrays.

[0052] Also, by arranging at least one of the coupling line 109 and the bias line 111 in a layer between two conductor layers that constitute the antenna, a layout-saving configuration can be realized. Specifically, the coupling line 109 and / or the bias line 111 are embedded in a surplus area other than the antennas in the dielectric layer 104 that constitutes the antennas 100a to 100i. This allows multiple transmission lines to be arranged in a relatively small space between adjacent antennas that are arranged at a pitch of about the wavelength, so that an increase in the number of lines that accompanies an increase in the number of antennas can be adequately accommodated.

[0053] In the terahertz band, resistance increases due to the skin effect, so conductor loss associated with high-frequency transmission between antennas cannot be ignored. Figure 3 shows the results of an analysis of the correlation between the dielectric layer thickness of a microstrip line with a configuration similar to that of this embodiment and the conductor loss at 0.5 THz. The microstrip line used in the analysis has an upper conductor layer (material: Au, 1 μm thick, conductivity: 2×10 7 S / m) and a ground conductor (material: Au, 1 μm thick, conductivity: 2×10 7 S / m) and dielectric (SiO2, ε r = 4, tan δ = 0). HFSS, a finite element method high frequency electromagnetic field solver made by ANSYS, was used to analyze the conductor loss.

[0054] As the current density between the conductor layers increases, the conductor loss (dB / mm) per unit length increases. Furthermore, as shown in FIG. 3, in the case of a microstrip line, the conductor loss (dB / mm) per unit length is inversely proportional to the square of the dielectric thickness. Therefore, in order to increase the radiation efficiency of the antenna array, it is preferable to reduce the conductor loss by thickening the dielectric constituting not only the antenna but also the coupling line 109. In contrast, in the semiconductor device 100 according to this embodiment, a bias line 111 is provided on the first conductor layer 106 side of the first dielectric layer 1041 to provide a bias line 111 at a frequency f THz In this configuration, the third conductor layer 110 through which high frequency waves of the terahertz band are transmitted is provided on the dielectric layer 104. With this configuration, it is possible to suppress the decrease in radiation efficiency of the antenna array due to conductor loss in the terahertz band. In this case, the antenna 1 In FIG. 00a, the substrate 113, the first conductor layer 106, the fourth conductor layers 111x1 and 111x2, the second conductor layer 103a, and the third conductor layers 110ad and 110ab are laminated in this order from the substrate 113 side. The relationship between the coupling line 109 and the bias line 111 that couple the other antennas is similar.

[0055] Thus, the semiconductor element 100 according to this embodiment has a configuration with good radiation efficiency. From the viewpoint of the conductor loss shown in FIG. 3, the thickness of the dielectric constituting the coupling line 109 is preferably 1 μm or more, and more preferably, if the dielectric thickness is set to 2 μm or more, the loss due to the conductor loss in the terahertz band is suppressed to about 20%. Similarly, from the viewpoint of the conductor loss, it is preferable that the gap in the thickness direction between the third conductor layer 110 constituting the coupling line 109 and the first conductor layer 106 is wider. Also, it is preferable that the gap in the thickness direction between the third conductor layer 110 constituting the coupling line 109 and the fourth conductor layer 111 constituting the bias line 111 is wider. For the bias line 111, the dielectric is set to 2 μm or less, preferably 1 μm or less, so that it can function as a low impedance line up to about the gigahertz band. Even if the dielectric is set to a thickness of 2 μm or more, it can be made to function as a low impedance line by connecting a shunt component to the bias line as in the semiconductor element 300.

[0056] In addition, in the semiconductor device 100 according to this embodiment, adjacent antennas are fed by a common bias line 111 arranged between the antennas. For example, as shown in FIG. 1(c), the antenna 100a is connected to the bias line 111y3 via the conductor 107a2 and the line 108a2, and the antenna 100d is connected to the bias line 111y3 via the conductor 107d1 and the line 108d1. Similarly, since the antennas 100a and 100b are adjacent to each other, the bias signal is fed by being connected to the common bias line 111x2 arranged between the two antennas. The same is true for the bias lines 111 of the other antennas 100b to 100i. In this way, by sharing the bias line 111, which is the wiring in the chip, between each antenna, it becomes possible to drive the antennas on the same channel, and the driving method can be simplified. In addition, the number of wirings is reduced and each wiring can be made thicker, so that the increase in wiring resistance due to the increase in the number of arrays and the associated operating point shift between the antennas are suppressed. This suppresses frequency and phase shifts between the antennas that occur when the number of arrays is increased, making it easier to achieve a synchronization effect through the arrays.

[0057] It should be noted that sharing the bias line 111 is not an essential configuration. For example, a configuration in which a plurality of bias lines 111 are provided for each antenna and power is fed individually by multi-layering or miniaturization may be used. In this case, isolation between the antennas via the bias line 111 is strengthened, so that the risk of low-frequency parasitic oscillation can be reduced. In addition, in the semiconductor device 100, the lines 108a1, 108a2 to the lines 108i1, 108i2 and the bias line 111 are connected to each other at an oscillation frequency f THz It is preferable that the impedance is lower than the negative resistance of the RTDs 101a to 101i in a lower frequency band. More preferably, the impedance is equal to or slightly smaller than the absolute value of the combined negative differential resistance of the RTDs 101a to 101i connected in parallel. This makes it possible to suppress multi-mode oscillation at low frequencies.

[0058] In this manner, according to this embodiment, the loss of the electromagnetic wave can be reduced more than ever before, and the terahertz wave can be generated or detected more efficiently.

[0059] [Example 1] A specific configuration of the semiconductor element 100 that oscillates terahertz waves according to the first embodiment will be described as Example 1 with reference to FIG. 1. The semiconductor element 100 is a semiconductor device that is capable of single-mode oscillation in the frequency band of 0.45 to 0.50 THz. RTDs 101a to 101 The RTD i is composed of a multiple quantum well structure of InGaAs / AlAs lattice-matched on an InP substrate 113, and in this embodiment, an RTD with a double barrier structure is used. The semiconductor layer heterostructure of the RTD is the structure disclosed in J Infrared Milli Terahz Waves (2014) 35:425-431 (Non-Patent Document 3).

[0060] The measured current-voltage characteristics of RTD101a to 101i are a peak current density of 9mA / μm 2 and the differential negative conductance per unit area is 10mS / μm 2 In the antenna 100a, a mesa structure is formed that is composed of a semiconductor layer 115a including the RTD 101a and a third electrode 116a that is an ohmic electrode. In this embodiment, the mesa structure is circular and has a diameter of 2 μm. In this case, the magnitude of the negative differential resistance of the RTD 101a is approximately −30 Ω per diode. In this case, the negative differential conductance (G RTD ) is estimated to be about 30mS, and the diode capacitance of the RTD101a (C RTD ) is estimated to be about 10 fF.

[0061] The antenna 100a is a patch antenna having a structure in which a dielectric layer 104 is sandwiched between a second conductor layer 103a, which is a patch conductor, and a first conductor layer 106, which is a ground conductor. A semiconductor layer 115a including an RTD 101a is integrated inside the antenna 100a. The antenna 100a is a square patch antenna in which the second conductor layer 103a has a side length of 150 μm, and the resonator length (L) of the antenna is 150 μm.

[0062] The second conductor layer 103a, which is a patch conductor, and the first conductor layer 106, which is a ground conductor, are made of a metal layer mainly made of a thin Au film having a low resistivity. The second conductor layer 103a is made of a metal containing Ti / Au (=5 / 300 nm). A dielectric layer 104 is disposed between the second conductor layer 103a and the first conductor layer 106. The dielectric layer 104 is made of a 5 μm thick BCB (benzocyclobutene, manufactured by Dow Chemical Company, ε r1 A first dielectric layer 1041 made of SiO2 (plasma CVD, ε r2 = 4) and the second dielectric layer 1042.

[0063] The first conductor layer 106 is a Ti / Pd / Au layer (20 / 20 / 200 nm) with an electron concentration of 1×10 18 cm -3 More than n + -It is composed of a semiconductor layer made of an InGaAs layer (100 nm), and the metal and semiconductor layer are connected with low resistance ohmic contact.

[0064] The electrode 116a is an ohmic electrode made of Ti / Pd / Au layers (20 / 20 / 200 nm). The electrode 116a is formed in the semiconductor layer 115a and has an electron concentration of 1×10 18 cm -3 More than n + -It is connected to a semiconductor layer consisting of an InGaAs layer (100 nm) through a low-resistance ohmic contact.

[0065] Around the RTD 101a, the substrate 113, the first conductor layer 106, the semiconductor layer 115a, the electrode 116a, the conductor 117a made of a conductor containing Cu, and the second conductor layer 103a are laminated in this order from the substrate 113 side and electrically connected. The RTD 101a is disposed at a position shifted by 40% (60 μm) of one side of the second conductor layer 103a from the center of gravity of the second conductor layer 103a in the resonance direction (AA' direction). Here, the input impedance when feeding high frequency from the RTD to the patch antenna is determined by the position of the RTD 101a in the antenna 100a. The second conductor layer 103a is connected to the lines 108a1 and 108a2 disposed in the lower layer via the conductors 107a1 and 107a2, which are vias formed of Cu.

[0066] The lines 108a1 and 108a2 are formed of a metal layer containing Ti / Au (=5 / 300 nm) laminated on the second dielectric layer 1042. The lines 108a1 and 108a2 are connected to the bias circuit 120 via the bias line 111, which is a common wiring formed in the chip. The bias line 111 is formed of a metal layer including Ti / Au (=5 / 300 nm) laminated on the second dielectric layer 1042. The antenna 100a is connected to a frequency f THz It is designed to achieve oscillation with a power of 0.2 mW at =0.5 THz.

[0067] Conductors 107a1 and 107a2 have a cylindrical structure with a diameter of 10 μm. Lines 108a1 and 108a2 are configured with a pattern formed of a metal layer containing Ti / Au (=5 / 300 nm) with a width of 10 μm and a length of 75 μm in the resonance direction (=A-A' direction). Conductors 107a1 and 107a2 are connected to second conductor layer 103a at the center in the resonance direction (=A-A' direction) and at the end in the B-B' direction. This connection position is located at the center of f THz This corresponds to the node of the electric field of the terahertz wave.

[0068] The semiconductor device 100 is an antenna array in which nine antennas 100a to 100i are arranged in a 3×3 matrix. Each antenna individually transmits a frequency f THz The antennas are designed to emit terahertz waves of 1000 nm and are arranged at a pitch (spacing) of 340 μm in both the A-A' and B-B' directions. Adjacent antennas are coupled to each other by a coupling line 109 including a third conductor layer 110 made of Ti / Au (=5 / 300 nm). For example, antennas 100a and 100b are coupled to each other by a coupling line 109ab. Second conductor layer 103a and second conductor layer 103b are directly connected to each other by a third conductor layer 110ab with a width of 5 μm and a length of 190 μm formed in the same layer. Antennas 100a and 100d are coupled to each other by a coupling line 109ad. Second conductor layer 103a and second conductor layer 103d are directly connected to each other by a third conductor layer 110ad with a width of 5 μm and a length of 440 μm formed in the same layer. The same is true between the other antennas. The antennas 100a to 100i have an oscillation frequency f THz At 0.5 THz, the two lasers are mutually injection locked and oscillate in a phase-aligned state (positive phase).

[0069] A bias line 111, which is a common wiring formed within the chip, is a bias wiring common to each of the antennas, and is connected to the lines 108a1, 108a2 to lines 108i1, 108i2 that are connected to each of the antennas 100a to 100i.

[0070] In the semiconductor element 100, the coupling line 109 and the bias line 111 are arranged on different layers, as shown in the relationship between the third conductor layer 110ab of the coupling line 109ab and the fourth conductor layer 111x1 of the bias line 111. In addition, the semiconductor element 100 is laminated in the order of the substrate 113, the first conductor layer 106, and the second conductor layer 103a from the substrate 113 side. In addition, as shown in the third conductor layer 110ab and the fourth conductor layer 111x1, the bias line 111 is arranged on a layer between the first conductor layer 106 and the second conductor layer 103. In addition, the coupling line 109 and the bias line 111 cross each other. The relationship between the coupling line 109 and the bias line 111 that couples the other antennas 100b to 100i is similar. This configuration reduces physical interference between the coupling line (coupling line 109) for synchronizing the antennas and the feed line (bias line 111) for supplying bias to each RTD 100. Therefore, the upper limit of the number of antennas that can be arranged increases, and a significant improvement in directivity and front intensity can be expected with an increase in the number of arrays.

[0071] (About the manufacturing method of semiconductor devices) Next, a method for manufacturing (fabrication) the semiconductor device 100 of this embodiment will be described. (1) First, an InGaAs / AlAs-based semiconductor multilayer structure constituting the semiconductor layers 115a to 115i including the RTDs 101a to 101i is formed by epitaxial growth on a substrate 113 made of InP. This can be achieved by a molecular beam epitaxy (MBE) method or the like. It is formed by methods such as metalorganic vapor phase epitaxy (MOVPE). (2) On the semiconductor layers 115a to 115i, Ti / Pd / Au layers (20 / 20 / 200 nm) constituting the electrodes 116a to 116i, which are ohmic electrodes, are formed by sputtering. (3) The electrodes 116a-116i and the semiconductor layers 115a-115i are shaped into a circular mesa shape having a diameter of 2 μm to form a mesa structure. Here, the mesa shape is formed by photolithography and dry etching using ICP (inductively coupled plasma).

[0072] (4) After the first conductor layer 106 is formed on the substrate 113 by lift-off on the etched surface, a silicon oxide film having a thickness of 2 μm that becomes the second dielectric layer 1042 is formed by plasma CVD. (5) A Ti / Au layer (=5 / 300 nm) is formed on the second dielectric layer 1042 as the fourth conductor layer 111 that constitutes the lines 108a1-i2 and the bias line 111. (6) Spin coating and dry etching are used to fill and planarize the first dielectric layer 1041 with BCB to a thickness of 5 μm.

[0073] (7) Photolithography and dry etching are used to remove the BCB and silicon oxide from the portions that form the conductors 117a-117i and 107a1-107i2 that will become vias, forming via holes (contact holes). At this time, if photolithography including grayscale exposure is used, the taper angles of the via holes for forming the first dielectric layer 1041, the second dielectric layer 1042, and the coupling line 109 can be controlled as desired. (8) Conductors 117a-117i and 107a1-107i2, which are vias, are formed in the via holes by a conductor containing Cu. The conductors 117a-117i and 107a1-107i2 are formed by filling the via holes with Cu and planarizing them using a sputtering method, an electroplating method, or a chemical mechanical polishing method. (9) An electrode Ti / Au layer (=5 / 300 nm) that becomes the third conductor layer 110 constituting the second conductor layers 103a to 103i of each antenna and the coupling line 109 is formed by sputtering.

[0074] (10) The second conductor layers 103a to 103i and the third conductor layer 110 constituting the coupling line 109 are patterned by photolithography and dry etching using ICP (inductively coupled plasma). (11) Finally, the shunt resistor 121 and the MIM capacitor 124 are formed and connected to the wiring 122 and the power supply 123 by wire bonding or the like, thereby completing the semiconductor element 100.

[0075] Power is supplied to the semiconductor element 100 from the bias circuit 120. When a bias voltage that is normally in a negative differential resistance region is applied and a bias current is supplied, the semiconductor element 100 operates as an oscillator.

[0076] <Embodiment 2> 4(a), 4(b), and 4(c) show a semiconductor device 200 according to the second embodiment. Note that configurations and structures of the semiconductor device 200 other than those described below are similar to those of the semiconductor device 100 according to the first embodiment, and therefore detailed description thereof will be omitted. Also in this embodiment, as in the first embodiment, the coupling line 209 and the bias line 211 are arranged in different layers.

[0077] The semiconductor device 200 is an antenna array in which nine antennas 200a to 200i are arranged in a 3×3 matrix. Unlike the first embodiment, the antenna 200a is a single antenna. The antenna 200a includes two active layers having electromagnetic wave gain or nonlinearity for terahertz waves. Specifically, the antenna 200a includes a semiconductor layer 215a1 including an RTD 201a1 and a semiconductor layer 215a2 including an RTD 201a2.

[0078] Electrodes 216a1 and 216a2 are arranged on the semiconductor layers 215a1 and 215a2 on the side opposite to the side on which the first conductor layer 206 is arranged. The electrode 216a1 and the semiconductor layer 215a1 are electrically connected, and the electrode 216a2 and the semiconductor layer 215a2 are electrically connected. A bias signal is supplied from the bias circuit 120 to the two RTDs 201a1 and 201a2 through the conductor layers 217a1 and 217a2, which are vias connected between the electrodes 216a1 and 216a2 and the second conductor layer 303a.

[0079] The RTD 201a1 is arranged at a position shifted by 40% of the length of one side of the second conductor layer 203a in the resonance direction (i.e., AA' direction) from the center of gravity of the second conductor layer 203a. On the other hand, the RTD 201a2 is arranged at a position shifted by -40% of the length of one side of the second conductor layer 203a in the resonance direction (i.e., AA' direction) from the center of gravity of the second conductor layer 203a. That is, the RTD 201a1 and the RTD 201a2 are arranged at positions that are symmetrical with respect to a straight line (center line) that passes through the center of gravity of the second conductor layer 203a and is perpendicular to the resonance direction and the lamination direction. In this case, the RTD 201a1 and the RTD 201a2 oscillate by mutual injection locking in a state in which the phases are inverted (opposite phases) with respect to each other. In this way, a configuration in which the RTDs are arranged symmetrically in the left and right and up and down in the antenna is a configuration that is more likely to obtain an improvement effect of directivity and frontal strength with an increase in the number of arrays.

[0080] The coupling line 209 is composed of a microstrip line in which the dielectric layer 204 and the dielectric layer 217 are sandwiched between the fourth conductor layer 210 and the first conductor layer 206, which are stacked on the dielectric layer 217 stacked on the dielectric layer 204. For example, as shown in Fig. 4(b), the coupling line 209ab has a structure in which the dielectric layer 204 and the dielectric layer 217 are sandwiched between the fourth conductor layer 210ab and the first conductor layer 206.

[0081] Similarly, the coupling line 209bc has the fourth conductor layer 210bc as an upper conductor layer, and the coupling line 209ad has the fourth conductor layer 210ad as an upper conductor layer, and has a structure in which the dielectric layer 204 and the dielectric layer 217 are sandwiched between the first conductor layer 206 and the coupling line 209bc.

[0082] The semiconductor element 200 is an antenna array in which the antennas are coupled by AC coupling (capacitive coupling). For example, the fourth conductor layer 210ab, which is an upper conductor layer of the coupling line 209ab that couples the antennas 200a and 200b, overlaps the second conductor layers 203a and 203b by 5 μm near the radiation ends in a plan view. The same applies to the coupling between the other antennas 200b to 200i.

[0083] In the overlapping portion of the conductor layers, the second conductor layers 203a and 203b, the dielectric layer 217, and the fourth conductor layer 210ab are stacked in this order to form a metal-insulator-metal (MIM) capacitance structure. In this case, the space between the second conductor layer 203a and the second conductor layer 203b is open at DC, and f THz In the low frequency region below f , the magnitude of coupling is small, so isolation between elements is ensured. On the other hand, at the oscillation frequency f THz In the frequency band, the magnitude of coupling between antennas can be adjusted by capacitance. This type of structure can significantly weaken the coupling between antennas, which also leads to the suppression of transmission loss between antennas and is expected to improve the radiation efficiency of the antenna array.

[0084] <Embodiment 3> 5(a), 5(b), and 5(c) show a semiconductor device 300 according to the third embodiment. Note that the configuration and structure of the semiconductor device 300 other than those described below are the same as those of the semiconductor device according to the second embodiment. Detailed description will be omitted since it is similar to the configuration of the same name of the element 200. Also in this embodiment, similar to the first embodiment, the coupling line 309 and the bias line 311 are arranged in different layers.

[0085] The semiconductor device 300 is an antenna array in which nine antennas 300a to 300i are arranged in a 3 × 3 matrix. Each of the antennas 300a to 300i includes two active layers having electromagnetic wave gain or nonlinearity for terahertz waves, similar to the semiconductor device 200 according to the second embodiment. Also, unlike the semiconductor device 200 according to the second embodiment, the semiconductor device 300 has an oscillation frequency f THz In order to suppress parasitic oscillation in a lower frequency band, the bias line 311 has a shunt structure. The shunt structure is arranged in parallel with the RTD, which is a negative resistance element, to reduce f THzThis structure suppresses parasitic oscillation by shorting out lower frequency bands. A shunt structure is a structure in which a resistive element or an element in which a resistor and a capacitor are connected in series is placed in parallel with the RTD. In a shunt structure, the values ​​of the resistance and capacitance are equal to or slightly lower than the absolute value of the combined negative differential resistance of multiple RTDs placed nearby.

[0086] The semiconductor device 300 has three dielectric layers as the dielectric layer 304: a first dielectric layer 3041, a second dielectric layer 3042, and a third dielectric layer 3043. The third dielectric layer 3043 is used as a dielectric for the shunt structure capacitor, and is therefore made of silicon nitride (ε r2 = 7) is used. When the dielectric layer 304 has a three-layer structure, the effective relative dielectric constant is determined taking into consideration the thickness and relative dielectric constant of the third dielectric layer 3043.

[0087] In addition, a fifth conductor layer 318 is laminated on the third dielectric layer 3043. Therefore, a metal-insulator-metal (MIM) capacitance structure is formed in which the first conductor layer 306, the third dielectric layer 3043, and the fifth conductor layer 318 are laminated in this order from the substrate 313 side, and this capacitance structure is disposed below the bias line 311. The fifth conductor layer 318 is disposed in a layer between the third conductor layer 310 and the fourth conductor layer 311 and the first conductor layer 306.

[0088] Here, each of the antennas 300a to 300i has a resistance and a capacitance due to the shunt structure. For example, in the antenna 300a, the resistor 319y4a connected to the bias line 311y4 corresponds to the resistance. And, the MIM capacitance structure in which the third dielectric layer 3043 is sandwiched between the fifth conductor layer 318y4a connected to the resistor 319y4a and the first conductor layer 306 corresponds to the capacitance. Thus, in this embodiment, the first conductor layer 306 and the bias line 311 are electrically connected via a capacitance and a resistance. Depending on the arrangement of the bias line 311 and the third conductor layer 310, the first conductor layer 306 and the third conductor layer 310 may be electrically connected via a resistance.

[0089] The fifth conductor layer 318y3ad is connected to a resistor 319y3ad that is connected to the bias line 311y3. The third dielectric layer 3043 is sandwiched between the fifth conductor layer 318y3ad and the first conductor layer 306, which constitutes an MIM capacitance structure. The shunt structure is used to generate a constant oscillation frequency f THz The configuration in which the ferroelectric capacitor is placed at the node of the high-frequency electric field of frequency f THz Since it has high impedance at frequency f THz This is a more suitable configuration for selectively oscillating only the high frequency.

[0090] However, there is a risk of unexpected low-frequency multimode oscillation occurring as the number of arrays in the antenna array increases and the bias lines are shared. For this reason, in the semiconductor device 300, the lines 308a1, 308a2 to the lines 308i1, 308i2 and the bias line 311 are THz This is a configuration in which the impedance is set lower than that of the negative resistance element (semiconductor layer 315) in a lower frequency band. Even if the number of modes increases, it is possible to suppress other-mode oscillation and obtain stable single-frequency oscillation in the terahertz band.

[0091] <Embodiment 4> 6(a) to 6(c), 7, and 8(a) to 8(c) show a semiconductor element 400 and a semiconductor element 500 according to the fourth embodiment. The semiconductor elements 400 and 500 are antenna arrays in which nine antennas are arranged in a 3×3 matrix. Here, the configuration is such that the coupling lines 409 and 509 are arranged in the lower layer, and the bias lines 411 and 511 are arranged in the upper layer. Since the coupling lines need to achieve phase matching between the antennas in the terahertz band, the shape of the coupling lines may become complicated depending on the antenna configuration. On the other hand, the bias line for bias power supply can be made into a relatively simple pattern. Therefore, the configuration in which the bias line is arranged in the upper layer and the coupling line is arranged in the lower layer as in this embodiment reduces interference between metal bodies other than the antennas and the radiated electromagnetic waves.

[0092] The semiconductor device 400 shown in Fig. 6(a) to Fig. 6(c) includes nine antennas, antennas 400a to 400i. As shown in Fig. 6(b), the third conductor layer 410ab is disposed below the fourth conductor layer 411x2, which constitutes the bias line 411 and is laminated on the first dielectric layer 4041. The third conductor layer 410ab is laminated on the first dielectric layer 4041, which constitutes the coupling line 409ab related to the antenna 400a. The other antennas 400b to 400i are similar to the antenna 400a.

[0093] Therefore, in the semiconductor element 400, the substrate 413, the first conductor layer 406 which is a ground conductor of the antenna, the third conductor layer 410a, the second conductor layer 403a which is a patch conductor, and the fourth conductor layer 411x2 are laminated in this order from the substrate 413 side. The antennas of the semiconductor element 400 are coupled by DC coupling. For example, the fourth conductor layer 410ab which is an upper conductor layer of the coupling line 409ab which couples the antenna 400a and the antenna 400b is directly connected to the second conductor layers 403a and 403b. The coupling between the other antennas is similar. Here, in the semiconductor element 400, the fourth conductor layer 410ab is formed below the second conductor layers 403a and 403b so as to be covered by the first dielectric layer 4041. In this embodiment, the second conductor layer 403 and the fourth conductor layer 411 are arranged on the same layer, but this is not limited to this, and the fourth conductor layer 411 may be formed below the second conductor layer 403.

[0094] 7 to 8(c) includes nine antennas, ie, antennas 500a to 500i. The semiconductor element 500 is an antenna array in which adjacent antennas are connected by a coupling line 509, which is a microstrip line having a third conductor layer 510 as an upper conductor layer. The third conductor layer 510 is disposed between a first conductor layer 506, which is a ground conductor, and second conductor layers 503a to 503i, which are patch conductors.

[0095] In the antenna 500a, a composite resonator including a patch antenna formed of a first conductor layer 506 and a second conductor layer 503a, and a coupling line 509a formed of a first conductor layer 506 and a third conductor layer 510a is integrated on an RTD 501a.

[0096] The coupling line 509a has a structure in which the second dielectric layer 5042 is sandwiched between the first conductor layer 506 and the third conductor layer 510a, and the longitudinal direction is perpendicular (i.e., CC' direction) to the resonance direction (i.e., AA' direction). The third conductor layer 510a is connected to a via 517a that connects the second conductor layer 503a and the RTD 501a. This allows the RTD 501a to be coupled to two resonators, the patch antenna determined by the second conductor layer 503a and the coupling line 509a determined by the third conductor layer 510a. Therefore, The length of the coupling line 509a and the size of the patch antenna are important parameters that determine the frequency of the oscillating electromagnetic wave. THz can be determined by the length of the second conductor layer 503a in the AA' direction and the length of the third conductor layer 510a in the CC' direction. Specifically, the length of the third conductor layer 510a in the CC' direction may be set to an integer multiple of the effective length of the desired oscillation wavelength, and the length of the second conductor layer 503a in the AA' direction may be set to 1 / 2 of the effective length of the desired oscillation wavelength. Here, the bias line 511 is composed of a fourth conductor layer 511y3 laminated on the first dielectric layer 5041, and the third conductor layer 510a is arranged below the fourth conductor layer 511y3. The same applies to the components of the other antennas 500b to 500i. In this embodiment, the second conductor layer 503 and the fourth conductor layer 511 are arranged on the same layer, but this is not limited thereto, and the fourth conductor layer 511 may be formed below the second conductor layer 503.

[0097] Adjacent antennas are DC-coupled by a coupling line 509. For example, antennas 500a and 500b are directly connected to each other by third conductor layers 510a and 510b at the ends of the third conductor layers 510a and 510b, which are upper conductor layers of the coupling lines 509a and 509b. Antennas 500a and 500d are directly connected to each other at the ends of the third conductor layers 510a and 510d, which are upper conductor layers of the coupling lines 509a and 509d. In order to strengthen the pull-in caused by synchronization between the antennas, it is preferable to use a standing electromagnetic wave (oscillation frequency f THz It is preferable to install the RTDs 501a to 501i at the maximum points of the electric field of the antenna. The same applies to the coupling between the other antennas.

[0098] In this way, since the third conductor layer 510 of the coupling line 509 is located on a different layer from the second conductor layer 503 that constitutes the patch antenna, the freedom of device design is improved when performing phase synchronization using an array.

[0099] <Embodiment 5> An oscillator 1000, which is a semiconductor device according to a fifth embodiment, will be described with reference to Figs. 9(a) and 9(b). Fig. 9(a) is a top view of the oscillator 1000 having 2 x 2 antennas. Fig. 9(b) is a cross-sectional view taken along line B-B' in Fig. 9(a). In this embodiment, the coupling line and the bias line are also arranged in different layers.

[0100] The oscillator 1000 includes a substrate 1001, a first conductor layer 1002 (ground metal (GND)), a negative resistance element 1003, a second dielectric layer 1004, and a third conductor layer 1005 (microstrip line (MSL) coupling line). The oscillator 1000 also includes a first dielectric layer 1006 and a second conductor layer 1007.

[0101] In this embodiment, a coupling line is formed by sandwiching a second dielectric layer 1004 between a third conductor layer 1005 and a first conductor layer 1002 .

[0102] The oscillator 1000 may also have a shunt structure 1008 (filter section), but the shunt structure 1008 is not an essential component. The shunt structure 1008 has a capacitance section 1009 and a resistance section 1010. The capacitance section 1009 is configured by an MIM structure in which a high dielectric constant layer 1011 is sandwiched between a conductive substrate 1001 and a conductor layer that is formed simultaneously when the first conductor layer 1002 is formed.

[0103] In this embodiment, the third conductor layer 1005 for synchronizing the phase of the second conductor layer 1007 and the adjacent antenna is formed on a layer different from the second conductor layer 1007, thereby increasing the design freedom and enabling multiple antennas to be arranged in an array.

[0104] The substrate 1001 has n + An InP substrate is used. In the substrate 1001, a semiconductor multilayer film that generates terahertz waves is included on the InP substrate, and has electromagnetic wave gain in the frequency range of terahertz waves.

[0105] The negative resistance element 1003 can be, for example, a resonant tunneling diode (RTD) or a Gunn diode, and in this embodiment, is configured by an RTD.

[0106] The substrate 1001 is connected to the first conductor layer 1002 by ohmic contact, and on the cathode side, a structure is used in which the first conductor layer 1002 is connected to the negative resistance element via the substrate 1001. On the anode side, a bias line is connected to the second conductor layer 1007, and the second conductor layer 1007 is connected to the negative resistance element 1003 via the third conductor layer 1005. For this reason, in this embodiment, a bias line (fourth conductor layer) is formed in the same layer as the second conductor layer 1007. By applying a bias to the negative resistance element 1003, it is possible to obtain oscillation of a terahertz wave by the second conductor layer 1007, the negative resistance element 1003, and the third conductor layer 1005 operating as a resonator.

[0107] In order to control the phase of the electromagnetic waves oscillated by adjacent antennas, the negative resistance elements 1003 between the adjacent antennas are connected by the third conductor layer 1005 (MSL coupling line). Here, by placing the negative resistance element 1003 (antenna) at the maximum point of the electric field of the electromagnetic waves standing on the third conductor layer 1005, the phase of the electromagnetic waves generated by each antenna is synchronized.

[0108] Furthermore, the length of the third conductor layer 1005 and the size of the second conductor layer 1007 are important parameters that determine the frequency of the oscillating electromagnetic wave. The length of the third conductor layer 1005 (MSL coupling line) in the resonance direction is preferably an integer multiple of the effective wavelength λ of the desired oscillation wavelength, and the length of the second conductor layer 1007 in the resonance direction is preferably 1 / 2 the effective wavelength λ of the desired oscillation wavelength.

[0109] In Fig. 9(a), antennas are arranged in 2 rows x 2 columns in the oscillation element 1000. Here, the third conductor layer 1005 is wired so that L1 = effective wavelength λ and L2 = λ / 2, and the negative resistance element 1003 is placed at a position λ / 2 from the far end of the third conductor layer 1005. In addition, the negative resistance elements 1003 of adjacent antennas are placed at a distance from the maximum point of the electric field of the standing electromagnetic wave, that is, an integer multiple of λ, as described above. In other words, in the oscillation element 1000, the antennas are arranged at a pitch of an integer multiple of λ.

[0110] In this embodiment, since an RTD element having a gain from low frequency to about 2 THz is used for the negative resistance element 1003, there is a possibility that oscillation (parasitic oscillation) occurs at a frequency other than the desired frequency. Therefore, it is preferable to form a filter to suppress the parasitic oscillation. For example, in order to suppress the parasitic oscillation, a resistor having a resistance value equal to or less than the absolute value of the negative resistance is inserted at the minimum point of the current of the electromagnetic wave standing on the third conductor layer 1005, and a loss is given to the electromagnetic wave other than the desired frequency, thereby suppressing the parasitic oscillation. In this embodiment, as shown in FIG. 9(a) and FIG. 9(b), a shunt structure 1008 using λ / 4 wiring, MIM capacitance, and resistance is installed. A λ / 4 wiring is connected to the minimum point of the electric field of the electromagnetic wave standing on the third conductor layer 1005, and is connected to the first conductor layer 1002 via a resistor section 1010 having a resistance value equal to or less than the absolute value of the negative resistance, and a capacitor section 1009 having a sufficiently large capacitance. At the portion of shunt structure 1008 in contact with third conductor layer 1005, the impedance becomes high at the desired oscillation frequency, making it difficult for current to flow into shunt structure 1008. However, at frequencies other than the desired oscillation frequency, the impedance becomes low and current flows through the shunt structure, causing loss in resistor portion 1010 and suppressing parasitic oscillation. In this way, stable oscillation can be obtained by appropriately installing the filter.

[0111] In this way, the antennas can be arranged in an array by connecting adjacent antennas with the third conductor layer 1005 formed between the first conductor layer 1002 and the second conductor layer 1007. Therefore, the antennas can be arranged at a pitch of the effective wavelength, and the directivity of the electromagnetic waves can be improved.

[0112] Example 2 A specific example 2 of the oscillation element 1000 according to the fifth embodiment will be described with reference to Fig. 10, Fig. 11(a) and Fig. 11(b). Fig. 10 is a top view of one antenna included in the oscillation element 1000. Fig. 11(a) is a cross-sectional view of the C-C' portion shown in Fig. 10. Fig. 11(b) is a top view of the antennas arranged in a 4x4 array. For the sake of simplification, the substrate 1001 and the first conductor layer 1002 are not shown in Fig. 10 and Fig. 11(b), and the shunt structure 1008 is not shown in Fig. 11(b).

[0113] In this embodiment, the single antennas shown in Fig. 10 are arrayed at intervals of the effective wavelength λ to realize the 4 x 4 antenna oscillation element 1000 shown in Fig. 11(b). Note that an oscillation element 1000 having m x n antennas (m and n are integers) can be realized by arranging them in the same way as the antennas shown in Fig. 10.

[0114] First, one antenna shown in Fig. 10 will be described. In determining the oscillation frequency of the oscillation element, important parameters include the length of second conductor layer 1007 in the resonance direction, the length of third conductor layer 1005 in the resonance direction, and the like, in addition to the dielectric constant of each dielectric layer. In this embodiment, second dielectric layer 1004 is made of silicon dioxide formed by plasma CVD. Also, first dielectric layer 1006 is made of BCB (benzocyclobutene).

[0115] In order to estimate the oscillation frequency of this embodiment, calculations were performed using an electromagnetic field simulator HFSS by ANSYS, Inc., and the result was that the effective wavelength λ for obtaining an oscillation frequency of 500 GHz was 320 μm. Therefore, it is advisable to set the length in the resonance direction of the second conductor layer 1007 to 160 μm, which is 1 / 2 of the effective wavelength λ, and the length in the resonance direction of the third conductor layer 1005 to 320 μm, which is the effective wavelength λ.

[0116] 12 shows a plot of the relationship between the length in the resonance direction of the third conductor layer 1005 (MSL) and the actual oscillation frequency. The length in the resonance direction of the patch antenna in this case is set to 1 / 2 the length in the resonance direction of the third conductor layer 1005. When the length in the resonance direction of the third conductor layer 1005 is 320 μm, the oscillation frequency is 460 GHz to 479 GHz, which is close to the above-mentioned 500 GHz.

[0117] In addition to the characteristics of the negative resistance element 1003, important parameters for determining the oscillation output of the oscillation element include the parasitic capacitance between the substrate 1001 and the first conductor layer 1002 and the third conductor layer 1005 and the second conductor layer 1007. The position of the negative resistance element 1003 in the second conductor layer 1007 is also an important parameter. In this embodiment, the area of ​​the third conductor layer 1005 and the dielectric constant and film thickness of the second dielectric layer 1004 have a great influence. For this reason, in order to reduce the parasitic resistance, the width of the MSL coupling line is made as narrow as possible and the film thickness of the second dielectric layer 1004 is made thick.

[0118] The impedance of the negative resistance element 1003 used in this embodiment is 50 to 60 Ω. In order to impedance match the second conductor layer 1007 and the negative resistance element 1003, the feed point impedance of the second conductor layer 1007 is matched with the impedance of the negative resistance element 1003.

[0119] FIG. 13(a) shows a diagram obtained by calculating the effect of the thickness of the silicon dioxide constituting the second dielectric layer 1004 on the oscillation output. FIG. 13(b) shows a diagram obtained by calculating the effect of the width of the third conductor layer 1005 (MSL) on the oscillation output. FIG. 13(c) shows a diagram obtained by calculating the effect of the distance between the negative resistance element 1003 and the center of the second conductor layer 1007 on the oscillation output. In this embodiment, the thickness of the silicon dioxide is set to 2 μm, the width of the third conductor layer 1005 is set to 4 μm, and the value obtained by dividing the distance from the negative resistance element 1003 to the center of the second conductor layer 1007 by the effective wavelength is set to 15%.

[0120] In addition, in order to realize the oscillator 1000 of this embodiment, parasitic oscillation at frequencies other than the desired oscillation frequency is suppressed. Therefore, the shunt structure 1008 is installed so as not to cause loss in the electromagnetic wave when oscillating at the desired oscillation frequency, and so as not to cause loss in the electromagnetic wave and cause oscillation at frequencies other than the desired frequency. As described above, in order to suppress parasitic oscillation, in this embodiment, a sufficiently large MIM capacitance is connected to the third conductor layer 1005 via a 20Ω resistor that makes the absolute value of the negative resistance of the negative resistance element 1003 50Ω or less, and a λ / 4 length wiring. The installation position of the λ / 4 length wiring on the third conductor layer 1005 is connected to a node of the electric field of the electromagnetic wave standing at the desired frequency. That is, in this embodiment, it is connected to a position that is λ / 4 from the far end of the third conductor layer 1005. This suppresses parasitic oscillation, and an oscillator with a desired oscillation frequency can be obtained.

[0121] As shown in FIG. 11(a), the central axis of the conductor 1012 and the central axis of the contact hole 1013 are offset in the stacking direction. The conductor 1012 is an electrode formed in a contact hole formed by removing the second dielectric layer 1004 on the negative resistance element 1003, which electrically connects the negative resistance element 1003 and the third conductor layer 1005. The contact hole 1013 is a hole penetrating the second dielectric layer 1004 (a part of the dielectric layer formed by combining the first dielectric layer 1006 and the second dielectric layer 1004) in the stacking direction. A part of the second conductor layer 1007 is formed on the surface of the contact hole 1013, thereby connecting the third conductor layer 1005 and the second conductor layer 1007. The central axes of the conductor 1012 and the contact hole 1013 may be aligned. However, in this embodiment, in order to protect the negative resistance element 1003, the two central axes are offset so that the upper side (in the stacking direction) of the negative resistance element 1003 is covered by the first dielectric layer 1006, which is a protective film.

[0122] By setting each parameter in this manner, an output of 460 GHz and 50 μW was obtained from the single antenna of this embodiment.

[0123] Moreover, as shown in FIG. 11(b), an oscillation element 1000 having 4×4 antennas can be realized by arranging the above-mentioned single antenna in an array at a pitch of the effective wavelength.

[0124] FIG. 14 shows the oscillation output when a voltage is applied to the oscillation element 1000. In FIG. 14, the dashed line indicates the oscillation output obtained by one antenna, and the solid line indicates the oscillation output obtained by 4×4 (16) antennas. Here, the oscillation output by the 4×4 antennas is 830 μW, and the oscillation frequency is 458 GHz, which is about 16 times the output obtained by a single antenna. In this way, the adjacent antennas are connected by the substrate 1001 and the third conductor layer 1005 formed between the first conductor layer 1002 and the second conductor layer 1007, and the antennas are arranged in an array, whereby the phases of the electromagnetic waves oscillated by each antenna can be synchronized.

[0125] (Manufacturing method) Next, a method for manufacturing (fabrication) the oscillation element 1000 according to this embodiment will be described with reference to the flowchart showing the manufacturing steps in FIG. 15 and FIGS. 16(a) to 16(h). 10. (a) to (h) are cross-sectional views of the antenna (oscillating element 1000) in each manufacturing process, showing the cross section taken along the line CC' in FIG.

[0126] In S2001, as shown in FIG. 16(a), a negative resistance element 1003 is formed. More specifically, a semiconductor multilayer film formed by epitaxial growth on an InP substrate doped with a high concentration of dopant and an electrode for ohmic contact are processed into a mesa shape. The semiconductor multilayer film constituting the negative resistance element 1003 is formed of InGaAs, AlAs, etc. The electrode for contact is formed of metals such as Mo, W, Ti, Ta, Al, Cu, Au, etc., alloys thereof, semiconductors doped to the same concentration, and laminated films thereof. In the subsequent processing method, a known semiconductor device process is used. In this embodiment, a Mo electrode is formed by sputtering on a semiconductor multilayer film formed by epitaxial growth, and a resist of a desired shape is formed by a photolithography process, and then dry etching is performed with a chlorine-based gas.

[0127] In S2002, as shown in Fig. 16(b), a high dielectric constant layer 1011, which is an MIM capacitor, is formed. In order to reduce the area of ​​the MIM capacitor, it is desirable that the high dielectric constant layer 1011 is made of a high dielectric constant material such as silicon nitride or aluminum oxide. In this embodiment, a silicon nitride film is formed by plasma CVD, and a resist of a desired shape is formed by a photolithography process, after which dry etching is performed with a fluorine-based gas.

[0128] In S2003, as shown in FIG. 16(c), a first conductor layer 1002 is formed. The first conductor layer 1002 is formed of metals such as Mo, W, Ti, Ta, Al, Cu, Au, or the like, alloys thereof, semiconductors doped to the same concentration, or laminated films thereof. At this time, the upper electrode of the MIM capacitor is also formed at the same time as the first conductor layer 1002. The first conductor layer 1002 is formed so as to be in ohmic contact with the substrate 1001. In this embodiment, a Mo electrode is formed by sputtering, and a resist of a desired shape is formed by a photolithography process, and then dry etching is performed with a chlorine-based gas. Although not shown, the mesa structure is protected by a high dielectric constant layer formed in S2002 during the etching in S2003.

[0129] In S2004, as shown in FIG. 16(d), a second dielectric layer 1004 is formed. The second dielectric layer 1004 is preferably made of a low dielectric constant material such as silicon dioxide, BCB, acrylic resin, polyimide, etc., in order to reduce the parasitic capacitance between the substrate 1001 and the first conductor layer 1002 and the third conductor layer 1005. In this embodiment, a silicon dioxide film is formed by plasma CVD, a resist of a desired shape is formed by a photolithography process, and then dry etching is performed with a fluorine-based gas. This dry etching forms a contact hole for forming the conductor 1012 in the next process.

[0130] In S2005, as shown in Fig. 16(e), a conductor 1012 and a third conductor layer 1005 (MSL) are formed. The third conductor layer 1005 is formed of metals such as Mo, W, Ti, Ta, Al, Cu, and Au, alloys thereof, semiconductors doped at the same concentration, and laminated films thereof. In this embodiment, an Au / Ti laminated electrode is formed by sputtering, and a resist of a desired shape is formed by a photolithography process, followed by wet etching.

[0131] In S2006, as shown in FIG. 16(f), the resistance portion 1010 is formed. As described above, it is preferable that the resistance of the resistance portion 1010 is equal to or less than the absolute value of the negative resistance of the negative resistance element 1003. In this embodiment, in order to set the resistance of the resistance portion 1010 to several ohms to several tens of ohms, A WTi alloy is used for the resistor portion 1010. Other materials that can be used for the resistor portion 1010 include metals such as Ti, TiN, Ta, Mo, and W, alloys thereof, semiconductors doped at the same concentration, and laminated films thereof. In this embodiment, WTi is formed by sputtering, and a resist of a desired shape is formed by a photolithography process, and then dry etching is performed with a fluorine-based gas.

[0132] In S2007, as shown in FIG. 16(g), a first dielectric layer 1006 is formed. The first dielectric layer 1006 is preferably made of a low dielectric constant material such as silicon dioxide, BCB, acrylic resin, polyimide, etc., in order to reduce the parasitic capacitance between the substrate 1001 and the first conductor layer 1002 and the second conductor layer 1007. At this time, a contact hole 1013 is also formed, but is formed so that the central axis of the contact hole 1013 does not coincide with the central axis of the conductor 1012 in the stacking direction. In other words, the contact hole 1013 is formed so that the stacking direction of the conductor 1012 is kept covered by the first dielectric layer 1006. In the embodiment, photosensitive BCB is formed by coating, and the desired shape of the first dielectric layer 1006 is obtained by a photolithography process.

[0133] In S2008, a second conductor layer 1007 is formed as shown in Fig. 16(h). The second conductor layer 1007 is formed of metals such as Mo, W, Ti, Ta, Al, Cu, Au, etc., alloys thereof, semiconductors doped at the same concentration, laminated films thereof, etc. In this embodiment, an Au / Ti laminated electrode is formed by sputtering, and a resist of a desired shape is formed by a photolithography process, followed by wet etching.

[0134] By forming antennas in this way, arranging them in an array, and coupling each element with a third conductor layer 1005 (MSL), it is possible to synchronize the phase of the electromagnetic waves generated by each antenna.

[0135] Example 3 Example 3, which is a modification of Example 2, will be described with reference to Fig. 17(a). For simplification, the substrate 1001, the first conductor layer 1002, and the shunt structure 1008 are not shown in Fig. 17(a). Each antenna in this example has the same configuration as in Example 2. This example shows an example in which the antenna connection method is changed from Example 2.

[0136] In the connection between antennas, the connection in the row direction is the same as that in FIG. 11(b) of the second embodiment. On the other hand, the connection in the column direction is not made by the third conductor layer 1005, but by electromagnetic waves propagating through space or an insulating film, adjacent antennas arranged in the column direction at an effective wavelength λ pitch are coupled to each other. By arranging the antennas in an array in this way and coupling each element by the third conductor layer 1005, it is possible to synchronize the phase of the electromagnetic waves generated in each antenna. Therefore, it is possible to arrange the antennas at a pitch of the effective wavelength, and it is possible to improve the directivity of the electromagnetic waves.

[0137] Example 4 Example 4, which is a modification of Example 3, will be described with reference to FIG. 17(b). In FIG. 17(b), for simplification, the substrate 1001, the first conductor layer 1002, and the shunt structure 1008 are not shown. In this example, an example of a connection method in the case where one antenna has multiple negative resistance elements is shown. In this example, similar to Example 3, the connection in the column direction is not made by the third conductor layer 1005, but adjacent antennas arranged in the column direction at an effective wavelength λ pitch are coupled to each other by electromagnetic waves propagating through space or an insulating film. In this example, two negative resistance elements are installed in one patch antenna, and are driven in a state where the phases are inverted from each other.

[0138] In this way, it is possible to synchronize the phase of the electromagnetic waves generated by each antenna by arranging antennas with multiple negative resistance elements in an array and coupling each element with the third conductor layer 1005. Therefore, it is possible to arrange the antennas at a pitch of the effective wavelength, and it is possible to improve the directivity of the electromagnetic waves.

[0139] (Other forms) Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention.

[0140] For example, in the above-mentioned embodiment and examples, the carriers are assumed to be electrons, but the present invention is not limited to this, and holes may be used. The materials of the substrate and dielectric may be selected according to the application, and may include semiconductor layers such as silicon, gallium arsenide, indium arsenide, and gallium phosphide, and resins such as glass, ceramic, polytetrafluoroethylene, and polyethylene terephthalate.

[0141] Furthermore, in the above-described embodiment and examples, a square patch antenna is used as a resonator for the terahertz wave, but the shape of the resonator is not limited to this. For example, a resonator having a structure using a patch conductor of a polygon such as a rectangle or a triangle, a circle, an ellipse, or the like may be used.

[0142] In addition, the number of negative differential resistance elements integrated in the semiconductor element is not limited to one, and a resonator having a plurality of negative differential resistance elements may be used. The number of lines is also not limited to one, and a configuration in which a plurality of lines are provided may be used. Using the semiconductor elements described in the above-mentioned embodiments and examples, it is possible to oscillate and detect terahertz waves.

[0143] In addition, in each of the above-mentioned embodiments, a double-barrier RTD made of InGaAs / AlAs grown on an InP substrate has been described as the RTD. However, the present invention is not limited to these structures and materials, and the semiconductor device can be provided with other structures and combinations of materials. For example, an RTD having a triple-barrier quantum well structure or an RTD having four or more multiple barrier quantum wells may be used.

[0144] In addition, the RTD materials may be any of the following combinations: GaAs / AlGaAs, GaAs / AlAs, InGaAs / GaAs / AlAs formed on GaAs substrate InGaAs / InAlAs, InGaAs / AlAs, InGaAs / AlGaAsSb formed on InP substrate InAs / AlAsSb and InAs / AlSb on InAs substrates ·SiGe / SiGe formed on a Si substrate The above-mentioned structure and materials may be appropriately selected depending on the desired frequency, etc. [Explanation of symbols]

[0145] 100: semiconductor element, 113: substrate, 106: first conductor layer, 115: semiconductor layer, 103: second conductor layer; 104: dielectric layer; 109: coupling line; 111: Bias line

Claims

[Claim 1] A substrate; a first conductor layer laminated on the substrate; a semiconductor layer that generates or detects terahertz waves and is electrically connected to the first conductor layer; a second conductor layer electrically connected to the semiconductor layer and facing the first conductor layer with the semiconductor layer interposed therebetween; A dielectric layer; An antenna array including a plurality of antennas, the substrate, the first conductor layer, the dielectric layer, and the second conductor layer are laminated in this order; a coupling line connected to the second conductor layer in order to synchronize the plurality of antennas with each other at a frequency of the terahertz wave; a bias line connecting a power source for supplying a bias signal to the semiconductor layer and the second conductor layer; having a wiring layer in which a portion of the coupling line extending in the in-plane direction of the substrate is provided and a wiring layer in which a portion of the bias line extending in the in-plane direction of the substrate are provided are different layers; A device characterized in that

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