DC Pulse Power Supply for Plasma Processing Equipment

Abstract

A high-voltage pulse voltage showing various waveform shapes is generated stably and with a simple configuration. 【Solution means】A stage voltage generation unit 4a to 4e that receives a P / N voltage common to each stage generated from externally supplied power and provided in each of stages 3a to 3e, and generates a stage voltage by an isolated bidirectional Cuk converter, and pulse generation units 5d and 5e that switch the stage voltage to generate individual pulse voltages, and a series connection unit 14 that serially connects the outputs of the individual pulse voltages. When charge is discharged from the load capacitance to the apparatus 1 due to plasma fluctuations or the like and the charging voltage of the capacitor 49e in any stage increases, the isolated bidirectional Cuk converter performs a reverse conversion operation without an interval. As a result, the energy due to the excessive charging voltage of the capacitor 49e is regenerated and recycled to the capacitor 28 common to stages 3a to 3e.

Description

Technical Field

[0001] The present invention relates to a DC pulse power supply device used in various plasma processing apparatuses for semiconductor manufacturing and the like.

Background Art

[0002] In various fields including semiconductor manufacturing processes, plasma processing apparatuses that utilize plasma to perform processing such as etching and sputtering on an object are used. In such plasma processing apparatuses, a combination of a high-frequency (RF) voltage and a DC pulse voltage is conventionally known for generating plasma, supplying power to the plasma, or accelerating charged particles in the plasma.

[0003] As such a DC pulse voltage, a peak value of about several hundred V to several kV is required. As a pulse power supply device for generating such a pulse voltage, for example, the devices described in Patent Documents 1 and 2 are known. In the pulse power supply devices described in these documents, the resonance phenomenon in a resonance circuit including a reactor and a capacitive load circuit is utilized to form the rising waveform and the falling waveform of the DC pulse voltage. By such a method, it is possible to shorten the rising time and the falling time of the high pulse voltage while suppressing the power loss in the DC pulse voltage.

[0004] Generally, in a DC pulse power supply device for a plasma processing apparatus, although there is a strong desire to make the rise and fall of the DC pulse voltage, which is a high voltage, as steep as possible, there are various other desires that are different from or contrary to this. For example, there is a desire to make the voltage waveforms of the rise and fall in the DC pulse voltage into a predetermined shape such as a ramp shape, and to arbitrarily set the speed of the voltage change. Also, there is a desire to generate a pulse voltage with a multi-level voltage level (multi-level) that switches to an arbitrary voltage level in each of a plurality of periods obtained by dividing one cycle period into three or more, not just a pulse voltage having two specific voltage levels. Furthermore, there is also a strong desire to increase the peak value of the outputtable DC pulse voltage to a higher voltage of 2.5 kV to 10 kV.

[0005] For example, in the pulse power supply devices described in Patent Documents 1 and 2 above, in order to change the voltage waveforms of the rise and fall of the DC pulse voltage, a saturable reactor with a large inductance value corresponding to a low resonance frequency is required, and an increase in the size and cost of the reactor is inevitable. Also, even when such measures are taken, it is difficult to make the waveform shapes of the rise and fall into a linear ramp shape.

[0006] On the other hand, in the pulse power supply device described in Patent Document 3, voltage pattern information corresponding to the output voltage waveform for at least one cycle is previously held in a memory, and a DC high voltage is switched and controlled based on the voltage pattern information to form rises and falls of a desired shape. Also, in the pulse power supply device described in Patent Document 3, a multi-stage (multi-level cascade) method has been proposed in which a plurality of units for forming a pulse waveform are prepared and their outputs are connected in series to obtain a high-voltage pulse voltage. Thereby, it is possible to generate a high-voltage pulse while keeping the withstand voltage of each unit relatively small. Also, in the multi-stage method, by independently controlling each stage, it is possible to also handle a multi-level output.

Prior Art Documents

Patent Documents

[0007] [Patent Document 1] Japanese Patent No. 6810316 [Patent Document 2] Japanese Patent No. 6810317 [Patent Document 3] Japanese Patent No. 7011118 [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] However, in a plasma processing apparatus, since the load of the power supply device is capacitive, when the outputs of a plurality of power supply circuits are connected in series, that is, when multi-staged to supply power to the load, depending on the conditions of the load and the like, the energy regenerated from the capacitive load circuit to the power supply device becomes larger than the energy supplied from the power supply device side to the capacitive load circuit, and the supply voltage may rise in some stages. When an imbalance occurs in the voltage for each stage in a multi-stage power supply device, the operation of the power supply device may become incomplete and the shape of the DC pulse voltage waveform may not become as desired. In addition, there is also a concern that circuit components may deteriorate or be damaged due to an undesired voltage increase.

[0009] Also, when trying to obtain a voltage waveform with a slow rise and fall or a multi-level voltage waveform as described above in a multi-stage power supply device, as the number of stages increases, the circuit configuration in each stage becomes complicated, and the increase in cost is significant. Therefore, in order to be able to set the waveform shapes of the rise and fall more flexibly and also to set the voltage levels more flexibly, a multi-stage circuit configuration corresponding to such requirements is demanded.

[0010] The present invention has been made to solve such problems, and in a DC pulse power supply device for a plasma processing apparatus that can output a high-voltage DC pulse voltage showing various waveform shapes, such as being able to arbitrarily set the waveform shapes of rise and fall, one object is to be able to stably generate a DC pulse voltage waveform of an arbitrary voltage level (multi-level) corresponding to such a high voltage with a simple configuration.

Means for Solving the Problems

[0011] The present invention made to solve the above problems is a DC pulse power supply device that outputs a DC pulse voltage to a capacitive load circuit in a plasma processing apparatus, a) generating a basic DC voltage common to a plurality of stages described later from the power supplied from the outside, and having a common capacitor (28) between a high-voltage side output terminal and a low-voltage side output terminal that output the basic DC voltage, a common voltage generation unit (2); b) provided in each of a plurality of stages (3a to 3e, 7a, 7b), including an isolated bidirectional converter (44a to 44e) and an individual capacitor (49a to 49e) connected between a high-voltage side output terminal and a low-voltage side output terminal of the isolated bidirectional converter, and an individual DC voltage generation unit (4a to 4e, 8a, 8b) that generates an individual DC voltage for each stage by receiving the basic DC voltage generated by the common voltage generation unit; c) provided in each of the plurality of stages, and an individual pulse voltage generation unit (5a to 5e, 9a, 9b) that generates an individual pulse voltage for each stage by switching the individual DC voltage generated by the individual DC voltage generation unit in that stage; d) a series connection unit (14) that serially connects and outputs the individual pulse voltages by the individual pulse voltage generation units in the plurality of stages; It is equipped with.

[0012] In the DC pulse power supply device according to the present invention, the isolated bidirectional converter is not limited to a specific circuit method, but as an example, it can be an isolated bidirectional Cuk converter.

[0013] Also, in the DC pulse power supply device according to the present invention, the individual pulse voltage generation unit includes a plurality of switching elements and a reactor, and by utilizing the resonance of a circuit including the reactor whose current flow direction is switched by the on / off operation of the plurality of switching elements and the capacitor of the load circuit, the rise and fall edges of the individual pulse voltage can be formed. Specifically, for example, a pulse generation circuit described in Patent Documents 1, 2, etc. as described later can be used.

[0014] In the DC pulse power supply device according to the present invention, the DC pulse voltage is formed by voltage addition of the individual pulse voltages generated by the individual pulse generation units included in each of the plurality of stages at the series connection part, and the DC pulse voltage is applied to the capacitive load circuit. When the load fluctuates during the operation of the power supply device and becomes, for example, no load or light load, charges are released from the capacitor in the load circuit charged to a high voltage to the power supply device side, and the individual capacitors of some stages are charged by the inflow of the charges, resulting in a voltage increase. Also, when there is a slight deviation in the edges even though the plurality of stages operate simultaneously and the individual pulse voltage rises or falls, a current corresponding to the deviation flows from the capacitor of the load circuit to the DC pulse power supply device side, and the individual capacitors of some stages are charged, resulting in a voltage increase.

[0015] On the other hand, in the DC pulse power supply device according to the present invention, when the voltage of the individual capacitor rises due to the charging current from the load, without an interval, by the reverse operation of the isolated bidirectional converter included in the stage where the voltage increase has occurred, the energy due to the charging voltage of the individual capacitor is regenerated to the input side and accumulated in the common capacitor shared by the plurality of stages. And the energy recovered in this common capacitor is utilized again to generate an individual DC voltage by the forward operation of the isolated bidirectional converter included in each stage. In this way, the energy regenerated from the capacitive load circuit is recycled quickly and without waste.

[0016] As one aspect of the DC pulse power supply device according to the present invention, all of the individual DC voltage generation units included in the plurality of stages generate the same voltage value corresponding to the voltage value of the basic DC voltage, and the peak value at each time point of the DC pulse voltage output from the device can be configured to be determined by the number of stages that are substantially operating at that time.

[0017] In the DC pulse power supply device having this configuration, for example, the voltage value of the individual DC voltage of each stage may be a value obtained by dividing the maximum peak value of the target DC pulse voltage by the number of stages. In this configuration, the voltage values of the individual DC voltages generated in all stages are the same, and the voltage value of the voltage output from the device at a certain time point is determined by the number of stages that are substantially operating at that time. The peak value of the DC pulse voltage is the maximum when all stages are substantially operating and outputting individual pulse voltages, and the DC pulse voltage also has a voltage value of 0 when all stages are not substantially operating and the individual pulse voltage is 0. Also, for example, in the rise of the DC pulse voltage, by sequentially increasing the number of stages operating with the passage of time, a ramp-shaped rise waveform in which the voltage increase is virtually linear can be formed. Further, by changing the length of the period during which the same number of stages are operating when sequentially increasing the number of stages, the slope of the ramp-shaped rise waveform can be adjusted. The same applies to the fall waveform.

[0018] According to this configuration, since it is not necessary to change the voltage value of the individual DC voltage independently generated in the individual voltage generation unit of each stage, the plurality of individual voltage generation units and the individual pulse voltage generation units can each have the same configuration. Thereby, the circuit configuration can be simplified and cost reduction can be achieved.

[0019] As another aspect of the DC pulse power supply device according to the present invention, the individual DC voltage generation units included in the stages that are not all of the plurality of stages generate a predetermined voltage value that is equal to or lower than the voltage value of the basic DC voltage. On the other hand, the individual DC voltage generation units included in the remaining stages of the plurality of stages generate a variable voltage value that is equal to or lower than the voltage value of the basic DC voltage. The peak value at each time point of the DC pulse voltage output from the device can be configured to be determined by the number of stages that are substantially operating at that time among the stages including the individual DC voltage generation units that generate the predetermined voltage value and the variable voltage value.

[0020] In the configuration of the above aspect, the voltage values of the individual DC voltages generated in all stages were the same. However, in the configuration of this aspect, the voltage value of the individual DC voltage is variable in at least one stage and is different from the voltage values of the individual DC voltages in other stages. And the voltage value of the voltage output from the device at a certain time point is determined by the number of stages that are substantially operating at that time and the variable voltage value. Therefore, according to this configuration, in particular, the voltage change when the voltage waveform changes such as rise and fall can be performed more flexibly, and a waveform closer to the desired rise and fall shape can be generated.

[0021] Further, the DC pulse power supply device according to the present invention includes a voltage pattern information acquisition unit that acquires voltage pattern information based on a stepped or stepped voltage change corresponding to an ideal voltage waveform for at least one cycle of the DC pulse voltage output from the device. and, Based on the voltage pattern information, the operations of the individual DC voltage generation units, the individual pulse voltage generation units, and, if necessary, the common voltage generation unit included in each stage are respectively controlled. further comprising a control unit It can be configured.

[0022] According to this configuration, by appropriately changing the voltage pattern information corresponding to the output voltage waveform, it is possible to output DC pulse voltages with various waveform shapes, for example, the waveforms of rise and fall are steep or slow. When generating such DC pulse voltages, it is not necessary to use a saturable reactor with a variable inductance value, which is advantageous for miniaturization, weight reduction, cost reduction, etc. of the device. Also, power loss can be suppressed, and power can be efficiently supplied to the plasma load.

[0023] Note that in the DC pulse power supply device according to the present invention, although the individual DC voltage generation units included in the plurality of stages each include an isolated bidirectional converter, even in a multi-stage configuration that does not necessarily include an isolated bidirectional converter, it is possible to adopt a configuration that outputs a high-voltage DC pulse voltage showing various waveform shapes in which the waveform shapes of rise and fall can be arbitrarily set.

[0024] That is, a DC pulse power supply device according to one aspect related to the present invention is a DC pulse power supply device that outputs a DC pulse voltage to a capacitive load circuit in a plasma processing device, a) a voltage pattern information acquisition unit that acquires voltage pattern information based on a stepped or stepped voltage change corresponding to an ideal voltage waveform for at least one cycle of the DC pulse voltage output from the device; b) a common voltage generation unit that generates a basic DC voltage common to the following plurality of stages from the power supplied from the outside; c) individual DC voltage generation units provided in each of the plurality of stages, which generate individual DC voltages for each stage from the basic DC voltage; d) individual pulse voltage generation units provided in each of the plurality of stages, which generate individual pulse voltages for each stage by switching the individual DC voltages generated by the individual DC voltage generation units in that stage; e) a series connection unit that serially connects and outputs the outputs of the individual pulse voltage generation units in the plurality of stages. f) A control unit that controls the operations of the individual DC voltage generation units and the individual pulse voltage generation units included in each stage based on the voltage pattern information, and, if necessary, the operation of the common voltage generation unit; The device includes individual DC voltage generation units, all of which generate the same voltage value corresponding to the voltage value of the basic DC voltage, and the peak value of the DC pulse voltage output from the device at each point in time is determined by the number of stages that are substantially operating at that time.

[0025] Also, a DC pulse power supply device according to another aspect related to the present invention is a DC pulse power supply device that outputs a DC pulse voltage to a capacitive load circuit in a plasma processing device, a) A voltage pattern information acquisition unit that acquires voltage pattern information based on a stepped or stepped voltage change corresponding to an ideal voltage waveform for at least one cycle of the DC pulse voltage output from the device; b) A common voltage generation unit that generates a basic DC voltage common to a plurality of subsequent stages from the power supplied from the outside; c) Individual DC voltage generation units provided in each of the plurality of stages, each generating an individual DC voltage for each stage from the basic DC voltage; d) Individual pulse voltage generation units provided in each of the plurality of stages, each generating an individual pulse voltage for each stage by switching the individual DC voltage generated by the individual DC voltage generation unit in that stage; e) A series connection unit that serially connects and outputs the outputs of the individual pulse voltage generation units in the plurality of stages; f) A control unit that controls the operations of the individual DC voltage generation units and the individual pulse voltage generation units included in each stage based on the voltage pattern information, and, if necessary, the operation of the common voltage generation unit; comprising, wherein the individual DC voltage generation units included in the stages that are not all of the plurality of stages generate a predetermined voltage value that is equal to or lower than the voltage value of the basic DC voltage, while the individual DC voltage generation units included in the remaining stages of the plurality of stages generate a variable voltage value that is equal to or lower than the voltage value of the basic DC voltage, and the peak value at each time point of the DC pulse voltage output from the device is determined by the number of stages that are substantially operating at that time among the stages including the individual DC voltage generation units that generate the predetermined voltage value, and the variable voltage value.

Advantages of the Invention

[0026] According to the DC pulse power supply device for a plasma processing apparatus according to the present invention, the charge released from the capacitive load circuit can be recovered and recycled to the common capacitor of the common voltage generation unit instead of each stage, so that abnormal increases in the individual DC voltages in each stage can be avoided, and a stable high-voltage multi-level DC pulse voltage waveform that is not affected by load fluctuations can be generated with a simple configuration. In addition, since the regenerative energy from the capacitive load circuit can be effectively utilized, power suitable for plasma can be supplied more efficiently.

Brief Description of the Drawings

[0027]

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Embodiments for Carrying Out the Invention

[0028] Hereinafter, specific embodiments of the DC pulse power supply device for a plasma processing apparatus according to the present invention will be described with reference to the accompanying drawings.

[0029] [First Embodiment] FIG. 1 is a schematic block configuration diagram of the DC pulse power supply device of the first embodiment. FIG. 2 is a diagram showing an example of an ideal waveform of the output voltage by the DC pulse power supply device of the first embodiment. The schematic configuration and operation of the DC pulse power supply device of the first embodiment will be described with reference to FIGS. 1 and 2.

[0030] As shown in FIG. 1, this DC pulse power supply device 1 receives three-phase AC power from an external three-phase AC power supply 10 and applies a DC pulse voltage Pv to a plasma load circuit 11 which is a capacitive load circuit in the plasma processing apparatus. This DC pulse power supply device 1 has a multi-stage configuration with 5 stages, and a P / N voltage V that receives three-phase AC power and is commonly supplied to each stage 3a to 3e P / N is generated by a P / N voltage generation unit 2, and the P / N voltage V P / NBased on this, stage voltage generation units 4a to 4e that generate stage voltages [1]Vs to [5]Vs insulated from each other, and pulse generation units 5a to 5e that generate independent pulse voltages [1]Ps to [5]Ps based on those stage voltages [1]Vs to [5]Vs, and a voltage pattern setting unit 6 that outputs control signals or instruction signals to the P / N voltage generation unit 2, stage voltage generation units 4a to 4e, and pulse generation units 5a to 5e according to voltage pattern information corresponding to the DC pulse voltage waveform. However, it goes without saying that the power supplied to this DC pulse power supply device 1 from the outside is not limited to three-phase AC power, and may be single-phase AC power or DC power.

[0031] Here, five stage voltage generation units 4a to 4e and pulse generation units 5a to 5e form five independent stages 3a to 3e. However, the number of stages is only an example, and it can be set to an appropriate number of two or more. The [1] to [5] in the stage voltages [1]Vs to [5]Vs and individual pulse voltages [1]Ps to [5]Ps corresponding to the individual DC voltages in the present invention correspond to these five stages 5a to 5e. Also, the numbers related to [1] to [5] correspond to the positions of the voltage levels in the DC pulse voltage output from this power supply device as shown in FIG. 2, where [1] forms the lowest voltage level and [5] forms the highest voltage level. The individual pulse voltages [1]Ps to [5]Ps output from the pulse generation units 5a to 5e are serially combined at the series connection part 14 and output as the DC pulse voltage Pv between the high potential output terminal 12 and the low potential output terminal 13. Either one of this high potential output terminal 12 and the low potential output terminal 13 can be set to the ground potential. In FIG. 1, the low potential output terminal 13 is set to the ground potential, but the high potential output terminal 12 may be grounded.

[0032] The voltage pattern setting unit 6 can be configured mainly around, for example, an FPGA (Field Programmable Gate Array). Based on the information of a desired, that is, an ideal DC pulse voltage waveform set by, for example, a user, the voltage pattern setting unit 6 generates voltage pattern information representing the change in voltage value according to the passage of time within at least one period T of the DC pulse voltage that is in a staircase or step shape as shown in FIG. 2. This voltage pattern information is, for example, numerical data capable of generating a waveform that changes in a staircase shape indicated by a solid line in FIG. 2.

[0033] Here, as an example, the voltage pattern information is defined as follows. That is, as shown in FIG. 2, a plurality (10 in this example) of periods (Ta to Tj in this example) obtained by dividing one period T and a plurality of (5 in this example) stages in each period are defined. And in order to change the rise and fall of the DC pulse voltage in a staircase shape following a virtual line that is in a ramp shape or an arbitrary curve shape, one or both of the number and length of the periods and the number of stages can be freely set. By appropriately determining the number and length of the periods and the number of stages, for example, the change speed of the waveforms of the ramp-shaped (or curved-shaped) rise and fall can be adjusted. Note that the voltage pattern setting unit 6 may calculate the voltage pattern information based on the virtual line of the desired DC pulse voltage waveform in advance and hold it in a memory or the like, or may obtain it by calculating from the virtual line of the desired DC pulse voltage waveform each time it operates.

[0034] Based on the acquired voltage pattern information, the voltage pattern setting unit 6 outputs a Vs setting signal to each stage voltage generation unit 4a to 4e in order to generate stage voltages [1]Vs to [5]Vs corresponding to the peak value V1 of the DC pulse voltage waveform. Also, the voltage pattern setting unit 6 generates a P / N voltage V that is higher than each stage voltage Vs or even higher. P / N For P / NOutput the setting signal to the P / N voltage generation unit 2. Furthermore, the voltage pattern setting unit 6 outputs Ps1 to Ps5 setting signals corresponding to the start time, end time, period, and cycle (pulse frequency) of the DC pulse voltage waveform to the pulse generation units 5a to 5e in order to generate the individual pulse voltages [1]Ps to [5]Ps for each stage. As will be described later, each unit that receives these setting signals has a local control unit included therein that generates a timing control signal according to the setting signal.

[0035] Regarding the peak value V1 of the DC pulse voltage, the P / N voltage V P / N is fixed to the voltage value for obtaining the stage voltage Vs with respect to the peak value V1 at the maximum rating max and the peak value V1 may be adjusted only by adjusting the Vs setting signal (that is, not adjusted by the V P / N setting signal). However, it is preferable to configure it such that the P / N voltage V P / N is changed according to the change in the peak value V1 to obtain the stage voltage Vs corresponding to the peak value V1. By configuring it in this way, especially at low output when the peak value V1 of the DC pulse voltage is low, the P / N voltage V P / N is lower than when the P / N voltage V P / N is set to a fixed value. Therefore, usually, the switching loss and the like of the stage voltage generation units 4a to 4e in which a plurality operate are reduced, and the power utilization efficiency can be improved.

[0036] Here, the method of determining the data included in the voltage pattern information with respect to the ideal waveform shown in FIG. 2 will be specifically described. Each individual pulse voltage [1]Ps to [5]Ps, which is rectangular as shown in FIG. 2, is an ideal waveform determined by the stage voltage [1]Vs to [5]Vs and the length of the pulse period. The DC pulse voltage Pv output from this DC pulse power supply device 1 increases or decreases periodically and stepwise as shown in FIG. 2. The broken line shown in FIG. 2 is the virtual line U1 when the DC pulse voltage Pv increases or decreases in a ramp shape. When this virtual line U1 increases from point a(0) to point b(V1), the time when the voltage becomes 0.5·Vs on this virtual line U1 is T0, the time when it becomes 1.5·Vs is T1, the time when it becomes 2.5·Vs is T2, the time when it becomes 3.5·Vs is T3, and the time when it becomes 4.5·Vs is T4. The individual pulse voltage [1]Ps is output at time T0, the individual pulse voltage [2]Ps at time T1, the individual pulse voltage [3]Ps at time T2, the individual pulse voltage [4]Ps at time T3, and the individual pulse voltage [5]Ps at time T4. Since the virtual line U1 is a linear function from point a to point b, the respective periods Ta to Td for times T0 to T4 are equal, i.e., Ta = Tb = Tc = Td, and the DC pulse voltage Pv increases stepwise following the ramp-shaped virtual line U1.

[0037] Next, when the virtual line U1 decreases from point c(V1) to point d(0), the time when the voltage becomes 4.5·Vs on this virtual line U1 is T5, the time when it becomes 3.5·Vs is T6, the time when it becomes 2.5·Vs is T7, the time when it becomes 1.5·Vs is T8, and the time when it becomes 0.5·Vs is T9. The individual pulse voltage [5]Ps is cut off at time T5, the individual pulse voltage [4]Ps at time T6, the individual pulse voltage [3]Ps at time T7, the individual pulse voltage [2]Ps at time T8, and the individual pulse voltage [1]Ps at time T9. At this time, since the virtual line U1 is a linear function from point c to point d, the respective periods Tf to Ti for times T5 to T9 are equal, i.e., Tf = Tg = Th = Ti, and the DC pulse voltage Pv decreases stepwise following the ramp-shaped virtual line.

[0038] On the one hand, the virtual line from point b to point c has a constant voltage of the pulse peak voltage V1, and the virtual line from point d to point a in the next cycle has a constant voltage of 0. The DC pulse voltage Pv is 5·Vs = V1 at time T4 and continues with V1 until time T5, so it is V1 during the period Te. Similarly, it is 0 at time T9 and continues with 0 until time T10(=0), so it is 0 during the period Tj. As described above, voltage pattern information for forming the waveform of the DC pulse voltage Pv with 5 stages, 6 voltage levels, and 10 periods is obtained, and generation information for the pulse voltages [1]Ps to [5]Ps in each stage is obtained.

[0039] To make the rise and / or fall changes of the DC pulse voltage steep, the periods Ta to Td and / or the periods Tf to Ti can be shortened. Conversely, to make the rise and / or fall changes of the DC pulse voltage slow, the periods Ta to Td and / or the periods Tf to Ti can be lengthened. When the virtual line is a curve instead of a straight line (broken line), the periods Ta to Td and / or the periods Tf to Ti can be set to respective values corresponding to the curved virtual line. In this case, the DC pulse voltage Pv increases or decreases stepwise following the curved virtual line. Also, as shown by the dotted line in Fig. 2, the change in voltage can be increased by superimposing a plurality of stage voltages Vs at the same time (time T1 in the example of Fig. 2).

[0040] Next, the configuration and operation of each part will be described in detail. Fig. 3 is a schematic circuit configuration diagram showing an example of the P / N voltage generation unit 2. This circuit is substantially the same as the circuit adopted in the power supply device described in Patent Document 3. The P / N voltage generation unit 2 includes a step-down converter 24. The three-phase AC voltage supplied from the three-phase AC power supply 10 is input to a rectifier circuit composed of a bridge diode 22 and a capacitor 23 through a fuse circuit 20 and a noise filter (NFL) 21. The voltage across both ends of the capacitor 23 is input to a step-down converter 24 composed of two complementary switches 25a and 25b formed by two series-connected switching elements 251, 252 and 253, 254, reactors 26a and 26b, and a capacitor 28. The on / off operation of the complementary switches 25a and 25b in the step-down converter 24 is controlled by a first control unit 101 which is a local control unit, whereby a P / N voltage V P / N is obtained.

[0041] A current transformer 27 is inserted between the connection point of the two reactors 26a and 26b and the capacitor 28, and the current value detected by this current transformer 27 is fed back to the first control unit 101. The step-down converter 24 is a two-phase interleaved converter in which the switching operation between the two complementary switches 25a and 25b has a phase difference with a duty ratio D = 0.5. The ripple frequency in the two-phase interleaved method is twice the switching frequency, and the high-frequency ripple current of the synthesized reactor at PWM duty ratio D = 0.5 becomes a theoretical value of 0. Therefore, the converter of this method operates advantageously with respect to ripple.

[0042] In addition, in the circuit configuration shown in FIG. 3, it is also possible to magnetically anti-couple the two reactors 26a and 26b, thereby reducing the peak current of the switching element while reducing the equivalent inductance of the output and improving the control response.

[0043] This P / N voltage V that is variable to a predetermined voltage value according to the peak value V1 of the DC pulse voltage waveform P / NThe above circuit method for amplitude control is a known technique known as the PAM (Pulse Amplitude Modulation) method. As is well known, the improvement of commercial ripple caused by three-phase AC voltage can be achieved by using peak current mode control in combination with the above PWM control.

[0044] In addition, since each switching element used in the buck converter 24 operates at a high switching frequency of about 100 kHz or more, for example, SiC-MOSFET is useful. Needless to say, in order to prevent short circuits in the arm, it is necessary to provide a dead time when switching the switching element.

[0045] FIG. 4 is a schematic circuit configuration diagram showing an example of a five-stage stage 3a to 3e including stage voltage generation units 4a to 4e and pulse generation units 5a to 5e in the DC pulse power supply device of the present embodiment. In order to avoid complicating the drawing, only the circuit configuration of the stage voltage generation unit 4e and the pulse generation unit 5e in the stage 3e is described in detail, and the descriptions of the other stages 3a to 3d are appropriately omitted, but the circuit configurations of these stages 3a to 3e are the same. In addition, even for the components whose descriptions are omitted in FIG. 4, in the following description, the components corresponding to the components (circuit elements) described in detail in FIG. 4 are respectively assigned corresponding reference numerals and used in the description. The same applies to FIG. 8 and the corresponding description.

[0046] As shown in FIG. 4, the stage voltage generation units 4a to 4e each include an isolated bidirectional Cuk converter. This converter shown in FIG. 4 combines the functions of a boost converter and a buck converter and operates in an inverted form that is DC-isolated, with the input side being a boost converter and the output side being a buck converter. However, the polarity of the output voltage can be changed depending on the polarity of the isolation transformers 44a to 44e.

[0047] The isolated bidirectional Cuk converter includes insulated transformers 44a to 44e connected such that the polarities of the primary winding n1 and the secondary winding n2 are different, input-side coupling capacitors 43a to 43e and output-side coupling capacitors 45a to 45e divided into two by the insulated transformers 44a to 44e, input-side reactors 40a to 40e and output-side reactors 48a to 48e, input-side switching elements 42a to 42e and output-side switching elements 46a to 46e that perform complementary on / off operations, and input-side capacitor 28 and output-side capacitors 49a to 49e, and is configured to have symmetry between the input side and the output side with the insulated transformers 44a to 44e interposed therebetween. Capacitor 28 is the capacitor 28 in the output stage of the P / N voltage generation unit 2 and is shared by the five-stage voltage generation units 4a to 4e connected in parallel. The P / N voltage V P / N between both ends of the capacitor 28 is supplied in parallel to the stage voltage generation units 4a to 4e.

[0048] The second control unit 102, which is a local control unit, controls the complementary on / off operations of the input-side switching elements 42a to 42e and the output-side switching elements 46a to 46e. As a result, stage voltages [1]Vs to [5]Vs having voltage values represented by the following equation (1) are obtained at both ends of the capacitors 49a to 49e provided in the output stage of the stage voltage generation units 4a to 4e. Vs = V P / N ×Na×Da / (1 - Da) …(1) Here, Na = (n2 / n1), and Da is the PWM duty ratio of the input switching element. Also, since bidirectional operation can be performed in the above converter, the following equation (2) also holds when the capacitors 49a to 49e are regarded as voltage sources. V P / N = Vs×Nb×Db / (1 - Db) …(2) Here, Nb = (n1 / n2), and Db is the PWM duty ratio of the output switching element.

[0049] From the above equations (1) and (2), when the PWM duty ratio Da or Db is fixed and PWM control is not substantially performed, the voltage V between both ends of the capacitor 28 P / NWhen it rises, the stage voltage Vs of the individual capacitors 49 (capacitors 49a to 49e) rises. On the other hand, when the stage voltage Vs of this individual capacitor 49 rises, the voltage V P / N across both ends of the capacitor 28 rises. For example, when the stage voltages [1]Vs to [5]Vs rise due to the regeneration of charges from the capacitive plasma load circuit 11 due to various factors as described later, from equation (2), the voltage V P / N across both ends of the capacitor 28 rises. That is, by transferring the regenerated charges from the individual capacitors 49 to the common capacitor 28, the voltage V P / N across both ends rises. By consuming or recycling this increase in other circuits connected to the common capacitor 28, when the voltage V P / N across both ends of the capacitor 28 returns to the value before the rise, the insulated bidirectional Cuk converter operates so that the voltage of the individual capacitor 49 becomes the stage voltage Vs before the voltage rise. This operation is of course performed in real time without intervals.

[0050] The voltage values of the stage voltages [1]Vs to [5]Vs that appear across both ends of the capacitors 49a to 49e in the output stage are detected and fed back to the second control unit 102. In response to this, the second control unit 102 controls the complementary on / off operations of the switching elements 42a to 42e, 46a to 46e so that [1]Vs to [5]Vs each become a constant voltage. That is, constant voltage control is performed. When the stage voltages [1]Vs to [5]Vs rise due to the regeneration of charges from the capacitive plasma load circuit 11 due to various factors as described later, although the PWM duty ratio Da of the input side switching elements 42a to 42e decreases by the above constant voltage control, the PWM duty ratio Db of the output side switching elements 46a to 46e increases, and this insulated bidirectional Cuk converter operates to increase the voltage V P / N across both ends of the capacitor 28 by the rising stage voltages [1]Vs to [5]Vs. That is, this is an operation of actively regenerating the increased charges to the input stage capacitor 28 in any one of the capacitors 49a to 49e in the output stage.

[0051] One capacitor 28 is shared by the five-stage voltage generation units 4a to 4e, and the capacitance of the capacitor 28 is set relatively large with respect to the capacitances of the capacitors 49a to 49e. Therefore, the P / N voltage V P / N across both ends of the capacitor 28 due to the regenerative energy as described above rises slowly. In addition, since this P / N voltage V P / N is supplied in parallel to the five-stage voltage generation units 4a to 4e, the charges regenerated in the capacitor 28 are output through the other stage voltage generation units 4a to 4e where the stage voltages [1]Vs to [5]Vs do not rise. In this way, in the DC pulse power supply device 1 of the present embodiment, since the regenerative energy is immediately recycled by using the isolated bidirectional Cuk converter, the stage voltages [1]Vs to [5]Vs can be efficiently controlled to a predetermined voltage value.

[0052] Each of the switching elements 42a to 42e, 46a to 46e used in the isolated bidirectional Cuk converter typically operates at a switching frequency of about 100 kHz, so SiC-MOSFETs are useful. Also, in order to prevent a short circuit in the circuit, it is natural that a dead time is provided for the complementary on / off operation of the switching elements. Further, in FIG. 4, voltage clamp circuits 41a to 41e, 47a to 47e are connected in parallel to the switching elements 42a to 42e, 46a to 46e, respectively. This is for the purpose of clamping the surge voltage caused by the leakage inductance of the isolation transformers 44a to 44e and preventing the voltage breakdown of the switching elements 42a to 42e, 46a to 46e. Note that in FIG. 4, the voltage clamp circuits 41a to 41e, 47a to 47e are denoted by TVS (Transient Voltage Suppressor), but it is natural that an active clamp circuit or a discharge blocking snubber circuit may be used instead.

[0053] In the DC pulse power supply device 1 of this embodiment, when assuming that the peak value V1 of the DC pulse voltage shown in Fig. 2 is 2.5 kV, the stage voltages [1]Vs to [5]Vs are each 500 V. Therefore, as circuit components such as switching elements with voltage rating constraints, it is possible to use relatively inexpensive circuit components that are generally available on the market. For this reason, it is obvious that such a multi-stage configuration contributes to cost reduction.

[0054] In addition, since two reactors 40a to 40e and 48a to 48e are used in each isolated bidirectional Cuk converter shown in Fig. 4, there is an advantage that the voltage ripples on the input side and the output side are reduced, and EMI can be efficiently reduced. However, when the single-unit capacity of the converter is small, such as several hundred W, an isolated bidirectional flyback converter or the like with a simpler configuration may be used, and it is not necessarily limited to using the circuit method of the Cuk converter.

[0055] The pulse generation units 5a to 5e connected to the outputs of the stage voltage generation units 4a to 4e can be, for example, those using the circuits in the pulse power supply devices described in Patent Documents 1, 2, etc. The pulse generation units 5a to 5e shown in Fig. 4 use the circuit described in Patent Document 1, and include a series circuit of switching elements 51a to 51e and switching elements 52a to 52e that perform complementary on / off operations, a series circuit of diodes 54a to 54e and diodes 55a to 55e, resonance reactors 53a to 53e, and resonance capacitors 56a to 56e. The stage voltages [1]Vs to [5]Vs generated in the stage voltage generation units 4a to 4e are independently input to the respective pulse generation units 5a to 5e.

[0056] The second control unit 102 controls the complementary on / off operations of the switching elements 51a to 51e and the switching elements 52a to 52e. As a result, pulse voltages [1]Ps to [5]Ps, whose voltage values at a predetermined pulse period are the voltage values of the stage voltages [1]Vs to [5]Vs, are obtained across the diodes 55a to 55e, respectively. When the switching elements 51a to 51e or 52a to 52e are turned on and when the pulse voltages [1]Ps to [5]Ps rise and fall, the resonance reactors 53a to 53e, in which the direction of current is switched by the respective switching elements 51a to 51e, 52a to 52e, the resonance capacitors 56a to 56e, and the capacitance Cp of the plasma load circuit 11 (omitted in FIG. 4, see FIG. 1) form a resonance operation in a circuit, thereby forming the rising waveform and the falling waveform of the DC pulse voltage. As a result, the pulse voltages [1]Ps to [5]Ps rise or fall with steep edges formed by resonance. By such a waveform forming method, it is possible to shorten the rise time and the fall time of the pulse voltage while suppressing power loss (in other words, while effectively using power).

[0057] Since each of the switching elements 51a to 51e, 52a to 52e used in the pulse generation units 5a to 5e typically operates at a switching frequency of about 400 kHz, SiC-MOSFETs are useful. Also, as described above, a dead time is provided for the complementary on / off operations of the switching elements to prevent a short circuit in the circuit.

[0058] The pulse voltages [1]Ps to [5]Ps obtained by the operations of the stage voltage generation units 4a to 4e and the pulse generation units 5a to 5e included in stages 3a to 3e are synthesized in series by the series connection unit 14 as shown in FIG. 4, and the voltage across both ends of this series connection unit 14 is output as a DC pulse voltage Pv between the high potential output terminal 12 and the low potential output terminal 13 via the current limiting resistor 63. This DC pulse voltage Pv is a voltage of the pattern having 5 stages, 6 levels, and 10 periods shown in FIG. 2, and is applied to the plasma load circuit 11 including the capacitor Cp and the resistor Rp. The resistor 61 is a voltage dividing resistor for the DC pulse voltage Pv, and the resistor 62 is a monitoring resistor for detecting the voltage waveform of the DC pulse voltage Pv. The waveform detected by this monitoring resistor 62 is fed back to the voltage pattern setting unit 6. The voltage pattern setting unit 6 that has received the detected waveform appropriately corrects the voltage pattern information in order to obtain the target accurate waveform shape. Thereby, in particular, the voltage drop due to the current limiting resistor 63 is corrected, and a voltage waveform of a desired shape can be applied to the plasma load circuit 11.

[0059] The device described above configures the circuit with the low potential side of the stage voltage Vs generated by the stage voltage generation units 4a to 4e as the common line. However, the circuit may be configured by moving the output side coupling capacitor and the output side reactor of the isolated bidirectional Cuk converter to the low potential side with the high potential side of the stage voltage Vs as the common line. Even in that case, it is obvious to those skilled in the art that the circuit operation is exactly the same as when the low potential side is the common line. In addition, as described above, in FIG. 1, the low potential output terminal 13 is grounded, but it can also be changed to ground the high potential output terminal 12, and the insertion positions of the current limiting resistor 63 and the monitoring resistor 62 can be moved according to which is the ground potential. As shown in FIG. 2, in the above device, it was assumed that the pulse was formed in the positive direction with reference to 0V (ground potential). However, it is also obvious that the circuit can be operated so that the high potential output terminal 12 is grounded and a pulse that rises in the negative direction with reference to the ground potential (that is, a pulse having a polarity opposite to the pulse waveform shown in FIG. 2) is formed as described in Patent Document 3.

[0060] In FIG. 4, resonance capacitors 56a to 56e are provided between the output terminals of the pulse voltages [1]Ps to [5]Ps of each stage 3a to 3e and the line on the low potential side of the stage voltage Vs. However, regardless of whether the common line is on the high potential side or the low potential side, these resonance capacitors 56a to 56e may be provided between the output terminals and the line on the high potential side of the stage voltage Vs (this point will also be clear from the description below). Further, two resonance capacitors each having a capacitance value of 1 / 2 of the resonance capacitors 56a to 56e may be provided between the output terminal and the line on the high potential side of the stage voltage Vs and between the output terminal and the line on the low potential side of the stage voltage Vs, respectively. That is, the resonance capacitors 56a to 56e may be each divided into two and arranged on the high potential side and the low potential side. Furthermore, instead of the five resonance capacitors 56a to 56e connected in series, a high voltage rated capacitor obtained by combining them into one may be provided, or the capacitor combined into one and the resonance capacitors 56a to 56e of each stage may be provided together.

[0061] [Second Embodiment] FIG. 5 is a schematic block configuration diagram of the DC pulse power supply device 1 according to the second embodiment. FIG. 6 is a diagram showing an example of an ideal waveform of the output voltage by the DC pulse power supply device 1 according to the second embodiment. FIG. 7 is a list of the values of the DC pulse voltage Pv, the operation states of the stages that output the pulse voltage Ps and the variable pulse voltage ΔP in each period Ta, Tb, Tc, Td shown in FIG. 6. FIGS. 5 and 6 are drawings corresponding to FIGS. 1 and 2 in the first embodiment, and the same or corresponding elements are denoted by the same reference numerals, and overlapping descriptions are omitted unless particularly necessary. The schematic configuration and operation of the DC pulse power supply device 1 according to the second embodiment will be described with reference to FIGS. 5 to 7.

[0062] As shown in FIG. 5, the DC pulse power supply device 1 of the present embodiment has, as an example, five stages 3a to 3e similar to those of the first embodiment and two additional variable voltage stages 7a and 7b. That is, the DC pulse power supply device 1 has a P / N voltage generation unit 2, stage voltage generation units 4a to 4e, pulse generation units 5a to 5e, and a series connection unit 14, and in addition, based on the P / N voltage V P / N generated by the P / N voltage generation unit 2, additional variable voltage generation units 8a and 8b that generate mutually insulated and independent additional variable voltages ΔV2 and ΔV3 respectively, a variable pulse generation unit 9a that generates a variable pulse voltage ΔP2 based on the voltage ΔV2, and a variable pulse generation unit 9b that generates a variable pulse voltage ΔP3 based on the voltage ΔV3. The voltage pattern setting unit 6 outputs, in addition to the respective instruction signals shown in FIG. 1, instruction signals for the additional variable voltage generation units 8a and 8b and the variable pulse generation units 9a and 9b.

[0063] The variable pulse voltages ΔP2 and ΔP3 respectively output from the variable pulse generation units 9a and 9b are serially combined by the series connection unit 14 with the pulse voltages [1]Ps to [5]Ps output from the respective stages 3a to 3e, and based on this, a DC pulse voltage Pv is output between the high potential output terminal 12 and the low potential output terminal 13. Similar to the first embodiment, either the high potential output terminal 12 or the low potential output terminal 13 can be set to the ground potential.

[0064] The voltage pattern setting unit 6 determines the number of stages of the stage voltage Vs with respect to the intermediate voltage value V2 of the DC pulse voltage waveform in order to generate the stage voltages [1]Vs to [5]Vs with respect to the peak value V1 of the DC pulse voltage waveform, and outputs an instruction signal to each of the stage voltage generation units 4a to 4e. Also, in order to generate the additional variable voltage ΔV2, an instruction signal corresponding to the set value of ΔV2 is instructed to the additional variable voltage generation unit 8a. Similarly, the voltage pattern setting unit 6 determines the number of stages of the stage voltage Vs with respect to the intermediate voltage value V3, outputs an instruction signal to each of the stage voltage generation units 4a to 4e, and outputs an instruction signal corresponding to the set value of ΔV3 to the additional variable voltage generation unit 8b in order to generate the additional variable voltage ΔV3.

[0065] Further, the voltage pattern setting unit 6 outputs a setting signal to the P / N voltage generation unit 2 to generate the stage voltages [1] to [5] Vs or a P / N voltage V that is even higher than those supplied to the stage voltage generation units 4a to 4e and the additional variable voltage generation units 8a and 8b. To generate the pulse voltages [1] Ps to [5] Ps and the variable pulse voltages ΔP2 and ΔP3 for each of the stages 3a to 3e, 7a, and 7b, the pulse generation units 5a to 5e and the variable pulse generation units 9a and 9b are output with setting signals for Ps1 to Ps5, ΔP2, and ΔP3 with respect to the start time, end time, period, and cycle (pulse frequency) of the DC pulse voltage waveform. Here, the number of stages 3a to 3e for the intermediate voltage value V2 or V3 is the value of the quotient obtained by dividing that voltage value by a predetermined stage voltage Vs, and the additional variable voltage ΔV2 or ΔV3 is the value of the remainder. P / N In addition, in order to generate P / N it, a setting signal is output to the P / N voltage generation unit 2.

[0066] As shown in FIGS. 6 and 7, by simultaneously starting the output of the pulse voltages [1] Ps to [3] Ps and the additional variable pulse voltage ΔP2 at time T0, the voltage value of the DC pulse voltage Pv in the period Ta is Pv = V2 = 3·Vs + ΔV2. At time T1, the pulse voltages [1] Ps to [3] Ps continue to be output, and in addition, the pulse voltages [4] Ps and [5] Ps are output, while the additional variable pulse voltage ΔP2 is cut off. As a result, the voltage value of Pv in the period Tb is Pv = V1 = 5·Vs.

[0067] Next, at time T2, the pulse voltage [1] Ps continues to be output, and a new additional variable pulse voltage ΔP3 is output, while the pulse voltages [2] Ps to [5] Ps are cut off. As a result, the voltage value of Pv in the period Tc is Pv = V3 = Vs + ΔV3. At time T3, since both the pulse voltage [1] Ps and the additional variable pulse voltage ΔP3 are cut off, Pv = 0 in the period Td. As described above, the waveform of the DC pulse voltage Pv, which is the added value of the voltages in each of the periods Ta, Tb, Tc, and Td within one cycle T as shown in FIG. 6, is obtained.

[0068] Thus, in the DC pulse power supply device 1 of this second embodiment, the voltage obtained by dividing the maximum peak value V1 of the DC pulse voltage by the number of stages 5 is used as the stage voltages [1]Vs to [5]Vs, and additional variable voltages ΔV2 and ΔV3 that are variable within the range of 0 to Vs are provided for the intermediate voltage values V2 and V3 that are lower than the peak value V1. As a result, the stage voltages [1]Vs to [2]Vs are the same between each period, and the stages 3a to 3e that output the stage voltage Vs can be shared, thus simplifying the configuration.

[0069] Also, in FIG. 5, the stage 3e that outputs the pulse voltage [5]Ps is replaced with another variable voltage stage that generates the variable pulse voltage ΔP1, and the voltage obtained by dividing the maximum peak value V1 of the DC pulse voltage by the number of stages 5 is used as the stage voltages [1]Vs to [4]Vs. By providing additional variable voltages ΔV1, ΔV2, and ΔV3 that can be independently variable between a minimum value of 0 and a maximum value of Vs for the peak value V1, the intermediate voltage values V2, and V3, the voltage value of the DC pulse voltage Pv in the period Tb may be set such that Pv = V1 = 4·Vs + ΔV1.

[0070] Next, the configuration and operation of each part of the DC pulse power supply device 1 of this second embodiment will be described. Since the P / N voltage generation unit 2 is the same as that of the DC pulse power supply device of the first embodiment, the description thereof will be omitted. FIG. 8 is a schematic circuit configuration diagram showing an example of the stage voltage generation units 4a to 4e, 8a, 8b and the pulse generation units 5a to 5b, 9a, 9b. The description of the configuration and operation of the isolated bidirectional Cuk converters in each of the stage voltage generation units 4a to 4e, 8a, 8b is the same as that of the first embodiment, and thus the description thereof will be omitted.

[0071] That is, also in this second embodiment, when the stage voltages [1]Vs to [5]Vs, additional variable voltages ΔV2 and ΔV3 increase due to various factors as described later, and charge is regenerated from the capacitive plasma load circuit 11, the increased charge is regenerated to the capacitor 28 in the input stage by the operation of the isolated bidirectional Cuk converter based on the control of the second control unit 102. Further, the charge regenerated to the capacitor 28 is output through the other stage voltage generation units 4a to 4e, 8a, and 8b where the stage voltages [1]Vs to [5]Vs, additional variable voltages ΔV2 and ΔV3 do not increase. Thus, also in the DC pulse power supply device 1 of this second embodiment, since the regenerative energy is immediately recycled by using the isolated bidirectional Cuk converter, the stage voltages [1]Vs to [5]Vs, additional variable voltages ΔV2 and ΔV3 can be efficiently controlled to predetermined voltage values.

[0072] In FIG. 8, the pulse generation units 5a to 5e and the variable pulse generation units 9a and 9b can be, for example, those using the circuits in the pulse power supply devices described in Patent Documents 1 and 2. The pulse generation units 5a to 5e and the variable pulse generation units 9a and 9b shown in FIG. 8 use the circuits described in Patent Document 2 and include series circuits of switching elements 51a to 51e and switching elements 52a to 52e, series circuits of switching elements 54a to 54e and switching elements 55a to 55e, resonance reactors 53a to 53e, and resonance capacitors 56a to 56e. The stage voltages [1]Vs to [5]Vs generated in the stage voltage generation units 4a to 4e are independently input to the pulse generation units 5a to 5e, respectively. Further, the variable pulse generation units 9a and 9b include series circuits of switching elements 91a, 91b and switching elements 92a, 92b, series circuits of switching elements 94a, 94b and switching elements 95a, 95b, resonance reactors 93a, 93b, and resonance capacitors 96a, 96b. The stage voltages ΔV2 and ΔV3 generated in the additional variable voltage generation units 8a and 8b are independently input to the variable pulse generation units 9a and 9b, respectively.

[0073] The switching elements 51a to 51e and 91a, 91b are the first semiconductor switching section, the switching elements 52a to 52e and 92a, 92b are the second semiconductor switching section, the switching elements 54a to 54e and 94a, 94b are the third semiconductor switching section, and the switching elements 55a to 55e and 95a, 95b are the fourth semiconductor switching section. The second control unit 102, which is a local control unit, alternately turns on the first semiconductor switching section and the second semiconductor switching section at a predetermined time interval determined by the resonance period, and turns on the third semiconductor switching section between the time when the first semiconductor switching section turns off and the time when the second semiconductor switching section turns on, and turns on the fourth semiconductor switching section between the time when the second semiconductor switching section turns off and the time when the first semiconductor switching section turns on, to control the on / off operation of each semiconductor switching section. As a result, pulse voltages [1]Ps to [5]Ps with voltage values of stage voltages [1]Vs to [5]Vs at respective predetermined pulse periods are obtained across the switching elements 55a to 55e. Also, variable pulse voltages ΔP2, ΔP3 with voltage values of additional variable voltages ΔV2, ΔV3 at respective predetermined pulse periods are obtained across the switching elements 95a, 95b.

[0074] When the switching elements 51a to 51e or the switching elements 52a to 52e turn on and when the pulse voltages [1]Ps to [5]Ps rise and fall, waveforms of the rise and fall of the DC pulse voltage are formed by resonance operation in a circuit including the resonance reactors 53a to 53e, the resonance capacitors 56a to 56e, and the capacitance Co of the plasma load circuit 11. Also, when the switching elements 91a, 91b or the switching elements 92a, 92e turn on and when the variable pulse voltages ΔP2, ΔP3 rise and fall, waveforms of the rise and fall of the DC pulse voltage are formed by resonance operation in a circuit including the resonance reactors 93a, 93b, the resonance capacitors 96a, 96b, and the capacitance Cp of the plasma load circuit 11. As a result, the pulse voltages [1]Ps to [5]Ps and the variable pulse voltages ΔP2, ΔP3 rise or fall with steep edges formed by resonance. By such a waveform shaping method, it is possible to shorten the rise time and fall time of the DC pulse voltage while suppressing power loss.

[0075] The pulse voltages [1]Ps to [5]Ps respectively obtained by the operations of the five stages 3a to 3e including the stage voltage generation units 4a to 4e and the pulse generation units 5a to 5e, and the variable pulse voltages ΔP2 and ΔP3 respectively obtained by the operations of the variable voltage stages 7a and 7b including the additional variable voltage generation units 8a, 8b and the variable pulse generation units 9a, 9b are all synthesized in series by the series connection unit 14, and from both ends of this series connection unit 14, it is output as a DC pulse voltage Pv between the high potential output terminal 12 and the low potential output terminal 13 via the current limiting resistor 63. The DC pulse voltage Pv is a DC pulse voltage having a pattern of 5 stages + 2 variable voltage stages, 4 levels, and 4 periods as shown in FIG. 6, and this pulse voltage is applied to the plasma load circuit 11 including the capacitor Cp and the resistor Rp. Regarding the configurations and functions of the resistors 61 to 63 shown in FIG. 8 and capacitors and the like that can be added, since they are the same as those in the first embodiment, the description is omitted.

[0076] It is obvious that various modifications or changes in the circuit configuration or operation of the DC pulse power supply device 1 of the first embodiment can also be similarly applied to the DC pulse power supply device 1 of this second embodiment.

[0077] [Problems of voltage rise due to capacitive load] As described above, in the DC pulse power supply device 1 of the first and second embodiments, by using an isolated bidirectional Cuk converter (or another type of isolated bidirectional converter) in the stage voltage generation unit, the energy released from the capacitive plasma load circuit 11 to the power supply side is favorably regenerated in the capacitor 28, and the regenerated energy is promptly and effectively utilized. The release of energy from such a capacitive load to the power supply side particularly poses a problem in a multi-stage configuration that generates a DC pulse voltage by serially synthesizing the outputs of multiple stages. This is because if the voltage of the power supply increases only in some of the multiple stages, an imbalance may occur and a pulse voltage waveform of a desired shape may not be generated. Here, the phenomenon and problems of the voltage increase of the power supply occurring in a part of an independent stage in the above-described multi-stage DC pulse power supply device will be described.

[0078] The above voltage increase occurs when discharging charges to a single or a small number of stages from a capacitive load circuit charged to a high voltage by synthesizing the output voltages of a large number of stages in series, as in the DC pulse power supply device 1 of the first embodiment, or when there is a slight deviation while most of the resonance periods in each stage overlap.

[0079] First, with reference to FIGS. 9 and 10, the phenomenon when discharging the charge from a capacitive load charged to a high voltage to a low-voltage power supply-side capacitor will be described. FIG. 9 shows, for the ideal waveform (a) of the DC pulse voltage Pv which is 5 stages, 3 levels, and 3 periods, the actual waveform (b) of the pulse voltage Pv including the edge resonance waveform, and the reactor current Li (c) and (d), the power supply current Pi (e) and (f), and the waveform (g) of the gate drive signal G of the switching element when applying the pulse generation unit (that is, the pulse generation circuit in the device described in Patent Document 1) used in the DC pulse power supply device 1 of the first embodiment. To avoid complexity, the dead time between each switching element is ignored. Further, FIG. 10 shows the current paths of the current Ci (Cp) of the capacitor Cp of the plasma load circuit 11, the currents Ci (56b - 56e) of the resonance capacitors 56b to 56e, and the current Li (53a) of the resonance reactor 53a in the period β starting from the time T1 shown in FIG. 9. Here, each stage voltage generation unit is simply indicated by the symbol of the DC power supply (the same applies to FIGS. 11, 13, 14, 16 - 19, 21 - 24). In the period β, the switching elements 51b - 51e, 52a are off, and the switching elements 52b - 52e, 51a are on.

[0080] When the charge of the capacitor Cp charged to 5·Vs is discharged in the period β, as shown by the broken line in FIG. 10, the sum value of the resonance reactors 53b - 53e and the resonance current Ci (Cp) by the capacitor Cp flow, and the capacitor 49a that has been charged to Vs until then is further charged by the power supply current [1] Pi that changes as shown in FIG. 9(f). At the same time, the currents Ci (56b - 56e) of the resonance capacitors 56b - 56e flow independently for each stage due to resonance with the resonance reactors 53b - 53e as shown by the two-dot chain line in FIG. 10, and the resonance capacitors 56b - 56e are discharged. On the other hand, in stage [1], there is no period in which the above-described resonance occurs in the other stages [2] - [5], and the reactor current Li (53a) shown by the one-dot chain line in FIG. 10 flows as a freewheeling current through the resonance reactor 53a.

[0081] That is, comparing with the waveforms of the power supply currents [2]Pi to [5]Pi in the stages [2] to [5] as shown in FIG. 9(e), it can be seen that an extra current Ci (Cp) flows in the power supply current [1]Pi of the stage [1] as shown in FIG. 9(f). An imbalance occurs between the charging current and the discharging current of the capacitor 49a. When the charging current thus increases, the charging voltage of the capacitor 49a rises. Usually, the resistance Rp of the plasma load circuit 11 is, for example, 1 MΩ with no load or in a light load state close to this. In such a case, the discharging current due to the load current can be regarded as substantially non-existent. Due to the above phenomena, the level of V2 in the actual waveform of the pulse voltage Pv rises above the original stage voltage Vs, and accordingly, the level of V1 also rises beyond 5·Vs. Such voltage increases are likely to occur when the pulse frequency is high, the potential difference between V1 and V2, the resistance Rp of the plasma load circuit 11, and the capacitor Cp are large respectively.

[0082] FIG. 11 shows the current path when the configuration is changed so that the high potential side of the output of the stage voltage generation unit (DC power supply in the figure) is the common line in the circuit shown in FIG. 10. Here, the positions of the resonance capacitors 56a to 56e are changed so that they are arranged between the output terminals of each stage and the high potential side. In accordance with the change, the symbols of the series-connected switching elements 51a to 51e and switching elements 52a to 52e, and the series-connected diodes 54a to 54e and diodes 55a to 55e are interchanged between the high potential side and the low potential side. As can be seen by comparing the current path in FIG. 11 with the current path in FIG. 10, except for the change in the current path corresponding to the change in the common line, the circuit operation is exactly the same. Therefore, the same problems as those in the circuit shown in FIG. 10 can occur in this circuit.

[0083] FIG. 12, similar to FIG. 9, shows the actual waveform (b) of the pulse voltage Pv including the edge resonance waveform, the reactor currents Li (c) and (d), the power supply currents Pi (e) and (f), and the waveform (g) of the gate drive signal G of the switching element when the pulse generation circuit in the device described in Patent Document 2 is applied to the ideal waveform of the DC pulse voltage Pv having 5 stages, 3 levels, and 3 divided periods. FIG. 13 shows the current paths of the current Ci (Cp) of the capacitor Cp of the plasma load circuit 11 and the currents Ci (56b to 56e) of the resonance capacitors 56b to 56e in the period β starting from the time T1 shown in FIG. 12. In this period β, the switching elements 51a to 51e, 52a, 54b to 54e, 55a to 55e are off, and the switching elements 52b to 52e, 54a are on.

[0084] As described above, when the charge of the capacitor Cp charged to 5·Vs is discharged in the period β, as shown by the broken line in FIG. 13, the resonance current Ci (Cp) by the added value of the resonance reactors 53b to 53e and the capacitor Cp flows, and the capacitor 49a, which has been charged to Vs until then, is further charged by the power supply current [1] Pi that changes as shown in FIG. 12(f). At the same time, the currents Ci (56b to 56e) of the resonance capacitors 56b to 56e flow due to resonance with the resonance reactors 53b to 53e independently for each stage as shown by the two-dot chain line in FIG. 13, and the resonance capacitors 56b to 56e are discharged. On the other hand, in stage [1], there is no period in which the above-described resonance occurs in other stages, and the path passing through the resonance reactor 53a is blocked, so no freewheel current flows. Similar to FIG. 9, it can be seen that an extra charging current Ci (Cp) flows in the power supply current [1] Pi of stage [1] shown in FIG. 12(f) compared to the waveforms of the power supply currents [2] Pi to [5] Pi of stages [2] to [5] shown in FIG. 12(e).

[0085] FIG. 14 shows a current path when the configuration is changed so that the high potential side of the output of the stage voltage generation unit (DC power supply in the figure) is used as the common line in the circuit shown in FIG. 13. The same change as the circuit configuration shown in FIG. 11 is made, and detailed description is omitted. As can be seen by comparing the current path in FIG. 14 with the current path in FIG. 13, the circuit operation is exactly the same except for the change in the current path corresponding to the change in the common line. Therefore, the same problem as the circuit shown in FIG. 13 can occur in this circuit.

[0086] As described above, even when the pulse generation circuits described in Patent Document 2 are used for the pulse generation units 5a to 5e, the charging voltage of the capacitor 49a increases when the charging current becomes large, similar to the case when the pulse generation circuit described in Patent Document 1 is used. Therefore, if no countermeasure is taken, the level of V2 due to the actual waveform of the pulse voltage Pv will rise above Vs, and accordingly, the level of V1 will also rise beyond 5·Vs. Also, the conditions under which the voltage easily rises are the same as described above.

[0087] In the DC pulse power supply device 1 of the first and second embodiments, as described above, when the voltage across the capacitors 49a to 49e at some stages rises, under the control of the second control unit 102 based on the detected value, the isolated bidirectional Cuk converter operates, and the charge due to the rising voltage is regenerated to the capacitor 28 on the input side. Thereby, the rise in the voltage across the capacitors 49a to 49e at some stages is suppressed, and the level of the output DC pulse voltage can be made as desired. Furthermore, since the energy regenerated to the capacitor 28 is recycled, effective utilization of power can be achieved.

[0088] Next, the case where the resonance periods of each stage mostly overlap with some deviation will be described. FIG. 15 shows the actual waveform (c) of the pulse voltage Pv including the edge resonance waveform, the reactor currents Li (d) and (e) of each stage, the diode currents Di (f) and (g) in the delayed stage [2], the power supply currents Pi (h) and (i), and the waveform (j) of the gate drive signal G of the switching element when the pulse generation circuit described in Patent Document 1 is applied under the condition that a delay time difference δ occurs between the pulse voltage [1] Ps of stage [1] and the pulse voltage [2] Ps of stage [2] with respect to the ideal waveform of the DC pulse voltage Pv which is 2-stage, 2-level, and 2-period. Here, a delay time difference δ is provided in all on / off operations for the gate drive signal G (51a, 52a) of the first stage with respect to the gate drive signal G (51b, 52b) of the second stage. Also, although it is originally 5-stage, only 2 stages are taken up for simplicity of explanation, and the dead time between the switching elements is ignored.

[0089] Let the time when the reactor current Li (53a) increases from time t0 and crosses 0 be ta, and then, when the resonance currents Ci (Cp), Ci (56a) both start to flow and the time when the resonance current Ci (Cp) and the reactor current Li (53b) become the same value be tb, and the period from time ta to time tb be α. FIG. 16 shows the current paths of the resonance currents Ci (Cp), Ci (56a), and the reactor current Li (53b) in period α. In this period, the switching elements 51a, 51b are on and 52a, 52b are off.

[0090] Next, let the time when the reactor current Li (53a) decreases from time t1 and crosses 0 be tc, and then, when the resonance currents Ci (Cp), Ci (56a) both start to flow and the time when the resonance current Ci (Cp) and the reactor current Li (53b) become the same value be td, and the period from time tc to time td be γ. FIG. 17 shows the current paths of the resonance currents Ci (Cp), Ci (56a) and the reactor current Li (53b) in period γ. In this period, the switching elements 51a, 51b are off and 52a, 52b are on.

[0091] First, in FIG. 16, just before time t0, a freewheel current flows through the resonance reactor 53a in the path of resonance reactor 53a → switching element 52a → diode 55a → resonance reactor 53a. At time t0, when the switching element 52a turns off and the switching element 51a turns on, a regenerative current flows in the path of resonance reactor 53a → switching element 51a → capacitor 49a → diode 55a → resonance reactor 53a. As a result, a voltage [1] Vs is applied to the resonance reactor 53a, and the reactor current Li(53a) increases linearly from a negative value toward 0 with a slope of di / dt = V / L. At time ta, when the reactor current Li(53a) becomes 0, the diode 55a cuts off, and during the period α until time tb, a resonance current Ci(Cp) indicated by a dashed line and a resonance current Ci(56a) indicated by a two-dot chain line in FIG. 16 flow. On the other hand, just before time t0δ, a freewheel current flows through the resonance reactor 53b in the path of resonance reactor 53b → switching element 52b → diode 55b → resonance reactor 53b.

[0092] At time t0δ, when the switching element 52b turns off and the switching element 51b turns on, a voltage [2] Vs is applied to the resonance reactor 53b, and the reactor current Li(53b) increases linearly from a negative value toward 0 with a slope of di / dt = V / L. And until the current exceeds 0, a regenerative current flows in the direction opposite to that indicated by a one-dot chain line in FIG. 16.

[0093] When a resonant current Ci(Cp) flows at time ta, both the resonant current and the reactor current Li(53b) flow through the diode 55b as a common path, and the reactor current Li(53b) flows in the direction indicated by the dashed-dotted line in Fig. 16 exceeding 0. At time tb, when the resonant current Ci(Cp) and the reactor current Li(53b) become the same value, the diode 55b cuts off and the diode current Di(55b) becomes 0. Instead of the resonance system composed of the voltage [1]Vs, the resonant reactor 53a, and the capacitor Cp, and the resonance system composed of the voltage [1]Vs, the resonant reactor 53a, and the resonant capacitor 56a starting from time ta, a new resonance system starting from time tb, composed of the voltage [1]Vs + [2]Vs, the resonant reactor 53b, and the capacitor Cp charged to Vp at time tb, and a new resonance system composed of [2]Vs, the resonant reactor 53b, and the resonant capacitor 56b cause the resonant currents Ci(Cp) and Ci(56b) to start flowing again, which continues until the DC pulse voltage Pv rises to the voltage [1]Vs + [2]Vs. Here, the resonant reactor 53a is in a freewheel state, and the current Ci(Cp) flows through the diode 54a.

[0094] Next, in Fig. 17, immediately before time t1, a freewheel current due to the resonant reactor 53a flows through the path of the resonant reactor 53a → diode 54a → switching element 51a → resonant reactor 53a. At time t1, when the switching element 51a turns off and the switching element 52a turns on, a regenerative current flows through the path of the resonant reactor 53a → diode 54a → capacitor 49a → switching element 52a → resonant reactor 53a. As a result, a reverse stage voltage -[1]Vs is applied to the resonant reactor 53a, and the reactor current Li(53a) linearly decreases from a positive value to 0 with a slope of di / dt = -V / L. At time tc, when the reactor current Li(53a) becomes 0, the diode 54a cuts off, and during the period γ until time td, the resonant current Ci(Cp) indicated by the broken line and the resonant current Ci(56a) indicated by the two-dot chain line in Fig. 17 flow.

[0095] On one hand, just before time t1δ, a freewheel current flows through the resonant reactor 53b in the path of resonant reactor 53b → diode 54b → switching element 51b → resonant reactor 53b. At time t1δ, when the switching element 51b turns off and the switching element 52b turns on, a reverse voltage -[2]Vs is applied to the resonant reactor 53b, and the reactor current Li(53b) decreases linearly from a positive value to 0 with a slope of di / dt = -V / L. Until the current exceeds 0, it flows in the direction opposite to that indicated by the dashed line in Fig. 17.

[0096] When the resonant current Ci(Cp) flows at time tc, both the resonant current and the reactor current Li(53b) flow through the diode 54b as a common path, and the reactor current Li(53b) flows beyond 0 in the direction indicated by the dashed line in Fig. 17. When the resonant current Ci(Cp) and the reactor current Li(53b) reach the same value at time td, the diode 54b cuts off and the diode current Di(54b) becomes 0. Instead of the capacitor Cp charged to [1]Vs + [2]Vs, the voltage -[2]Vs, and the resonant system formed by the resonant reactor 53a starting from time tc, and the resonant capacitor 56a charged to [1]Vs and the resonant system formed by the resonant reactor 53a, a new resonant system formed by the capacitor (Cp) with the charging voltage Vp at time td and the resonant reactor 53b starting from time td, and a new resonant system formed by the resonant capacitor 56b with the charging voltage of [2]Vs and the resonant reactor 53b causes the resonant currents Ci(Cp) and Ci(56b) to start flowing again, which continues until the DC pulse voltage Pv drops to 0. Here, the resonant reactor 53a is in a freewheel state, and the current Ci(Cp) flows through the diode 55a.

[0097] During the period γ in the operation description of the above-described resonance period, since the resonance current Ci (Cp) indicated by the broken line in FIG. 16 charges the capacitor 49b, compared with the waveform of the power supply current [1] Pi in stage [1] shown in FIG. 15(i), in the power supply current [2] Pi in stage [2] shown in FIG. 15(h), it can be seen that an extra charging current observed in the diode current Di (54b) shown in FIG. 15(f) flows. That is, due to the imbalance between the charging current and the discharging current of the capacitor 49b, when the charging current becomes large in this way, surplus charges are generated in the capacitor 49b. At this time, when the resistance Rp of the plasma load circuit 11 is a light load close to no load, for example, 1 MΩ, the discharging current due to the load current can be regarded as substantially non-existent.

[0098] Due to the above phenomena, when the power regeneration of the surplus charges of the capacitor 49b by the isolated bidirectional converter is not performed in the stage voltage generation unit, the level of [2] V2 in the actual waveform of the pulse voltage Pv rises above Vs, and accordingly, the level of V1 also rises beyond 2·Vs. This voltage rise is likely to occur when the pulse frequency is high, the voltage level of V1 is large, the delay time difference δ within the resonance period is large, the resistance Rp of the plasma load circuit 11 is large, the capacitor Cp is large, etc.

[0099] FIGS. 18 and 19 show current paths when the configuration is changed such that the high potential side of the output of the stage voltage generation unit (DC power supply in the figure) is used as the common line in the circuits shown in FIGS. 16 and 17. The same change as the circuit configuration shown in FIG. 11 has been made, and detailed description is omitted. As can be seen by comparing the current path in FIG. 18 with the current path in FIG. 16 and comparing the current path in FIG. 19 with the current path in FIG. 17, the current path changes according to the change of the common line, and the basic circuit operation is the same except that the direction of the freewheel current and the regeneration current flowing through the resonance reactors 53a and 53b is reversed. Therefore, the same problems as those in the circuits shown in FIGS. 16 and 17 can occur in this circuit.

[0100] FIG. 20 shows, as in FIG. 15, the actual waveform (c) of the pulse voltage Pv including the edge resonance waveform, the reactor currents Li (d) and (e) of each stage, the diode currents Di (f) and (g) in the delayed stage [2], the power supply currents Pi (h) and (i), and the waveform (j) of the gate drive signal G of the switching element, when the pulse generation circuit described in Patent Document 2 is applied to the pulse generation unit under the condition that a delay time difference δ occurs between the pulse voltage [1] Ps of stage [1] and the pulse voltage [2] Ps of stage [2] with respect to the ideal waveform of the DC pulse voltage Pv which is two-stage, two-level, and two-period. Here too, a delay time difference δ is provided in all on / off operations for the gate drive signal G (51a, 52a) of the first stage with respect to the gate drive signal G (51b, 52b) of the second stage.

[0101] Since the reactor current Li (53a) is 0 at time t0, time t0 and time ta coincide, and then the resonance currents Ci (Cp), Ci (56a) start to flow. Let the period from time ta until the time tb when the resonance current Ci (Cp) and the reactor current Li (53b) become the same value be α. FIG. 21 shows the current paths of the resonance currents Ci (Cp), Ci (56a), and the reactor current Li (53b) during the period α. During this period, the switching elements 51a, 51b are on, and the switching elements 52a, 52b, 54a, 54b, 55a, 55b are off. Also, since the reactor current Li (53a) is 0 at time t1, time t1 and time tc coincide, and then the resonance currents Ci (Cp), Ci (56a) start to flow. Let the period from time tc until the time td when the resonance current Ci (Cp) and the reactor current Li (53b) become the same value be γ. FIG. 22 shows the current paths of the resonance currents Ci (Cp), Ci (56a), and the reactor current Li (53b) during the period γ. During this period, the switching elements 51a, 51b, 54a, 54b, 55a, 55b are off, and the switching elements 52a, 52b are on.

[0102] First, in FIG. 21, when the switching element 52a is off and the switching element 51a is on at time t0, a resonance current Ci (Cp) indicated by a broken line and a resonance current Ci (56a) indicated by a two-dot chain line in FIG. 21 flow during a period α from time ta (= t0) to time tb. On the other hand, at time t0δ, when the switching element 52b is off and the switching element 51b is on, a voltage [2] Vs is applied to the resonance reactor 53b, and a reactor current Li (53b) flows in the direction indicated by a one-dot chain line in FIG. 21 with a slope of di / dt = V / L using the parasitic diode of the switching element 55b as a common path. When the resonance current Ci (Cp) and the reactor current Li (53b) become the same value at time tb, the current Si (55b) of the parasitic diode is cut off and becomes 0. Then, instead of the resonance system composed of the voltage [1] Vs, the resonance reactor 53a, and the capacitor Cp, and the resonance system composed of the voltage [1] Vs, the resonance reactor 53a, and the resonance capacitor 56a starting from time ta, a new resonance system composed of the voltage [1] Vs + [2] Vs, the resonance reactor 53b, and the capacitor Cp charged to Vp at time tb, and a new resonance system composed of the voltage [2] Vs, the resonance reactor 53b, and the resonance capacitor 56b starting from time tb cause the resonance currents Ci (Cp) and Ci (56b) to start flowing again, which continues until the DC pulse voltage Pv rises to the voltage [1] Vs + [2] Vs. Here, the resonance reactor 53a is in a free-wheeling state, and Ci (Cp) flows through the parasitic diode of the switching element 54a.

[0103] Next, in FIG. 22, when the switching element 51a is off and the switching element 52a is on at time t2, a resonance current Ci (Cp) indicated by a broken line and a resonance current Ci (56a) indicated by a two-dot chain line in FIG. 22 flow during a period γ from time tc (= t2) to time td. On the other hand, when the switching element 51b is off and the switching element 52b is on at time t2δ, a voltage -[2]Vs is applied to the resonance reactor 53b, and a reactor current Li (53b) flows in the direction indicated by a one-dot chain line in FIG. 22 with a slope of di / dt = -V / L using the parasitic diode of the switching element 54b as a common path. When the resonance current Ci (Cp) and this reactor current Li (53b) become the same value at time td, the current Si (54b) of the parasitic diode is cut off and becomes zero. Then, instead of the resonance system composed of the capacitor Cp charged with the voltage [1]Vs + [2]Vs starting from time tc, the stage voltage -[2]Vs, and the resonance reactor 53a, a new resonance system starting from time td, including the capacitor Cp charged to Vp at time td, the resonance reactor 53b, and the resonance capacitor 56b charged with [2]Vs, and the resonance reactor 53b, causes the resonance currents Ci (Cp) and Ci (56b) to start flowing again, and they flow until the DC pulse voltage Pv becomes zero. Here, the resonance reactor 53a is in a freewheeling state, and Ci (Cp) flows through the parasitic diode of the switching element 55a.

[0104] During the period γ in the operation explanation of the above-described resonance period, since the resonance current Ci (Cp) indicated by a broken line in FIG. 21 charges the capacitor 49b, compared with the waveform of the power supply current [1]Pi of stage [1] shown in FIG. 20(i), in the power supply current [2]Pi of stage [2] shown in FIG. 20(h), an extra charging current is observed in the parasitic diode current Si (54b) of the switching element 54b, which is the difference between the resonance current Ci (Cp) and the reactor current Li (53b) shown in FIG. 20(f). As a result, surplus charges are generated in the capacitor 49b.

[0105] Figures 23 and 24 show current paths when the configuration is changed so that the high-potential side of the output of the stage voltage generation unit (DC power supply in the figure) is the common line in the circuits shown in Figures 21 and 22. The same changes as those in the circuit configuration shown in Figure 11 have been made, and detailed explanations are omitted. As can be seen by comparing the current path in Figure 23 with the current path in Figure 21 and the current path in Figure 24 with the current path in Figure 21, the current path changes according to the change of the common line, and except that the direction of the freewheel current and the regenerative current flowing through the resonance reactors 53a and 53b is reversed, the basic circuit operation is the same. Therefore, similar problems to those in the circuits shown in Figures 21 and 22 can occur in this circuit as well.

[0106] Thus, even when the pulse generation circuit described in Patent Document 2 is adopted as the pulse generation unit, a phenomenon occurs in which surplus charge is generated in the capacitor 49b, similar to the case where the pulse generation circuit described in Patent Document 1 is adopted. Therefore, if no countermeasure is taken, the charging voltage of the capacitor 49b may increase, and a problem may occur that the peak value of the output DC pulse voltage does not become as desired. On the other hand, in the DC pulse power supply device 1 of the first and second embodiments, as described above, when the voltage across the capacitors 49a to 49e of some stages increases, under the control of the second control unit 102 based on the detected value, the isolated bidirectional Cuk converter operates, and the charge due to the increased voltage is regenerated to the capacitor 28 on the input side. Thereby, the increase in the voltage across the capacitors 49a to 49e of some stages is suppressed, and the level of the output DC pulse voltage can be made as desired. Furthermore, since the energy regenerated to the capacitor 28 is recycled, effective utilization of power can be achieved.

[0107] It should be noted that the above embodiments and modifications are merely examples of the present invention, and it is obvious that appropriate modifications, changes, and additions within the scope of the gist of the present invention are also included in the scope of the claims of this application.

Explanation of Reference Numerals

[0108] 1... DC pulse power supply device 10…Three-phase AC power supply 11…Plasma load circuit 12…High-potential output terminal 13…Low-potential output terminal 14…Series connection part 2…P / N voltage generation unit 20…Fuse circuit 22…Bridge diode 23, 28…Capacitor 24…Step-down converter 251, 252, 253, 254…Switching element 25a, 25b…Complementary switch 26a, 26b…Reactor 27…Current transformer 3a~3e…Stage 4a~4e…Stage voltage generation unit 40a~40e, 48a~48e…Reactor 41a~41e, 47a~47e…Voltage clamp circuit 42a~42e, 46a~46e…Switching element 43a~43e, 45a~45e…Coupling capacitor 44a~44e…Isolation transformer 49a~49e…Capacitor 5a~5e…Pulse generation unit 51a~51e, 52a~52e, 54a~54e, 55a~55e…Switching element (or diode) 53a~53e…Resonant reactor 56a~56e…Resonant capacitor 61, 62, 63…Resistor 6…Voltage pattern setting unit 7a, 7b…Variable voltage stage 8a, 8b…Additional variable voltage generation unit 9a, 9b…Variable pulse generation unit 91a, 91b, 92a, 92b, 94a, 94b, 95a, 95b…Switching element 93b…Resonant reactor 96b…Resonant capacitor 101…First control unit 102…Second control unit

Claims

1. A DC pulse power supply device that outputs a DC pulse voltage to a capacitive load circuit in a plasma processing device, a) a common voltage generating unit that generates a basic DC voltage common to a plurality of stages described below from power supplied from an external source, the common voltage generating unit having a common capacitor between a high-voltage output terminal and a low-voltage output terminal that output the basic DC voltage; b) an individual DC voltage generation unit provided in each of a plurality of stages, the individual DC voltage generation unit including an isolated bidirectional converter and an individual capacitor connected between a high-voltage side output terminal and a low-voltage side output terminal of the isolated bidirectional converter, the individual DC voltage generation unit receiving the basic DC voltage generated by the common voltage generation unit and generating an individual DC voltage for each stage; c) an individual pulse voltage generating unit provided in each of the plurality of stages, the individual pulse voltage generating unit generating an individual pulse voltage for each stage by switching the individual DC voltage generated by the individual DC voltage generating unit in the stage; d) a series connection unit that connects the individual pulse voltages generated by the individual pulse voltage generating units in the plurality of stages in series and outputs the individual pulse voltages; A DC pulse power supply device for a plasma processing device comprising:

2. 2. The DC pulse power supply device for a plasma processing apparatus according to claim 1, wherein the isolated bidirectional converter is an isolated bidirectional Cuk converter.

3. 2. The DC pulse power supply device for plasma processing apparatus according to claim 1, wherein the individual pulse voltage generating unit includes a plurality of switching elements and a reactor, and forms rising and falling edges of the individual pulse voltages by utilizing resonance of a circuit including the reactor, in which a direction of current flow is switched by on / off operation of the plurality of switching elements, and a capacitor of the load circuit.

4. 2. The DC pulse power supply device for plasma processing apparatus according to claim 1, wherein all of the individual DC voltage generating units included in the plurality of stages generate the same voltage value corresponding to the voltage value of the basic DC voltage, and the peak value at each point in time of the DC pulse voltage output from the device is determined by the number of stages substantially operating at that time.

5. 2. The DC pulse power supply device for plasma processing apparatus according to claim 1, wherein the individual DC voltage generating units included in not all of the plurality of stages generate a predetermined voltage value that is equal to or lower than a voltage value of the basic DC voltage, while the individual DC voltage generating units included in the remaining stages of the plurality of stages generate a variable voltage value that is equal to or lower than a voltage value of the basic DC voltage, and a peak value at each point in time of the DC pulse voltage output from the device is determined by the number of stages that are actually operating at that time among the stages including individual DC voltage generating units that generate the predetermined voltage value, and by the variable voltage value.

6. 6. The DC pulse power supply device for plasma processing apparatus according to any one of claims 1 to 5, further comprising: a voltage pattern information acquisition unit that acquires voltage pattern information based on a stepped or stepped voltage change corresponding to an ideal voltage waveform for at least one cycle of a DC pulse voltage output from the apparatus; and a control unit that controls operation of the individual DC voltage generation unit and the individual pulse voltage generation unit included in each stage, and, as necessary, the common voltage generation unit, based on the voltage pattern information.

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