Semiconductor optical device and method for manufacturing the same

Abstract

To provide a semiconductor optical device in which current leakage can be suppressed, and a method of manufacturing the same.SOLUTION: A semiconductor optical device is provided in which a light emitting region that emits light and a reflecting region that reflects the light to the light emitting region side are integrated, the semiconductor optical device includes a core layer provided in the light emitting region, and a waveguide layer which is provided in the reflecting region and optically coupled to the core layer, and has a bandgap larger than the energy of the light. The reflecting region has a first thyristor that overlaps the waveguide layer in a direction intersecting a propagation direction of the light.SELECTED DRAWING: Figure 2B

Description

Technical Field

[0001] The present disclosure relates to a semiconductor optical element and a method for manufacturing the same.

Background Art

[0002] As a light source used in optical communication or the like, a semiconductor optical element having a butt-joint structure in which a semiconductor laser element and other optical elements are integrated is known. A DR (Distributed Reflector) laser element in which a distributed feedback (DFB) laser having a core layer with a multiple quantum well structure and a distributed Bragg reflector (DBR) are integrated has been developed (for example, Non-Patent Document 1). By reflecting the light emitted from a light-emitting region where a DFB laser or the like is formed in a reflection region where a DBR or the like is formed, the light output is improved.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor optical element, it is preferable to selectively inject current into the core layer of the light-emitting region. However, current may leak from the light-emitting region to the reflection region. Due to the current leakage, the energy efficiency may decrease and the characteristics may deteriorate. Therefore, an object of the present invention is to provide a semiconductor optical element capable of suppressing current leakage and a method for manufacturing the same.

Means for Solving the Problems

[0005] The semiconductor optical element according to the present disclosure is a semiconductor optical element in which a light-emitting region that emits light and a reflection region that reflects the light toward the light-emitting region are integrated, and includes a core layer provided in the light-emitting region, and a waveguide layer provided in the reflection region, optically coupled to the core layer, and having a bandgap larger than the energy of the light. The reflection region has a first thyristor that overlaps the waveguide layer in a direction intersecting the propagation direction of the light.

[0006] The method for manufacturing a semiconductor optical element according to the present disclosure is a method for manufacturing a semiconductor optical element in which a light-emitting region that emits light and a reflection region that reflects the light toward the light-emitting region are integrated, and includes a step of growing a core layer in the light-emitting region, a step of growing a waveguide layer in the reflection region, optically coupled to the core layer and having a bandgap larger than the energy of the light, and a step of forming a first thyristor in the reflection region that overlaps the waveguide layer in a direction intersecting the propagation direction of the light.

Effects of the Invention

[0007] According to the present disclosure, it is possible to provide a semiconductor optical element capable of suppressing current leakage and a method for manufacturing the same.

Brief Description of the Drawings

[0008]

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[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0010] One embodiment of the present disclosure is a semiconductor optical element in which a light-emitting region that emits light and a reflection region that reflects the light toward the light-emitting region side are integrated, and includes a core layer provided in the light-emitting region and a waveguide layer provided in the reflection region, optically coupled to the core layer, and having a bandgap larger than the energy of the light. The reflection region is a semiconductor optical element having a first thyristor overlapping the waveguide layer in a direction intersecting the propagation direction of the light. By forming the first thyristor in the reflection region, leakage of current to the reflection region can be suppressed. (2) A first semiconductor layer of a first conductivity type provided under the core layer and the waveguide layer, a second semiconductor layer of a second conductivity type provided on the waveguide layer and different from the first conductivity type, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of the second conductivity type provided on the core layer and the second semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer may form the first thyristor. By forming the first thyristor in the reflection region, leakage of current to the reflection region can be suppressed. (3) The first semiconductor layer and the core layer form a first mesa protruding in a direction intersecting the light propagation direction, and the first semiconductor layer and the waveguide layer form a second mesa protruding in a direction intersecting the light propagation direction. The first mesa and the second mesa extend in the light propagation direction and are adjacent to each other. The first thyristor may be formed at a position overlapping the second mesa and on both sides of the second mesa in a direction intersecting the light propagation direction. The light-emitting region is a DFB region, and the reflection region is a DBR region. By forming the first thyristor overlapping the second mesa in the DBR region, leakage of current from the DFB region to the DBR region can be suppressed. (4) In the reflection region, the second semiconductor layer and the third semiconductor layer are provided on both sides and on the second mesa of the second mesa, and the fourth semiconductor layer is provided on the third semiconductor layer so as to cover the second mesa and both sides of the second mesa. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer may form the first thyristor at a position overlapping the second mesa and on both sides of the second mesa. By forming the first thyristor at a position overlapping the second mesa in the reflection region, leakage of current to the reflection region is suppressed. Since it is difficult for current to flow through the waveguide layer of the second mesa, deviation of the reflection wavelength in the reflection region is suppressed. (5) In the light-emitting region, the second semiconductor layer and the third semiconductor layer are provided on both sides of the first mesa, and the fourth semiconductor layer is provided on the third semiconductor layer and on the first mesa. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer may form a second thyristor on both sides of the first mesa. Since it is difficult for current to flow through the second thyristor, current can be selectively injected into the core layer of the first mesa. Since the fourth semiconductor layer becomes a current path, the electrical resistance is reduced and heat generation is suppressed. Good characteristics can be obtained even in high-temperature and high-output operations. (6) The first mesa has a first diffraction grating, the second mesa has a second diffraction grating, and the shape of the first diffraction grating may be equal to the shape of the second diffraction grating. Since the first diffraction grating and the second diffraction grating can be formed together, the yield can be improved. (7) A first electrode and a second electrode are provided in the light-emitting region, and at least one of the first electrode and the second electrode may not be provided in the reflection region. A current is injected into the light-emitting region, and light is output. Since no current is injected into the reflection region, current loss is suppressed. (8) The first semiconductor layer and the third semiconductor layer may contain n-type indium phosphide, and the second semiconductor layer and the fourth semiconductor layer may contain p-type indium phosphide. These layers can be grown by using the same raw material and switching between an n-type dopant and a p-type dopant. (9) A method for manufacturing a semiconductor optical element in which a light-emitting region that emits light and a reflection region that reflects the light toward the light-emitting region are integrated, the method including: a step of growing a core layer in the light-emitting region; a step of growing, in the reflection region, a waveguide layer that is optically coupled to the core layer and has a bandgap larger than the energy of the light; and a step of forming a first thyristor in the reflection region that overlaps the waveguide layer in a direction intersecting the propagation direction of the light. By forming the first thyristor in the reflection region, leakage of current into the reflection region is suppressed. (10) The method may include a step of etching the core layer and the waveguide layer to form a first diffraction grating in the core layer and a second diffraction grating adjacent to the first diffraction grating in the waveguide layer. Since the first diffraction grating and the second diffraction grating are formed together, the yield can be improved.

[0011] [Details of Embodiments of the Present Disclosure] Specific examples of the semiconductor optical element and the method for manufacturing the same according to the embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0012] (Semiconductor Optical Element) FIG. 1A is a plan view illustrating a semiconductor optical element 100 according to an embodiment. FIG. 1B is a cross-sectional view taken along line A-A of FIG. 1A. FIG. 2A is a cross-sectional view taken along line B-B of FIG. 1A. FIG. 2B is a cross-sectional view taken along line C-C of FIG. 1A. In the figure, the X-axis direction is the light propagation direction. The Z-axis direction is the layer stacking direction and is orthogonal to the X-axis direction. The Y-axis direction is orthogonal to the X-axis direction and the Z-axis direction.

[0013] As shown in FIG. 1A, the planar shape of the semiconductor optical element 100 in the XY plane is rectangular and has sides extending in the X-axis direction and sides extending in the Y-axis direction. As shown in FIGS. 1A and 1B, the semiconductor optical element 100 is a DR laser element having a butt-joint structure with a DFB region 10 (emitting region) and a DBR region 30 (reflecting region). In the X-axis direction, the DFB region 10 and the DBR region 30 are adjacent to each other. The length L1 of the DFB region 10 in the X-axis direction and the length L2 of the DBR region 30 in the X-axis direction are, for example, 500 μm each. A mesa 13 is provided in the DFB region 10. A mesa 33 is provided in the DBR region 30. The mesas 13 and 33 are adjacent to each other and extend in the X-axis direction.

[0014] FIG. 2A is a cross-sectional view of the DFB region 10. The central portion of the substrate 12 (first semiconductor layer) in the Y-axis direction protrudes in the Z-axis direction compared to the outer portion, and a core layer 14 is stacked on the protruding portion. The substrate 12 and the core layer 14 form a mesa 13 (first mesa) protruding in the Z-axis direction. The width W of the mesa 13 is, for example, 1.5 μm.

[0015] The buried layer 16 (second semiconductor layer) is provided on the substrate 12, on both sides of the mesa 13 in the Y-axis direction, and on the mesa 13, and embeds the mesa 13 from both sides and above. Two buried layers 18 (third semiconductor layer) are provided on the buried layer 16. The two buried layers 18 are arranged in the Y-axis direction, are spaced apart from each other on the mesa 13, and sandwich the mesa 13. The cladding layer 20 (fourth semiconductor layer) is provided on the mesa 13 and the buried layer 18 and contacts the buried layer 16 between the two buried layers 18. The dotted line in FIG. 2A is the boundary between the buried layer 16 and the cladding layer 20.

[0016] The electrode 25 is provided on the upper surface of the cladding layer 20 and is electrically connected to the cladding layer 20. The electrode 25 is formed of a metal such as a laminate of titanium, platinum, and gold (Ti / Pt / Au), for example. The electrode 24 is provided on the lower surface of the substrate 12 and is electrically connected to the substrate 12. The electrode 24 is formed of a metal such as an alloy of gold, germanium, and Ni (AuGeNi), for example. As shown in FIG. 2A, the electrodes 24 and 25 sandwich the mesa 13 in the Z-axis direction.

[0017] The core layer 14 includes a plurality of well layers and barrier layers formed of, for example, undoped gallium indium arsenide phosphide (i-GaInAsP) and has a multiple quantum well structure (MQW: Multi Quantum Well). The substrate 12 is formed of, for example, n-type indium phosphide (n-InP) and functions as an n-type cladding layer. The buried layer 16 is formed of, for example, p-InP with a thickness of 800 nm. The buried layer 18 is formed of, for example, n-InP with a thickness of 500 nm. The cladding layer 20 is formed of, for example, p-InP. Silicon (Si) is used as an n-type dopant, for example. Zinc (Zn) is used as a p-type dopant, for example.

[0018] On both sides of the mesa 13, the n-type substrate 12, the p-type buried layer 16, the n-type buried layer 18, and the p-type cladding layer 20 are laminated in this order. A structure in which an n-type semiconductor layer and a p-type semiconductor layer are alternately laminated is defined as a thyristor 22 (second thyristor). The thyristor 22 does not have a gate electrode. The thyristor 22 extends in the Z-axis direction, suppresses the flow of current in the Z-axis direction, and functions as a current constriction structure.

[0019] FIG. 2B is a cross-sectional view of the DBR region 30. The central portion of the substrate 12 in the Y-axis direction protrudes in the Z-axis direction compared to the outer portions, and the waveguide layer 32 is laminated on the protruding portion. The waveguide layer 32 includes, for example, a plurality of well layers and barrier layers formed of i-GaInAsP and has an MQW structure. The waveguide layer 32 may have, for example, a single-layer structure or a two-layer structure as long as the bandgap is larger than the energy of the emitted light in the DFB region 10. The substrate 12 and the waveguide layer 32 form a mesa 33 (second mesa) protruding in the Z-axis direction. The width and height of the mesa 33 are the same as those of the mesa 13.

[0020] The buried layer 16 is provided on the substrate 12, on both sides of the mesa 33 in the Y-axis direction, and on the mesa 33, and embeds the mesa 33 from both sides and above. The buried layer 18 is provided on the buried layer 16 and embeds the mesa 33 from both sides and above. The cladding layer 20 is provided on the buried layer 18. In the DBR region 30, an n-type substrate 12, a p-type buried layer 16, an n-type buried layer 18, and a p-type cladding layer 20 are laminated in this order at positions overlapping the mesa 33 and on both sides of the mesa 33. A structure in which an n-type semiconductor layer and a p-type semiconductor layer are alternately laminated is defined as a thyristor 34 (first thyristor).

[0021] The thyristor 34 overlaps the mesa 33 in the Z-axis direction and is also provided on both sides of the mesa 33. The thyristor 34 extends in a direction intersecting the light propagation direction and suppresses the flow of current in that direction. In the example of FIG. 2B, the thyristor 34 extends in the Z-axis direction and suppresses the flow of current in the Z-axis direction.

[0022] An electrode 24 is provided on the lower surface of the substrate 12. The electrode 25 is not provided in the DBR region 30. That is, both the electrodes 24 and 25 are provided in the DFB region 10. The electrode 24 may or may not be provided in the DBR region 30. The electrode 25 may or may not be provided in the DBR region 30.

[0023] Figure 1B shows a cross-section including mesas 13 and 33. Mesa 13 and mesa 33 are arranged along the X-axis direction. The core layer 14 and the waveguide layer 32 are adjacent to each other in the X-axis direction and are optically coupled to each other. A diffraction grating 15 is provided on mesa 13. Periodic unevenness along the X-axis direction provided on the upper surface of the core layer 14 functions as the diffraction grating 15. A diffraction grating 35 is provided on mesa 33. Periodic unevenness along the X-axis direction provided on the upper surface of the waveguide layer 32 functions as the diffraction grating 35. The diffraction grating 15 and the diffraction grating 35 are continuous in the X-axis direction. The depth of the diffraction grating 15 is equal to the depth of the diffraction grating 35. The depth D is, for example, 20 nm. The pitch of the diffraction grating 15 is equal to the pitch of the diffraction grating 35. The pitch P is, for example, 240 nm. The coupling coefficient of each of the diffraction gratings 15 and 35 is, for example, 50 cm -1 is.

[0024] By inputting a voltage to the electrodes 24 and 25 and injecting current into the core layer 14, the core layer 14 emits light in the X-axis direction. The wavelength of the light is, for example, 1.3 μm to 1.55 μm, etc. The DBR region 30 has a high reflectivity for light of the said wavelength and reflects the light toward the DFB region 10. The light is emitted from the end face of the semiconductor optical element 100 located on the side opposite to the DBR region 30. The DFB region 10 and the DBR region 30 form a resonator, and by the reflected light from the DBR region 30 returning to the DFB region 10, a high light output can be obtained.

[0025] As shown in Fig. 2A, since the thyristors 22 are formed on both sides of the mesa 13, it is difficult for current to flow outside the mesa 13. Specifically, a p-type semiconductor layer and an n-type semiconductor layer are alternately laminated on both sides of the mesa 13, resulting in a laminated structure of a total of four semiconductor layers. Due to the high electrical resistance of the laminated portion (thyristor 22) with respect to the voltage applied between the electrode 24 and the electrode 25, the current is blocked. Leakage of current from the core layer 14 to the buried layers 18 and 16 is suppressed. On the other hand, no buried layer 18 is provided on the mesa 13, and a p-type clad layer 20 is provided. The current constriction is strengthened by the thyristor 22, and current can be selectively injected into the mesa 13 through the clad layer 20. Loss of current can be suppressed, and the semiconductor optical element 100 can be driven with high energy efficiency. The clad layer 20 has a large width and covers the upper part of the buried layer 18 and the upper part of the mesa 13. By widening the clad layer 20, the electrical resistance can be reduced, and heat generation can be suppressed. By suppressing heat generation, the characteristics are less likely to deteriorate even when high-power operation is performed at high temperatures.

[0026] As shown in Fig. 2B, since the thyristors 34 are formed at positions overlapping the mesa 33 in the DBR region 30 and on both sides of the mesa 33, leakage of current from the DFB region 10 to the DBR region 30 is suppressed. Wavelength shift due to carrier accumulation in the waveguide layer 32 is suppressed.

[0027] (Manufacturing method) A method for manufacturing the semiconductor optical element 100 will be described. Figs. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 11A, 13A, 15A, 17A, and 19A are plan views illustrating the manufacturing method of the semiconductor optical element 100. Figs. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 11B, 13B, 15B, 17B, and 19B are cross-sectional views taken along line A-A of the corresponding plan views. Figs. 10A, 12A, 14A, 16A, 18A, and 20A are cross-sectional views taken along line B-B of the corresponding plan views. Figs. 10B, 12B, 14B, 16B, 18B, and 20B are cross-sectional views taken along line C-C of the corresponding plan views.

[0028] As shown in FIGS. 3A and 3B, for example, by an organometallic vapor phase epitaxy (OMVPE) method or the like, a core layer 14 and a cap layer 40 are epitaxially grown on a substrate 12 in this order. For example, an insulating film 42 is formed on a part of the cap layer 40 by a plasma CVD (Chemical Vapor Deposition) method or the like. The portion that becomes the DFB region 10 is covered with the insulating film 42, and the portion that becomes the DBR region 30 is exposed. The cap layer 40 is formed of, for example, p-InP with a thickness of 100 nm. The insulating film 42 is formed of an insulator such as silicon oxide (SiO 2 ).

[0029] As shown in FIGS. 4A and 4B, etching is performed using the insulating film 42 as a mask, and the portions of the cap layer 40 and the core layer 14 that are exposed from the insulating film 42 are removed. The etching is, for example, dry etching such as reactive ion etching (RIE), or wet etching. After the etching, the substrate 12 is partially exposed. The portions of the cap layer 40 and the core layer 14 that are covered with the insulating film 42 are not etched.

[0030] As shown in FIGS. 5A and 5B, by an OMVPE method or the like, a waveguide layer 32 and a cap layer 44 of p-InP are epitaxially grown in this order on the portion of the substrate 12 that is exposed from the insulating film 42. The thickness of the waveguide layer 32 may be equal to or different from the thickness of the core layer 14. The thickness of the cap layer 44 may be equal to or different from the thickness of the cap layer 40. As long as there is no hindrance to the propagation of light between the DFB region 10 and the DBR region 30, the thickness of the waveguide layer 32 may be different from the thickness of the core layer 14, and the thickness of the cap layer 44 may be different from the thickness of the cap layer 40. The cap layer 44 is exposed from the insulating film 42.

[0031] As shown in FIGS. 6A and 6B, CF 4Remove the insulating film 42 by dry etching using (fluorocarbon) or wet etching using BHF (buffered hydrofluoric acid), and further remove the cap layers 40 and 44 by etching. The core layer 14 and the waveguide layer 32 are exposed.

[0032] As shown in FIGS. 7A and 7B, perform resist patterning by electron beam lithography or the like, and perform wet etching to form a diffraction grating 15 in the core layer 14 and a diffraction grating 35 in the waveguide layer 32. More specifically, by simultaneously performing electron beam lithography on the core layer 14 and the waveguide layer 32 and simultaneously performing wet etching, the diffraction gratings 15 and 35 are formed collectively.

[0033] As shown in FIGS. 8A and 8B, by the OMVPE method, an embedded layer 16a of, for example, p-InP is epitaxially grown on the core layer 14 and the waveguide layer 32. The embedded layer 16a covers the entire core layer 14 and the entire waveguide layer 32 and embeds the diffraction gratings 15 and 35.

[0034] As shown in FIGS. 9A to 10B, by a plasma CVD method or the like, an insulating film 46 of, for example, SiO 2 is provided on the embedded layer 16a. As shown in FIGS. 9A and 9B, the insulating film 46 extends in the X-axis direction. As shown in FIGS. 10A and 10B, the width of the insulating film 46 in the Y-axis direction is smaller than the width of the core layer 14 and the width of the waveguide layer 32.

[0035] As shown in FIGS. 11A to 12B, using the insulating film 46 as a mask, perform dry etching, for example, on the substrate 12, the core layer 14, and the waveguide layer 32 to form a mesa 13 in the DFB region 10 and a mesa 33 in the DBR region 30. The depth D1 of the mesa 13 shown in FIG. 12A and the depth D2 of the mesa 33 shown in FIG. 12B are each, for example, 1.5 μm. The substrate 12 is exposed on both sides of the mesa 13 and on both sides of the mesa 33.

[0036] As shown in FIGS. 13A to 14B, after the mesa is formed, the insulating film 46 on the mesa 33 is removed, and the insulating film 46 on the mesa 13 is left. The upper surface of the mesa 33 is exposed.

[0037] As shown in FIGS. 15A to 16B, using the insulating film 46 as a mask, for example, the OMVPE method is performed to epitaxially grow the embedded layer 16b and the embedded layer 18 in sequence. The embedded layer 16b is formed of, for example, p-InP, and together with the embedded layer 16a, forms the embedded layer 16. After adding a p-type dopant to the source gas to grow the embedded layer 16b, the dopant is changed to an n-type to grow the embedded layer 18. As shown in FIG. 16A, since the insulating film 46 is provided on the mesa 13, the embedded layer 16b and the embedded layer 18 do not grow on the mesa 13. The embedded layer 16b and the embedded layer 18 grow on both sides of the mesa 13 in the Y-axis direction. As shown in FIG. 16B, since the mesa 33 is not covered with the insulating film 46, the embedded layer 16b and the embedded layer 18 grow on and on both sides of the mesa 33. After growth, the insulating film 46 is removed.

[0038] As shown in FIGS. 17A to 18B, the cladding layer 20 is epitaxially grown by the OMVPE method or the like. As shown in FIG. 18A, the cladding layer 20 is formed on the embedded layers 16 and 18 and contacts the embedded layer 16 between the two embedded layers 18. The substrate 12, the embedded layer 16, the embedded layer 18, and the cladding layer 20 form the thyristor 22 on both sides of the mesa 13. As shown in FIG. 18B, the cladding layer 20 covers the embedded layer 18. The substrate 12, the embedded layer 16, the embedded layer 18, and the cladding layer 20 form the thyristor 34 at positions overlapping the mesa 33 and on both sides of the mesa 33.

[0039] As shown in FIGS. 19A to 20A, an electrode 25 is provided on the upper surface of the cladding layer 20 in the DFB region 10 by, for example, vapor deposition. The electrode 25 is not provided in the DBR region 30. As shown in FIGS. 19B to 20B, an electrode 24 is provided on the lower surface of the substrate 12 by, for example, vapor deposition. Through the above steps, the semiconductor optical element 100 is manufactured.

[0040] (Comparative Example 1) FIG. 21A and FIG. 21B are cross-sectional views illustrating the semiconductor optical element 100R1 according to Comparative Example 1. FIG. 21A illustrates a cross-section corresponding to FIG. 1B, and FIG. 21B illustrates a cross-section corresponding to FIG. 2A.

[0041] As shown in FIG. 21A, the semiconductor optical element 100R1 does not have a waveguide layer 32. The core layer 14 is provided in the DFB region 10 and the DBR region 30. The mesa 13 includes the core layer 14 and extends into the DFB region 10 and the DBR region 30. A diffraction grating 15 is provided in the core layer 14 of the DFB region 10. A diffraction grating 17 is provided in the core layer 14 of the DBR region 30. The depth of the diffraction grating 17 is larger than that of the diffraction grating 15. The coupling coefficient of the diffraction grating 15 is, for example, 50 cm -1 is. The coupling coefficient of the diffraction grating 17 is, for example, 100 cm -1 is. The length L3 of the DFB region 10 is, for example, 500 μm. The length L4 of the DBR region 30 is, for example, 100 μm. The reflectivity of light in the DBR region 30 is, for example, 60%. The electrodes 24 and 25 are provided in the DFB region 10 and the DBR region 30.

[0042] FIG. 21B shows the DFB region 10. On the core layer 14, a clad layer 20 having the same width as the core layer 14 is provided. The buried layer 50 is located on both sides of the mesa 13 and is provided in the DFB region 10 and the DBR region 30. The buried layer 50 is formed of, for example, semi-insulating InP doped with iron (Fe). The buried layers 16 and 18 are not provided.

[0043] By applying a voltage to electrodes 24 and 25, current is injected into the core layer 14. The cladding layer 20 serves as the current path. However, current may leak from the cladding layer 20 to the buried layer 50 and flow toward the substrate 12 side. Since the current leaking into the buried layer 50 does not contribute to the optical output, the energy efficiency decreases, making it difficult to obtain a high optical output. The cladding layer 20 serving as the current path is narrower compared to the example of FIG. 2A and has a high electrical resistance. When current flows, the cladding layer 20 is likely to generate heat. Particularly, a large amount of heat is generated during high-output operation at high temperatures, and there is a risk of deterioration of characteristics such as a decrease in output. When the drive current is 400 mA, the output at room temperature (25°C) is 60 mW. The output at 85°C is 20 mW, which is reduced to about 30% of the output at room temperature.

[0044] As shown in FIG. 21A, since the core layer 14, electrodes 24 and 25 are provided in the DBR region 30, current is also injected into the core layer 14 of the DBR region 30. Since current is injected into the DBR region 30 with poor optical gain, the energy efficiency decreases. For example, about 20% of the current input to the semiconductor optical element 100R1 is input to the DBR region 30 and does not contribute to the optical output.

[0045] In order to form the diffraction gratings 15 and 17 with different depths shown in FIG. 21A, electron beam lithography and etching are performed on the core layer 14 twice each. In such processes, dimensional and positional deviations may occur, and the yield may decrease.

[0046] (Comparative Example 2) FIGS. 22A and 22B are cross-sectional views illustrating a semiconductor optical element 100R2 according to Comparative Example 2. FIG. 22A shows a cross-section corresponding to FIG. 1B, and FIG. 22B shows a cross-section corresponding to FIG. 2B. The configuration of the DFB region 10 is the same as that in FIG. 2A.

[0047] As shown in FIGS. 22A and 22B, a waveguide layer 32 is provided in the DBR region 30. As shown in FIG. 22B, buried layers 16 and 18 are provided on both sides of the mesa 33. The buried layer 18 is not located directly above the mesa 33. The cladding layer 20 is provided on the mesa 33 and the buried layer 18. The substrate 12, the buried layers 16 and 18, and the cladding layer 20 form thyristors 22 on both sides of the mesas 13 and 33. The thyristor 22 is not formed at a position overlapping the mesa 33.

[0048] Since the thyristors 22 are formed on both sides of the mesa 13, leakage of current into the buried layer can be suppressed, and current can be selectively injected into the core layer 14 of the DFB region 10. Since the cladding layer 20 has a larger width compared to Comparative Example 1, it is less likely to generate heat.

[0049] However, the buried layers 16 and 18 and the cladding layer 20 are each conductive from the DFB region 10 to the DBR region 30 in the X-axis direction. As shown in FIG. 22B, the thyristor 22 is not formed at a position overlapping the mesa 33. The cladding layer 20, the waveguide layer 32, and the substrate 12 form a p-i-n structure in the Z-axis direction. Current leaks from the DFB region 10 to the DBR region 30 through the buried layer 18 and the like, and also flows into the waveguide layer 32. Due to the leakage of current, carriers accumulate in the waveguide layer 32, and the refractive index of the waveguide layer 32 changes. Due to the change in the refractive index, the wavelength (reflection wavelength) at which the DBR region 30 exhibits high reflectivity changes and deviates from the oscillation wavelength of the DFB region 10. Since the DBR region 30 no longer exhibits the desired reflection function, the characteristics of the semiconductor optical element 100R2 deteriorate.

[0050] According to this embodiment, as shown in FIG. 2B, the n-type substrate 12, the p-type buried layer 16, the n-type buried layer 18, and the p-type clad layer 20 form thyristors 34 at positions overlapping the mesa 33 in the Z-axis direction and on both sides of the mesa 33 in the DBR region 30. The n-p-n-p stacked structure of the thyristor 34 increases the electrical resistance. The presence of the thyristor 34 makes it difficult for current to flow in the DBR region 30, suppressing the leakage of current from the DFB region 10 to the DBR region 30. By suppressing the current loss, the energy efficiency of the semiconductor optical element 100 is increased. Since the thyristor 34 overlaps the waveguide layer 32 in the Z-axis direction, it is difficult for current to flow in the waveguide layer 32, suppressing the accumulation of carriers in the waveguide layer 32. The reflection wavelength of the DBR region 30 is less likely to deviate from the oscillation wavelength of the DFB region 10. The light emitted from the DFB region 10 is reflected by the DBR region 30, returns to the DFB region 10, and is emitted outside the semiconductor optical element 100. The semiconductor optical element 100 can exhibit desired characteristics.

[0051] As shown in FIG. 2A, the substrate 12, the buried layers 16 and 18, and the clad layer 20 form thyristors 22 on both sides of the mesa 13 in the DFB region 10. Leakage of current into the buried layers 16 and 18 is suppressed. Since the current is selectively injected into the mesa 13, the energy efficiency of the semiconductor optical element 100 is increased. Since the clad layer 20 has a larger width compared to the example of FIG. 21B, the electrical resistance of the clad layer 20 is low. Due to the decrease in the electrical resistance of the clad layer 20, heat generation when current flows is suppressed, and deterioration of characteristics is suppressed. As will be described later, deterioration of characteristics during high-temperature high-output operation is particularly suppressed.

[0052] As shown in FIG. 1B, electrodes 24 and 25 are provided in the DFB region 10, and current is input through these electrodes. On the other hand, at least one of the electrodes 24 and 25 is not provided in the DBR region 30. In the example of FIG. 1B, the electrode 25 is not provided, and no current is injected into the DBR region 30. Therefore, current loss is suppressed, and the energy efficiency of the semiconductor optical element 100 is increased.

[0053] According to this embodiment, compared with Comparative Example 1, the energy efficiency is improved by 30% to 40% at room temperature and about doubled at high temperature (85°C). For example, when the drive current is 400 mA, the output at room temperature is 100 mW. The output at 85°C is 50 mW, maintaining 50% of the output at room temperature. The semiconductor optical element 100 has high energy efficiency and is particularly suitable for high-temperature and high-output operations.

[0054] Instead of the DBR region 30, a high-reflection film can be attached to the DFB region 10 to reflect light in the DFB region 10. Since the high-reflection film is provided at the cleavage position of the wafer, the phase of the reflected light is determined according to the cleavage position. Because it is difficult to control the cleavage position, the phase of the reflected light varies from element to element. The sub-mode suppression ratio (SMSR) varies from element to element, and the yield decreases. The semiconductor optical element 100R1 of Comparative Example 1 is an element with a butt-joint structure that does not use a high-reflection film. However, since the diffraction grating 15 and the diffraction grating 17 are formed in separate processes, positional deviations and the like may occur. The phase of the light does not become as designed, and the yield decreases.

[0055] On the other hand, the semiconductor optical element 100 is a DR laser element with a butt-joint structure having a DFB region 10 and a DBR region 30. As shown in FIG. 1B, a mesa 13 and a diffraction grating 15 are provided in the DFB region 10. A mesa 33 and a diffraction grating 35 are provided in the DBR region 30. The DFB region 10 and the DBR region 30 are designed in consideration of the phase of light. The diffraction grating 15 and the diffraction grating 35 have the same shape. That is, the pitch of the diffraction grating 15 is equal to the pitch of the diffraction grating 35. The depth of the diffraction grating 15 is equal to the depth of the diffraction grating 35. As shown in FIGS. 7A and 7B, the diffraction grating 15 and the diffraction grating 35 can be formed together by the same electron beam lithography and the same etching. Positional deviations and the like are suppressed, and the SMSR and the yield are improved. Compared with Comparative Example 1, the yield is, for example, doubled.

[0056] The diffraction grating 15 may be provided in the core layer 14 or in other layers. The diffraction grating 35 may be provided in the waveguide layer 32 or in other layers. This embodiment may be applied to elements other than the elements shown in FIGS. 1A and 1B. In a butt-joint structure in which a light-emitting region having a core layer and a reflection region having a waveguide layer are integrated, a thyristor is provided so as to include the waveguide layer of the reflection region. Leakage of current to the reflection region can be suppressed.

[0057] The substrate 12 and the buried layer 18 are formed of n-InP. The buried layers 16 and the cladding layer 20 are formed of p-InP. By using the same source gas and switching between a p-type dopant and an n-type dopant, layers can be grown by the OMVPE method. The substrate 12, the buried layers 16 and 18, and the cladding layer 20 may be formed of a compound semiconductor other than InP. The stacking order of the n-type layer and the p-type layer may be changed, and a p-type, n-type, p-type, and n-type layer may be stacked from the bottom. Since the bandgap of the waveguide layer 32 is larger than the energy of light, absorption of light by the waveguide layer 32 is suppressed.

[0058] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present disclosure described in the claims.

Description of Reference Numerals

[0059] 10 DFB region 12 Substrate 13, 33 Mesa 14 Core layer 15, 17, 35 Diffraction grating 16, 16a, 16b, 18 Buried layer 20 Cladding layer 22, 34 Thyristor 24, 25 Electrode 30 DBR region 32 Waveguide layer 40, 44 Cap layer 42, 46 Insulating film 100, 100R1, 100R2 semiconductor optical elements

Claims

1. A semiconductor optical element in which a light-emitting region that emits light and a reflection region that reflects the light toward the light-emitting region side are integrated, a core layer provided in the light-emitting region, and a waveguide layer provided in the reflection region, optically coupled to the core layer, and having a bandgap larger than the energy of the light. The semiconductor optical element includes: The reflection region has a first thyristor that overlaps the waveguide layer in a direction intersecting the light propagation direction and in the direction in which the core layer and the waveguide layer are stacked.

2. a first semiconductor layer of a first conductivity type provided under the core layer and the waveguide layer, a second semiconductor layer of a second conductivity type provided on the waveguide layer and different from the first conductivity type, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of the second conductivity type provided on the core layer and the second semiconductor layer. The semiconductor optical element according to claim 1, wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer form the first thyristor.

3. The first semiconductor layer and the core layer form a first mesa protruding in a direction intersecting the light propagation direction, The first semiconductor layer and the waveguide layer form a second mesa protruding in a direction intersecting the light propagation direction, The first mesa and the second mesa extend in the light propagation direction and are adjacent to each other, The semiconductor optical element according to claim 2, wherein the first thyristor is formed at a position overlapping the second mesa and on both sides of the second mesa in a direction intersecting the light propagation direction.

4. In the reflection region, the second semiconductor layer and the third semiconductor layer are provided on both sides of the second mesa and on the second mesa, The fourth semiconductor layer is provided on the third semiconductor layer so as to cover the second mesa and both sides of the second mesa, The semiconductor optical element according to claim 3, wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer form the first thyristor at a position overlapping the second mesa and on both sides of the second mesa.

5. In the light-emitting region, the second semiconductor layer and the third semiconductor layer are provided on both sides of the first mesa, The fourth semiconductor layer is provided on the third semiconductor layer and on the first mesa. ​ The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are the semiconductor optical element according to claim 3 or claim 4, which forms a second thyristor on both sides of the first mesa.

6. The first mesa has a first diffraction grating, The second mesa has a second diffraction grating, The semiconductor optical element according to any one of claims 3 to 5, wherein the shape of the first diffraction grating is equal to the shape of the second diffraction grating.

7. A first electrode and a second electrode are provided in the light-emitting region, The semiconductor optical element according to any one of claims 1 to 6, wherein at least one of the first electrode and the second electrode is not provided in the reflection region.

8. The first semiconductor layer and the third semiconductor layer contain n-type indium phosphide, The semiconductor optical element according to any one of claims 2 to 6, wherein the second semiconductor layer and the fourth semiconductor layer contain p-type indium phosphide.

9. A method for manufacturing a semiconductor optical element in which a light-emitting region that emits light and a reflection region that reflects the light toward the light-emitting region side are integrated, comprising: A step of growing a core layer in the light-emitting region; A step of growing a waveguide layer in the reflection region that is optically coupled to the core layer and has a bandgap larger than the energy of the light; A method for manufacturing a semiconductor optical element, comprising: forming a first thyristor in the reflection region that overlaps the waveguide layer in a direction intersecting the light propagation direction and in a direction in which the core layer and the waveguide layer are stacked.

10. The method for manufacturing a semiconductor optical element according to claim 9, further comprising a step of forming a first diffraction grating in the core layer and a second diffraction grating adjacent to the first diffraction grating in the waveguide layer by etching the core layer and the waveguide layer.

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