Method for manufacturing a thermo-optical component

Abstract

The invention relates to a method for manufacturing a thermo-optical component, comprising the following steps: a) providing an SOI substrate, the SOI substrate comprising: a surface layer made of monocrystalline silicon and disposed on a dielectric layer disposed on a silicon carrier and extending within a major plane; at least one recessed cavity formed in the carrier and opening below the dielectric layer; and b) forming an optical waveguide extending on the major plane, surrounded by an optical confinement layer including the dielectric layer, and including a core formed in the surface layer; c) fabricating at least one heating element in the optical waveguide, the heating element being arranged in the main plane perpendicular to a segment of the optical waveguide or on either side of said segment, the heating element and the segment of the optical waveguide being arranged perpendicular to the at least one buried cavity; Includes:

Description

Technical Field

[0001] [Field of the Invention] The present invention relates to the field of photonics. More particularly, it relates to a method for manufacturing thermo-optical components, i.e., components whose optical properties (primary refractive index) are modified via local or global variations in temperature caused by internal or external heat sources of the component.

Background Art

[0002] [Technical Background of the Invention] Silicon photonics is becoming increasingly interesting because this technology enables optical communication links to be improved through the provision of many integrated functions such as switches and optical phase shifters, modulators, filters, lasers, etc.

[0003] Switches and optical phase shifters, in particular, must be able to efficiently carry a very large number of signals while satisfying specifications regarding compactness, low power consumption, and high switching speed. Because silicon has a high thermo-optical effect, it has made possible the development of small and fast thermo-optical switches on silicon-on-insulator (SOI) substrates, and reference may be made in particular to components such as ring resonators or Mach-Zender interferometers.

[0004] The document US Patent Application Publication No. 2015 / 253510 provides a small thermo-optical switch. The switch realizes switching because its optical waveguide is suspended above the carrier substrate, mainly surrounded by air, and attached to the carrier substrate by pillars that limit the flow of heat, significantly minimizing the power required to achieve switching: thermal confinement improves the efficiency of the switch (limits power consumption). The structure of this thermo-optical switch is obtained using an SOI substrate, where the silicon surface layer and the buried oxide respectively form a part of the core of the optical waveguide and the optical confinement layer around the core, and the heating element is arranged in the waveguide. From the front side, the steps of structuring and etching the SOI substrate enable the formation of deep trenches and voids between the waveguide and the carrier substrate. One drawback of such a structure may result from the fact that multiple peripheral regions of the thermo-optical component are in contact with air, leading to a decrease in its transient response to temperature and the fluctuations caused by the heating element. In particular, when the heating element stops, the time required for the waveguide to return from a high temperature T1 to temperature T0, i.e., the fall time, is increased due to the thermal inertia caused by the surrounding air.

Summary of the Invention

Problems to be Solved by the Invention

[0005] [Subject Matter of the Invention] The present invention relates to an alternative solution to the solutions known in the prior art. The invention relates to a method for manufacturing a thermo-optical component that enables good thermal insulation, is favorable for the efficiency of the thermo-optical effect, while maintaining a very good transient dynamic component response. This manufacturing method further enables the simplification of the manufacturing steps while the component provides a high integration density and excellent mechanical stability.

Means for Solving the Problems

[0006] [Brief Description of the Invention] The present invention relates to a method for manufacturing a thermo-optical component, the following steps: a) Providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate is made of single-crystalline silicon, disposed on a dielectric layer that is itself disposed on a silicon carrier, and having a surface layer that extends in a main plane, and at least one buried cavity formed within the carrier and opening beneath the dielectric layer and comprising; b) Forming an optical waveguide comprising a core formed in the surface layer, extending in the main plane, and surrounded by an optical confinement layer including the dielectric layer; c) Fabricating at least one heating element in the optical waveguide, wherein the heating element is disposed in the main plane, perpendicular to a segment of the optical waveguide, or on both sides of the segment, and the heating element and the segment of the optical waveguide are disposed perpendicular to the at least one buried cavity. and including.

[0007] According to some advantageous features of the invention, the features may be implemented alone or in any feasible combination. In step b), an aperture is fabricated through the optical waveguide for disposing the at least one cavity under an external pressure. The aperture is blocked so as to maintain or hermetically seal the at least one cavity. The at least one cavity remains hermetically sealed throughout steps a), b) and c). The dielectric layer is made of silicon oxide and has a thickness between 100 nm and 3 microns. The surface layer has a thickness between 100 nm and 500 nm. The optical confinement layer comprises an additional dielectric layer having a thickness between 0.5 microns and 1.5 microns. The at least one cavity has a lateral dimension in the main plane that includes a range between 10 microns and several millimeters, and a depth along an axis perpendicular to the main plane that includes a range between several microns and 100 microns, advantageously between 5 microns and 10 microns.

[0008] The invention further relates to a thermo-optical component fabricated using the above-described manufacturing method for forming a switch, a phase shifter, a modulator, a laser emitter, an amplifier, a bidirectional coupler, a filter and / or a multiplexer.

[0009] Other features and advantages of the invention will become apparent from the following detailed description with reference to the accompanying drawings.

Brief Description of the Drawings

[0010]

Figure 1a

Figure 1b

Figure 1c

Figure 1d

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Figure 4a

Figure 4b

Embodiments for Carrying Out the Invention

[0011] [Detailed Description of the Invention] The figures are schematic representations which are not necessarily to scale for ease of reading. In particular, the thickness of the layers along the z-axis is not to scale with respect to the lateral dimensions along the x-axis and y-axis. In the figures, the same reference signs may be used for elements of the same nature.

[0012] It must be understood that the various possibilities (the variants and embodiments illustrated and / or detailed in the following description) are not mutually exclusive and may be combined together.

[0013] The invention relates to a method for manufacturing thermo-optical components. By thermo-optical components is meant any type of optoelectronic device such as a switch, a phase shifter, a modulator, a directional coupler, a filter and an optical multiplexer, a laser emitter, an amplifier, etc., the optical properties of which (in particular the primary refractive index) are changed by local (or global) temperature variations caused by a heat source inside or outside the device.

[0014] The manufacturing method involves preparing for the fabrication of an optical waveguide 50 based on single-crystalline silicon and a heating element 60 in proximity to a segment of the waveguide 50, such that the temperature variations induced by the heating element 60 in a segment 52' of the silicon core of the waveguide 50 have the effect of changing the refractive index of the silicon, and thus changing the effective refractive index of the optical mode of the said waveguide 50.

[0015] The manufacturing method includes step a) of providing a silicon-on-insulator (SOI) substrate 10 made from single-crystalline silicon, extending in the main plane (x, y), and comprising a surface layer 4 disposed in a dielectric layer 3 which is itself disposed on a silicon carrier 1 (Figure 1d). The SOI substrate 10 preferably takes the form of a circular wafer having a diameter including the range between 150 mm and 450 mm and a carrier 1 thickness typically varying between 300 microns and 1000 microns.

[0016] To satisfy the requirements for photonic applications, it is advantageous for the surface layer 4 to have a thickness including between 100 nm and 500 nm. This surface layer 4 forms the core of the optical waveguide 50.

[0017] However, but not limited to, it is again advantageous for the dielectric layer 3 to be made of silicon oxide and to have a thickness including between 100 nm and 3 microns.

[0018] The SOI substrate 10 further includes at least one embedded cavity 2 formed in the carrier 1 and opening under the dielectric layer 3. The following refers to the embedded cavity 2 for simplicity, but it is advantageous for the SOI substrate 10 to include a plurality of cavities 2, and it will be understood that the cavities will be distributed in the main plane (x, y) according to the structure, type and number of the thermo - optical component 100 to be provided on the SOI substrate 10. It should be further noted that since the embedded cavity 2 may be related to various structures or types of components, not all embedded cavities 2 necessarily have the same dimensions (length and width in the main plane (x, y), and depth along the z - axis perpendicular to the main plane (x, y)).

[0019] The embedded cavity 2 may have a lateral dimension including between 10 microns and several millimeters in the main plane (x, y), and a depth including between several microns and 100 microns, preferably between 5 microns and 10 microns. The embedded cavity 2 may have any shape in the main plane (x, y), for example, square, rectangular, polygonal, circular, annular, etc.

[0020] The embedded cavity 2 of the SOI substrate 10 may be filled with a sacrificial solid material or may be without a sacrificial solid material. In the latter case, the embedded cavity 2 may be filled with air or gas at atmospheric pressure or at a defined and controlled pressure.

[0021] As an example, the sacrificial material will probably be selected from silicon oxides such as low density or doped silicon oxides, doped polysilicon, porous silicon, etc. The sacrificial material will optionally have an etch rate with respect to the other materials of the SOI substrate 10 that is high enough to avoid significant etching of the substrate 10 when this sacrificial material is subsequently removed in the process, i.e., with respect to thermal silicon oxide and single crystal silicon.

[0022] The fabrication of such an SOI substrate 10 having the embedded cavity 2 preferably is based on a thin layer transfer process known as the Smart Cut™ process.

[0023] Prior to the transfer of the surface layer 4, the carrier 1 used is a single crystal silicon substrate, the front side 1a of which is etched (FIG. 1a) to form - at least one - cavity 2. In a variant where the cavity 2 is filled with a sacrificial material, the material is then deposited in the cavity 2 so as to be flush with the silicon surface of the front side 1a. Conventional steps of photolithography, masking, etching, deposition and polishing, which are not described here, are used to form the cavity and, if necessary, to fill the cavity.

[0024] A donor substrate 40 made of single crystal silicon is implanted through the front side 40a of the donor substrate so as to define an embedded weakening plane 41 that is substantially parallel to the front side 40a and outlines the thin layers 3, 4 to be transferred together with the front side 40a (FIG. 1b). The implantation is typically performed using light element species such as hydrogen ions or helium ions or a combination of these two elemental species. The weakening plane 41 is so named because it contains nano-cracks in a lens-shaped form generated by the implanted light element species.

[0025] According to one preferred option, the thin layers 3, 4 to be transferred are from the front side 40a of the donor substrate 40 to the embedding weakening surface 41, including the dielectric layer 3 and the silicon layer 4, and these layers will respectively form the embedded dielectric layer 3 and the silicon surface layer 4 of the SOI substrate 10. The implantation energy for light element species is selected and adjusted so as to form an embedding weakening surface (relatively localized at the implantation peak) at a depth corresponding to the desired thickness of the surface layer 4, taking into account the finishing step (described below) that consumes some of the material of the layer 4.

[0026] The donor substrate 40 and the carrier 1 are then joined by direct bonding between the front sides 40a, 1a of the substrates 40, 1 to form a bonded structure (Fig. 1c). As is well known in the field of direct bonding, cleaning and / or activation of the surfaces of the front sides 40a, 1a will probably be carried out to obtain a good-quality bond. It is possible for the substrate to be joined under a controlled atmosphere; this particularly enables the pressure in the cavity (to be filled following the joining operation) to be controlled when there is no sacrificial material in the said cavity.

[0027] The cracking at the embedding weakening surface 41 is preferably brought about by the application of heat treatment at an intermediate temperature, typically between 350 °C and 500 °C, due to the combination of gaseous element species and the growth of microcracks through pressurization (Fig. 1d). Alternatively or in conjunction, the cracking may be brought about by applying mechanical pressure to the bonded structure.

[0028] At the end of this cracking, an intermediate SOI substrate is obtained on one side and the remainder 40' of the donor substrate on the other side. Finishing procedures including cleaning, surface treatment (etching, polishing, etc.) and / or heat treatment are applied to the intermediate SOI substrate in a conventional manner to ensure that the silicon surface layer 4 again has a good surface finish (roughness and number of defects) and good crystal quality. After this, the SOI substrate 10 is available.

[0029] Although the production of the SOI substrate 10 having the embedded cavity 2 has been described herein with reference to the Smart Cut process, such an SOI substrate 10 may also be produced using other thin layer transfer processes known in this art.

[0030] The manufacturing method according to the invention then comprises step b) of forming an optical waveguide 50 comprising cores 52, 52' extending in a main plane (x, y) and surrounded by an optical confinement layer 53 formed in the surface layer 4 and including a dielectric layer 3 (FIG. 2).

[0031] The formation of the optical waveguide 50 requires locally etching the surface layer 4 so as to define the dimensions and shape of the waveguide in the main plane (x, y).

[0032] FIGS. 4a and 4b illustrate two different structures of the waveguide 50 in the case of a Mach-Zehnder interferometer and in the case of a ring resonator, respectively, as seen from above, i.e., in the main plane (x, y). Cores 52, 52' of the waveguide 50 may be seen in the figures, with one or more segments 52' of the core of the waveguide 50 being arranged perpendicular to one or more cavities 2 (dashed lines in FIGS. 4a and 4b). The length of the core 52 in the main plane (x, y) may vary depending on the target structure, and the width of the core is included in the conventional manner between 0.2 microns and 1 micron, preferably between 0.3 microns and 0.6 microns.

[0033] The formation of the optical waveguide 50 further requires that an additional dielectric layer 3' be deposited on the cores 52, 52' so as to encapsulate the cores 52, 52' in the dielectric layer 3 of the SOI substrate 10 and in the optical confinement layer 53, which is here called the cladding. The additional dielectric layer 3' is preferably made from silicon oxide. Its thickness typically includes between 0.5 microns and 1.5 microns.

[0034] In step b), after the optical waveguide 50 is formed, it is advantageous that an aperture (not shown) may be fabricated through the optical waveguide 50 in order to place at least one cavity 2 under an external pressure. The aperture is typically fabricated through the confinement layer 53 outside the region including the silicon cores 52, 52'. This aperture will likely be maintained or sealed after this placement under the external pressure to seal the cavity 2.

[0035] In the case where the embedded cavity 2 is filled with a sacrificial material, at least one aperture is formed to allow access to the material and to enable wet or dry etching aimed at removing the material and emptying the cavity 2 filled with the solid material. Again, the aperture will likely be maintained or sealed after the cavity 2 is emptied.

[0036] It is recalled that the cavity 2 is hermetically sealed at the end of step a) and may remain in this state during the use of the thermo - optical component, in certain embodiments, in step b) and / or step c), or even after the manufacture of the thermo - optical component. The hermeticity of the cavity 2 makes it possible to avoid the effects resulting from unwanted intrusion of gaseous or liquid elemental species into this cavity 2 during the manufacturing process, and these effects potentially cause problems associated with drying, bonding of the upper film structure, various types of contamination, degradation of the upper film structure, etc. Keeping the cavity 2 hermetic during the use of the component can also make it possible to guarantee the reproducibility of the operating point (especially in terms of thermal environment and mechanical deformation).

[0037] The manufacturing method then includes step c) of fabricating at least one heating element 60 in the optical waveguide 50 (Figure 3). This heating element 60 is arranged in the main plane (x, y) perpendicular to the embedded cavity 2. It is advantageous that the dimensions of the heating element 60 in this plane are smaller than the dimensions of the cavity 2, as shown in Figures 3, 4a and 4b.

[0038] Thus, again on the main plane (x, y), the heating element 60 is arranged either perpendicular to the core segment 52' of the optical waveguide 50 or on both sides of said segment 52' (Figs. 4a, 4b). This segment 52' corresponds to the part of the waveguide 50 that is subject to temperature variations applied by the heating element 60 and thus gives rise to the component 100 having the thermo-optical properties of the heating element.

[0039] According to one particular exemplary embodiment, the heating element 60 is formed by directly depositing a Ti / TiN laminate on the confinement layer 53 perpendicular to the segment 52' of the waveguide. The laminate may have a thickness of about 100 nm.

[0040] The heating element 60 further comprises two metal contact pads that are connected to a current source. When a current is applied, the heating element 60 dissipates heat via Joule heating and thus raises the temperature experienced by the core segment 52' of the waveguide 50.

[0041] The manufacturing method according to the invention is simple and effective: it limits the technical steps required to define and insulate the thermo-optical component 100, these steps being particularly based on chemical etching which is often difficult to control, and also further enables a high integration density to be achieved. The presence of (at least) one buried cavity 2 in the SOI substrate 10 facilitates the thermal insulation of the waveguide segment 52' which causes the thermo-optical effect, which makes it possible to limit heat losses via conduction, and the air or gas in the cavity forms an excellent insulator. In parallel, the thermal continuity of the optical confinement layer 53 around the core 52 of the optical waveguide 50 ensures a short transient response time during temperature changes of the heating element 60 and thus gives a component 100 with very good responsiveness. The presence of the dielectric layer 3 under the core 52' of the optical waveguide makes it possible to obtain a good compromise between the component response speed of waveguide control and the energy efficiency.

[0042] The manufacturing method according to the invention further provides a long-lasting thermo-optical component 100 because complex etching through the front or back side of the SOI substrate 10 is not required to form an insulator, and these etchings tend to reduce the mechanical strength of the component.

[0043] Needless to say, the invention is not limited to the described embodiments, and modified embodiments may be used without departing from the scope of the invention as defined by the claims.

Claims

1. A method for manufacturing a thermo-optical component (100), comprising: a) providing a silicon-on-insulator (SOI) substrate (10), said SOI substrate (10) comprising a surface layer (4) made of single-crystalline silicon, disposed on a dielectric layer (3) disposed on a silicon carrier (1) and extending in the main plane (x, y), and at least one buried cavity (2) formed in said carrier (1) and opening beneath said dielectric layer (3), and then b) forming an optical waveguide (50) extending in said main plane (x, y), comprising a core (52, 52') formed in said surface layer (4) and surrounded by a light confinement layer (53) comprising said dielectric layer (3), and then c) fabricating at least one heating element (60) in said optical waveguide (50), said heating element (60) being disposed in said main plane (x, y) perpendicular to a segment (52') of said optical waveguide (50) or on both sides of said segment (52'), and said heating element (60) and said segment (52') of said optical waveguide being disposed perpendicular to said at least one buried cavity (2). A method as described above.

2. The method for manufacturing a thermo-optical component (100) according to claim 1, wherein in step b), an aperture is fabricated through said optical waveguide (50) for disposing said at least one cavity (2) under an external pressure.

3. The method for manufacturing a thermo-optical component (100) according to claim 2, wherein said aperture is closed so as to airtight seal said at least one cavity (2).

4. The method for manufacturing a thermo-optical component (100) according to claim 1, wherein said at least one cavity (2) remains airtight sealed throughout steps a), b) and c).

5. The method for manufacturing a thermo-optical component (100) according to any one of claims 1 to 4, wherein said dielectric layer (3) is made of silicon oxide and has a thickness between 100 nm and 3 μm.

6. The method for manufacturing a thermo-optical component (100) according to any one of claims 1 to 5, wherein said surface layer (4) has a thickness between 100 nm and 500 nm.

7. A method for manufacturing a thermo-optical component (100) according to any one of claims 1 to 6, wherein the optical confinement layer (53) comprises an additional dielectric layer (3') having a thickness including a range between 0.5 μm and 1.5 μm.

8. A method for manufacturing a thermo-optical component (100) according to any one of claims 1 to 7, wherein the at least one cavity (2) has a lateral dimension including a range between 10 μm and several millimeters in the main plane (x, y), and a depth including a range between several μm and 100 μm along an axis (z) perpendicular to the main plane (x, y).

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