Electronic module and electronic device

Abstract

To suppress propagation of power supply noise.SOLUTION: A printed wiring board 300 of a processing module 100 has a ground line 320G for electrically connecting between an electrode 12 of a capacitor 151 and an electrode 14 of a capacitor 152. The ground line 320G includes a ground via 351G, a ground via 352G, and a ground pattern 350G arranged in an insulation substrate. The electrode 12 of the capacitor 151 is electrically connected with the ground pattern 350G via the ground via 351G. The electrode 14 of the capacitor 152 is electrically connected with the ground pattern 350G via the ground via 352G.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an electronic module and an electronic device including the electronic module.

Background Art

[0002] An electronic module mounted on an electronic device has a printed wiring board and a semiconductor device mounted on the printed wiring board. As an example of the semiconductor device, there is a semiconductor package. The semiconductor package has a semiconductor element and a package substrate on which the semiconductor element is mounted. When the semiconductor element operates, a current due to the operation of the semiconductor element flows through the power supply paths of the package substrate and the printed wiring board. The impedance of the power supply path is called the power supply impedance. A potential fluctuation occurs due to the product of the current flowing through the power supply path and the power supply impedance. This potential fluctuation is called a power supply potential fluctuation or a power supply noise.

[0003] Patent Document 1 describes a technique for reducing power supply noise by providing a plurality of bypass capacitors on the back surface of the mounting portion of the semiconductor device on the printed wiring board.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, some semiconductor devices include a plurality of circuits. In this type of semiconductor device, when each circuit operates, power supply noise caused by the operation of each circuit is generated. When the grounds are made common by a plurality of bypass capacitors, the power supply noise generated by the operation of one of the plurality of circuits may be propagated to the other circuits of the plurality of circuits via the ground.

[0006] The present invention aims to suppress the propagation of power supply noise.

Means for Solving the Problems

[0007] An aspect of the present disclosure No. 1 includes a printed wiring board having an insulating substrate, a first semiconductor device disposed on a first main surface of the insulating substrate, a first capacitor disposed on a second main surface of the insulating substrate opposite to the first main surface and overlapping the first semiconductor device in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface and overlapping the first semiconductor device in the direction. The first semiconductor device has a plurality of terminals including a first power supply terminal and a second power supply terminal, a first circuit electrically connected to the first power supply terminal, and a second circuit electrically connected to the second power supply terminal. The first capacitor has a first electrode and a second electrode, the second capacitor has a third electrode and a fourth electrode, and the printed wiring board has a first power supply line electrically connecting the first power supply terminal of the first semiconductor device and the first electrode of the first capacitor, a second power supply line electrically connecting the second power supply terminal of the first semiconductor device and the third electrode of the second capacitor, and a ground line electrically connecting the second electrode of the first capacitor and the fourth electrode of the second capacitor. The first power line includes a first power via, and the second power line includes a second power via. The ground line includes a first ground via, a second ground via, and a ground pattern disposed inside the insulating substrate. The first electrode of the first capacitor is electrically connected to the first power terminal via the first power via. The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via. The third electrode of the second capacitor is electrically connected to the second power terminal via the second power via. The fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via. The first power via and the second power via are surrounded by the ground pattern. It is an electronic module characterized by the above. A second aspect of the present disclosure includes a printed wiring board having an insulating substrate, a first semiconductor device disposed on a first main surface of the insulating substrate, a first capacitor disposed on a second main surface of the insulating substrate opposite to the first main surface and overlapping the first semiconductor device in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface and overlapping the first semiconductor device in the direction. The first semiconductor device includes a plurality of terminals including a first power terminal and a second power terminal, a first circuit electrically connected to the first power terminal, and a second circuit electrically connected to the second power terminal. The first capacitor has a first electrode and a second electrode, and the second capacitor has a third electrode and a fourth electrode. The printed wiring board has a first power line electrically connecting the first power terminal of the first semiconductor device and the first electrode of the first capacitor, a second power line electrically connecting the second power terminal of the first semiconductor device and the third electrode of the second capacitor, and a ground line electrically connecting the second electrode of the first capacitor and the fourth electrode of the second capacitor. The ground line includes a first ground via, a second ground via, and a ground pattern disposed inside the insulating substrate. The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via, and the fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via. The center-to-center distance between the first ground via and the second ground via is not more than twice the center-to-center distance between two adjacent terminals among the plurality of terminals. The electronic module is characterized by this. A third aspect of the present disclosure includes a printed wiring board having an insulating substrate, a first semiconductor device disposed on a first main surface of the insulating substrate, a first capacitor disposed on a second main surface of the insulating substrate opposite to the first main surface and at a position overlapping the first semiconductor device in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface and at a position overlapping the first semiconductor device in the direction. The first semiconductor device has a plurality of terminals including a first power supply terminal and a second power supply terminal, a first circuit electrically connected to the first power supply terminal, and a second circuit electrically connected to the second power supply terminal. The first capacitor has a first electrode and a second electrode, and the second capacitor has a third electrode and a fourth electrode. The printed wiring board has a first power supply line electrically connecting the first power supply terminal of the first semiconductor device and the first electrode of the first capacitor, a second power supply line electrically connecting the second power supply terminal of the first semiconductor device and the third electrode of the second capacitor, and a ground line electrically connecting the second electrode of the first capacitor and the fourth electrode of the second capacitor. The ground line includes a first ground via, a second ground via, and a ground pattern disposed inside the insulating substrate. The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via, and the fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via. The electronic module further includes a second semiconductor device having a ground terminal electrically connected to the ground line. The ground line has a third ground via, and the ground terminal is electrically connected to the ground pattern via the third ground via. A center-to-center distance between the first ground via and the second ground via is shorter than each of a center-to-center distance between the first ground via and the third ground via and a center-to-center distance between the second ground via and the third ground via. A fourth aspect of the present disclosure includes a printed wiring board having an insulating substrate, a first semiconductor device disposed on a first main surface of the insulating substrate, a first capacitor disposed on a second main surface of the insulating substrate opposite to the first main surface and overlapping the first semiconductor device in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface and overlapping the first semiconductor device in the direction. The first semiconductor device includes a plurality of terminals including a first power terminal and a second power terminal, a first circuit electrically connected to the first power terminal, and a second circuit electrically connected to the second power terminal. The first capacitor has a first electrode and a second electrode, the second capacitor has a third electrode and a fourth electrode, the printed wiring board has a first power line electrically connecting the first power terminal of the first semiconductor device and the first electrode of the first capacitor, a second power line electrically connecting the second power terminal of the first semiconductor device and the third electrode of the second capacitor, and a ground line electrically connecting the second electrode of the first capacitor and the fourth electrode of the second capacitor. The ground line includes a first ground via, a second ground via, and a ground pattern disposed inside the insulating substrate. The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via, the fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via, and the electronic module further includes an electrical component that electrically connects the first power line and the second power line, and the electrical component is a low-pass filter component.

Advantages of the Invention

[0008] According to the present invention, the propagation of power supply noise can be suppressed.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of a digital camera 600 which is an example of an electronic device according to an embodiment. The digital camera 600 which is an imaging device is an interchangeable-lens digital camera and includes a camera body 601. A lens unit (lens barrel) 602 including a lens is detachable from the camera body 601. The camera body 601 includes a housing 611, and a processing module 100 and a sensor module 900 which are disposed inside the housing 611. The processing module 100 is an example of an electronic module and is composed of a printed circuit board. The processing module 100 and the sensor module 900 are electrically connected by a cable 400. A battery (not shown) is provided inside the housing 611.

[0011] The sensor module 900 includes an image sensor 901 which is an imaging device, and a printed wiring board 902. The image sensor 901 is mounted on the printed wiring board 902. The image sensor 901 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor. The image sensor 901 has a function of converting the light incident through the lens unit 602 into an electrical signal.

[0012] The processing module 100 includes a semiconductor device 200, a power supply device 140, and a printed wiring board 300. The semiconductor device 200 is an example of a first semiconductor device. The power supply device 140 is an example of a second semiconductor device.

[0013] The semiconductor device 200 and the power supply device 140 are mounted on the printed wiring board 300. The printed wiring board 300 is a rigid wiring board. The semiconductor device 200 is, for example, a digital signal processor, and has a function of acquiring an electrical signal from the image sensor 901, performing a process of correcting the acquired electrical signal, and generating image data. The power supply device 140 is a device that supplies power from a battery (not shown) to each part of the digital camera 600 including the semiconductor device 200. The power supply device 140 is an IC having a power supply element. The power supply device 140 applies a DC voltage to the semiconductor device 200 via the printed wiring board 300 to supply the necessary power for operation, that is, the power supply current. A power supply path including a power supply line and a ground line for supplying power, that is, the power supply current, from the power supply device 140 to the semiconductor device 200 is formed on the printed wiring board 300.

[0014] FIG. 2 is a perspective view showing a part of the processing module 100 according to the embodiment. The semiconductor device 200 is a semiconductor package, and in this embodiment, it is a BGA (Ball Grid Array) semiconductor package. The semiconductor device 200 includes a package substrate 201 and a semiconductor element 202 mounted on the package substrate 201.

[0015] The semiconductor element 202 is a semiconductor chip and has a die 2020 encapsulated with a sealing resin. The die 2020 has a plurality of core circuits that perform arithmetic processing on the received digital signal, and a plurality of transmission circuits (buffers) that transmit the digital signal output from the plurality of core circuits to an external device or another semiconductor device. In the present embodiment, the plurality of transmission circuits include a circuit 2021 which is an example of a first circuit, and a circuit 2022 which is an example of a second circuit. The circuit 2021 is, for example, an LVCMOS transmission circuit. The circuit 2022 is, for example, a USB transmission circuit. The power supply current supplied to the circuit 2021 when the circuit 2021 operates is larger than the power supply current supplied to the circuit 2022 when the circuit 2022 operates. Each of the circuits 2021 and 2022 is any one of the plurality of transmission circuits, but may also be any one of the plurality of core circuits.

[0016] The package substrate 201 is an example of an interposer. The semiconductor element 202 is electrically and mechanically connected to the package substrate 201 by a plurality of solder bumps 203. The semiconductor device 200 has a plurality of terminals 204 disposed on the main surface of the package substrate 201 opposite to the main surface on which the semiconductor element 202 is mounted among the pair of main surfaces of the package substrate 201. The package substrate 201 is electrically and mechanically connected to the printed wiring board 300 by the plurality of terminals 204. Each terminal 204 is composed of, for example, a solder ball. The plurality of terminals 204 are arranged in a grid pattern.

[0017] The processing module 100 has a plurality of capacitors, for example, two capacitors 151 and 152, mounted on the printed wiring board 300. The capacitor 151 is an example of a first capacitor, and the capacitor 152 is an example of a second capacitor. These capacitors 151 and 152 are bypass capacitors provided in the power supply path to suppress power supply potential fluctuations, that is, power supply noise, generated by the operation of the semiconductor device 200. Each of the capacitors 151 and 152 is provided between a power supply line and a ground line included in the power supply path. That is, one of the pair of electrodes of each of the capacitors 151 and 152 is electrically connected to the power supply line, and the other electrode is electrically connected to the ground line.

[0018] The printed wiring board 300 has an insulating substrate 310. The insulating substrate 310 is flat and has a pair of main surfaces 311 and 312. The main surface 312 is the main surface opposite to the main surface 311. The main surface 311 is an example of a first main surface, and the main surface 312 is an example of a second main surface. In the present embodiment, the semiconductor device 200 is disposed on the main surface 311 of the insulating substrate 310 of the printed wiring board 300, and each of the capacitors 151 and 152 is disposed on the main surface 312 of the insulating substrate 310 of the printed wiring board 300. Each of the capacitors 151 and 152 is disposed at a position overlapping the semiconductor device 200 when viewed in the Z direction. The Z direction is a direction perpendicular to the main surfaces 311 and 312.

[0019] FIG. 3 is a schematic diagram for explaining the wiring structure of the mounting portions of the capacitors 151 and 152 in the processing module 100 according to the embodiment. Note that in FIG. 3, the illustration of the insulating substrate 310 is omitted. The printed wiring board 300 has a plurality of conductor layers 301, 302, 303 and a solder resist layer (not shown). Each of the conductor layers 301 to 303 is a layer on which a conductor pattern is arranged. The conductor layer 301 is an outer layer, that is, a surface layer, arranged on the main surface 311, and the conductor layer 302 is an outer layer, that is, a surface layer, arranged on the main surface 312. The conductor layer 303 is an inner layer arranged inside the insulating substrate 310, that is, between the conductor layer 301 and the conductor layer 302. Portions other than the pads used for soldering in the conductor patterns of the conductor layers 301 and 302 are covered with the solder resist layer. The pads are SMD (Solder Mask Defined) or NSMD (Non-solder Mask Defined) pads.

[0020] The plurality of terminals 204 includes a power supply terminal 211E, a ground terminal 211G, a power supply terminal 212E, and a ground terminal 212G. The power supply terminal 211E is an example of a first power supply terminal. The ground terminal 211G is an example of a first ground terminal. The power supply terminal 212E is an example of a second power supply terminal. The ground terminal 212G is an example of a second ground terminal. The power supply terminal 211E is electrically connected to the power supply side of the circuit 2021, and the ground terminal 211G is electrically connected to the ground side of the circuit 2021. The power supply terminal 212E is electrically connected to the power supply side of the circuit 2022, and the ground terminal 212G is electrically connected to the ground side of the circuit 2022.

[0021] The printed wiring board 300 has a power line 321E electrically connected to the power terminal 211E and a power line 322E electrically connected to the power terminal 212E. The power line 321E is an example of a first power line. The power line 322E is an example of a second power line. Also, the printed wiring board 300 has a ground line 320G electrically connected to the ground terminals 211G and 212G. That is, the ground terminals 211G and 212G are electrically connected by a common ground line 320G.

[0022] The capacitor 151 has a pair of electrodes 11 and 12. The capacitor 152 has a pair of electrodes 13 and 14. The electrode 11 is an example of a first electrode, and the electrode 12 is an example of a second electrode. The electrode 13 is an example of a third electrode, and the electrode 14 is an example of a fourth electrode.

[0023] The power terminal 211E of the semiconductor device 200 and the electrode 11 of the capacitor 151 are electrically connected by the power line 321E. The power terminal 212E of the semiconductor device 200 and the electrode 13 of the capacitor 152 are electrically connected by the power line 322E. The ground terminals 211G and 212G of the semiconductor device 200, the electrode 12 of the capacitor 151, and the electrode 14 of the capacitor 152 are electrically connected by the ground line 320G. The power lines 321E and 322E and the ground line 320G are power supply paths for supplying power to the semiconductor device 200 by the power supply device 140. Therefore, each circuit 2021 and 2022 of the semiconductor element 202 is supplied with power, that is, a power supply current, by the power supply device 140 via the respective power lines 321E and 322E.

[0024] Each of the power line 321E, the power line 322E, and the ground line 320G is composed of a conductor, for example, copper provided on the insulating substrate 310.

[0025] The power line 321E includes a power pattern 331E formed in the conductor layer 301, a power pattern 341E formed in the conductor layer 302, and a power via 351E formed in contact with the power pattern 331E and the power pattern 341E.

[0026] The power via 351E is a via conductor that connects the power pattern 331E and the power pattern 341E. The power pattern 331E has a pad 3311E, and a power terminal 211E is joined to the pad 3311E. The power pattern 341E has a pad 3411E, and an electrode 11 of the capacitor 151 is joined to the pad 3411E.

[0027] The power line 322E includes a power pattern 332E formed in the conductor layer 301, a power pattern 342E formed in the conductor layer 302, and a power via 352E formed in contact with the power pattern 332E and the power pattern 342E.

[0028] The power via 352E is a via conductor that connects the power pattern 332E and the power pattern 342E. The power pattern 332E has a pad 3321E, and a power terminal 212E is joined to the pad 3321E. The power pattern 342E has a pad 3421E, and an electrode 13 of the capacitor 152 is joined to the pad 3421E.

[0029] The ground line 320G includes a ground pattern 331G formed on the conductor layer 301 and a ground pattern 332G formed on the conductor layer 301. Further, the ground line 320G includes a ground pattern 341G formed on the conductor layer 302 and a ground pattern 342G formed on the conductor layer 302. Further, the ground line 320G includes a ground via 351G formed in contact with the ground pattern 331G and the ground pattern 341G. Further, the ground line 320G includes a ground via 352G formed in contact with the ground pattern 332G and the ground pattern 342G. The ground via 351G is an example of a first ground via, and the ground via 352G is an example of a second ground via.

[0030] The ground via 351G is a via conductor that connects the ground pattern 331G and the ground pattern 341G. The ground pattern 331G has a pad 3311G, and a ground terminal 211G is joined to the pad 3311G. The ground pattern 341G has a pad 3411G, and an electrode 12 of the capacitor 151 is joined to the pad 3411G.

[0031] The ground via 352G is a via conductor that connects the ground pattern 332G and the ground pattern 342G. The ground pattern 332G has a pad 3321G, and a ground terminal 212G is joined to the pad 3321G. The ground pattern 342G has a pad 3421G, and an electrode 14 of the capacitor 152 is joined to the pad 3421G.

[0032] The power supply via 351E is arranged in proximity to the capacitor 151. In the present embodiment, the power supply via 351E is arranged relatively close to the capacitor 151 among the capacitors 151, 152 and the power supply device 140.

[0033] The power via 352E is arranged in proximity to the capacitor 152. In this embodiment, the power via 352E is arranged relatively close to the capacitor 152 among the capacitors 151, 152 and the power supply device 140.

[0034] The ground via 351G is arranged in proximity to the capacitor 151. In this embodiment, the ground via 351G is arranged relatively close to the capacitor 151 among the capacitors 151, 152 and the power supply device 140.

[0035] The ground via 352G is arranged in proximity to the capacitor 152. In this embodiment, the ground via 352G is arranged relatively close to the capacitor 152 among the capacitors 151, 152 and the power supply device 140.

[0036] The power supply device 140 includes a power supply circuit 1401, a power supply terminal (not shown), and a ground terminal 1402. The power supply terminal (not shown) and the ground terminal 1402 are electrically connected to the power supply circuit 1401. The power supply terminal (not shown) of the power supply device 140 is electrically connected to the power supply line 321E. The ground terminal 1402 of the power supply device 140 is electrically connected to the ground line 320G. The power supply circuit 1401 is an example of a third circuit. The power supply circuit 1401 is a circuit for supplying power to each of the circuits 2021, 2022.

[0037] The ground line 320G includes a ground pattern 363G formed in the conductor layer 302 and a ground via 353G arranged in proximity to the power supply device 140. The ground via 353G is an example of a third ground via. In this embodiment, the ground via 353G is arranged relatively close to the power supply device 140 among the capacitors 151, 152 and the power supply device 140. The ground terminal 1402 of the power supply device 140 is joined to the pad of the ground pattern 363G. The ground pattern 363G is connected to the ground via 353G by contacting the ground via 353G.

[0038] The power supply line 321E and the power supply line 322E are electrically connected by a low-pass filter component, which is a ferrite bead 160 in this embodiment. The ferrite bead 160 is an example of an electrical component.

[0039] As described above, the power supply terminals of the power supply device 140 are electrically connected to the power supply terminals 211E and 212E of the semiconductor device 200, the electrode 11 of the capacitor 151, and the electrode 13 of the capacitor 152 via the power supply lines 321E, 322E and the ferrite bead 160. Also, the ground terminal 1402 of the power supply device 140 is electrically connected to the ground terminals 211G and 212G of the semiconductor device 200, the electrode 12 of the capacitor 151, and the electrode 14 of the capacitor 152 via the ground line 320G.

[0040] Here, the processing module of the comparative example will be described. FIG. 4 is a perspective view showing a part of the processing module 100Y of the comparative example. The processing module 100Y includes a printed wiring board 300Y and a semiconductor device 200Y mounted on the printed wiring board 300Y. The semiconductor device 200Y is a semiconductor package and has a package substrate 201Y and a semiconductor element 202Y mounted on the package substrate 201Y. The semiconductor element 202Y is a semiconductor chip and has a die 2020Y encapsulated with a sealing resin. The die 2020Y has a circuit 2021Y and a circuit 2022Y. The power supply current supplied to the circuit 2021Y when the circuit 2021Y operates is larger than the power supply current supplied to the circuit 2022Y when the circuit 2022Y operates.

[0041] The semiconductor element 202Y is electrically and mechanically connected to the package substrate 201Y by a plurality of solder bumps 203Y. The package substrate 201Y of the semiconductor device 200Y is electrically and mechanically connected to the printed wiring board 300Y by a plurality of terminals 204Y. Each terminal 204Y is composed of, for example, a solder ball. The plurality of terminals 204Y are arranged in a grid pattern.

[0042] The processing module 100Y includes two capacitors 151Y and 152Y mounted on the printed wiring board 300Y. Each of the capacitors 151Y and 152Y is a bypass capacitor.

[0043] The printed wiring board 300Y has an insulating substrate 310Y. The insulating substrate 310Y has a pair of main surfaces 311Y and 312Y. The semiconductor device 200Y is disposed on the main surface 311Y of the insulating substrate 310Y, and each of the capacitors 151Y and 152Y is disposed on the main surface 312Y of the insulating substrate 310Y. Each of the capacitors 151Y and 152Y is disposed at a position overlapping the semiconductor device 200Y when viewed in the Z direction.

[0044] FIG. 5 is a schematic diagram for explaining the wiring structure of the mounting portions of the capacitors 151Y and 152Y in the processing module 100Y of the comparative example. The processing module 100Y includes a power supply device 140Y mounted on the printed wiring board 300Y. The printed wiring board 300Y has a plurality of conductor layers 301Y and 302Y and a solder resist layer (not shown). The conductor layer 301Y is an outer layer, i.e., a surface layer, disposed on the main surface 311Y, and the conductor layer 302Y is an outer layer, i.e., a surface layer, disposed on the main surface 312Y. The plurality of terminals 204Y of the semiconductor device 200Y include a power supply terminal 211EY, a ground terminal 211GY, a power supply terminal 212EY, and a ground terminal 212GY. The power supply terminal 211EY is electrically connected to the power supply side of the circuit 2021Y, and the ground terminal 211GY is electrically connected to the ground side of the circuit 2021Y. The power supply terminal 212EY is electrically connected to the power supply side of the circuit 2022Y, and the ground terminal 212GY is electrically connected to the ground side of the circuit 2022Y.

[0045] The printed wiring board 300Y has a power line 321EY electrically connected to the power terminal 211EY and a power line 322EY electrically connected to the power terminal 212EY. The printed wiring board 300Y also has a ground line 320GY electrically connected to the ground terminals 211GY and 212GY. That is, the ground terminals 211GY and 212GY are electrically connected by a common ground line 320GY.

[0046] The capacitor 151Y has a pair of electrodes 11Y and 12Y. The capacitor 152Y has a pair of electrodes 13Y and 14Y. The power terminal 211EY of the semiconductor device 200Y and the electrode 11Y of the capacitor 151Y are electrically connected by the power line 321EY. The power terminal 212EY of the semiconductor device 200Y and the electrode 13Y of the capacitor 152Y are electrically connected by the power line 322EY. The ground terminals 211GY and 212GY of the semiconductor device 200Y, the electrode 12Y of the capacitor 151Y, and the electrode 14Y of the capacitor 152Y are electrically connected by the ground line 320GY. The power supply device 140Y supplies power, that is, a power supply current, to each of the circuits 2021Y and 2022Y of the semiconductor element 202Y via the power lines 321EY and 322EY.

[0047] The power line 321EY includes a power pattern 331EY formed in the conductor layer 301Y, a power pattern 341EY formed in the conductor layer 302Y, and a power via 351EY formed in contact with the power pattern 331EY and the power pattern 341EY.

[0048] The power via 351EY is a via conductor that connects the power pattern 331EY and the power pattern 341EY. The power terminal 211EY is joined to the pad of the power pattern 331EY. The electrode 11Y of the capacitor 151Y is joined to the pad of the power pattern 341EY.

[0049] The power line 322EY includes a power pattern 332EY formed on the conductor layer 301Y, a power pattern 342EY formed on the conductor layer 302Y, and a power via 352EY formed in contact with the power pattern 332EY and the power pattern 342EY.

[0050] The power via 352EY is a via conductor that connects the power pattern 332EY and the power pattern 342EY. A power terminal 212EY is joined to the pad of the power pattern 332EY. An electrode 13Y of the capacitor 152Y is joined to the pad of the power pattern 342EY.

[0051] The ground line 320GY includes a ground pattern 331GY formed on the conductor layer 301Y and a ground pattern 332GY formed on the conductor layer 301Y. The ground line 320GY also includes a ground pattern 341GY formed on the conductor layer 302Y and a ground pattern 342GY formed on the conductor layer 302Y. The ground line 320GY further includes a ground via 351GY formed in contact with the ground pattern 331GY and the ground pattern 341GY. The ground line 320GY also includes a ground via 352GY formed in contact with the ground pattern 332GY and the ground pattern 342GY.

[0052] The ground via 351GY is a via conductor that connects the ground pattern 331GY and the ground pattern 341GY. A ground terminal 211GY is joined to the pad of the ground pattern 331GY. An electrode 12Y of the capacitor 151Y is joined to the pad of the ground pattern 341GY.

[0053] The ground via 352GY is a via conductor that connects the ground pattern 332GY and the ground pattern 342GY. A ground terminal 212GY is joined to the pad of the ground pattern 332GY. An electrode 14Y of the capacitor 152Y is joined to the pad of the ground pattern 342GY.

[0054] The power supply device 140Y includes a power supply circuit 1401Y, a power supply terminal (not shown), and a ground terminal 1402Y. The power supply terminal (not shown) and the ground terminal 1402Y are electrically connected to the power supply circuit 1401Y. The power supply terminal (not shown) of the power supply device 140Y is electrically connected to the power supply line 321EY. The ground terminal 1402Y of the power supply device 140Y is electrically connected to the ground line 320GY.

[0055] The ground line 320GY includes a ground pattern 363GY formed in the conductor layer 302Y and a ground via 353GY. The ground terminal 1402Y of the power supply device 140Y is joined to the pad of the ground pattern 363GY. The ground pattern 363GY is connected to the ground via 353GY by contacting the ground via 353GY.

[0056] The power supply line 321EY and the power supply line 322EY are electrically connected by a ferrite bead 160Y.

[0057] In the comparative example, the ground line 320GY includes a ground pattern 340GY formed in the conductor layer 302Y that connects the ground via 351GY and the ground via 352GY. The ground pattern 340GY is also a conductor pattern that connects the ground pattern 341GY and the ground pattern 342GY in the conductor layer 302Y. The width of the ground pattern 340GY is wider than the diameter of each of the ground vias 351GY, 352GY. Also, the width of the ground pattern 340GY is equal to or greater than the diameter of the via land of each of the ground vias 351GY, 352GY. Thus, in the comparative example, the shortest path among the conduction paths between the electrode 12Y of the capacitor 151Y and the electrode 14Y of the capacitor 152Y is formed by the ground pattern 341GY, the wide ground pattern 340GY, and the ground pattern 342GY.

[0058] In circuit 2021Y, power, that is, power current, is supplied from power supply device 140Y via power supply line 321EY. When circuit 2021Y operates, a power supply potential fluctuation corresponding to its operation, that is, power supply noise, is generated in circuit 2021Y. By supplying charge to circuit 2021Y by capacitor 151Y disposed between power via 351EY and ground via 351GY, the power supply potential fluctuation in circuit 2021Y is suppressed. At this time, a power supply potential fluctuation corresponding to the inductance of the wiring from capacitor 151Y to circuit 2021Y occurs between electrode 11Y and electrode 12Y in capacitor 151Y.

[0059] The power supply potential fluctuation occurring between electrode 11Y and electrode 12Y in capacitor 151Y becomes a potential fluctuation in ground line 320GY. The inventors have found that this potential fluctuation propagates to capacitor 152Y via ground pattern 340GY, and a power supply potential fluctuation occurs between electrode 13Y and electrode 14Y in capacitor 152Y. The power supply potential fluctuation propagated to capacitor 152Y may cause the operation of circuit 2022Y to become unstable when it propagates to circuit 2022Y.

[0060] Note that the same applies when circuit 2022Y operates, but the current value of the power supply current supplied to circuit 2022Y by the operation of circuit 2022Y is smaller than the current value of the power supply current supplied to circuit 2021Y by the operation of circuit 2021Y. Therefore, the power supply potential fluctuation generated by the operation of circuit 2022Y is smaller than the power supply potential fluctuation generated by the operation of circuit 2021Y.

[0061] Since circuit 2022Y has a relatively small current value of the operating current, the allowable value of the power supply potential fluctuation is small. For such a circuit 2022Y, it is preferable to prevent power supply noise from other power supply lines 321EY from flowing in by ferrite bead 160Y in printed wiring board 300Y. Therefore, in the comparative example, the power supply noise flowing from power supply line 321EY to power supply line 322EY is suppressed by ferrite bead 160Y.

[0062] However, as described above, the capacitor 151Y that functions as a charge supply source supplies charge to the circuit 2021Y, causing a potential fluctuation between the electrode 11Y and the electrode 12Y. The electrode 12Y of the capacitor 151Y is electrically connected to the ground terminal 1402Y of the power supply device 140Y via the ground pattern 340GY. Therefore, depending on the impedance of the ground pattern 340GY, a potential fluctuation occurs in the ground pattern 340GY. Then, a potential fluctuation occurs between the power supply pad and the ground pad of the circuit 2022Y via the capacitor 152Y connected to the ground pattern 340GY.

[0063] Therefore, in the present embodiment, by controlling the impedance of the wiring structure between the electrode 12 of the capacitor 151 and the electrode 14 of the capacitor 152 in the printed wiring board 300, the propagation of power supply noise from the circuit 2021 to the circuit 2022 is suppressed.

[0064] As shown in FIG. 3, the ground line 320G has a ground pattern 350G disposed in the conductor layer 303 inside the insulating substrate 310 (FIG. 2). The ground pattern 350G is a solid conductor pattern and is formed over substantially the entire conductor layer 303. The ground pattern 350G is in contact with the ground vias 351G, 352G, 353G in the conductor layer 303 and is connected to the ground vias 351G, 352G, 353G. Thereby, the electrode 12 of the capacitor 151 is electrically connected to the ground pattern 350G via the ground via 351G, and the electrode 14 of the capacitor 152 is electrically connected to the ground pattern 350G via the ground via 352G.

[0065] In this embodiment, the ground line 320G does not include a conductor pattern that directly connects the ground via 351G and the ground via 352G in the conductor layer 302, that is, the ground pattern 340GY of the comparative example shown in FIG. 5. In other words, in the conductor layer 302, the ground pattern 341G and the ground pattern 342G are not electrically connected by a conductor pattern such as the ground pattern 340GY. In this embodiment, since the ground pattern 340GY does not exist, the ground pattern 350G is included in the shortest path P among the conduction paths between the electrode 12 of the capacitor 151 and the electrode 14 of the capacitor 152. The shortest path P includes the portion between the conductor layer 302 and the conductor layer 303 in the ground via 351G and the portion between the conductor layer 302 and the conductor layer 303 in the ground via 352G. That is, the electrode 12 of the capacitor 151 is electrically connected to the electrode 14 of the capacitor 152 via the ground pattern 350G of the conductor layer 303. As a result, the shortest path P becomes longer than the straight-line distance between the ground via 351G and the ground via 352G by passing through the ground pattern 350G. Therefore, in the high-frequency band where the voltage level of the power supply noise becomes high, the impedance value in the wiring between the electrode 12 of the capacitor 151 and the electrode 14 of the capacitor 152 increases. Accordingly, the propagation of the power supply noise from the circuit 2021 to the circuit 2022 through the capacitors 151 and 152 is suppressed. Thereby, the operation of the circuit 2022 becomes more stable.

[0066] When viewed in the Z direction, the center-to-center distance D2 between the ground via 351G and the ground via 352G is preferably not more than twice the center-to-center distance D1 between two adjacent ones of the plurality of terminals 204. Here, the center of each of the ground vias 351G, 352G, and 353G is the center of the circle of each of the ground vias 351G, 352G, and 353G when viewed in the Z direction. The center-to-center distance D2 is the distance between a center line extending in the Z direction passing through the center of the ground via 351G and a center line extending in the Z direction passing through the center of the ground via 352G when viewed in the Z direction. The center of each terminal 204 is also the center of the circle of each terminal 204 when viewed in the Z direction. The center-to-center distance D1 is the distance between two center lines extending in the Z direction passing through the centers of the two terminals 204 when viewed in the Z direction. By making the center-to-center distance D2 not more than twice the center-to-center distance D1, it is possible to effectively suppress the propagation of power supply noise from the circuit 2021 to the circuit 2022 when realizing high-density wiring on the printed wiring board 300.

[0067] From the perspective of high-density wiring, when viewed in the Z direction, it is preferable that the center-to-center distance D2 is 1 times or less of the center-to-center distance D1. Hereinafter, the description will be made with reference to FIG. 3 of the present embodiment and FIG. 5 of the comparative example. When the center-to-center distance D2 is 1 times or less of the center-to-center distance D1, let the amount of noise propagated from the capacitor 151 to the capacitor 152 be V1. Also, when the center-to-center distance D2Y between the ground via 351GY and the ground via 352GY is 1 times or less of the center-to-center distance D1Y between two adjacent terminals 204Y, let the amount of noise propagated from the capacitor 151Y to the capacitor 152Y be V1Y. Further, when the center-to-center distance D2 exceeds 1 times and is 2 times or less of the center-to-center distance D1, let the amount of noise propagated from the capacitor 151 to the capacitor 152 be V2. Also, when the center-to-center distance D2Y exceeds 1 times and is 2 times or less of the center-to-center distance D1Y, let the amount of noise propagated from the capacitor 151Y to the capacitor 152Y be V2Y. The ratio V1 / V1Y of the noise amount V1 to the noise amount V1Y is smaller than the ratio V2 / V2Y of the noise amount V2 to the noise amount V2Y. That is, when the center-to-center distance D2 is 1 times or less of the center-to-center distance D1, the effect of reducing the power supply noise propagated from the capacitor 151 to the capacitor 152 is improved. Therefore, in the present embodiment, when realizing high-density wiring on the printed wiring board 300, the power supply noise propagated from the circuit 2021 to the circuit 2022 can be effectively reduced.

[0068] [Example] Hereinafter, the experimental results of Example 1 and Comparative Example 1 will be described. Example 1 is a specific example of the above embodiment. Comparative Example 1 is a specific example of the above comparative example.

[0069] (Example 1) The thickness of the printed wiring board 300 was set to 1.2 mm. The thickness of each conductor layer 301, 302 of the printed wiring board 300 was set to 0.0043 mm. The thickness of the conductor layer 303 was set to 0.0035 mm. The thickness of the dielectric layer between the conductor layer 301 and the conductor layer 303 in the insulating substrate 310 was set to 0.1 mm. The center-to-center distance D1 between the two terminals 204 in the semiconductor device 200 was set to 0.8 mm. The diameter of each via 351E, 352E, 351G, 352G, 353G was set to 0.25 mm, and the diameter of the via pad formed in each conductor layer 301, 302 for each via 351E, 352E, 351G, 352G, 353G was set to 0.5 mm. The center-to-center distance D2 was set to be not more than twice the center-to-center distance D1, specifically 1.6 mm.

[0070] The ground terminal 1402 of the power supply device 140 is electrically connected to the ground pattern 350G via the ground via 353G. When viewed in the Z direction, the center-to-center distance D3 between the ground via 351G and the ground via 353G was set to be longer than 1.6 mm. Specifically, the center-to-center distance D3 was set to 100 mm. Also, when viewed in the Z direction, the center-to-center distance D4 between the ground via 352G and the ground via 353G was set to be longer than 1.6 mm. Specifically, the center-to-center distance D 4 was set to 100 mm.

[0071] Here, the center-to-center distance D3 is the distance between the center line extending in the Z direction passing through the center of the ground via 351G when viewed in the Z direction and the center line extending in the Z direction passing through the center of the ground via 353G when viewed in the Z direction. The center-to-center distance D4 is the distance between the center line extending in the Z direction passing through the center of the ground via 35 2It is the distance between the center line extending in the Z direction passing through the center of G and the center line extending in the Z direction passing through the center of the ground via 353G when viewed in the Z direction. The wiring width of each power supply pattern 341E, 342E was set to 0.38 mm. Each capacitor 151, 152 was a chip component of 0603 size. For each capacitor 151, 152, one with a nominal electrostatic capacitance (rated capacitance) of 1 μF was used. The ferrite bead 160 was a chip component of 1005 size. For the ferrite bead 160, one with an impedance value of 120 Ω at 100 MHz was used.

[0072] (Comparative Example 1) The center-to-center distance D1Y between two adjacent terminals 204Y among the plurality of terminals 204Y was set to 0.8 mm. The center-to-center distance D2Y between the ground via 351GY and the ground via 352GY was set to 1.6 mm.

[0073] Each capacitor 151Y, 152Y was a chip component of 0603 size. The ferrite bead 160Y was a chip component of 1005 size.

[0074] The thickness of the printed wiring board 300Y was set to 1.2 mm. Also, the diameter of each via 351EY, 351GY, 352EY, 352GY, 353GY was set to 0.25 mm. For each capacitor 151Y, 152Y, one with a nominal electrostatic capacitance of 1 μF was used. For the ferrite bead 160Y, one with an impedance value of 120 Ω at 100 MHz was used.

[0075] In the above configuration, the transfer impedance characteristics (Z21) in Example 1 and Comparative Example 1 were measured. In Example 1, the transfer impedance characteristics between the power supply pad and the ground pad of circuit 2021 and the power supply pad and the ground pad of circuit 2022 were measured. In Comparative Example 1, the transfer impedance characteristics between the power supply pad and the ground pad of circuit 2021Y and the power supply pad and the ground pad of circuit 2022Y were measured.

[0076] Fig. 6(a) is a graph showing the transfer impedance characteristics of Example 1 and Comparative Example 1. The transfer impedance characteristics indicate how much noise propagates to the other circuit when a power supply current flows through one circuit. The solid line represents Example 1, and the dashed line represents Comparative Example 1. The operating currents of circuits 2021, 2022, 2021Y, and 2022Y were made the same as each other.

[0077] In each of Example 1 and Comparative Example 1, when the operating current of each of circuits 2021 and 2021Y is I1, the propagated noise voltage V21 observed in each of circuits 2022 and 2022Y is represented by Equation (1). V21 = I1 × Z21 (1)

[0078] Fig. 6(b) is a graph showing the waveforms of the power supply potential fluctuations observed in Example 1 and Comparative Example 1. The solid line represents Example 1, and the dashed line represents Comparative Example 1. For Example 1, the waveform of the power supply potential fluctuation observed between the power supply pad and the ground pad of circuit 2022 when circuits 2021 and 2022 were operated is illustrated in Fig. 6(b). For Comparative Example 1, the waveform of the power supply potential fluctuation observed between the power supply pad and the ground pad of circuit 2022Y when circuits 2021Y and 2022Y were operated is illustrated in Fig. 6(b).

[0079] The operating current of circuit 2021Y becomes instantaneously about 100 times larger than the operating current of circuit 2022Y. The amplitude of the power supply potential fluctuation in Comparative Example 1 was about 230 mV. Here, the allowable value of the power supply potential fluctuation of each of circuits 2022 and 2022Y is 50 mV. Therefore, the amplitude of the power supply potential fluctuation in Comparative Example 1 exceeds the allowable value.

[0080] On the one hand, in Example 1, as shown in FIG. 6(a), particularly at frequencies higher than 1 MHz, the transfer impedance characteristics are reduced to 1 / 10 or less compared to Comparative Example 1. In Example 1, in the conduction path from the electrode 12 of the capacitor 151 to the electrode 14 of the capacitor 152, a low-impedance ground pattern 350G is interposed. As a result, in Example 1, the propagation of the power supply potential fluctuation generated in the capacitor 151 to the capacitor 152 is suppressed.

[0081] Also, referring to the power supply potential fluctuation shown in FIG. 6(b), in Example 1, the power supply potential fluctuation is reduced compared to Comparative Example 1. Specifically, the amplitude of the power supply potential fluctuation between the power supply pad and the ground pad of the circuit 2022 in Example 1 was 16 mV. Therefore, the power supply potential fluctuation between the power supply pad and the ground pad of the circuit 2022 in Example 1 is reduced to 1 / 10 or less of the power supply potential fluctuation between the power supply pad and the ground pad of the circuit 2022Y in Comparative Example 1.

[0082] The present invention is not limited to the embodiments described above, and many modifications are possible within the technical idea of the present invention. Also, the effects described in the embodiments are merely an enumeration of the most preferable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

[0083] In the above-described embodiment, the case where the power supply line 321E and the power supply line 322E are electrically connected via the ferrite bead 160 has been described, but the present invention is not limited thereto. For example, instead of the ferrite bead 160, a low-pass filter component such as an inductor may be arranged. Also, for example, when the voltage applied to the power supply line 321E is different from the voltage applied to the power supply line 322E, electrical components such as the ferrite bead 160 may be omitted so that the power supply line 321E and the power supply line 322E are not electrically connected.

[0084] In the above-described embodiment, the case where there is a ground via 353G has been described, but the case where there is no ground via 353G may also be applicable.

[0085] In the above-described embodiment, the case where the ground via 351G and the ground via 352G are not connected in the conductor layer 302 of the printed wiring board 300 has been described, but the present invention is not limited thereto. For example, in the conductor layer 302, the ground via 351G and the ground via 352G may be connected by a conductor having a diameter equal to or less than that of each ground via 351G, 352G. In this case, in the conductor layer 302, it is preferable that the ground via 351G and the ground via 352G are connected by a conductor having a diameter less than that of the via land of each ground via 351 G, 352 G's 352G. Further, for example, in the conductor layer 302, the ground via 351G and the ground via 352G may be electrically connected by an electrical component such as a resistive component or a ferrite bead. In this case, it is preferable that the electrical component has a high impedance value in a frequency band where the power supply noise becomes a high voltage level.

[0086] In the above-described embodiment, the case where the semiconductor element 202 and the package substrate 201 are connected by the solder bumps 203 has been described, but the present invention is not limited thereto, and other connection methods, for example, wire bonding, may be used.

[0087] In the above-described embodiment, the case where one capacitor 151 is mounted on the printed wiring board 300 for the circuit 2021 and one capacitor 152 is mounted on the printed wiring board 300 for the circuit 2022 has been described, but the present invention is not limited thereto. A plurality of capacitors may be mounted on the printed wiring board 300 for the circuit 2021, and a plurality of capacitors may be mounted on the printed wiring board 300 for the circuit 2022.

[0088] Also, in the above-described embodiment, the case where the power supply device 140 is mounted on the printed wiring board 300 has been described, but the present invention is not limited thereto. It is sufficient that the power is configured to be supplied to the semiconductor device 200 via the printed wiring board 300. For example, the power supply device 140 may be mounted on another wiring board that is electrically connected to the printed wiring board 300. At that time, the ground terminal 1402 of the power supply device 140 may be electrically connected to the ground line 320G.

[0089] Also, in the above-described embodiment, the case where the electronic module of the present invention is applied to an imaging device such as a digital camera as an electronic device has been described, but the present invention is not limited thereto. The electronic module module of the present invention is applicable to, for example, mobile devices, in-vehicle devices, image forming devices, etc. as electronic devices. Image forming devices include, for example, printers, copiers, facsimiles, and multifunction devices having these functions.

Description of Reference Numerals

[0090] 11... electrode (first electrode), 12... electrode (second electrode), 13... electrode (third electrode), 14... electrode (fourth electrode), 100... processing module (electronic module), 151... capacitor (first capacitor), 152... capacitor (second capacitor), 200... semiconductor device (first semiconductor device), 204... terminal, 211E... power supply terminal (first power supply terminal), 212E... power supply terminal (second power supply terminal), 300... printed wiring board, 310... insulating substrate, 311... main surface (first main surface), 312... main surface (second main surface), 320G... ground line, 321E... power supply line (first power supply line), 322E... power supply line (second power supply line), 351G... ground via (first ground via), 352G... ground via (second ground via), 2021... circuit (first circuit), 2022... circuit (second circuit)

Claims

1. A printed wiring board having an insulating substrate; A first semiconductor device disposed on a first main surface of the insulating substrate; A first capacitor disposed on a second main surface of the insulating substrate opposite to the first main surface and at a position overlapping the first semiconductor device in a direction perpendicular to the first main surface; A second capacitor disposed on the second main surface and at a position overlapping the first semiconductor device in the direction, comprising: The first semiconductor device has a plurality of terminals including a first power supply terminal and a second power supply terminal, a first circuit electrically connected to the first power supply terminal, and a second circuit electrically connected to the second power supply terminal; The first capacitor has a first electrode and a second electrode; The second capacitor has a third electrode and a fourth electrode; The printed wiring board has a first power supply line electrically connecting the first power supply terminal of the first semiconductor device and the first electrode of the first capacitor, a second power supply line electrically connecting the second power supply terminal of the first semiconductor device and the third electrode of the second capacitor, and a ground line electrically connecting the second electrode of the first capacitor and the fourth electrode of the second capacitor; The first power supply line includes a first power supply via; The second power supply line includes a second power supply via; The ground line includes a first ground via, a second ground via, and a ground pattern disposed inside the insulating substrate; The first electrode of the first capacitor is electrically connected to the first power supply terminal via the first power supply via; The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via; The third electrode of the second capacitor is electrically connected to the second power supply terminal via the second power supply via; The fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via. The first power via and the second power via are surrounded by the ground pattern. An electronic module characterized by the above.

2. A printed wiring board having an insulating substrate, A first semiconductor device disposed on a first main surface of the insulating substrate, A first capacitor disposed on a second main surface of the insulating substrate opposite to the first main surface and at a position overlapping the first semiconductor device in a direction perpendicular to the first main surface, A second capacitor disposed on the second main surface and at a position overlapping the first semiconductor device in the direction, and comprising: The first semiconductor device has a plurality of terminals including a first power terminal and a second power terminal, a first circuit electrically connected to the first power terminal, and a second circuit electrically connected to the second power terminal. The first capacitor has a first electrode and a second electrode. The second capacitor has a third electrode and a fourth electrode. The printed wiring board has a first power line that electrically connects the first power terminal of the first semiconductor device and the first electrode of the first capacitor, a second power line that electrically connects the second power terminal of the first semiconductor device and the third electrode of the second capacitor, and a ground line that electrically connects the second electrode of the first capacitor and the fourth electrode of the second capacitor. The ground line includes a first ground via, a second ground via, and a ground pattern disposed inside the insulating substrate. The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via. The fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via. The center-to-center distance between the first ground via and the second ground via is equal to or less than twice the center-to-center distance between two adjacent terminals among the plurality of terminals. An electronic module, characterized in that.

3. A printed wiring board having an insulating substrate, A first semiconductor device disposed on a first main surface of the insulating substrate, A first capacitor disposed on a second main surface of the insulating substrate opposite to the first main surface and at a position overlapping the first semiconductor device in a direction perpendicular to the first main surface, A second capacitor disposed on the second main surface and at a position overlapping the first semiconductor device in the direction, and comprising: The first semiconductor device has a plurality of terminals including a first power supply terminal and a second power supply terminal, a first circuit electrically connected to the first power supply terminal, and a second circuit electrically connected to the second power supply terminal. The first capacitor has a first electrode and a second electrode. The second capacitor has a third electrode and a fourth electrode. The printed wiring board has a first power supply line that electrically connects the first power supply terminal of the first semiconductor device and the first electrode of the first capacitor, a second power supply line that electrically connects the second power supply terminal of the first semiconductor device and the third electrode of the second capacitor, and a ground line that electrically connects the second electrode of the first capacitor and the fourth electrode of the second capacitor. The ground line includes a first ground via, a second ground via, and a ground pattern disposed inside the insulating substrate. The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via. The fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via. The electronic module further includes a second semiconductor device having a ground terminal electrically connected to the ground line. The ground line has a third ground via, and the ground terminal is electrically connected to the ground pattern via the third ground via, and a center-to-center distance between the first ground via and the second ground via is shorter than each of a center-to-center distance between the first ground via and the third ground via and a center-to-center distance between the second ground via and the third ground via. An electronic module characterized by the above.

4. A printed wiring board having an insulating substrate, a first semiconductor device disposed on a first main surface of the insulating substrate, a first capacitor disposed on a second main surface of the insulating substrate opposite to the first main surface and at a position overlapping the first semiconductor device in a direction perpendicular to the first main surface, and a second capacitor disposed on the second main surface and at a position overlapping the first semiconductor device in the direction, The first semiconductor device has a plurality of terminals including a first power terminal and a second power terminal, a first circuit electrically connected to the first power terminal, and a second circuit electrically connected to the second power terminal, The first capacitor has a first electrode and a second electrode, The second capacitor has a third electrode and a fourth electrode, The printed wiring board has a first power line electrically connecting the first power terminal of the first semiconductor device and the first electrode of the first capacitor, a second power line electrically connecting the second power terminal of the first semiconductor device and the third electrode of the second capacitor, and a ground line electrically connecting the second electrode of the first capacitor and the fourth electrode of the second capacitor, The ground line includes a first ground via, a second ground via, and a ground pattern disposed inside the insulating substrate, The second electrode of the first capacitor is electrically connected to the ground pattern via the first ground via. The fourth electrode of the second capacitor is electrically connected to the ground pattern via the second ground via. The electronic module further includes an electrical component that electrically connects the first power line and the second power line. The electrical component is a low-pass filter component. An electronic module characterized by the above.

5. The center-to-center distance between the first ground via and the second ground via is equal to or less than twice the center-to-center distance between two adjacent terminals among the plurality of terminals. The electronic module according to claim 1, 3, or 4, characterized by the above.

6. The electronic module further includes a second semiconductor device having a ground terminal electrically connected to the ground line. The ground line has a third ground via. The ground terminal is electrically connected to the ground pattern via the third ground via. The center-to-center distance between the first ground via and the second ground via is shorter than the center-to-center distance between the first ground via and the third ground via, and the center-to-center distance between the second ground via and the third ground via, respectively. The electronic module according to claim 1, 2, or 4, characterized by the above.

7. The second semiconductor device is a power supply device that supplies power to the first semiconductor device. The electronic module according to claim 3 or 6, characterized by the above.

8. The electronic module further includes an electrical component that electrically connects the first power line and the second power line. The electronic module according to claim 1, 2, or 3, characterized by the above.

9. The electrical component is a low-pass filter component. The electronic module according to claim 8, characterized in that.

10. The low-pass filter component is a ferrite bead. The electronic module according to claim 9, characterized in that.

11. The center-to-center distance between the first ground via and the second ground via is 1 times or less the center-to-center distance between two adjacent terminals among the plurality of terminals. The electronic module according to any one of claims 1 to 10, characterized in that.

12. The plurality of terminals include a first ground terminal electrically connected to the first circuit and a second ground terminal electrically connected to the second circuit. The first ground terminal and the second ground terminal are electrically connected to the ground line. The electronic module according to any one of claims 1 to 11, characterized in that.

13. The ground pattern is included in the shortest conduction path among the conduction paths between the second electrode of the first capacitor and the fourth electrode of the second capacitor. The electronic module according to any one of claims 1 to 12, characterized in that.

14. A housing, An electronic device comprising the electronic module according to any one of claims 1 to 13 disposed inside the housing.

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