Circuit board

Abstract

A printed circuit board according to an embodiment includes an insulating layer including a via hole, and a via disposed in the via hole of the insulating layer, the via including a connecting portion disposed in the via hole of the insulating layer, a first pad disposed on an upper surface of the insulating layer and an upper surface of the connecting portion, and a second pad disposed on a lower surface of the insulating layer and below a lower surface of the connecting portion, wherein the upper surface of the connecting portion has a concave shape in a downward direction, the lower surface of the connecting portion has a concave shape in an upward direction, the lower surface of the first pad has a convex shape corresponding to the upper surface of the connecting portion, and the upper surface of the second pad has a convex shape corresponding to the lower surface of the connecting portion.

Description

Technical Field

[0001] The embodiments relate to Back subgrade Plate thereof.

Background Art

[0002] As miniaturization, weight reduction, and integration of electronic components are accelerating, the circuit line width is being miniaturized. In particular, as the design rule of semiconductor chips is integrated on the nanometer scale, the circuit line width of the package substrate or printed circuit board on which the semiconductor chips are mounted is being miniaturized to several micrometers or less.

[0003] In order to increase the circuit integration density of printed circuit boards, that is, to miniaturize the circuit line width, various methods have been proposed. For the purpose of preventing the loss of circuit line width in the etching step for forming a pattern after copper plating, methods such as semi-additive process (SAP) and modified semi-additive process (MSAP) have been proposed.

[0004] After that, in order to realize a finer circuit pattern, an Embedded Trace Substrate (hereinafter referred to as "ETS") method of embedding and filling a copper foil in an insulating layer has been used in the industry. Since the ETS method manufactures in an embedded form in the insulating layer instead of forming a copper foil circuit on the surface of the insulating layer, there is no circuit loss due to etching, which is advantageous for miniaturizing the circuit pitch.

[0005] On the other hand, in order to meet the recent demand for wireless data traffic, efforts have been made to develop an improved 5G (5th generation) communication system or a pre-5G communication system. Here, the 5G communication system uses an ultra-high frequency (mmWave) band (sub6 giga (6 GHz), 28 giga 28 GHz, 38 giga 38 GHz, or a frequency higher than that) to achieve a high data transmission rate.

[0006] In order to mitigate the path loss of radio waves and increase the transmission distance of radio waves in the millimeter-wave band, 5G communication systems have developed aggregation technologies such as beamforming, massive MIMO, and array antennas. Considering that such a frequency band consists of hundreds of active antennas with wavelengths, the antenna system becomes relatively large.

[0007] Since such antennas and AP modules are patterned or mounted on a printed circuit board, low loss of the printed circuit board is very important. This means that a plurality of substrates constituting the active antenna system, namely, an antenna substrate, an antenna power supply substrate, a transceiver substrate, and a baseband substrate, must be integrated into one compact unit.

[0008] On the other hand, recently, printed circuit boards including large-area vias have been developed to improve heat dissipation characteristics and shielding characteristics. The large-area vias can be formed by filling a metal substance into a large-diameter via hole. However, it is not easy to fill the inside of the large-diameter via hole with a metal substance, and thus conventional large-area vias include a dimple region recessed in the direction of the inside of the via hole on one surface. And the dimple region may affect via hole processing when additional lamination is performed, which affects the reliability of the printed circuit board. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] In an embodiment, a printed circuit board including vias with a new structure and a method of manufacturing the same are provided.

[0010] Also, in an embodiment, a printed circuit board including vias composed of a plurality of via parts arranged in a multi-layer structure in a via hole and a method of manufacturing the same are provided.

[0011] In the proposed embodiment, the technical problem to be solved is not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those having ordinary knowledge in the technical field to which the embodiment belongs from the following description.

Means for Solving the Problem

[0012] The printed circuit board according to the embodiment includes an insulating layer including via holes, and vias disposed in the via holes of the insulating layer. The vias include a connecting portion disposed in the via holes of the insulating layer, a first pad disposed on the upper surface of the insulating layer and on the upper surface of the connecting portion, and a second pad disposed under the lower surface of the insulating layer and under the lower surface of the connecting portion. The upper surface of the connecting portion includes a shape recessed in the downward direction, the lower surface of the connecting portion includes a shape recessed in the upward direction, the lower surface of the first pad includes a convex shape corresponding to the upper surface of the connecting portion, and the upper surface of the second pad includes a convex shape corresponding to the lower surface of the connecting portion.

[0013] The printed circuit board also includes a seed layer disposed between the inner wall of the via hole and the connecting portion, between the insulating layer and the first pad, and between the insulating layer and the second pad.

[0014] Also, a first portion of the upper surface of the connecting portion is located lower than the upper surface of the insulating layer, and a first portion of the lower surface of the connecting portion is located higher than the lower surface of the insulating layer.

[0015] Also, a second portion of the upper surface of the connecting portion is located higher than the upper surface of the insulating layer, and a second portion of the lower surface of the connecting portion is located lower than the lower surface of the insulating layer.

[0016] Also, a second portion of the upper surface of the connecting portion is located higher than the lower surface of the first pad, and a second portion of the lower surface of the connecting portion is located lower than the upper surface of the second pad.

[0017] Further, the distance from the upper surface of the insulating layer to the first part of the upper surface of the connecting part has a range of 5% to 40% of the thickness of the insulating layer, and the distance from the lower surface of the insulating layer to the first part of the lower surface of the connecting part has a range of 5% to 40% of the thickness of the insulating layer.

[0018] Further, the connecting part includes an X shape.

[0019] Further, the second part of the upper surface of the connecting part is located between the upper surface of the seed layer disposed on the upper surface of the insulating layer and the lower surface of the first pad, and the second part of the lower surface of the connecting part is located between the lower surface of the seed layer disposed on the lower surface of the insulating layer and the upper surface of the second pad.

[0020] Further, each of the first pad and the second pad includes a first region disposed on the upper surface or the lower surface of the insulating layer, and a second region disposed in the via hole and including a convex portion corresponding to the upper surface or the lower surface of the connecting part.

[0021] On the one hand, the printed circuit board according to the embodiment includes a first insulating layer including a first via hole, a second insulating layer including a second via hole and disposed on the first insulating layer, a first via disposed in the first via hole of the first insulating layer, and a second via disposed in the second via hole of the second insulating layer. The lower surface of the second via contacts the upper surface of the first via, and the upper surface of the second via includes a first connecting part recessed in the downward direction, and a first pad disposed on the second insulating layer and having a convex lower surface corresponding to the upper surface of the first connecting part.

[0022] Further, it includes a third insulating layer disposed under the first insulating layer and including a third via hole, and a third via disposed in the third via hole of the third insulating layer. The upper surface of the third via contacts the lower surface of the first via, and the lower surface of the third via includes a second connecting part recessed in the upward direction, and a second pad disposed under the third insulating layer and having a convex upper surface corresponding to the lower surface of the first connecting part.

[0023] Further, the first portion of the upper surface of the first connecting portion is located lower than the upper surface of the second insulating layer, and the second portion of the upper surface of the first connecting portion is located higher than the upper surface of the second insulating layer and the lower surface of the first pad.

[0024] Further, the first portion of the lower surface of the second connecting portion is located higher than the lower surface of the third insulating layer, and the second portion of the lower surface of the second connecting portion is located lower than the lower surface of the third insulating layer and the upper surface of the second pad.

[0025] On the other hand, the manufacturing method of the printed circuit board according to the embodiment includes preparing an insulating layer, forming via holes in the insulating layer, forming a seed layer on the surface of the insulating layer and the inner wall of the via holes, disposing a first mask having a first opening region exposing the via holes on the seed layer, performing plating based on the seed layer to form a connecting portion of a via filling a part of the via holes, removing the first mask, disposing a second mask having a second opening region exposing the connecting portion on the seed layer, performing plating based on the seed layer to form a pad protruding on the surface of the insulating layer while filling the remaining part of the via holes, and removing the second mask. The width of the first opening region is smaller than the upper width of the via hole, the upper surface of the connecting portion includes a shape recessed in the downward direction, and the lower surface of the pad includes a convex shape corresponding to the upper surface of the connecting portion.

[0026] Further, the width of the first opening region of the first mask has a level of 80% to 95% of the upper width of the via hole.

[0027] Further, the first portion of the upper surface of the connecting portion is located lower than the upper surface of the insulating layer, and the second portion of the upper surface of the connecting portion is located higher than the upper surface of the insulating layer.

[0028] Further, the second portion of the upper surface of the connecting portion is located higher than the lower surface of the pad.

Advantages of the Invention

[0029] According to this embodiment, in the case of conventional large-area vias, there are restrictions on the plating of large-diameter via holes. However, through the modification of the plating method for this, the restrictions on the plating of large-diameter via holes in large-area vias can be broken, and the plating of large-diameter via holes can be stably realized thereby. Also, according to this embodiment, the uniformity of via plating can be ensured compared with the existing method, and the quality reliability can be ensured by improving the laser quality after additional lamination.

[0030] Also, conventionally, there was a process-limiting ratio for stably realizing the plating inside the via hole between the thickness of the insulating layer and the size of the bar hole. However, according to this embodiment, the design constraints for realizing a highly reliable plating state inside the via hole can be broken, and the degree of freedom in design can be improved thereby. Also, according to the embodiment, by increasing the size of the via, the interference between circuits generated in the area where the circuits are concentrated using this can be completely shielded, and the heat dissipation characteristics in the area where the role of heat dissipation is required can be improved.

Brief Description of the Drawings

[0031]

Figure 1a

Figure 1b

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Figure 14

Mode for Carrying Out the Invention

[0032] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the attached drawings. However, the same or similar components will be given the same reference numerals regardless of the reference signs, and duplicate explanations thereof will be omitted. The suffixes "module" and "section" for the components used in the following description are given or mixed only for the ease of preparing the specification, and do not have meanings or roles that are distinguished from each other by themselves. Further, when it is determined that a specific description of a related known technique may obscure the gist of the embodiments disclosed in this specification in the description of the embodiments disclosed in this specification, the detailed description thereof will be omitted. Also, the attached drawings are only for facilitating the understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings, and should be understood to include all modifications, equivalents or alternatives included in the idea and technical scope of the present invention.

[0033] Terms including ordinal numbers such as second and first can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

[0034] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it may be directly coupled or connected to the other component, or there may be intervening components. On the contrary, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no intervening components.

[0035] Singular expressions include plural expressions unless the context clearly dictates otherwise.

[0036] In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and are not to be construed as precluding the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings as follows.

[0038] FIGS. 1a and 1b are diagrams showing a printed circuit board according to a comparative example.

[0039] Referring to FIG. 1a, a printed circuit board 10 according to a comparative example includes an insulating layer 11.

[0040] And the printed circuit board 10 includes a circuit pattern 12 and vias 13.

[0041] The circuit pattern 12 is disposed on at least one of the upper and lower surfaces of the insulating layer 11. And the vias 13 penetrate the insulating layer 11 and connect circuit patterns disposed in different layers from each other.

[0042] At this time, the via 13 includes a first pad 14 disposed on the upper surface of the insulating layer 11, a second pad 16 disposed on the lower surface of the insulating layer 11, and a connecting portion 15 disposed within the insulating layer 11 and connecting the first pad 14 and the second pad 16.

[0043] The first pad 14 and the second pad 16 can also be said to be circuit patterns 12 disposed on the upper and lower surfaces of the insulating layer 11.

[0044] The connecting portion 15 is formed by filling the inside of a via hole (not shown) formed in the insulating layer 11 with a metal material. Preferably, the connecting portion 15 is formed by plating a metal material inside the via hole.

[0045] The upper or lower surface of the connecting portion 15 has a first width w1. For example, the first width w1 is 80 μm or less. That is, the connecting portion 15 is formed by filling a via hole having a diameter of 80 μm or less in the upper or lower region with a metal material. In this case, the upper and lower surfaces of the connecting portion 15, the upper surface of the first pad 14, and the lower surface of the second pad 16 are substantially flat. That is, the upper and lower surfaces of the connecting portion 15, the upper surface of the first pad 14, and the lower surface of the second pad 16 are placed on the same plane as the upper or lower surface of the insulating layer 11.

[0046] On the other hand, recently, in order to improve the performance of vias that play roles in heat dissipation, shielding, and signal transmission, the size of the via holes has been greatly increased, and accordingly, the size of the via holes and vias also tends to increase.

[0047] Referring to FIG. 1b, a printed circuit board 20 according to a comparative example includes an insulating layer 21.

[0048] And the printed circuit board 20 includes a circuit pattern 22 and a via 23.

[0049] The circuit pattern 22 is disposed on at least one of the upper and lower surfaces of the insulating layer 21. And the via 23 penetrates the insulating layer 21 and connects circuit patterns disposed in different layers from each other.

[0050] At this time, the via 23 includes a first pad 24 disposed on the upper surface of the insulating layer 21, a second pad 26 disposed on the lower surface of the insulating layer 21, and a connecting portion 25 disposed in the insulating layer 21 and connecting the first pad 24 and the second pad 26.

[0051] The first pad 24 and the second pad 26 can also be said to be circuit patterns 22 disposed on the upper and lower surfaces of the insulating layer 21.

[0052] The connecting portion 25 is formed by filling the inside of a via hole (not shown) formed in the insulating layer 21 with a metallic material. Preferably, the connecting portion 25 is formed by plating a metallic material inside the via hole.

[0053] The upper or lower surface of the connecting portion 25 has a second width w2. For example, the second width w2 can be 100 μm or more, which is larger than the first width w1. That is, the connecting portion 25 is formed by filling a via hole having a size with a diameter of 100 μm or more in the upper or lower region with a metallic material. In this case, the upper and lower surfaces of the connecting portion 25, the upper surface of the first pad 24, and the lower surface of the second pad 26 are substantially curved surfaces. That is, the upper and lower surfaces of the connecting portion 25, the upper surface of the first pad 24, and the lower surface of the second pad 26 can include a concave shape recessed in the upper or lower direction. That is, the via 23 in the comparative example can include a dimple region.

[0054] That is, when the size of the via hole is processed to have a diameter of 100 μm or more, the via fill plating is not performed smoothly, and the concave dimple region DP as described above is generated.

[0055] FIG. 2 is a diagram showing various examples of the shape or size of vias.

[0056] Referring to FIG. 2, as shown in (a), the connecting portion 15 can include a circular cross-sectional shape having a first width w1 with a diameter of 80 μm or less.

[0057] As shown in (b) of FIG. 2, the connecting portion 25 can include a circular cross-sectional shape having a second width w2 with a diameter of 100 μm or more.

[0058] Also, as shown in (c) of FIG. 2, the connecting portion 25A can include an elliptical cross-sectional shape or a bar shape having a first width w1 in the first direction and a third width w3 with a diameter of 100 μm or more in the second direction.

[0059] FIG. 3 is a diagram for explaining the dimple region shown in the comparative example.

[0060] Referring to FIG. 3, in the case of vias with a relatively small size as shown in (a) of FIG. 2, plating is performed smoothly throughout the entire area of the via hole.

[0061] However, when the diameter of the via hole exceeds 100 μm as shown in (b) or (c) of FIG. 2, via filling plating is not performed smoothly, and there is a dimple region DR1 recessed in the downward direction at the upper part of the via as shown in (a) of FIG. 3, or there are dimple regions DR2 and DR3 recessed in the downward and upward directions respectively at the upper and lower parts of the via as shown in (b) of FIG. 3.

[0062] And when the depth of the dimple regions DR1, DR2, and DR3 is 10 μm or more, it is determined as defective and cannot be used, or there is a problem that the processing of the via hole in this region is not performed smoothly during the additional lamination process after the core layer shape of the printed circuit board.

[0063] On the one hand, in recent years, in order to improve the performance of vias that play roles in heat dissipation, shielding, and signal transmission, the size of via holes has been significantly increased, and accordingly, the size of via holes and vias also tends to increase. In the embodiments, even for large-area vias of 10 μm or more as described above, a printed circuit board with a new structure and a manufacturing method thereof are provided, in which uniform plating is performed over the entire area of the via hole, thereby removing the dimple region of the via.

[0064] FIG. 4 is a diagram showing a printed circuit board according to the first embodiment, and FIG. 5 is an enlarged view of the via of the printed circuit board of FIG. 4.

[0065] Referring to FIGS. 4 and 5, the printed circuit board 100 includes an insulating layer 110, a seed layer 120, a circuit pattern 130, and a via 140.

[0066] The insulating layer 110 is a substrate in which an electric circuit capable of changing wiring is formed, and can include all printed materials, wiring boards, and insulating substrates made of an insulating material capable of forming a circuit pattern on the surface.

[0067] When the printed circuit board 100 has a plurality of laminated structures, the insulating layer 110 can mean the insulating layer disposed in the center among the plurality of insulating layers having the plurality of laminated structures, but is not limited thereto. Preferably, the insulating layer 110 can mean the insulating layer in which PTH (Plated Through Hole) vias are formed among the plurality of insulating layers.

[0068] For example, the insulating layer 110 can be rigid or flexible. For example, the insulating layer 110 can include glass or plastic. Specifically, the insulating layer 110 can include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or can include reinforced or ductile plastics such as Polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or can include sapphire.

[0069] In addition, the insulating layer 110 can include an optically isotropic film. As an example, the insulating layer 110 can include Cyclic Olefin Copolymer (COC), Cyclic Olefin Polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA), etc.

[0070] In addition, the insulating layer 110 can be partially curved and bent. That is, the insulating layer 110 can have a flat surface in part and can be curved while having a curved surface in part. Specifically, the insulating layer 110 can be curved with an end having a curved surface or can be curved while having a surface with a random curvature.

[0071] In addition, the insulating layer 110 can be a flexible substrate having flexible characteristics. Also, the insulating layer 110 can be a curved or bended substrate. At this time, based on the circuit design, the insulating layer 110 can represent the electrical wiring connecting circuit components in a wiring pattern and reproduce the electrical conductor on the insulator. Also, the insulating layer 110 can mount electrical components and form wiring for connecting them circuitously, and can mechanically fix components other than the electrical connection function of the components.

[0072] The circuit pattern 130 can be disposed on the surface of the insulating layer 110. For example, a plurality of circuit patterns 130 can be arranged on the upper surface of the insulating layer 110 at regular intervals from each other. For example, a plurality of circuit patterns 130 can be arranged on the lower surface of the insulating layer 110 at regular intervals from each other.

[0073] The insulating layer 110 can have a thickness of 20 μm to 500 μm. Preferably, the insulating layer 110 can have a thickness of 40 μm to 400 μm. More preferably, the insulating layer 110 can have a thickness of 60 μm to 250 μm. When the thickness of the insulating layer 110 is less than 20 μm, it may be difficult to form the circuit pattern 130 on the surface of the insulating layer 110. When the thickness of the insulating layer 110 exceeds 500 μm, the overall thickness of the printed circuit board 100 may increase.

[0074] On the other hand, the circuit pattern 130 as described above is a wiring for transmitting an electrical signal and can be formed of a metal material having high electrical conductivity. For this purpose, the circuit pattern 130 can be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Further, the circuit pattern 130 can be formed of a paste or a solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding force. Preferably, the circuit pattern 130 can be formed of copper (Cu) having high electrical conductivity and relatively low cost.

[0075] The circuit pattern 130 can be formed by an additive process, a subtractive process, an MSAP (Modified Semi Additive Process), an SAP (Semi Additive Process), etc., which are the manufacturing processes of a normal printed circuit board. Here, detailed descriptions are omitted.

[0076] On one hand, the seed layer 120 can be disposed between the insulating layer 110 and the circuit pattern 130. The seed layer 120 can be selectively omitted. That is, when the circuit pattern 130 is formed by electrolytic plating, the seed layer 120 can be disposed between the insulating layer 110 and the circuit pattern 130. Also, when the circuit pattern 130 is formed by electroless plating, the seed layer 120 can be omitted.

[0077] Thus, it can be said that a circuit pattern layer is formed including the circuit pattern 130 and the seed layer 120. The circuit pattern layer can have a range of 10 μm to 25 μm. Preferably, when the circuit pattern layer includes the circuit pattern 130 and the seed layer 120, the total thickness of the circuit pattern 130 and the seed layer 120 can have a range of 10 μm to 25 μm. And when the circuit pattern layer includes only the circuit pattern 130, the thickness of the circuit pattern 130 can have a range of 10 μm to 25 μm.

[0078] The via 140 can be disposed within the insulating layer 110. The via 140 can be disposed to penetrate the insulating layer 110. Preferably, the via 140 can connect the circuit patterns 130 disposed on the upper surface and the lower surface of the insulating layer 110 to each other. At this time, the circuit patterns connected by the via 140 can be any of a signal pattern for an electrical signal transmission function, a shielding pattern for a signal shielding function, and a heat dissipation pattern for a heat dissipation function, but are not limited thereto.

[0079] The via 140 can be disposed to penetrate the upper surface and the lower surface of the insulating layer 110. The via 140 can electrically connect the circuit pattern 130 disposed on the upper surface of the insulating layer 110 and the circuit pattern disposed on the lower surface of the insulating layer 110.

[0080] The via 140 can include a connecting portion 141, a first pad 142, and a second pad 143.

[0081] The first pad 142 and the second pad 143 may be disposed on the upper and lower surfaces of the insulating layer 110, respectively. Preferably, the first pad 142 and the second pad 143 may be one of the circuit pattern layers. That is, the first pad 142 and the second pad 143 may mean a circuit pattern connected to the connection portion 141 of the via 140 among the circuit patterns 130 disposed on the upper and lower surfaces of the insulating layer 110.

[0082] A connection portion 141 having one end connected to the first pad 142 and the other end connected to the second pad 143 may be disposed in the insulating layer 110.

[0083] The connection portion 141 may be disposed in a via hole formed in the insulating layer 110. Preferably, the connection portion 141 may be formed by filling a part of the via hole formed in the insulating layer 110.

[0084] That is, the connection portion 141 may be formed by filling only a part, rather than the whole, of the via hole formed in the insulating layer 110.

[0085] Thereby, the connection portion 141 can have a curved surface whose surface is not flat. Preferably, the upper surface of the connection portion 141 can include a shape recessed in the downward direction. Also, the lower surface of the connection portion 141 can include a shape recessed in the upward direction. Thereby, the length of the upper surface of the connection portion 141 may be greater than the upper width of the via hole formed in the insulating layer 110. That is, the upper surface of the connection portion 141 can have a curved surface, and thereby the length of the upper surface of the connection portion 141 may be greater than the upper width of the via hole.

[0086] A part of the upper surface of the connecting portion 141 may be located lower than the upper surface of the insulating layer 110. For example, the central region of the upper surface of the connecting portion 141 may be located lower than the upper surface of the insulating layer 110. That is, a concave portion may be formed on the upper surface of the connecting portion 141. Thereby, the length of the lower surface of the connecting portion 141 may be larger than the lower width of the via hole formed in the insulating layer 110. That is, the lower surface of the connecting portion 141 may have a curved surface, and thereby the length of the lower surface of the connecting portion 141 may be larger than the lower width of the via hole.

[0087] Also, a part of the lower surface of the connecting portion 141 may be located higher than the lower surface of the insulating layer 110. For example, the central region of the lower surface of the connecting portion 141 may be located higher than the lower surface of the insulating layer 110. That is, a concave portion may be formed on the lower surface of the connecting portion 141.

[0088] Thereby, concave portions may be formed on the upper surface and the lower surface of the connecting portion 141 respectively, and the connecting portion 141 may include an "X" shape as a whole.

[0089] Specifically, the via hole may include a first region located at the center of the insulating layer 110, a second region located above the insulating layer 110 on the first region, and a third region located below the insulating layer 110 under the first region. And the entire region of the first region of the via hole may be filled by the connecting portion 141. In contrast, only a part of the regions of the second region and the third region of the via hole may be filled by the connecting portion 141.

[0090] On the other hand, the concave portion formed on the upper surface of the connecting portion 141 may be formed to have a first depth D1 from the upper surface of the insulating layer 110. Also, the concave portion formed on the lower surface of the connecting portion 141 may be formed to have a second depth D2 from the lower surface of the insulating layer 110.

[0091] At this time, the first depth D1 may be the same as the second depth D2. For example, the first depth D1 may be 0.95 times to 1.05 times the second depth D2.

[0092] The first depth D1 can have a level of 5% to 40% of the thickness of the insulating layer 110. For example, the first depth D1 can have a level of 10% to 20% of the thickness of the insulating layer 110. When the first depth D1 is less than 5% of the thickness of the insulating layer 110, the thickness of the protruding region of the connecting portion 141 described below may increase, and thereby the thickness of the first pad 142 may increase. Also, when the first depth D1 is greater than 40% of the thickness of the insulating layer 110, a dimple region may occur in the process of forming the first pad 142 in the future.

[0093] The second depth D2 can have a thickness at a level of 5% to 40% of the thickness of the insulating layer 110. For example, the second depth D2 can have a thickness at a level of 10% to 20% of the thickness of the insulating layer 110. When the second depth D2 is less than 5% of the thickness of the insulating layer 110, the thickness of the protruding region of the connecting portion 141 described below may increase, and thereby the thickness of the second pad 143 may increase. Also, when the second depth D2 is greater than 40% of the thickness of the insulating layer 110, a dimple region may occur in the process of forming the second pad 143 later.

[0094] On the other hand, the first pad 142 may be disposed on the upper surface of the insulating layer 110.

[0095] Preferably, the seed layer 120 may be further disposed between the first pad 142 and the upper surface of the insulating layer 110. The seed layer 120 may be disposed between the first pad 142 and the upper surface of the insulating layer 110. Also, the seed layer 120 may be disposed on the inner wall of the via hole. Preferably, the seed layer 120 may be disposed between the inner wall of the via hole and the side surface of the connecting portion 141.

[0096] The lower surface of the first pad 142 can contact the upper surface of the connecting portion 141. Thereby, the lower surface of the first pad 142 can include a shape corresponding to the upper surface of the connecting portion 141. Specifically, the lower surface of the first pad 142 can be a curved surface having a curvature corresponding to the upper surface of the connecting portion 141. For example, the first pad 142 can have a convex portion corresponding to a concave portion formed on the upper surface of the connecting portion 141.

[0097] Thereby, at least a part of the lower surface of the first pad 142 can be positioned lower than the upper surface of the seed layer 120. For example, a part of the lower surface of the first pad 142 can be positioned lower than the upper surface of the insulating layer 110. For example, a part of the lower surface of the first pad 142 can be positioned lower than the upper surface of the connecting portion 141. For example, a part of the lower surface of the first pad 142 can be positioned lower than an end portion of the upper surface of the connecting portion 141. Specifically, the central portion of the lower surface of the first pad 142 can be positioned lower than the end portion of the upper surface of the connecting portion 141.

[0098] Thereby, a part of the upper surface of the connecting portion 141 can be positioned higher than a part of the lower surface of the first pad 142. Also, another part of the upper surface of the connecting portion 141 can be positioned lower than another part of the lower surface of the first pad 142.

[0099] On the other hand, the second pad 143 can be disposed on the lower surface of the insulating layer 110.

[0100] Preferably, the seed layer 120 can be further disposed between the second pad 143 and the lower surface of the insulating layer 110. The seed layer 120 can be disposed between the second pad 143 and the lower surface of the insulating layer 110.

[0101] The upper surface of the second pad 143 can contact the lower surface of the connecting portion 141. Thereby, the upper surface of the second pad 143 can include a shape corresponding to the lower surface of the connecting portion 141. Specifically, the upper surface of the second pad 143 can be a curved surface having a curvature corresponding to the lower surface of the connecting portion 141. For example, the second pad 143 can have a convex portion corresponding to a concave portion formed on the lower surface of the connecting portion 141.

[0102] Thereby, at least a part of the upper surface of the second pad 143 can be positioned higher than the lower surface of the seed layer 120. For example, a part of the upper surface of the second pad 142 can be positioned higher than the lower surface of the insulating layer 110. For example, a part of the upper surface of the second pad 143 can be positioned higher than the lower surface of the connecting portion 141. For example, a part of the lower surface of the second pad 143 can be positioned higher than the end of the lower surface of the connecting portion 141. Specifically, the central portion of the upper surface of the second pad 143 can be positioned higher than the end of the lower surface of the connecting portion 142.

[0103] Thereby, a part of the lower surface of the connecting portion 141 can be positioned lower than a part of the upper surface of the second pad 143. Also, another part of the lower surface of the connecting portion 141 can be positioned higher than another part of the upper surface of the second pad 143.

[0104] As described above in the embodiment, in the process of forming the via 140, without filling the via hole formed in the insulating layer 110 at once, after forming the connecting portion 141 that fills a part of the via hole as described above, while filling the remaining part of the via hole, the first pad 142 and the second pad 143 protruding from the upper surface and the lower surface of the insulating layer 110 are formed.

[0105] According to such an embodiment of the present invention, in the case of conventional large-area vias, there are restrictions on the plating of large-diameter via holes. However, through the change of the plating method for this, the restrictions on the plating of large-diameter via holes in large-area vias can be broken, and the plating of large-diameter via holes can be stably realized thereby. Further, according to this embodiment, the uniformity of via plating can be ensured as compared with the existing method, and the quality reliability due to the improvement of laser quality after additional lamination can be ensured.

[0106] Also, conventionally, there was a process limit ratio for stably realizing the plating inside the via hole between the thickness of the insulating layer and the size of the bar hole. However, according to this embodiment, the design constraints for realizing a highly reliable plating state inside the via hole can be broken, and the degree of freedom of design can be improved thereby. Further, according to the embodiment, by increasing the size of the via, the interference between circuits generated in the region where the circuits are concentrated using this can be completely shielded, and the heat dissipation characteristics in the region where the role of heat dissipation is required can be improved.

[0107] On the other hand, as shown in FIG. 5, a part of the upper surface of the connecting portion 141 can be positioned higher than the upper surface of the insulating layer 110. For example, a part of the upper surface of the connecting portion 141 can be positioned higher than the upper surface of the seed layer 120.

[0108] That is, the connecting portion 141 can include a first region 141a disposed in the via hole formed in the insulating layer 110, a second region 141b positioned on the first region 141a and disposed between the second region 141b and the seed layer 120, and a third region 141c positioned on the second region 141b and having an upper surface positioned higher than the upper surfaces of the seed layer 120 and the insulating layer 110. At this time, the third region 141c can also be said to be a protruding region protruding outside the via hole among all regions of the connecting portion 141.

[0109] Further, although not specifically illustrated in FIG. 5, a part of the lower surface of the connecting portion 141 can be positioned lower than the lower surface of the insulating layer 110. For example, a part of the lower surface of the connecting portion 141 can be positioned lower than the lower surface of the seed layer 120. That is, the lower surface of the connecting portion 141 can also include a protruding region that protrudes below the lower surfaces of the insulating layer 110 and the seed layer 120.

[0110] Hereinafter, the manufacturing method of the printed circuit board shown in FIG. 4 will be specifically described.

[0111] FIGS. 6 to 13 are diagrams showing the manufacturing method of the printed circuit board shown in FIG. 4 in the order of processes.

[0112] First, referring to FIG. 6(a), the insulating layer 110 serving as the basis of the printed circuit board is prepared.

[0113] Also, as shown in FIG. 6(b), a metal layer 115 can be laminated on the surface of the insulating layer 110. The metal layer 115 can be formed by electroless plating a metal containing copper on the surface of the insulating layer 110. Also, different from forming the metal layer 115 by performing electroless plating on the insulating layer 110, a CCL (Copper Clad Laminate) can also be used.

[0114] Hereinafter, a method for manufacturing the printed circuit board 100 according to the embodiment having the insulating layer 110 on which the metal layer 115 is not formed will be described. However, the embodiment is not limited thereto, and when the following steps are performed in a state where the metal layer 115 as shown in FIG. 6(b) is formed, the metal layer 115 may be further disposed between the upper / lower surfaces of the insulating layer 110 and the seed layer 120 described later. However, the metal layer 115 is not disposed on the inner wall of the via hole, and only the seed layer 120 can be disposed.

[0115] Next, referring to FIG. 7, at least one via hole VH1 can be formed in the insulating layer 110. The via hole VH1 can be formed to penetrate the upper and lower surfaces of the insulating layer 110. At this time, the formation of the via hole VH1 can be performed in the upper and lower regions of the insulating layer 110, respectively. Thereby, one via hole VH1 can be formed by a combination of a first via groove (not shown) formed in the upper region of the insulating layer 110 and a second via groove (not shown) formed in the lower region of the insulating layer 110. Thereby, the via hole VH1 can include a shape in which the width gradually increases toward the upper and lower sides with the center as a reference. For example, the via hole VH1 can include an hourglass shape.

[0116] Next, as shown in FIG. 8, a step of forming the seed layer 120 on the insulating layer 110 can be performed.

[0117] The seed layer 120 can be formed on the upper surface of the insulating layer 110 and the inner wall of the via hole VH1.

[0118] The seed layer 120 can be formed on the upper surface of the insulating layer 110 and the inner wall of the via hole VH1 by a chemical copper plating method.

[0119] Next, as shown in FIG. 9, a step of forming a first mask M1 for forming the connecting portion 141 inside the via hole VH1 can be performed.

[0120] The first mask M1 can be disposed on the seed layer 120 disposed on the upper surface of the insulating layer 110. Also, the first mask M1 can be disposed under the seed layer 120 disposed on the lower surface of the insulating layer 110.

[0121] And the first mask M1 can be disposed while covering the surfaces of the seed layer 120 disposed on the upper and lower surfaces of the insulating layer 110, and can include a first opening region OR1 that exposes a portion where the connecting portion 141 is formed.

[0122] Preferably, the first mask M1 may include the first opening region OR1 that exposes the via hole VH1. At this time, the via hole VH1 and the first opening region OR1 may be at least partially aligned in the vertical direction.

[0123] At this time, the first opening region OR1 of the first mask M1 may expose only a partial region rather than the entire region of the via hole VH1. That is, the first mask M1 may be disposed to cover a part of the via hole VH1.

[0124] That is, the width of the first opening region OR1 may be smaller than the width of the via hole VH1.

[0125] Specifically, the first opening region OR1 of the first mask M1 disposed on the upper portion of the insulating layer 110 may be smaller than the upper width of the via hole VH1. As a result, a part of the upper region of the via hole VH1 may be exposed by the first opening region OR1, and the remaining part may be covered by the first mask M1.

[0126] In addition, the first opening region OR1 of the first mask M1 disposed on the lower portion of the insulating layer 110 may be smaller than the lower width of the via hole VH1. As a result, a part of the lower region of the via hole VH1 may be exposed by the first opening region OR1, and the remaining part may be covered by the first mask M1.

[0127] That is, the first mask M1 may include a first portion disposed on the seed layer 120 and a second portion extending from the first portion and not in contact with the seed layer 120 and the insulating layer 110. The second portion of the first mask M1 may be disposed to float on the via hole.

[0128] At this time, according to the width W2 of the second portion, the depth of the recess of the connecting portion 141 to be formed in the via hole VH1 hereafter is determined. When the width W2 of the second portion increases, the thickness of the protruding region of the connecting portion 141 increases, and when the width W2 of the second portion decreases, the depth of the recess of the connecting portion 141 increases. And when the thickness of the protruding region increases, the thickness of the first pad 142 may be increased accordingly. Also, when the depth of the recess increases, there may be a dimple region in the first pad 142 corresponding thereto. Thus, in the embodiment, the width W2 of the second portion is set to have a level of 5% to 20% of the upper width or the lower width of the via hole VH1. When the width W2 of the second portion is less than 5% of the upper width or the lower width of the via hole VH1, there may be a dimple region in the first pad 142. Also, when the width W2 of the second portion is greater than 20% of the upper width or the lower width of the via hole VH1, the thickness of the protruding region of the connecting portion 141 increases, whereby the thickness of the first pad 142 or the second pad 143 may increase, and further the overall thickness of the printed circuit board 100 may increase.

[0129] In other words, the width of the first opening region OR1 can have a level of 80% to 95% of the upper width or the lower width of the via hole VH1.

[0130] Next, referring to FIG. 10, electrolytic plating is performed based on the seed layer 120 to form the connecting portion 141 of the via 140 in the via hole VH1.

[0131] The connecting portion 141 can be formed of any metal material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd).

[0132] At this time, the connecting portion 141 can be disposed in a via hole formed in the insulating layer 110. Preferably, the connecting portion 141 can be formed by filling a part of the via hole formed in the insulating layer 110.

[0133] That is, the connecting portion 141 may be formed by filling only a part of the via holes formed in the insulating layer 110, rather than the whole of the via holes.

[0134] Thereby, the connecting portion 141 can have a curved surface whose surface is not a flat surface. Preferably, the upper surface of the connecting portion 141 can include a shape that is recessed in the downward direction. Also, the lower surface of the connecting portion 141 can include a shape that is recessed in the upward direction. Thereby, the length of the upper surface of the connecting portion 141 may be larger than the upper width of the via holes formed in the insulating layer 110. That is, the upper surface of the connecting portion 141 can have a curved surface, and thereby the length of the upper surface of the connecting portion 141 may be larger than the upper width of the via holes.

[0135] A part of the upper surface of the connecting portion 141 can be positioned lower than the upper surface of the insulating layer 110. For example, the central region of the upper surface of the connecting portion 141 can be positioned lower than the upper surface of the insulating layer 110. That is, a recess can be formed in the upper surface of the connecting portion 141. Thereby, the length of the lower surface of the connecting portion 141 may be larger than the lower width of the via holes formed in the insulating layer 110. That is, the lower surface of the connecting portion 141 can have a curved surface, and thereby the length of the lower surface of the connecting portion 141 may be larger than the lower width of the via holes.

[0136] Also, a part of the lower surface of the connecting portion 141 can be positioned higher than the lower surface of the insulating layer 110. For example, the central region of the lower surface of the connecting portion 141 can be positioned higher than the lower surface of the insulating layer 110. That is, a recess can be formed in the lower surface of the connecting portion 141.

[0137] Thereby, the connecting portion 141 may have recesses formed in the upper surface and the lower surface respectively, and can include an overall "X" shape.

[0138] Specifically, the via hole may include a first region located at the center of the insulating layer 110, a second region located above the insulating layer 110 on the first region, and a third region located below the insulating layer 110 under the first region. And the entire region of the first region of the via hole can be filled by the connecting portion 141. In contrast, only a part of the regions of the second and third regions of the via hole can be filled by the connecting portion 141.

[0139] On the other hand, the recess formed on the upper surface of the connecting portion 141 may be formed to have a first depth D1 from the upper surface of the insulating layer 110. Also, the recess formed on the lower surface of the connecting portion 141 may be formed to have a second depth D2 from the lower surface of the insulating layer 110.

[0140] At this time, the first depth D1 may be the same as the second depth D2. For example, the first depth D1 may be 0.95 times to 1.05 times the second depth D2.

[0141] The first depth D1 can have a thickness at a level of 5% to 40% of the thickness of the insulating layer 110. For example, the first depth D1 can have a thickness at a level of 10% to 20% of the thickness of the insulating layer 110. When the first depth D1 is less than 5% of the thickness of the insulating layer 110, the thickness of the protruding region of the connecting portion 141 described later may increase, and thereby the thickness of the first pad 142 may increase. Also, when the first depth D1 is greater than 40% of the thickness of the insulating layer 110, a dimple region may occur in the process of forming the first pad 142 in the future.

[0142] The second depth D2 can have a thickness at a level of 5% to 40% of the thickness of the insulating layer 110. For example, the second depth D2 can have a thickness at a level of 10% to 20% of the thickness of the insulating layer 110. When the second depth D2 is less than 5% of the thickness of the insulating layer 110, the thickness of the protruding region of the connecting portion 141 described later may increase, and thereby the thickness of the second pad 143 may increase. Also, when the second depth D2 is greater than 40% of the thickness of the insulating layer 110, a dimple region may occur in the process of forming the second pad 143 later.

[0143] On the other hand, the connecting portion 141 can include a protruding region protruding from the surface of the insulating layer 110 and the surface of the seed layer 120. This is because the second portion of the first mask M1 is not disposed in a state supported on the seed layer 120 like the first portion, but is disposed to be floating.

[0144] Thereby, a part of the upper surface of the connecting portion 141 can be located higher than the upper surface of the insulating layer 110. For example, a part of the upper surface of the connecting portion 141 can be located higher than the upper surface of the seed layer 120.

[0145] Also, a part of the lower surface of the connecting portion 141 can be located lower than the lower surface of the insulating layer 110. For example, a part of the lower surface of the connecting portion 141 can be located lower than the lower surface of the seed layer 120. That is, the lower surface of the connecting portion 141 can also include a protruding region protruding below the lower surface of the insulating layer 110 and the lower surface of the seed layer 120.

[0146] Next, referring to FIG. 11, the first mask M1 disposed on the seed layer 120 is removed. Thereafter, a second mask M2 having a second opening region OR2 that exposes a region where the circuit pattern 130, the first pad 142, and the second pad 143 are to be formed is formed on the seed layer 120.

[0147] The second mask M2 may be disposed on the seed layer 120 disposed on the upper surface of the insulating layer 110, and may also be disposed below the seed layer 120 disposed on the lower surface of the insulating layer 110 in the same manner.

[0148] The second opening region OR2 may expose a region of the upper surface of the seed layer 120 where the circuit pattern 130 is formed.

[0149] Also, the second opening region OR2 may expose a region of the upper surface of the seed layer 120 where the first pad 142 and the second pad 143 are formed.

[0150] Also, the second opening region OR2 may expose the upper region and the lower region of the connecting portion 141.

[0151] Next, referring to FIG. 12, a circuit pattern 130, a first pad 142, and a second pad 143 are formed on the seed layer 120 and the connecting portion 141 exposed through the second opening region OR2 of the second mask M2.

[0152] Next, as shown in FIG. 13, the second mask M2 can be removed. Thereafter, a step of removing the remaining portion of the seed layer 120 disposed on the insulating layer 110 except for the portion disposed in the region overlapping the circuit pattern 130, the first pad 142, and the second pad 143 can be performed.

[0153] According to this embodiment, in the case of a conventional large-area via, restrictions on the plating of a large-diameter via hole occur. However, through a change in the plating method for this, the restrictions on the plating of the large-diameter via hole of the large-area via can be broken, and thus the plating of the large-diameter via hole can be stably realized. Also, according to this embodiment, the uniformity of the via plating can be ensured as compared with the existing method, and the quality reliability due to the improvement of the laser quality after additional lamination can be ensured.

[0154] Conventionally, there has been a process limitation ratio for stably realizing plating inside the via hole between the thickness of the insulating layer and the size of the via hole. However, according to this embodiment, it is possible to break the design constraints for realizing a highly reliable plating state inside the via hole, thereby improving the degree of freedom in design. Also, according to the embodiment, by increasing the size of the via, it is possible to completely shield the interference between circuits generated in the region where the circuits are concentrated using this, and improve the heat dissipation characteristics in the region where the role of heat dissipation is required.

[0155] FIG. 14 is a diagram showing a printed circuit board according to the second embodiment.

[0156] Referring to FIG. 14, the printed circuit board 100A includes a first insulating layer 110, a second insulating layer 170, a third insulating layer 180, a first via 140, a second via 150, a third via 160, a circuit pattern 130, a seed layer 120, a first protective layer 190, and a second protective layer 195.

[0157] In FIG. 14, the same reference numerals are given to the substantially same configurations as those described in the explanation of FIG. 4, and thus, detailed explanations thereof are omitted.

[0158] Referring to FIG. 14, the printed circuit board 100A has a plurality of laminated structures. Among these, the first insulating layer 110 located in the center includes a seed layer 120, a circuit pattern 130, and at least one first via 140. And the at least one first via 140 includes a first pad 142, a second pad 143, and a connecting portion 141.

[0159] Here, the first insulating layer 110, the seed layer 120, the circuit pattern 130, and the first via 140 have already been described with reference to FIGS. 4 and 5 above, so they are omitted.

[0160] The second insulating layer 170 is disposed on the first insulating layer 110. And the third insulating layer 180 is disposed under the first insulating layer 110.

[0161] The second insulating layer 170 may be disposed to cover the circuit pattern 130 and the first pad 142 of the first via 140 disposed on the upper surface of the first insulating layer 110.

[0162] The third insulating layer 180 may be disposed to cover the circuit pattern 130 and the second pad 143 of the first via 140 disposed on the lower surface of the first insulating layer 110.

[0163] On the other hand, although not labeled in FIG. 14, circuit patterns may be disposed on the upper surface of the second insulating layer 170 and the lower surface of the third insulating layer 180, respectively.

[0164] A second via 150 may be disposed to penetrate the second insulating layer 170. The lower surface of the second via 150 may be connected to the circuit pattern 130 or the first pad 142 disposed on the upper surface of the first insulating layer 110.

[0165] The second via 150 may have a shape corresponding to that of the first via 140. However, the first via 140 is a PTH (Plated Through Hole) via. In contrast, the second via 150 is a BVH (Blind Via Hole) via. Accordingly, unlike the first via 140, the second via 150 may include only one pad.

[0166] Specifically, the second via 150 may include a second seed layer 151, a second connecting portion 152, and a third pad 153. The lower surface of the second connecting portion 152 may be connected to the first pad 142 of the first via 140. Also, the upper surface of the second connecting portion 152 may be connected to the third pad 153.

[0167] The second connection part 152 may be formed by filling only a part, rather than the whole, of the via hole formed in the second insulating layer 170. Accordingly, the upper surface of the second connection part 152 may include a shape that is recessed in the downward direction. Thereby, the length of the upper surface of the second connection part 152 may be greater than the upper width of the via hole formed in the second insulating layer 170. That is, the upper surface of the second connection part 152 may have a curved surface, and thereby the length of the upper surface of the second connection part 152 may be greater than the upper width of the via hole formed in the second insulating layer 170.

[0168] A part of the upper surface of the second connection part 152 may be positioned lower than the upper surface of the second insulating layer 170. For example, the central region of the upper surface of the second connection part 152 may be positioned lower than the upper surface of the second insulating layer 170. That is, a recess may be formed in the upper surface of the second connection part 152.

[0169] That is, a recess may be formed in the upper surface of the second connection part 152, and thereby a "V" shape may be included.

[0170] Specifically, the via hole formed in the second insulating layer 170 may include a first region positioned below the second insulating layer 170 and a second region positioned above the second insulating layer 170 on the first region. And the entire region of the first region of the via hole formed in the second insulating layer 170 may be filled by the second connection part 152. In contrast, only a partial region of the second region of the via hole formed in the second insulating layer 170 may be filled by the second connection part 152.

[0171] On the other hand, the recess formed in the upper surface of the second connection part 152 may be formed to have a certain depth from the upper surface of the second insulating layer 170.

[0172] The depth of the recess of the second connection portion 152 can have a thickness at a level of 5% to 40% of the thickness of the second insulating layer 170. For example, the depth of the recess of the second connection portion 152 can have a thickness at a level of 10% to 20% of the thickness of the second insulating layer 170. When the depth of the recess of the second connection portion 152 is less than 5% of the thickness of the second insulating layer 170, the thickness of the protruding region of the second connection portion 152 increases, and thereby the thickness of the third pad 153 may increase. Also, when the depth of the recess of the second connection portion 152 is greater than 40% of the thickness of the second insulating layer 170, a dimple region may exist in the third pad 152.

[0173] On the other hand, the third pad 153 may be disposed on the upper surface of the second insulating layer 170. Preferably, a second seed layer 151 may be further disposed between the third pad 153 and the upper surface of the second insulating layer 170. The second seed layer 151 may be disposed between the third pad 153 and the upper surface of the second insulating layer 170. Also, the second seed layer 151 may be disposed on the inner wall of the via hole.

[0174] The lower surface of the third pad 153 may be in contact with the upper surface of the second connection portion 152. Thereby, the lower surface of the third pad 153 can include a shape corresponding to the upper surface of the second connection portion 152. Specifically, the lower surface of the third pad 153 can be a curved surface having a curvature corresponding to the upper surface of the second connection portion 152. For example, the third pad 153 can have a convex portion corresponding to the recess formed in the upper surface of the second connection portion 152.

[0175] As a result, at least a part of the lower surface of the third pad 153 can be positioned lower than the upper surface of the second seed layer 151. For example, a part of the lower surface of the third pad 153 can be positioned lower than the upper surface of the second insulating layer 170. For example, a part of the lower surface of the third pad 153 can be positioned lower than the upper surface of the second connecting portion 152. For example, a part of the lower surface of the third pad 153 can be positioned lower than the end of the upper surface of the second connecting portion 152. Specifically, the central portion of the lower surface of the third pad 153 can be positioned lower than the end of the upper surface of the second connecting portion 152.

[0176] As a result, a part of the upper surface of the second connecting portion 152 can be positioned higher than a part of the lower surface of the third pad 153. Also, another part of the upper surface of the second connecting portion 152 can be positioned lower than another part of the lower surface of the third pad 153.

[0177] The third via 160 can have a shape corresponding to the second via 150. That is, the first via 140 is a PTH (Plated Through Hole) via. In contrast, the second via 150 and the third via 160 are BVH (Blind Via Hole) vias. Thereby, the third via 160 can include only one pad so as to correspond to the second via 150.

[0178] Specifically, the third via 160 can include a third seed layer 161, a third connecting portion 162, and a fourth pad 163. The upper surface of the third connecting portion 162 can be connected to the second pad 143 of the first via 140.

[0179] The third connecting portion 162 may be formed by filling only a part of the via holes formed in the third insulating layer 180, rather than the entire via holes. Therefore, the lower surface of the third connecting portion 162 may include a shape that is recessed in the upward direction. As a result, the length of the lower surface of the third connecting portion 162 may be greater than the upper width of the via holes formed in the third insulating layer 180. That is, the lower surface of the third connecting portion 162 may have a curved surface, and thus the length of the lower surface of the third connecting portion 162 may be greater than the lower width of the via holes formed in the third insulating layer 180.

[0180] A part of the lower surface of the third connecting portion 162 may be located higher than the lower surface of the third insulating layer 180. For example, the central region of the lower surface of the third connecting portion 162 may be located higher than the lower surface of the third insulating layer 180. That is, a recess may be formed in the lower surface of the third connecting portion 162.

[0181] That is, a recess may be formed in the lower surface of the third connecting portion 162, and thus it may include an "inverted V" shape.

[0182] Specifically, the via holes formed in the third insulating layer 180 may include a first region located above the third insulating layer 180 and a second region located below the third insulating layer 180 under the first region. And the entire region of the first region of the via holes formed in the third insulating layer 180 may be filled by the third connecting portion 162. In contrast, only a partial region of the second region of the via holes formed in the third insulating layer 180 may be filled by the third connecting portion 162.

[0183] On the other hand, the recess formed in the lower surface of the third connecting portion 162 may be formed to have a certain depth from the lower surface of the third insulating layer 180.

[0184] The depth of the recess of the third connecting portion 162 can be a thickness at a level of 5% to 40% of the thickness of the third insulating layer 180. For example, the depth of the recess of the third connecting portion 162 can be a thickness at a level of 10% to 20% of the thickness of the third insulating layer 180. When the depth of the recess of the third connecting portion 162 is less than 5% of the thickness of the third insulating layer 180, the thickness of the protruding region of the third connecting portion 162 may increase, and thereby the thickness of the fourth pad 163 may increase. Also, when the depth of the recess of the third connecting portion 162 is greater than 40% of the thickness of the third insulating layer 180, a dimple region may exist in the fourth pad 162.

[0185] On the other hand, the fourth pad 163 may be disposed on the lower surface of the third insulating layer 180. Preferably, a third seed layer 161 may be further disposed between the fourth pad 163 and the lower surface of the third insulating layer 180. The third seed layer 161 may be disposed between the fourth pad 163 and the lower surface of the third insulating layer 180. Also, the third seed layer 161 may be disposed on the inner wall of the via hole formed in the third insulating layer 180.

[0186] The upper surface of the fourth pad 163 may be in contact with the lower surface of the third connecting portion 162. Thereby, the upper surface of the fourth pad 163 can include a shape corresponding to the lower surface of the third connecting portion 162. Specifically, the upper surface of the fourth pad 163 can be a curved surface having a curvature corresponding to the lower surface of the third connecting portion 162. For example, the fourth pad 163 can have a convex portion corresponding to the recess formed in the lower surface of the third connecting portion 162.

[0187] As a result, at least a part of the upper surface of the fourth pad 163 can be positioned higher than the lower surface of the third seed layer 161. For example, a part of the upper surface of the fourth pad 163 can be positioned higher than the lower surface of the third insulating layer 180. For example, a part of the upper surface of the fourth pad 163 can be positioned higher than the lower surface of the third connecting portion 162. For example, a part of the upper surface of the fourth pad 163 can be positioned higher than the end portion of the lower surface of the third connecting portion 162. Specifically, the central portion of the upper surface of the fourth pad 163 can be positioned higher than the end portion of the lower surface of the third connecting portion 162.

[0188] As a result, a part of the lower surface of the third connecting portion 162 can be positioned lower than a part of the upper surface of the fourth pad 163. Also, another part of the lower surface of the third connecting portion 162 can be positioned higher than another part of the upper surface of the fourth pad 163.

[0189] On the other hand, a part of the upper surface of the second connecting portion 152 can be positioned higher than the upper surface of the second insulating layer 170. For example, a part of the upper surface of the second connecting portion 152 can be positioned higher than the upper surface of the second seed layer 151.

[0190] Preferably, a part of the upper surface of the second connecting portion 152 can be arranged higher than the lower surface of the third pad 153. That is, the second connecting portion 152 can include a protruding region protruding in the upper direction from the second insulating layer 170 and the second seed layer 151.

[0191] Also, similarly, a part of the lower surface of the third connecting portion 162 can be positioned lower than the lower surface of the third insulating layer 180. For example, a part of the lower surface of the third connecting portion 162 can be positioned lower than the lower surface of the third seed layer 161.

[0192] Preferably, a part of the lower surface of the third connecting portion 162 can be positioned lower than the upper surface of the fourth pad 163. That is, the third connecting portion 162 can include a protruding region protruding downward from the third insulating layer 180 and the third seed layer 161.

[0193] According to such an embodiment, in the case of a conventional large-area via, there are restrictions on the plating of a large-diameter via hole. However, through a change in the plating method for this, the restrictions on the plating of the large-diameter via hole of the large-area via can be broken, and thus the plating of the large-diameter via hole can be stably realized. Further, according to this embodiment, the uniformity of via plating can be ensured as compared with the existing method, and the quality reliability due to the improvement of laser quality after additional lamination can be ensured.

[0194] Also, conventionally, there was a process limit ratio for stably realizing plating inside the via hole between the thickness of the insulating layer and the size of the bar hole. However, according to this embodiment, the design constraints for realizing a highly reliable plating state inside the via hole can be broken, and thus the degree of freedom in design can be improved. Further, according to the embodiment, by increasing the size of the via, the interference between circuits generated in the region where the circuits are concentrated using this can be completely shielded, and the heat dissipation characteristics in the region where the role of heat dissipation is required can be improved.

Claims

1. A first insulating layer including a through hole penetrating an upper surface and a lower surface opposite to the upper surface; A first metal layer including a first portion disposed on the upper surface of the first insulating layer and a second portion disposed on the inner wall of the through hole; A second metal layer disposed on the second portion of the first metal layer and including an upper surface recessed with respect to the upper surface of the first insulating layer; The horizontal width of the upper surface of the second metal layer is Equal to or less than the width of the upper region of the through hole adjacent to the upper surface of the first insulating layer; The upper surface of the second metal layer does not overlap with the upper surface of the first insulating layer in the vertical direction and includes a protruding portion positioned higher than the first portion of the first metal layer, a circuit board.

2. The horizontal width of the upper surface of the second metal layer is Smaller than the width of the upper region of the through hole, the circuit board according to claim 1.

3. The upper surface of the second metal layer is A first region positioned lower than the upper surface of the first insulating layer; A second region adjacent to the inner wall of the through hole rather than the first region and positioned higher than the upper surface of the first insulating layer, the circuit board according to claim 1 or 2.

4. The upper surface of the second metal layer is Does not overlap with the upper surface of the first insulating layer in the vertical direction, the circuit board according to any one of claims 1 to 3.

5. Further includes a third metal layer disposed on the first portion of the first metal layer and the second metal layer; The third metal layer overlaps vertically with the upper surface of the second metal layer and includes a lower surface convex toward the upper surface of the second metal layer, the circuit board according to any one of claims 1 to 4.

6. The lower surface of the third metal layer is A third region positioned lower than the upper surface of the first insulating layer; The circuit board according to claim 5, comprising a fourth region adjacent to the inner wall of the through hole and higher than the upper surface of the first insulating layer, relative to the third region.

7. The second metal layer includes a first part adjacent to the upper surface of the first insulating layer and having a first inclination with a width decreasing toward the lower surface of the first insulating layer; The circuit board according to any one of claims 1 to 6, comprising a second part adjacent to the lower surface of the first insulating layer and having a second inclination with a width increasing toward the lower surface of the first insulating layer.

8. The circuit board according to claim 7, wherein the first inclination and the second inclination incline in different directions from each other.

9. The second metal layer includes a convex lower surface with reference to the lower surface of the first insulating layer, and the horizontal width of the lower surface of the second metal layer is equal to or less than the width of the lower region of the through hole adjacent to the lower surface of the first insulating layer. The circuit board according to any one of claims 1 to 8.

10. The horizontal width of the lower surface of the second metal layer is smaller than the width of the lower region of the through hole. The circuit board according to claim 9.

11. The lower surface of the second metal layer includes a fifth region located higher than the lower surface of the first insulating layer, and a sixth region adjacent to the inner wall of the through hole and lower than the lower surface of the first insulating layer, relative to the fifth region. The circuit board according to claim 9 or 10.

12. The lower surface of the second metal layer does not overlap with the lower surface of the first insulating layer in the vertical direction. The circuit board according to any one of claims 9 to 11.

13. The first metal layer includes a third portion disposed on the lower surface of the first insulating layer, Further comprising a fourth metal layer disposed under the third portion of the first metal layer and the second metal layer, The circuit board according to any one of claims 9 to 12, wherein the fourth metal layer overlaps perpendicularly with the lower surface of the second metal layer and includes an upper surface convex toward the lower surface of the second metal layer.

14. The upper surface of the fourth metal layer, A seventh region located higher than the lower surface of the first insulating layer, and The circuit board according to claim 13, comprising an eighth region adjacent to the inner wall of the through hole and lower than the lower surface of the first insulating layer with respect to the seventh region.

15. The circuit board according to any one of claims 1 to 14, wherein the vertical distance from the lowest height of the upper surface of the second metal layer to the upper surface of the first insulating layer satisfies the range of 5% to 40% of the thickness of the first insulating layer.

16. The circuit board according to any one of claims 9 to 15, wherein the vertical distance from the highest height of the lower surface of the second metal layer to the lower surface of the first insulating layer satisfies the range of 5% to 40% of the thickness of the first insulating layer.

17. A second insulating layer disposed on the upper surface of the first insulating layer, and Further comprising a fifth metal layer that overlaps perpendicularly with the second metal layer and penetrates the second insulating layer, The lower surface of the fifth metal layer is flat, The circuit board according to any one of claims 9 to 16, wherein the upper surface of the fifth metal layer is recessed with respect to the upper surface of the second insulating layer.

18. A third insulating layer disposed under the lower surface of the first insulating layer, and Further comprising a sixth metal layer that overlaps perpendicularly with the second metal layer and penetrates the third insulating layer, The upper surface of the sixth metal layer is flat, The package substrate according to any one of claims 9 to 17, wherein the lower surface of the sixth metal layer is recessed with respect to the lower surface of the third insulating layer.

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