Semiconductor devices and related methods for measurement improvement

Abstract

Disclosed are semiconductor devices, particularly semiconductor devices for improved resistance measurements, and related methods. Contact structures for semiconductor devices are disclosed that provide access for resistance measurements with reduced test-related resistance effects, thereby improving test accuracy, particularly for semiconductor devices with low on-resistance ratings. The semiconductor device may include an active area and a non-active area disposed along the periphery of the active area. The semiconductor device may be disposed with a top-side contact that provides access for resistance measurements, such as Kelvin-sense resistance measurements. Related methods include performing resistance measurements from the top side of the semiconductor device, even when the active area of ​​the semiconductor device forms a vertical contact structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices and related methods for improving measurements.

Background Art

[0002] Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide-bandgap semiconductor material systems such as gallium nitride (GaN) and silicon carbide (SiC) are increasingly being used in semiconductor devices to push the boundaries of device performance in areas such as switching speed, power handling capabilities, and thermal conductivity. Examples include individual devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), insulated-gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, high electron mobility transistors (HEMTs), and integrated circuits such as monolithic microwave integrated circuits (MMICs) that include one or more individual devices.

[0003] Semiconductor devices for power-switching applications typically include a device region of a semiconductor die that may in some cases be surrounded by an edge termination region. The device region forms the active part or active region, while the edge termination region forms the non-active part of the power semiconductor device that can act to reduce the concentration of the electric field along the device edge for preventing breakdown in the blocking mode. The active regions of some semiconductor devices can include a number of unit cells that are electrically coupled in parallel to each other between one or more electrodes to provide the selective current conduction ability and voltage blocking ability for the device.

[0004] Semiconductor devices for power switching applications are continuously being developed with improved operating characteristics to meet the evolving requirements of modern electronics. As the operating characteristics are continuously improved, there can be challenges when using conventional evaluation techniques to accurately quantify the latest semiconductor devices.

[0005] The technology continues to seek improved semiconductor devices and characteristic evaluation techniques that can overcome the challenges associated with conventional semiconductor devices.

Summary of the Invention

Means for Solving the Problems

[0006] The present disclosure relates to semiconductor devices, and in particular to semiconductor devices and related methods for measurement improvement. A contact structure for a semiconductor device is disclosed that provides access to resistance measurements with reduced influence of resistance related to testing, thereby improving test accuracy for semiconductor devices having particularly low on-resistance ratings. The semiconductor device can include an active region and a non-active region disposed along the outer periphery of the active region. The semiconductor device may be disposed with an upper contact that provides access for resistance measurements, such as Kelvin sense resistance measurements. Related methods are disclosed that include performing resistance measurements from above the semiconductor device even when the active region of the semiconductor device forms a vertical contact structure.

[0007] In one aspect, a semiconductor device includes: a drift region including an active region and a non-active region, the non-active region being disposed along an outer peripheral portion of the active region; a first contact on a first side of the drift region; and a second contact on a second side of the drift region opposite the first side, the second contact being disposed along the non-active region. The second contact can form a Kelvin sense contact on the second side of the drift region. The semiconductor device can further include a passivation layer on the second side of the drift region, and the second contact is accessible through an opening formed in the passivation layer. In one embodiment, the non-active region includes an edge termination region between the active region and an outer peripheral edge of the drift region, and the second contact is disposed on a portion of the drift region between the edge termination region and the outer peripheral edge of the drift region. In one embodiment, the drift region includes a surface depletion protection region having the same doping type as the doping type of the drift region and a higher doping concentration than the doping concentration of the drift region, the edge termination region is disposed between the active region and the surface depletion protection region, and the second contact is on the surface depletion protection region. In one embodiment, the drift region includes silicon carbide (SiC). In one embodiment, the active region includes a SiC metal-oxide-semiconductor field-effect transistor (MOSFET). In one embodiment, the first contact is a first drain contact on the first side of the drift region, and the second contact is a second drain contact on the second side of the drift region. The second contact may be disposed on a first surface of the drift region and on a sidewall of the drift region. The semiconductor device can further include a substrate, the first contact is disposed on a first side of the substrate, and the second contact is further disposed on a portion of the substrate outside an outer peripheral edge of the drift region, or the second contact is further disposed on a portion of the first contact outside an outer peripheral edge of the substrate. In one embodiment, the edge termination region forms a ring having a corner portion curved around the active region, and the second contact is provided between one of a plurality of curved corner portions of the edge termination region and an outer peripheral corner portion of the semiconductor device.The semiconductor device may further include an additional second contact disposed between other curved corner portions of the edge termination region and other outer peripheral corner portions of the semiconductor device. In certain embodiments, the outer peripheral corner portions of the semiconductor device form part of a rectangular shape with respect to the semiconductor device. In certain embodiments, the outer peripheral corner portions of the semiconductor device form part of a hexagonal shape with respect to the semiconductor device. In certain embodiments, the semiconductor device further includes a substrate disposed between the drift region and the first contact. In certain embodiments, the semiconductor device includes a surface depletion region disposed in a non-active region.

[0008] In another aspect, a method of performing a Kelvin sensing measurement includes mounting and electrically connecting a first side of a semiconductor device to a conductive support structure, and measuring a Kelvin sensing voltage from a second side of the semiconductor device that is opposite the first side. In certain embodiments, measuring the Kelvin sensing voltage includes supplying a current to the semiconductor device from a first terminal connected to the second side of the semiconductor device and a second terminal connected to the conductive support structure, and measuring the Kelvin sensing voltage with a first sensing terminal and a second sensing terminal both connected to the second side of the semiconductor device. In certain embodiments, the semiconductor device is a MOSFET, the first terminal and the first sensing terminal are connected to the source contact of the MOSFET, the second terminal is connected to the first drain contact of the MOSFET, and the second sensing terminal is connected to the second drain contact of the MOSFET. In certain embodiments, the MOSFET includes an active region and a non-active region disposed along an outer periphery of the active region, and the second drain contact is provided on the non-active region. In certain embodiments, the non-active region includes an edge termination region, and the second drain contact is on a portion of the non-active region that is between the edge termination region and the outer edge of the semiconductor device.

[0009] In another aspect, the method includes: providing a semiconductor device including a drift region having an active region and a non-active region; mounting a first side of the semiconductor device on a support structure; and measuring characteristics of the semiconductor device using a contact disposed on a second side of the semiconductor device opposite the first side, wherein the contact is disposed on the non-active region. In one embodiment, measuring the characteristics of the semiconductor device includes: supplying current to the semiconductor device from a first terminal connected to the active region from the second side of the semiconductor device and a second terminal connected to the active region from the first side of the semiconductor device; and measuring voltage with a first sensing terminal connected to the active region and a second sensing terminal connected to the contact. In one embodiment, the semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET), the first terminal and the first sensing terminal are connected to a source contact of the MOSFET, the second terminal is connected to a first drain contact of the MOSFET, and the contact is a second drain contact of the MOSFET. In one embodiment, the characteristic is the resistance of the semiconductor device. In one embodiment, the contact is a Kelvin sensing contact.

[0010] In another aspect, any of the foregoing aspects, individually or together, and / or various separate aspects and features as described herein may be combined for further advantages. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein to the contrary.

[0011] Those skilled in the art will recognize the scope of the present disclosure and will understand further aspects of the present disclosure after reading the following detailed description of the preferred embodiments in relation to the accompanying drawing figures.

[0012] The accompanying drawing figures, which are incorporated herein and form a part hereof, illustrate some aspects of the disclosure, together with the description serving to explain the principles of the disclosure.

Brief Description of the Drawings

[0013]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0014] The examples described below represent the information necessary for one of ordinary skill in the art to execute the examples and illustrate the best mode of carrying out the examples. Reading the following description in consideration of the accompanying drawing figures, one of ordinary skill in the art will understand the disclosed concepts and recognize the application of these concepts that are not specifically addressed herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0015] Although the terms first, second, etc. may be used herein to describe various elements, it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] When an element such as a layer, region, or substrate is said to be "on" or to "extend onto" another element, it should be understood that it may be directly on or extend directly into the other element, or intervening elements may also be present. In contrast, when an element is said to be "directly on" or to "extend directly onto" another element, no intervening elements are present. Similarly, when an element such as a layer, region, or substrate is said to be "over" or to "extend over" another element, it should be understood that it may be directly over or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is said to be "directly over" or to "extend directly over" another element, no intervening elements are present. When an element is said to be "connected" or "coupled" to another element, it should also be understood that it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0017] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It should be understood that these terms, as well as those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" include plural referents as well, unless the context clearly dictates otherwise. It is further to be understood that when the terms "comprises", "comprising", "includes" and / or "including" are used in this specification, they specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is further understood that terms used herein are to be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and that they are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0020] Embodiments are described with reference to schematic illustrations of embodiments disclosed herein. As such, the actual dimensions of layers and elements may differ, and for example, variations from the shape of the illustrative drawings are expected as a result of manufacturing techniques and / or tolerances. For example, regions illustrated or described as square or rectangular may have rounded or curved outlines, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the exact shape of regions of the device nor are they intended to limit the scope of the disclosure. Additionally, the size of a structure or region may be exaggerated relative to other structures or regions for illustrative purposes and thus may be provided to illustrate the general structure of the subject matter and may or may not be drawn to scale. Common elements between multiple figures may be shown herein using common element numbers and may not be described again later.

[0021] The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices and related methods for measurement improvement. A contact structure for a semiconductor device is disclosed that provides access for resistance measurements in a state where the influence of resistance related to testing is reduced, thereby improving test accuracy particularly for semiconductor devices having a low on-resistance rating. The semiconductor device can include an active region and a non-active region disposed along the outer periphery of the active region. The semiconductor device may have an upper contact disposed to provide access for resistance measurements, such as Kelvin sense resistance measurements. Related methods are disclosed that include performing resistance measurements from above the semiconductor device even when the active region of the semiconductor device forms a vertical contact structure.

[0022] FIG. 1 is a top view illustration of an exemplary semiconductor device 10 according to the present disclosure. The semiconductor device 10 includes an active region 12 and an edge termination region 14 surrounding the active region 12 near the outer periphery of the semiconductor device 10. Depending on the particular application, the active region 12 can include, among other things, one or more power semiconductor switching devices or cells formed within the active region, such as one or more metal-oxide-semiconductor field effect transistors (MOSFETs), metal-insulator-semiconductor field effect transistors (MISFETs), PiN diodes, and insulated gate bipolar transistors (IGBTs). The semiconductor device 10 can include a wide bandgap semiconductor device, such as a silicon carbide (SiC)-based device, and even further a 4H-SiC-based device. The edge termination region 14 reduces the concentration of the electric field at the edge of the semiconductor device 10 to improve the performance of the semiconductor device. For example, the edge termination region 14 can increase the breakdown voltage of the semiconductor device 10 and reduce leakage current, such as that of the semiconductor device 10 over time, as discussed in detail below. By way of example, the edge termination region 14 can include one or more guard rings, junction termination extensions (JTEs), and combinations thereof. In one aspect, the edge termination region 14 can form at least a portion of the non-active region of the semiconductor device 14.

[0023] Advances in the design of power semiconductor switching devices have led to devices with lower on-resistance ratings, thereby providing further reduction of power loss and heat generation in smaller device layouts. As an example, SiC MOSFETs and SiC MISFETs with low on-resistance ratings are continuously being developed to enable, among other applications, the advancement of battery-powered electric vehicle technology. In examples of SiC MOSFETs, devices are being developed that have an on-resistance rating of less than 20 milliohms (20 mΩ), or less than 15 mΩ, or less than 10 mΩ, or in the range of 1 mΩ to 20 mΩ at 25 °C, or even lower on-resistance ratings. Conventional device characterization techniques may not be suitable for accurately measuring devices with such low on-resistance ratings. For example, during the characterization of low on-resistance devices, the device wafer is typically mounted on a conductive chuck for testing, and the resistance introduced by the cables and / or probes that are coupled to the device and the chuck can give an unacceptably large contribution to the overall measured resistance. To accommodate this test voltage drop and to enable more accurate on-resistance measurements, Kelvin sensing techniques are typically used. With regard to Kelvin sensing, a first set of a plurality of drive terminals connected to the source and drain of the MOSFET is used to supply a forward current, and a second set of a plurality of sense terminals connected to the source and drain is provided to collect voltage measurements. In this arrangement, the second set of the plurality of sense terminals typically has little or no current flow to minimize the test voltage drop. Even when conventional Kelvin sensing measurement techniques are employed, not all test resistances and corresponding voltage drops may be completely mitigated, thereby complicating the accurate characterization of low on-resistance devices.

[0024] FIG. 2 is a cross-sectional view of an exemplary semiconductor device 16 configured for Kelvin sensing measurement. As an example, the semiconductor device 16 of FIG. 2 is a planar MOSFET having a vertical contact structure. However, the principles of the present disclosure are applicable to other semiconductor switching devices, including but not limited to trench MOSFETs, MISFETs, and IGBTs. The semiconductor device 16 includes a substrate 18 and a drift region 20 on the substrate 18. The drift region 20 can include one or more drift layers of a wide bandgap semiconductor material, such as SiC. The vertical dashed line is illustrated in the drift region 20 to delineate the edge termination region 14 from the active region 12. Additionally, the portion of the semiconductor device 16 outside the active region 12 including the edge termination region 14 may be referred to as the non-active region. In the edge termination region 14, several guard rings 22 are provided in the drift region 20. Specifically, the guard rings 22 are adjacent to, and in fact directly adjacent to, the upper surface 20A of the drift region 20 opposite the substrate 18. The guard rings 22 may be formed by ion implantation, and the implant used may include aluminum (Al), boron (B), or any other suitable p-type dopant when the drift region 20 is configured as an n-type layer. Each guard ring 22 forms a small region having a doping type opposite to that of the drift region 20 within the edge termination region 14. In this example, the drift region 20 is an n-type layer, while the guard rings 22 are p-type small regions. However, the principles of the present disclosure equally apply to devices having an opposite polarity configuration where the doping types may be reversed as illustrated in FIG. 2. For illustrative purposes, five guard rings 22 are shown, but the number of guard rings 22 may be five or more, or ten or more, or twenty or more, or within the range from five to twenty, or within the range from ten to twenty, depending on the application.

[0025] When the voltage is supported by the drift region 18, the electric field concentration tends to be greater at the outer edge of the edge termination region 14 than at the portion of the edge termination region 14 closer to the active region 12. In certain embodiments, a surface depletion protection region 24, or a channel stop, may be further provided in the drift region 20 at the outer edge of the edge termination region 14. The surface depletion protection region 24 may have the same doping type as the drift region 20, but may have a doping concentration higher than the doping concentration of the drift region 20. In this way, the surface depletion protection region 24 can prevent depletion in a region near or at the upper surface 20A of the drift region 20 in order to further improve the performance of the semiconductor device 10. In certain embodiments, the surface depletion protection region 24 is provided by implantation. A passivation layer 26 may be provided on the upper surface 20A of the drift region 20 opposite the substrate 16 to passivate the upper surface 20A of the drift region 20. The passivation layer 26 can be embodied as one or more layers of an insulating material of any suitable material, for example, one or more layers of a dielectric layer of an oxide and / or nitride system. In certain embodiments, the passivation layer 26 can embody a multilayer structure including one or more of a field oxide layer, one or more intermetallic dielectric layers, and an upper insulating layer. In certain embodiments, an additional passivation layer 28 including a material having chemical stability, mechanical stability, and high-temperature stability, for example, polyimide capable of forming a scratch-resistant coating, may be provided on the passivation layer 26.

[0026] The substrate 18 may have a doping concentration between 1×10 17 cm -3 and 1×10 20 cm -3 In various embodiments, the doping concentration of the substrate 18 may be prepared in any small range between 1×10 17 cm -3 and 1×10 20 cm -3 For example, the doping concentration of the substrate 16 may be between 1×10 18 cm -3 and 1×10 20 cm-3 between 1×10 19 cm -3 and 1×10 20 cm -3 between 1×10 17 cm -3 and 1×10 19 cm -3 between 1×10 17 cm -3 and 1×10 18 cm -3 between, and 1×10 18 cm -3 and 1×10 19 cm -3 it may be between.

[0027] The drift region 20 may have a doping concentration between 1×10 14 cm -3 and 1×10 18 cm -3 In various embodiments, the doping concentration of the drift region 18 may be any small range between 1×10 14 cm -3 and 1×10 18 cm -3 For example, the doping concentration of the drift region 18 may be between 1×10 15 cm -3 and 1×10 18 cm -3 between 1×10 16 cm -3 and 1×10 18 cm -3 between 1×10 17 cm -3 and 1×10 18 cm -3 between 1×10 14 cm -3 and 1×10 17 cm -3 between 1×10 14 cm -3 and 1×10 16 cm -3 between 1×10 14 cm -3 and 1×10 15 cm -3 between 1×10 15cm -3 and 1×10 17 cm -3 and between 1×10 15 cm -3 and 1×10 16 cm -3 and between, and 1×10 16 cm -3 and 1×10 17 cm -3 and between may also be. The surface depletion protection region 24 may have a doping concentration higher than the doping concentration of the drift region 20. In various embodiments, the surface depletion protection region 24 may have a doping concentration within the range from 2 times to 10 5 times that of the doping concentration of the drift region 20.

[0028] The guard ring 22 may have a doping concentration between 5×10 16 cm -3 and 1×10 21 cm -3 In various embodiments, the doping concentration of the guard ring 22 may be prepared in any small range between 5×10 16 cm -3 and 1×10 21 cm -3 For example, the doping concentration of the guard ring 20 may be between 5×10 18 cm -3 and 1×10 21 cm -3 and between 5×10 19 cm -3 and 1×10 21 cm -3 and between 5×10 20 cm -3 and 1×10 21 cm -3 and between 5×10 16 cm -3 and 1×10 20 cm -3 and between 5×10 16 cm -3 and 1×10 19 cm -3 and between, and 5×10 16 cm -3 and 1×10 20cm -3 It may also be between.

[0029] As discussed above, the active region 12 can include one or more semiconductor devices. In the example of FIG. 2, the active region 12 includes at least one MOSFET cell 30, for example, a SiC-based MOSFET in which the drift region 20 includes one or more layers of SiC. The MOSFET cell 30 includes a substrate 18 and a drift region 20. A plurality of junction implantation portions 32 are provided in the drift region 20, specifically, on the upper surface 20A of the drift region 20 opposite to the substrate 18. The junction implantation portion 32 includes a first well region 32A having a doping type opposite to that of the drift region 20, and a second well region 32B having the same doping type as that of the drift region 20. The upper portion 32C of the first well region 32A may be provided with the same doping type as the first well region 32A at a doping concentration equal to or higher than the doping concentration of the first well region 32A. A junction field effect transistor (JFET) region may be defined between the junction implantation portions 32. In one embodiment, the JFET region may have the same doping type as the drift region 20 at a doping concentration equal to or higher than the doping concentration of the drift region 20. A source contact 34 is provided above each one of the plurality of junction implantation portions 32 on the upper surface 20A of the drift region 20 opposite to the substrate 18, so that the source contact 34 contacts a part of the first well region 32A and a part of the second well region 32B. A source contact connector 36 may be provided to be electrically connected to each source contact 34. A gate oxide layer 38, which can include other insulating materials for other semiconductor devices, is provided on the upper surface 20A of the drift region 20 opposite to the substrate 18 and on a part of each one of the plurality of junction implantation portions 32, so that the gate oxide layer 38 partially overlaps with each one of the plurality of second well regions 32B. A gate contact 40 is provided on the gate oxide layer 34. A drain contact 42 is provided on the surface of the substrate 18 opposite to the drift region 20. In one embodiment, the drain contact 42 can include a multilayer contact structure having a first layer 42' of the drain contact 42 that provides an improvement in ohmic contact with the substrate 18.The MOSFET cells 30 may be arranged across the entire active region 12 or may be arranged in a desired pattern with one or more other semiconductor devices (e.g., diodes) to provide a desired function.

[0030] In FIG. 2, the semiconductor device 16 is arranged for resistance measurement, e.g., for Kelvin sense measurement. In this regard, the semiconductor device 16 is arranged on a conductive support structure 44 such as a chuck. A first terminal 46-1 is electrically connected to the source contact 34 (via the source contact connector 36 in FIG. 2), and a second terminal 46-2 is electrically connected to the drain contact 42 via the conductive support structure 44. A first sense terminal 48-1 is also connected to the source contact 34 (via the source contact connector 36), and a second sense terminal 48-2 is electrically connected to the drain contact 42 via the conductive support structure 44. During testing, a signal is supplied at the gate contact 40 to turn on the MOSFET cell 30, and a current I F is supplied through the drain contact 42 via the first and second terminals 46-1, 46-2. The Kelvin sense voltage (V S,Kelvin ) at the source contact 34 is provided by the first sense terminal 48-1, and the Kelvin sense voltage (V D,Kelvin ) at the drain contact 42 is provided by the second sense terminal 48-2. In this way, the on-resistance (R DS(on) ) between the drain and source of the MOSFET cell 30 may be calculated by the formula R DS(on) =(V D,Kelvin -V S,Kelvin ) / I F . Several factors affect such R DS(on)It may affect the accuracy of the measured values. At the source contact 34, biasing across the source metallization requires careful probe positioning to obtain an accurate reading of the device resistance. At the drain contact 42, since the drain contact 42 is contacted by the conductive support structure 44, it may be difficult to ensure careful probe positioning. In addition, for wafer-level testing, the second sensing terminal 48-2 may only be able to contact near the outer peripheral edge of the conductive support structure 44, which can be far from the location of the MOSFET cell 30 (e.g., >100 millimeters (mm) in some arrangements). The conductive support structure 44 may also be subject to a biasing effect that can be exacerbated by the quality of the contact to the conductive support structure 44. Such contact quality may vary depending on dirt on the back side of the semiconductor device 16 or changes in the quality of the vacuum supplied by the conductive support structure 44 to hold the semiconductor device 16 in place. In this regard, the V D,Kelvin measured value may still have a significant offset due to an added measurement resistance that is not related to the structure of the semiconductor device 16.

[0031] FIG. 3 is a cross-sectional view of a semiconductor device 50 having a vertical contact structure and further including a second drain contact 42-2 disposed on the upper side of the device for improving resistance measurements, e.g., Kelvin sense measurements. The semiconductor device 50 is similar to the semiconductor device 16 of FIG. 2, but further includes a second drain contact 42-2 on the upper side of the semiconductor device 50, which is opposite to the bottom side of the semiconductor device 50 where the main drain contact (or first drain contact 42-1) is located. The bottom side may also be referred to as the first side of the drift region 20 where the first drain contact 42-1 is present, and the upper side may also be referred to as the second side of the drift region 20 where the second drain contact 42-2 is present. In this arrangement, the drift region 20 is disposed between the first drain contact 42-1 and the second drain contact 42-2, and the second drain contact 42-2 is provided on the same side of the semiconductor device 50 as the source contact 34 and the gate contact 40. By providing the second drain contact 42-2 on the upper side of the semiconductor device 50, the Kelvin sense measurement may be realized when measured at the second drain contact 42-2 without the additional measurement resistance provided by the conductive support structure 44. In this regard, the connection for the Kelvin sense measurement may be made from the same side (e.g., the upper side) of the vertical structure semiconductor device 50, thereby reducing unnecessary yield loss and resulting in improved accuracy. D,Kelvin The detected drain voltage V

[0032] The second drain contact 42-2 can thus form a probe pad that is accessible from above the semiconductor device 50. As shown, the second drain contact 42-2 is provided in the edge termination region 14, or in other words, the second drain contact 42-2 is provided in the non-active region of the semiconductor device 50. The second drain contact 42-2 may also be referred to as a Kelvin sense contact. As shown, the portion of the second drain contact 42-2 is not covered by the passivation layer 26 and the additional passivation layer 28 to provide upper access for the second sense terminal 48-2. In one embodiment, the second drain contact 42-2 is accessible through an opening formed by one or more of the passivation layer 26 and the additional passivation layer 28. The second drain contact 42-2 can include a multi-layer contact structure that realizes an improvement in ohmic contact between the first layer 42-2' of the second drain contact 42-2 and the drift region 20 or the surface depletion protection region 24 of the drift region 20. In one embodiment, the surface depletion protection region 24 can define the boundary of the edge termination region 14, thereby forming a channel stop region 52 between the edge termination region 14 and the outer peripheral edge 50' of the semiconductor device 50 and the side wall 20' of the drift region 20. In this regard, the edge termination region 14 and the channel stop region 52 can together form the non-active region of the semiconductor device 50.

[0033] The side wall 20' may also be referred to as the outer peripheral edge of the drift region 20. In this regard, the second drain contact 42-2 may be configured to make an electrical connection with a portion of the drift region 20 that includes the channel stop region 52 and is outside the edge termination region 14 and the active region 12. For example, the second drain contact 42-2 may be provided between the edge termination region 14 and the outer peripheral edge of the semiconductor device 50. In such an arrangement, the second drain contact 42-2 may be provided without reducing the area of either the edge termination region 14 or the active region 12.

[0034] As described above, FIG. 3 illustrates one or more characteristics of the semiconductor device 50, or aspects of a method for measuring electrical characteristics. In one embodiment, the characterization can be a resistance measurement or a voltage measurement that can perform a Kelvin sensing measurement on the semiconductor device 50. In particular, the method can include mounting the bottom side of the semiconductor device 50 to the conductive support structure 44 and measuring the Kelvin sensing voltage from the upper side of the semiconductor device 50. During the test, a signal is supplied at the gate contact 40 to turn on the MOSFET cell 30, and a current I F is supplied to the first drain contact 42-1. The current I F is supplied via a first terminal 46-1 connected to the upper side of the semiconductor device 50 and a second terminal 46-2 connected to the conductive support structure 44. Then the Kelvin sensing voltage (V S,Kelvin ) at the source contact 34 is measured at the first sensing terminal 48-1, and the Kelvin sensing voltage (V D,Kelvin ) at the drain contact 42 is measured at the second sensing terminal 48-2. In this way, the on-resistance (R DS(on) ) between the drain and source of the MOSFET cell 30 can be calculated by the formula R DS(on) = (V D,Kelvin - V S,Kelvin ) / I F .

[0035] FIG. 4 is a cross-sectional view of a semiconductor device 54 similar to the semiconductor device 50 of FIG. 3, but at least a portion of the second drain contact 42-2 is disposed outside the channel stop region 52 to form an electrical connection to the substrate 18. In one embodiment, a portion of the drift region 20 near the outer peripheral edge 54' of the semiconductor device 54 may be removed by an etching process, and a portion of the second drain contact 42-2 may be provided in this etched area. The second drain contact 42-2 (and the corresponding first layer 42-2' when present) may then be conformally formed, such that a portion of the second drain contact 42-2 is provided along the sidewall 20' of the drift region 20 on the upper surface 20A of the drift region, and on the upper surface of the substrate 18 not covered by the drift region 20 or outside the outer peripheral edge of the drift region 20. In this way, the second drain contact 42-2 may be formed with an increased contact area. In addition, the second drain contact 42-2 can form electrical connections to the drift region 20 and to the substrate 18 at a location closer to the first drain contact 42-1.

[0036] FIG. 5 is a cross-sectional view of a semiconductor device 56 similar to the semiconductor device 54 of FIG. 4, but at least a portion of the second drain contact 42-2 is arranged to form an electrical connection to the first drain contact 42-1 that penetrates the substrate 18. In one embodiment, a portion of the substrate 18 may also be etched to provide access to the first drain contact 42-1. The second drain contact 42-2 (and the corresponding first layer 42-2' when present) may then be conformally formed, such that a portion of the second drain contact 42-2 is provided along the sidewall 20' of the drift region 20 on the upper surface 20A of the drift region, and on the upper surface of the substrate 18 not covered by the substrate 18 or outside the outer peripheral edge of the substrate 18. In this way, an electrical path is formed from the first drain contact 42-1, excluding the substrate 18 or the drift region 20, to the upper side of the semiconductor device 56.

[0037] FIG. 6A is a top layout view of a semiconductor device 58 having an improved Kelvin sensing structure according to the principles of the present disclosure. The semiconductor device 58 may be configured similarly to any of the semiconductor devices 50, 54, and 56 of FIGS. 3, 4, and 5, respectively. In the top layout view, a gate contact pad 60 and a number of source contact pads 62 are provided in the active region 12. The gate contact pad 60 may include one or more gate contact extensions 60' or a bus arranged to supply a gate signal from the gate contact 60 to other portions of the active region 12. The gate contact pad 60 is electrically coupled to a gate contact (e.g., 40 as shown in FIG. 3). The source contact pads 62 may be provided above other portions of the active region 12, including above a portion that may include passivation. The source contact pads 62 are electrically coupled to a source contact (e.g., 34 as shown in FIG. 3) and / or any source contact connector (e.g., 36 as shown in FIG. 3). In one arrangement, the source contact pad 62 may include the source contact connector 36 of FIG. 3.

[0038] As shown in FIG. 6A, one or more second drain contacts 42-2 may be provided near the corner of the semiconductor device 58 outside the edge termination region 14. The active region 12 can occupy a majority of the total device area, while the edge termination region 14 can form a ring having a curved corner around the edge termination region 14. By disposing the second drain contact 42-2 outside the edge termination region 14, the presence of the second drain contact 42-2 may not take up area from either the active region 12 or the edge termination region 14. In FIG. 6A, four of the plurality of second drain contacts 42-2 are provided at each corner of the semiconductor device 58 having a square or rectangular shape in the region between the curved corner of the edge termination region 14 and the outer peripheral corner of the semiconductor device 58. This can advantageously provide redundancy for the second drain contact 42-2 in cases where one or more are damaged by the probe tip during the Kelvin sensing test. In addition, a plurality of the second drain contacts 42-2 at various locations can provide easier access during the Kelvin sensing test depending on the orientation of the probe tip. In other embodiments, fewer than all of the device corners, for example, at most three corners, or at most two corners, can include the second drain contact 42-2. In yet further embodiments, the improvement of the Kelvin sensing test may be provided by a single second drain contact 42-2. FIG. 6B is an enlarged view of the corner of the semiconductor device 58 of FIG. 6A. As shown, the second drain contact 42-2 is disposed in the area between the edge termination region 14 and the outer peripheral edge 58' of the semiconductor device 58. In this way, the second drain contact 42-2 may be provided along the non-active portion of the semiconductor device 58 with a small size. By installing the second drain contact 42-2 at the corner of the device, extra surface area may be formed between the curved boundary of the edge termination region 14 and the square corner of the semiconductor device 58.

[0039] FIG. 7 is a top layout view of another semiconductor device 64 having an improved Kelvin sensing structure according to the principles of the present disclosure. The semiconductor device 64 is similar to the semiconductor device 58 of FIG. 6B but includes a different layout with respect to the gate contact pad 60 and the source contact pad 62. As shown, four of the plurality of second drain contacts 42-2 may be provided at each of the non-active corner portions of the semiconductor device 64. As previously explained, one or more of the plurality of second drain contacts 42-2 may be provided at a single corner portion, two corner portions, or three corner portions in other arrangements. In further embodiments, one or more of the plurality of second drain contacts 42-2 may be provided along one or more of the plurality of outer peripheral edges of the semiconductor device 64 that are between corner portions without departing from the principles of the present disclosure.

[0040] FIG. 8 is a top layout view of a semiconductor device 66 that forms a non-rectangular shape and further includes an improved Kelvin sensing structure according to the principles of the present disclosure. As an example, the semiconductor device 66 of FIG. 8 is formed in a hexagonal shape. In this regard, one or more of the plurality of second drain contacts 42-2 may be disposed along one or more of the six vertices or corner portions of the semiconductor device 66. Similar to other embodiments, not all vertices may include the second drain contact 42-2 while still realizing a semiconductor device 66 having improved Kelvin sensing capabilities.

[0041] While embodiments of the present disclosure are provided in the context of an exemplary MOSFET device structure, the principles of the present disclosure are applicable to other device structures, such as, among others, trench MOSFETs, MISFETs, and IGBTs. These other device structures can include wide-bandgap semiconductor devices, such as SiC-based devices, and even further 4H-SiC-based devices. In the case of an IGBT, the source contact as described above can include the emitter contact of the IGBT, and the first and second drain contacts as described above can include the first and second collector contacts of the IGBT. Additionally, while some embodiments of the present disclosure are provided in the context of wafer-level measurement and testing, the disclosed principles are also applicable to the measurement and testing of devices of any form factor, including individual devices after being singulated from a device wafer. For example, individual devices as disclosed herein may be configured to be suitable for resistance measurement improvement, including Kelvin sensing measurement, for known good die characterization, testing on inspection lines, and any other semiconductor die-level characterization.

[0042] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein, may be combined for additional advantages. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments as long as not indicated to the contrary herein.

[0043] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the scope of the appended claims.

Claims

1. A drift region including an active region and a non-active region, wherein the non-active region is disposed along the outer peripheral portion of the active region, the drift region; A first contact on a first side of the drift region; A second contact on a second side of the drift region opposite to the first side of the drift region, the second contact being disposed along the non-active region; A semiconductor device comprising: The non-active region includes a channel stop region at an outer peripheral edge of the drift region, the second contact is on the channel stop region and on a side wall of the outer peripheral edge of the drift region, the semiconductor device.

2. The semiconductor device according to claim 1, wherein the second contact forms a Kelvin sensing contact on the second side of the drift region.

3. The semiconductor device according to claim 1, further comprising a passivation layer on the second side of the drift region, the second contact being accessible through an opening formed in the passivation layer.

4. The non-active region includes an edge termination region between the active region and the outer peripheral edge of the drift region, the second contact being on the channel stop region between the edge termination region and the outer peripheral edge of the drift region, the semiconductor device according to claim 1.

5. The channel stop region is a surface depletion protection region having the same doping type as the doping type of the drift region and a doping concentration higher than the doping concentration of the drift region, The edge termination region is disposed between the active region and the surface depletion protection region, The second contact is on the surface depletion protection region, The semiconductor device according to claim 4.

6. The semiconductor device according to claim 1, wherein the drift region contains silicon carbide (SiC).

7. The semiconductor device according to claim 1, wherein the active region includes a silicon carbide (SiC) metal-oxide-semiconductor field effect transistor (MOSFET).

8. The semiconductor device according to claim 7, wherein the first contact is a first drain contact on the first side of the drift region, and the second contact is a second drain contact on the second side of the drift region.

9. The semiconductor device according to claim 1, wherein the second contact is disposed on the upper surface of the drift region and on the sidewall of the drift region.

10. The semiconductor device according to claim 9, further comprising a substrate, wherein the first contact is disposed on a first side of the substrate, and the second contact is further disposed on a portion of the substrate outside the outer peripheral edge of the drift region or on a portion of the first contact outside the outer peripheral edge of the substrate.

11. The edge termination region forms a ring having a plurality of curved corner portions around the active region, and the second contact is provided between one of the plurality of curved corner portions of the edge termination region and an outer peripheral corner portion of the semiconductor device. The semiconductor device according to claim 4.

12. The semiconductor device according to claim 11, further comprising an additional second contact disposed between another curved corner portion of the edge termination region and another outer peripheral corner portion of the semiconductor device.

13. The semiconductor device according to claim 11, wherein the outer peripheral corner portion of the semiconductor device forms a part of a rectangular shape or a hexagonal shape related to the semiconductor device.

14. The semiconductor device according to claim 1, further comprising a substrate disposed between the drift region and the first contact.

15. The semiconductor device according to claim 1, further comprising a surface depletion region disposed in the non-active region.

16. A step of preparing a semiconductor device including a drift region having an active region and a non-active region; A step of mounting a first side of the semiconductor device on a support structure; A step of measuring characteristics of the semiconductor device using a contact disposed on a second side of the semiconductor device opposite to the first side and disposed in the non-active region; The method comprising: The non-active region includes a channel stop region at an outer peripheral edge of the drift region, the contact is on the channel stop region and on a sidewall of the outer peripheral edge of the drift region.

17. The mounting step includes mounting and electrically connecting the first side of the semiconductor device to the support structure, and the support structure is a conductive support structure. The method according to claim 16, wherein the step of measuring the characteristics includes measuring a Kelvin sense voltage from a second side of the semiconductor device opposite to the first side.

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