Architecture and method for NAND memory operations

Abstract

To provide an apparatus and a method for reducing hot carrier injection (HCI) induced edge sum (ESUM) losses and reducing power consumption during verifying / reading memory cells in a 3D-NAND memory device.SOLUTION: A method includes a pre-verification step of applying a first verify voltage to a gate terminal of a selected memory cell of a first string of memory cells; programming and positioning the selected memory cell between a first adjacent memory cell and a second adjacent memory cell; and applying a first bias voltage to a gate terminal of at least one memory cell of the first string of memory cells that is not to be programmed, and a verification step of applying a second verify voltage to gate terminals of the selected memory cells of the first string of memory cells; and applying a second bias voltage, less than the first bias voltage, to a gate terminal of at least one memory cell in the first string of memory cells that is not to be programmed.SELECTED DRAWING: Figure 10

Description

Background Art

[0001] Flash memory devices have witnessed rapid development in recent years. Flash memory devices can retain stored data over a long period without the application of voltage. Furthermore, the read rate of flash memory devices is relatively high, and it is also easy to erase the stored data and rewrite data to the flash memory devices. For this reason, flash memory devices have been widely used in microcomputers, automatic control systems, and the like. To increase the bit density and reduce the bit cost of flash memory devices, three-dimensional (3D) NAND (Not AND) flash memory devices have been developed.

[0002] 3D-NAND memory devices can include a plurality of memory cell strings. Each of the memory cell strings can include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series. In a method of verifying / reading the memory cells of a programmed 3D-NAND flash memory device, a pre-pulse scheme (or step) and a verification / reading scheme (or step) can be included. In the pre-pulse scheme, a pass voltage such as 6.8 volts can be applied to the word line (WL) of the memory cells in the selected memory cell string, while the gate terminal of the TSG transistor can be turned on in the unselected memory cell strings. In the verification / reading scheme, the pass voltage can be maintained through the verification / reading scheme in the unselected WL of the selected memory cell string, and a verification voltage can be applied to the WL of the selected memory cells in the selected memory cell string.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present disclosure relates generally to embodiments of an apparatus and method for verifying / reading memory cells of a 3D-NAND memory device that reduces the edge sum (ESUM) loss induced by hot carrier injection (HCI) and reduces the power consumption during verification / reading of the memory cells of the 3D-NAND memory device. **Means for Solving the Problem**

[0004] According to an aspect of the present disclosure, a method for reading a memory device is provided. The memory device can include a first memory cell string and a second memory cell string. The first memory cell string can include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series. The second memory cell string can include a BSG transistor, a memory cell, and a TSG transistor connected in series. In the method, in a pre-verification stage, a first verification voltage can be applied to the gate terminal of a selected memory cell of the first memory cell string. The selected memory cell can be programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. In the pre-verification stage, a first bias voltage can be applied to the gate terminal of at least one memory cell of the first memory cell string positioned between the first adjacent memory cell of the selected memory cell and the TSG transistor of the first memory cell string. In the verification stage, a second verification voltage can be applied to the gate terminal of the selected memory cell of the first memory cell string. Further, in the verification stage, a second bias voltage can be applied to the gate terminal of at least one memory cell of the first memory cell string positioned between the first adjacent memory cell of the selected memory cell and the TSG transistor. The second bias voltage is smaller than the first bias voltage.

[0005] In some embodiments, the second bias voltage can be 20% to 30% less than the first bias voltage.

[0006] In the method, during the pre-verification stage, the first gate voltage can be applied to the gate terminal of the TSG transistor of the second memory cell string. The first pass voltage can be applied to the gate terminal of the first adjacent memory cell of the selected memory cell of the first memory cell string. The first read voltage can be applied to the gate terminal of the second adjacent memory cell of the selected memory cell of the first memory cell string. Further, during the verification stage, the second gate voltage can be applied to the gate terminal of the TSG transistor of the second memory cell string. The second pass voltage can be applied to the gate terminal of the first adjacent memory cell of the selected memory cell in the first memory cell string. The second read voltage can be applied to the gate terminal of the second adjacent memory cell of the selected memory cell in the first memory cell string. Further, at least one of the second pass voltage and the second read voltage can be greater than the second gate voltage.

[0007] In the method, the bottom bias voltage can be applied to the gate terminal of the BSG transistor of the first memory cell string during the pre-verification stage and the verification stage. The top bias voltage can be applied to the gate terminal of the TSG transistor of the first memory cell string during the pre-verification stage and the verification stage. During the pre-verification stage and the verification stage, a positive voltage can be applied to the gate terminal of any memory cell positioned between the second adjacent memory cell of the selected memory cell and the BSG transistor of the first memory cell string.

[0008] In some embodiments, the first verification voltage can be less than the second verification voltage.

[0009] In some embodiments, the first bias voltage can be increased from an initial voltage in a first part of the pre-verification stage and then reduced to a second bias voltage, and the first bias voltage can be equal to the second bias voltage in a second part of the pre-verification stage. The first pass voltage can be increased from the initial voltage to a second pass voltage in the pre-verification stage. The first read voltage can be increased from the initial voltage to a second read voltage in the pre-verification stage. The first gate voltage can be increased from the initial voltage to a voltage that is maintained for a certain duration, and then the first gate voltage can be reduced to a second gate voltage in a first part of the pre-verification stage, and the first gate voltage can be equal to the second gate voltage in a second part of the pre-verification stage.

[0010] In some embodiments, the bottom bias voltage can be increased from an initial voltage to a voltage that is maintained through a second part of the pre-verification stage and the verification stage. The top bias voltage can be increased from the initial voltage to a voltage that is maintained through a second part of the pre-verification stage and the verification stage. The positive voltage can be increased from the initial voltage in the pre-verification stage.

[0011] According to another aspect of the present disclosure, a method for reading a memory device is provided. The memory device can include a first memory cell string and a second memory cell string. The first memory cell string can include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series. The second memory cell string can include a BSG transistor, a memory cell, and a TSG transistor connected in series. In the method, in a pre-verification stage, a first verification voltage can be applied to the gate terminal of a selected memory cell of the first memory cell string, and the selected memory cell can be programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. In the pre-verification stage, a first bias voltage can be applied to the gate terminal of at least one memory cell of the first memory cell string positioned between the second adjacent memory cell of the selected memory cell and the BSG transistor of the first memory cell string. In the verification stage, a second verification voltage can be applied to the gate terminal of the selected memory cell of the first memory cell string. Further, in the verification stage, a second bias voltage can be applied to the gate terminal of at least one memory cell of the first memory cell string positioned between the second adjacent memory cell of the selected memory cell and the BSG transistor of the first memory cell string. The second bias voltage can be smaller than the first bias voltage.

[0012] In some embodiments, the second bias voltage can be 20% to 30% smaller than the first bias voltage.

[0013] In the method, in the pre-verification stage, a first gate voltage can be applied to the gate terminal of the TSG transistor of the second memory cell string. A first pass voltage can be applied to the gate terminal of the first adjacent memory cell of the selected memory cell in the first memory cell string. A first read voltage can be applied to the gate terminal of the second adjacent memory cell of the selected memory cell in the first memory cell string. Further, in the verification stage, a second gate voltage can be applied to the gate terminal of the TSG transistor of the second memory cell string. A second pass voltage can be applied to the gate terminal of the first adjacent memory cell of the selected memory cell in the first memory cell string. A second read voltage can be applied to the gate terminal of the second adjacent memory cell of the selected memory cell in the first memory cell string. Further, at least one of the second pass voltage and the second read voltage can be greater than the second gate voltage.

[0014] In the method, a bottom bias voltage can be applied to the gate terminal of the BSG transistor of the first memory cell string in the pre-verification stage and the verification stage. A top bias voltage can be applied to the gate terminal of the TSG transistor of the first memory cell string in the pre-verification stage and the verification stage. A positive voltage can be applied to the gate terminal of any memory cell positioned between the first adjacent memory cell of the selected memory cell and the TSG transistor of the first memory cell string in the pre-verification stage and the verification stage.

[0015] In some embodiments, a first verification voltage can be less than a second verification voltage.

[0016] In some embodiments, a first bias voltage can be increased from an initial voltage in a first portion of a pre-verification stage and then reduced to a second bias voltage. The first bias voltage can be equal to the second bias voltage in a second portion of the pre-verification stage. A first pass voltage can be increased from the initial voltage to a second pass voltage in the pre-verification stage. A first read voltage can be increased from the initial voltage to a second read voltage in the pre-verification stage. A first gate voltage can be increased from the initial voltage to a voltage that is maintained for a certain duration, and then the first gate voltage is reduced to a second gate voltage in a first portion of the pre-verification stage. The first gate voltage can be equal to the second gate voltage in a second portion of the pre-verification stage.

[0017] In some embodiments, a bottom bias voltage can be increased from an initial voltage to a voltage that is maintained through a second portion of a pre-verification stage and a verification stage. A top bias voltage can be increased from the initial voltage to a voltage that is maintained through a second portion of the pre-verification stage and the verification stage. A positive voltage can be increased from the initial voltage in the pre-verification stage.

[0018] According to yet another aspect of the present disclosure, an apparatus for reading a memory device is provided. The memory cell can include a first memory cell string and a second memory cell string. The first memory cell string can include a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series. The second memory cell string can include a BSG transistor, a memory cell, and a TSG transistor connected in series. The apparatus can include a processing circuit configured to apply a first verification voltage to the gate terminal of a selected memory cell of the first memory cell string in a pre-verification stage, and the selected memory cell can be programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. Also, it is possible that the processing circuit is configured to apply a first bias voltage to the gate terminal of at least one memory cell of the first memory cell string that is not programmed in the pre-verification stage. The processing circuit can be configured to apply a second verification voltage to the gate terminal of a selected memory cell of the first memory cell string in a verification stage. Further, the processing circuit can be configured to apply a second bias voltage to the gate terminal of at least one memory cell of the first memory cell string that is not programmed in the verification stage. The second bias voltage can be smaller than the first bias voltage.

[0019] In some embodiments, at least one memory cell of the first memory cell string that receives the first bias voltage and the second bias voltage can be positioned between the first adjacent memory cell of the selected memory cell and the TSG transistor of the first memory cell string.

[0020] In some embodiments, at least one memory cell of a first memory cell string that receives a first bias voltage and a second bias voltage is positioned between a second adjacent memory cell of a selected memory cell and a BSG transistor of the first memory cell string.

[0021] In a pre-verification stage, the processing circuit can be further configured to apply a first gate voltage to a gate terminal of a TSG transistor of a second memory cell string. The processing circuit can be configured to apply a first pass voltage to a gate terminal of a first adjacent memory cell of a selected memory cell in the first memory cell string. The processing circuit can be configured to apply a first read voltage to a gate terminal of a second adjacent memory cell of a selected memory cell in the first memory cell string. In a verification stage, the processing circuit can be configured to apply a second gate voltage to a gate terminal of a TSG transistor of the second memory cell string. Also, the processing circuit can be configured to apply a second pass voltage to a gate terminal of a first adjacent memory cell of a selected memory cell in the first memory cell string. The processing circuit can be configured to apply a second read voltage to a gate terminal of a second adjacent memory cell of a selected memory cell in the first memory cell string, and at least one of the second pass voltage and the second read voltage can be greater than the second gate voltage.

[0022] In an embodiment, the processing circuit can have a bottom bias voltage applied to the gate terminals of the BSG transistors of the first memory cell string in a pre-verification stage and a verification stage. The processing circuit can be configured to apply a top bias voltage to the gate terminals of the TSG transistors of the first memory cell string in a pre-verification stage and a verification stage. The processing circuit can be configured to apply a positive voltage to the gate terminals of any memory cells positioned between the second adjacent memory cell of a selected memory cell and the BSG transistors of the first memory cell string in a pre-verification stage and a verification stage.

[0023] In another embodiment, the processing circuit can be configured to apply a bottom bias voltage to the gate terminals of the BSG transistors of the first memory cell string in a pre-verification stage and a verification stage. The processing circuit can be configured to apply a top bias voltage to the gate terminals of the TSG transistors of the first memory cell string in a pre-verification stage and a verification stage. The processing circuit can be configured to apply a positive voltage to the gate terminals of any memory cells positioned between the first adjacent memory cell of a selected memory cell and the TSG transistors of the first memory cell string in a pre-verification stage and a verification stage.

[0024] Also, an aspect of the present disclosure provides a non-transitory computer-readable storage medium storing instructions that, when executed by a computer to verify / read a memory device, cause the computer to execute one or more of the methods described above.

[0025] Aspects of the present disclosure can be understood from the following detailed description when read in conjunction with the accompanying drawings. Note that various features are not necessarily drawn to scale in accordance with industry standard practice. In fact, the dimensions of various features may be enlarged or reduced for clarity of explanation.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0027] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described later to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above, or on top of, a second feature in the following description may include embodiments in which the first feature and the second feature may be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and / or reference characters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations being described.

[0028] Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to facilitate description of the relationship of one element or feature to another element or feature illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be in a different orientation (rotated 90 degrees, or otherwise), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0029] In related embodiments, a pre-pulse scheme (or stage) and a verify / read scheme (or stage) can be included in a verify / read operation to verify / read memory cells of a programmed 3D-NAND memory device. In the pre-pulse scheme, a pass voltage, such as 6.8 volts, can be applied to a word line (WL) of a memory cell in a selected memory cell string, while a gate terminal of a TSG transistor can be turned on in a non-selected memory cell string. In the verify / read scheme, the pass voltage can be maintained through the verify / read scheme further at a non-selected WL of the selected memory cell string, and a verify voltage can be applied to a WL of a selected memory cell in the selected memory cell string.

[0030] When a sufficient pre-pulse time is applied in the pre-pulse scheme, the pass voltage can be raised high enough prior to the TSG transistor in the non-selected memory cell string being turned off. As a result, when the TSG transistor of the non-selected memory cell string is turned off in the verify / read scheme, although the drain side channel (or terminal) of the non-selected memory cell string is insulated from the bit line coupled to the non-selected memory cell string, a large gradient of the channel potential does not have to be induced by subsequent verify / read voltages in the verify / read scheme. Thus, hot carrier injection (HCI) does not have to be generated from the selected memory cell to the upper memory cell of the selected memory cell in the selected memory cell string. For this reason, an edge sum (ESUM) loss can be prevented. The ESUM loss can be related to the read margin of the 3D-NAND memory device.

[0031] However, when an insufficient pre-pulse time is applied in the pre-pulse scheme, the pass voltage may not be raised high enough prior to the TSG transistor being turned off in the unselected memory cell string. In the verify / read scheme, when the TSG transistor is turned off in the unselected memory cell string, the pass voltage applied to the WL of the memory cell positioned above the selected memory cell in the selected memory cell string can still be raised to a target value such as 6.8 volts. Thus, the drain side channel of the unselected memory cell string can be additionally raised by the increment of the pass voltage in the verify / read scheme, which can cause HCI between the selected memory cell and the upper adjacent memory cell of the selected memory cell, resulting in an ESUM loss.

[0032] In the present disclosure, for verifying / reading the programmed memory cells of a 3D-NAND memory device, in a pre-verify scheme, a pre-pulse voltage can be applied to at least one memory cell of the selected memory cell string positioned above the upper adjacent memory cell of the selected memory cell string. In the verify / read scheme, a pass voltage smaller than the pre-pulse voltage can be applied to at least one memory cell of the selected memory cell string positioned above the upper adjacent memory cell of the selected memory cell. Further, the pass voltage applied to one of the upper adjacent memory cell and the lower adjacent memory cell of the selected memory cell can be greater than the bias voltage applied to the TSG transistor of the unselected memory cell string in the verify / read scheme, and the bias voltage is applied to turn off the TSG transistor of the unselected memory cell string. Therefore, the ESUM loss induced by hot carrier injection (HCI) can be prevented, and the power consumption during verifying / reading the memory cells of the 3D-NAND memory device can be reduced.

[0033] A 3D-NAND device may include a plurality of planes. Each of the planes may include a plurality of blocks. FIG. 1 is an exemplary embodiment of a 3D-NAND device 100 (or device 100). As shown in FIG. 1, device 100 may include plane 102 and plane 104. Each of plane 102 and plane 104 may include two respective blocks. For example, plane 102 may include two blocks 106 and 108, and plane 104 may include two blocks 110 and 112. Further, each of the blocks may include a plurality of memory cell strings in which memory cells are sequentially arranged in series along the height direction of device 100 on a substrate. Of course, FIG. 1 is only an example, and it should be noted that device 100 may include any number of planes, and each of the planes may include any number of blocks depending on the device design.

[0034] In device 100, each of the planes may be coupled to a respective cache structure such as a dynamic data cache (DDC) or a static page buffer (SPB). For example, block 106 may be coupled to cache structure 114, and block 108 may be coupled to cache structure 116. The cache structure may include sense amplifiers configured to detect signals during operations of 3D-NAND device 100 such as verifying / reading, programming, or erasing the memory cells of D-NAND device 100, which are coupled to bit lines. Also, device 100 may include peripheral circuit 122 that may include a decoder structure, a driver structure, a charging structure, and other structures for operating the memory cells.

[0035] In device 100, each of the blocks can include a staircase region and an array region formed in a stack of word line layers and insulating layers. FIG. 2 is an exemplary embodiment of block 106 of device 100. As shown in FIG. 2, block 106 can include an array region 200A and staircase regions 200B-200C disposed in dielectric layer 24. Array region 200A can be disposed between staircase regions 200B-200C and formed in a stack of alternating word line layers 12a-12p and insulating layers 14a-14q on substrate 10. Word line layers 12a-12p can include one or more bottom select gate (BSG) layers, a gate layer (or word line layer), and one or more top select gate (TSG) layers sequentially disposed on substrate 10. For example, word line layer 12a can be a BSG layer, and word line layer 12p can be a TSG layer in device 100.

[0036] In some embodiments, device 100 can include one or more bottom dielectric trenches (e.g., 26 and 28) formed in one or more BSGs (e.g., in word line layer 12a). Bottom dielectric trenches 26 and 28 can extend in the X direction of substrate 10 to separate the BSG into a plurality of sub - BSGs (e.g., 12a - 1, 12a - 2, and 12a - 3). Further, one or more top dielectric trenches (e.g., 30 and 32) can be formed in one or more TSGs (e.g., in word line layer 12p). Top dielectric trenches 30 and 32 can also extend in the X direction of substrate 10 to separate the TSG into a plurality of sub - TSGs (e.g., 12p - 1, 12p - 2, and 12p - 3). The sub - BSGs and sub - TSGs can divide device 100 into a plurality of sub - blocks. Each of the sub - blocks can have its respective sub - BSG and its respective sub - TSG. Thus, the memory cell strings in corresponding sub - blocks can be individually operated by controlling their respective sub - BSGs and their respective sub - TSGs.

[0037] The array region 200A can include a plurality of channel structures 18. Each of the channel structures 18 can include respective top channel contacts 19 and respective bottom channel contacts 21. Each of the channel structures 18 can extend through the stack and be coupled to the word line layers 12a - 12p to form respective vertical NAND memory cell strings. The vertical NAND memory cell strings can include one or more bottom select transistors (BSTs), a plurality of memory cells (MCs), and one or more top select transistors (TSTs) that are sequentially arranged in series on the substrate along the height direction (e.g., Z direction) of the substrate 10. One or more BSTs can be formed from the channel structure and one or more BSG layers, MCs can be formed from the channel structure and the word line layer, and one or more TSTs can be formed from the channel structure and one or more TSG layers.

[0038] In the device 100, each of the memory cells can store one logic bit or multiple logic bits according to the device design. For example, the memory cell can be a single level cell (SLC), a multi - level cell (MLC), or a triple - level cell (TLC). Thus, each of the memory cells can store one logic bit, two logic bits, or three logic bits.

[0039] Still referring to FIG. 2, the word line layers 12a - 12p can be formed in a stepped configuration in the stepped regions 200A - 200B, and a plurality of word line contacts 22 can be formed along the height direction and be coupled to the word line layers 12a - 12p. For this reason, the gate voltage can be applied to the gates of the memory cells via the word line contacts 22 coupled to the word line layers 12a - 12p.

[0040] Furthermore, each of the channel structures can be further coupled to respective bit lines (or bit line structures). In some embodiments, the bit lines are connected to the top channel contacts 19 of the channel structure 18 and can be configured to apply a bias voltage when operating the channel structure, such as programming, erasing, or reading the channel structure. The device 100 can have a plurality of slit structures (or gate line slit structures). For example, two slit structures 20a - 20b are included in FIG. 2. The slit structures 20a - 20b can be made of a conductive material and positioned on the array common source (ACS) region 16 to serve as contacts. The ACS region is formed in the substrate 10 to serve as the common source of the device 100.

[0041] FIG. 3 is a schematic diagram of NAND memory cell strings (or strings) 300A and 300B that can be formed in device 100. As shown in FIG. 3, string 300A includes a bottom select transistor (BST) or bottom select gate (BSG) transistor 302A, a plurality of memory cells (MC) 304A, and a top select transistor (TST) or top select gate (TSG) transistor 306A, which are sequentially arranged in series on the substrate along the height direction (e.g., Z direction) of substrate 10. Similarly, string 300B includes a bottom select transistor (BST) or bottom select gate (BSG) transistor 302B, a plurality of memory cells (MC) 304B, and a top select transistor (TST) or top select gate (TSG) transistor 306B, which are sequentially arranged in series on the substrate along the height direction (e.g., Z direction) of substrate 10. String 300A can be coupled to bit line 308A via the drain terminal of TST 306A and can be coupled to ACS (e.g., 16) via the source terminal of BST 302A. String 300B can be coupled to bit line 308B via the drain terminal of TST 306B and can be coupled to ACS (e.g., 16) via the source terminal of BST 302B. During operation of device 100, appropriate voltages can be applied to bit lines 308A and 308B, to the gates of TSTs 306A and 306B via the lower TSG layer (e.g., 12p-1, 12p-2, and 12p-3), to the gates of MCs 304A and 304B via the WL layer (e.g., 12b~12o), to the gates of BSTs 302A and 302B via the lower BSG layer (e.g., 12a-1, 12a-2, and 12a-3), and further to ACS via a slit structure (e.g., 20a or 20b).

[0042] When a selected memory cell of a 3D-NAND memory device is programmed, a verify / read operation can be applied to verify whether the selected memory cell (e.g., MCn) has been successfully programmed. In the verify / read operation, bias voltages (or pass voltages) can be applied to the gate terminal (or gate) of the TSG transistor through the TSG layer, to the BSG transistor through the BSG layer, and further to the unselected MCs through the WL layer, respectively. A bias voltage such as 6.8 volts may be sufficient to turn on the TSG transistor, the BSG transistor, and the unselected MCs. Further, a read (or verify) voltage can be applied to the gate terminal (or gate) of the selected memory cell MCn through the WL layer (e.g., WLn) coupled to the selected memory cell MCn. The read voltage can be equal to the threshold voltage of the selected memory cell when the selected memory cell is not programmed. When the selected memory cell is programmed, the threshold voltage can be increased. Therefore, when the selected memory cell is successfully programmed, the read voltage cannot turn on the selected memory cell. Accordingly, the sense amplifier cannot detect the current flowing from the ACS region (e.g., 16) to the bit line through the memory cell string. When the selected memory cell is not successfully programmed, the read voltage can turn on the selected memory cell, and the sense amplifier can detect the current flowing from the ACS region (e.g., 16) to the bit line through the memory cell string.

[0043] FIG. 4 is a first schematic diagram of a verify / read operation for verifying / reading memory cells of a 3D-NAND memory device (e.g., device 100) in a related embodiment. As shown in FIG. 4, the verify / read operation can include an initial stage, a pre-pulse stage, a verify / read stage, a post-pulse stage, and a recovery stage. The verify / read operation can be configured to verify whether the memory cells have been successfully programmed by applying appropriate bias voltages to the word line layer of the memory cells, the TSG layer of the TSG transistors, and the BSG layer of the BSG transistors. In the exemplary embodiment of FIG. 4, the memory cells of device 100 can be programmed in a forward order. For this reason, the memory cells in the memory cell string are programmed from the bottom MC adjacent to the BSG transistor to the top MC adjacent to the TSG transistor. For example, in the memory cell string 300A, the memory cells are sequentially programmed from MC0 to the top MC adjacent to the TSG transistor 306A.

[0044] FIG. 4 shows bias voltages applied to two exemplary memory cell strings including a selected memory cell string (e.g., 300A) and a non-selected memory cell string (e.g., 300B). The selected memory cell string can have a selected TSG layer coupled to a TSG transistor (e.g., 306A), a selected word line layer WLn coupled to a selected memory cell (e.g., MCn), a word line layer WLn+1 coupled to a memory cell MCn+1 which is the upper adjacent memory cell of the selected memory cell MCn, a word line layer WLn-1 coupled to a memory cell MCn-1 which is the lower adjacent memory cell of the selected memory cell MCn, a word line layer WL(>n+1) coupled to a non-selected memory cell positioned above the memory cell MCn+1, a word line layer WL(<n-1) coupled to a non-selected memory cell positioned below the memory cell MCn-1, and a BSG layer coupled to a BSG transistor (e.g., 302A). The TSG transistor (or TST) 306A, the memory cell, and the BSG transistor (BST) 302A are connected in series as can be shown in FIG. 3.

[0045] Still referring to FIG. 4, the unselected memory cell string (e.g., 300B) has an unselected TSG layer coupled to a TSG transistor (e.g., 306B), a selected word line layer WLn coupled to the selected memory cell (e.g., MCn), a word line layer WLn+1 coupled to the memory cell MCn+1 which is the upper adjacent memory cell of the selected memory cell MCn, a word line layer WLn-1 coupled to the memory cell MCn-1 which is the lower adjacent memory cell of the selected memory cell MCn, a word line layer WL(>n+1) coupled to an unselected memory cell positioned above the memory cell MCn+1, a word line layer WL(<n-1) coupled to an unselected memory cell positioned below the memory cell MCn-1, and a BSG layer coupled to a BSG transistor (e.g., 302B). As shown in FIG. 3, the TSG transistor (or TST) 306B, the memory cell, and the BSG transistor (or BST) 302B are connected in series.

[0046] In some embodiments, the selected and unselected TSG layers can be one of the lower TSG layers 12p-1, 12p-2, and 12p-3 separated from each other by, for example, top dielectric trenches 30 and 32. In some embodiments, the word line layers in the selected memory cell string and the word line layers in the unselected memory cell string can be the word line layers 12b-12o illustrated in FIG. 2. Thus, the memory cells of the selected memory cell string are coupled to the memory cells at the corresponding positions of the unselected memory cells. For example, the selected memory cell MCn of the selected memory cell string 300A is coupled to the selected memory cell MCn of the unselected memory cell string 300B via the same word line layer.

[0047] When the verification / reading operation is started, at the initial stage of the verification / reading operation shown in FIG. 4, an initial voltage such as 0 volts can be applied to the selected TSG layer, the non-selected TSG layer, WL(>n + 1), WLn+1, WLn, WL(<n - 1), and the BSG layer. Further, in the pre-pulse stage, an appropriate bias voltage can be applied to the selected TSG layer, the non-selected TSG layer, WL(>n + 1), WLn+1, WLn, WL(<n - 1), and the BSG layer respectively. For example, a bias voltage (or top bias voltage) such as 5 volts can be applied to the selected TSG layer of the selected memory cell string. A bias voltage (or gate voltage) such as 5 volts can be applied to the non-selected TSG layer of the non-selected memory cell string. A bias voltage such as 6.8 volts can be applied to WL(>n + 1). A bias voltage (or pass voltage) such as 6.8 volts can be applied to WLn+1. A bias voltage (or verification voltage) such as 6.8 volts can be applied to the selected word line layer WLn. A bias voltage (or read voltage) such as 6.8 volts can be applied to WLn - 1. A bias voltage (or positive voltage) such as 6.8 volts can be applied to WL(<n - 1). Further, a bias voltage (or bottom bias voltage) such as 5 volts can be applied to the BSG layer. The pre-pulse stage can be configured to apply a sufficient bias voltage to form a conductive channel in the selected memory cell string and the non-selected memory cell string respectively.

[0048] When the verification / read operation proceeds to the verification / read stage, the bias voltage (or top bias voltage) applied to the selected TSG layer of the selected memory cell string remains as it is. The bias voltage (or gate voltage) applied to the unselected TSG layer of the unselected memory cell string can be reduced to a lower voltage such as 0 volts so as to turn off the TSG transistor (e.g., 306B) of the unselected memory cell string. Thus, the unselected memory cell string is insulated from the bit line (e.g., 308B). The bias voltage applied to WL(>n+1) can be maintained so as to keep the channel of the selected memory cell string conductive. The bias voltage (or pass voltage) applied to WLn+1 can be increased by, for example, 1 volt from the bias voltage applied in the pre-pulse stage. Further, the bias voltage (or read voltage) applied to WLn-1 can be increased by, for example, 1 volt from the bias voltage applied in the pre-pulse stage. The higher bias voltages applied to WLn+1 and WLn-1 can help form the source / drain regions for the selected memory cell MCn.

[0049] Still referring to FIG. 4, the bias voltage (or verification voltage) applied to the selected word line layer WLn can be reduced to the programming verification (PV) level. In some embodiments, the PV level can be in the range from 0 volts to 1 volt. The bias voltage (or positive voltage) applied to WL(<n-1) can be maintained to keep the channel of the selected memory cell string conductive. Further, the bias voltage (or bottom bias voltage) applied to the BSG layer can be maintained to keep the channel of the selected memory cell string conductive. As described above, the bias voltage (or verification voltage) applied to the selected word line layer WLn can be equal to the threshold voltage of the selected memory cell when the selected memory cell is not programmed. When the selected memory cell is programmed, the threshold voltage can be increased. Therefore, when the selected memory cell is successfully programmed, the read voltage cannot turn on the selected memory cell. Accordingly, the sense amplifier cannot detect the current flowing from the ACS to the bit line through the memory cell string. When the selected memory cell is not successfully programmed, the read voltage can turn on the selected memory cell, and the sense amplifier can detect the current flowing from the ACS to the bit line through the memory cell string.

[0050] In FIG. 4, it should be noted that in the pre-pulse stage, a long pre-pulse time such as in the range from 1 nanosecond to 10 microseconds is applied. When that long pre-pulse time is sufficient for the bias voltage to be sufficiently increased prior to the TSG transistor being turned off in the unselected memory cell string, a large gradient of the channel potential may not be induced by the subsequent verification / read pulse in the verification / read stage. For this reason, hot carrier injection (HCI) may not be generated from the selected memory cell to the upper adjacent memory cell of the selected memory cell in the selected memory cell. However, when that long pre-pulse time is insufficient for the bias voltage in the pre-pulse stage to be sufficiently increased prior to the TSG transistor being turned off in the unselected memory cell string, a large gradient of the channel potential may be induced by the subsequent verification / read pulse in the verification / read stage, and HCI may be generated from the selected memory cell to the upper memory cell of the selected memory cell in the selected memory cell.

[0051] FIG. 5 is a second schematic diagram of a verify / read operation for verifying / reading memory cells of a 3D-NAND memory device (e.g., device 100) that is also programmed in a forward order in a related embodiment. The verify / read operation can have a pre-pulse stage with a short pre-pulse time. The short pre-pulse time may be insufficient for the bias voltages applied to WL(>n + 1), WLn+1, WLn, WLn-1, and WL(<n - 1) to be sufficiently increased during the pre-pulse stage. For example, as shown in FIG. 5, the bias voltage is less than a target value such as 6.8 volts. The bias voltage can still be increased to a target value such as 6.8 volts during the verify / read stage. For this reason, the drain-side channel of the unselected memory cell string can be additionally raised by incrementing the bias voltage during the verify / read stage, which can result in HCI between the selected memory cell (WLn) and the upper adjacent memory cell (WLn+1) of the selected memory cell, resulting in an ESUM loss.

[0052] FIG. 6 is a first schematic diagram of a verify / read operation for verifying / reading memory cells of a 3D-NAND memory device (e.g., device 100) according to an exemplary embodiment of the present disclosure. As shown in FIG. 6, the memory cells can be programmed in a forward order, and the verify / read operation can include a long pre-pulse time in the pre-pulse stage. In the exemplary embodiment of FIG. 6, memory cells MC0 to MCn are programmed, and the memory cells above MCn are not programmed. Further, the memory cell MCn coupled to WLn is selected to receive the verify / read operation.

[0053] Compared with the verification / read operation of FIG. 4, the bias voltage applied to WL(>n + 1) in the verification / read stage is lower than the bias voltage applied to WL(>n + 1) in the pre-pulse stage. In the exemplary embodiment of FIG. 6, the bias voltage applied to WL(>n + 1) in the verification / read stage can be 3 volts, and the bias voltage applied to WL(>n + 1) in the pre-pulse stage can be 6.8 volts. In some embodiments, the bias voltage applied to WL(>n + 1) in the verification / read stage is lower by a certain percentage (e.g., 20% to 30%) than the bias voltage applied to WL(>n + 1) in the pre-pulse stage. In some embodiments, each of the memory cells positioned above the upper adjacent memory cell of the selected memory cell MCn can receive a bias voltage lower than the bias voltage in the pre-pulse stage through WL(>n + 1) in the verification / read stage. In some embodiments, at least one of the memory cells positioned between the upper adjacent memory cell of the selected memory cell MCn and the TSG transistor can receive a bias voltage lower than the bias voltage in the pre-pulse stage through WL(>n + 1) in the verification / read stage. For example, the memory cell adjacent to the TSG transistor can receive a bias voltage lower than the bias voltage in the pre-pulse stage in the verification / read stage.

[0054] By introducing a lower bias voltage in the verification / read stage to the memory cell positioned above the upper adjacent memory cell MCn+1 of the selected memory cell MCn, the gradient of the channel potential of the selected memory cell string can be reduced. Therefore, HCI cannot be generated from the selected memory cell with respect to the upper adjacent memory cell of the selected memory cell in the selected memory cell string. For this reason, ESUM loss can be prevented.

[0055] FIG. 7 is a second schematic diagram of a verify / read operation for verifying / reading memory cells of a 3D-NAND memory device (e.g., device 100) according to an exemplary embodiment of the present disclosure. As shown in FIG. 7, the memory cells can be programmed in a forward order, and the verify / read operation can include a short pre-pulse time in the pre-pulse stage. As shown in FIG. 7, the pre-pulse stage can include a first portion T1 and a second portion T2. Compared with the verify / read operation in FIG. 5, the bias voltage applied in the pre-pulse stage can be increased sufficiently (or reach completely) to the target value in FIG. 7. For example, the bias voltage applied to WL(>n + 1) can be increased sufficiently in the pre-pulse stage. As shown in FIG. 7, the bias voltage applied to WL(>n + 1) can be increased from an initial voltage to the target value in the first portion of the pre-pulse stage. The target value can be, for example, 6.8 volts. Thereafter, the bias voltage can be reduced to a lower value (e.g., 3 volts) equal to the bias voltage of the verify / read stage in the first portion of the pre-verify stage. The bias voltage is further maintained in the second portion of the pre-verify stage.

[0056] Still referring to FIG. 7, in the pre-verification stage, the pass voltage applied to WLn+1 can be increased from the initial voltage to a target value (e.g., 7.8 volts), and the target value is equal to the pass voltage in the verification / reading stage. In the pre-verification stage, the reading voltage applied to WLn-1 can be increased from the initial voltage to a target value (e.g., 7.8 volts), and the target value is equal to the reading voltage in the verification / reading stage. In the first part of the pre-pulse stage, the gate voltage applied to the non-selected TSG can be increased from the initial voltage to a target value (e.g., 5 volts). Then, the gate voltage is maintained for a certain duration, and then, in the first part of the pre-verification stage, it can be reduced to a value equal to the gate voltage in the verification / reading stage. The gate voltage can be maintained equal to the gate voltage in the verification / reading stage in the second part of the pre-verification stage.

[0057] In the first part of the pre-pulse stage, the bottom bias voltage applied to the BSG transistor can be increased from the initial voltage to a target value (e.g., 5 volts), and the target value is equal to the bottom bias voltage in the verification / reading stage. The bottom bias voltage can be maintained through the second part of the pre-verification stage and the verification stage. Similarly, in the first part of the pre-pulse stage, the top bias voltage applied to the selected TSG transistor can be increased from the initial voltage to a target value (e.g., 5 volts). The top bias voltage can be further maintained through the second part of the pre-verification stage and the verification stage. In the pre-pulse stage, the positive voltage applied to WL(<n-1) can be increased from the initial voltage in the pre-verification stage to a target value (e.g., 6.8 volts), and the target value is equal to the positive voltage applied in the verification / reading stage.

[0058] In the verification / read operation in FIG. 7, the bias voltage applied to WL(>n + 1) in the verification / read stage can be lower than the bias voltage applied to WL(>n + 1) in the pre-pulse stage. In the exemplary embodiment of FIG. 7, the bias voltage applied to WL(>n + 1) in the verification / read stage can be 3 volts, and the bias voltage applied to WL(>n + 1) in the pre-pulse stage can be 6.8 volts. In some embodiments, each of the memory cells positioned above the upper adjacent memory cell MCn+1 of the selected memory cell MCn can receive a bias voltage lower than the bias voltage in the pre-pulse stage through WL(>n + 1) in the verification / read stage. In some embodiments, at least one of the memory cells positioned between the upper adjacent memory cell MCn+1 of the selected memory cell MCn and the TSG transistor can receive a bias voltage lower than the bias voltage in the pre-pulse stage through WL(>n + 1) in the verification / read stage. For example, the memory cell adjacent to the TSG transistor can receive a bias voltage lower than the bias voltage in the pre-pulse stage in the verification / read stage.

[0059] Furthermore, in the verification / read operation of FIG. 7, at least one of the upper adjacent memory cell MCn+1 and the lower adjacent memory cell MCn−1 of the selected memory cell MCn can receive a bias voltage higher than the bias voltage applied to the non-selected TSG transistor in the verification / read stage.

[0060] Compared with the verification / read operation of FIG. 5, the bias voltage applied in the pre-pulse stage of the verification / read operation in FIG. 7 is sufficiently increased to the target value. Further, for the memory cell positioned above the upper adjacent memory cell of the selected memory cell MCn, a lower bias voltage is introduced in the verification / read stage. Accordingly, the gradient of the channel potential of the selected memory cell string can be reduced, and the formation of HCI from the selected memory cell to the upper adjacent memory cell of the selected memory cell in the selected memory cell string can be prevented. For this reason, the ESUM loss can be prevented.

[0061] FIG. 8 is a first schematic diagram of a verification / read operation for verifying / reading memory cells programmed in a reverse order according to an exemplary embodiment of the present disclosure. As shown in FIG. 8, the memory cells can be programmed in a reverse order in that the memory cells are programmed from the top memory cell adjacent to the TSG transistor to the bottom memory cell (e.g., MC0) adjacent to the BSG transistor. In the exemplary embodiment of FIG. 8, the selected memory cell MCn and the memory cell above the selected memory cell MCn are programmed. Further, the pre-pulse stage of the verification / read operation in FIG. 8 can have a long pre-pulse time.

[0062] As shown in FIG. 8, compared to the verify / read operation shown in FIG. 6 that verifies / reads memory cells programmed in a forward order, the bias voltage applied to WL(<n-1) in the verify / read stage is lower than the bias voltage applied to WL(<n-1) in the pre-pulse stage. In some embodiments, each of the memory cells positioned between the lower adjacent memory cell MCn-1 of the selected memory cell MCn and the BSG transistor can receive, through WL(<n-1), a bias voltage lower than the bias voltage in the pre-pulse stage in the verify / read stage. In some embodiments, at least one of the memory cells positioned between the lower adjacent memory cell MCn-1 of the selected memory cell MCn and the BSG transistor can receive, through WL(<n-1), a bias voltage lower than the bias voltage in the pre-pulse stage in the verify / read stage. For example, the memory cell adjacent to the BSG transistor can receive a bias voltage lower than the bias voltage in the pre-pulse stage in the verify / read stage.

[0063] FIG. 9 is a second schematic diagram of a verify / read operation for verifying a memory cell programmed in a reverse order according to an exemplary embodiment of the present disclosure. Compared to the verify / read operation shown in FIG. 7 for verifying a memory cell programmed in a forward order, the bias voltage applied to WL(<n-1) in the verify / read stage is lower than the bias voltage applied to WL(<n-1) in the pre-pulse stage. In some embodiments, each of the memory cells positioned below the lower adjacent memory cell MCn-1 of the selected memory cell MCn is capable of receiving, through WL(<n-1), a bias voltage lower than the bias voltage in the pre-pulse stage in the verify / read stage. In some embodiments, at least one of the memory cells positioned between the lower adjacent memory cell MCn-1 of the selected memory cell MCn and the BSG transistor is capable of receiving, through WL(<n-1), a bias voltage lower than the bias voltage in the pre-pulse stage in the verify / read stage. For example, the memory cell adjacent to the BSG transistor is capable of receiving a bias voltage lower than the bias voltage in the pre-pulse stage in the verify / read stage.

[0064] Similar to the verify / read operations shown in FIGS. 6 and 7, the verify / read operations shown in FIGS. 8 and 9 include a bias voltage that can be sufficiently increased in the pre-pulse stage. Further, the bias voltage applied to at least one of the memory cells not programmed in the pre-pulse stage can be lower than the bias voltage applied in the verify / read stage. Thus, the gradient of the channel potential of the selected memory cell string can be reduced, and the formation of HCI from the selected memory cell MCn to the lower adjacent memory cell MCn-1 of the selected memory cell in the selected memory cell string can be prevented. For this reason, the ESUM loss can be prevented.

[0065] FIG. 10 is a flowchart of a method 1000 for reading a memory device including a first memory cell string and a second memory cell string. The first memory cell string can include bottom select gate (BSG) transistors, memory cells, and top select gate (TSG) transistors connected in series. The second memory cell string can include BSG transistors, memory cells, and TSG transistors connected in series. As shown in FIG. 10, method 1000 can start at S1002 and proceed to S1004, where a first verification voltage can be applied to the gate terminal of a selected memory cell of the first memory cell string in a pre-verification stage. The selected memory cell can be programmed and arranged between a first adjacent memory cell and a second adjacent memory cell.

[0066] At S1004, in the pre-verification stage, a first bias voltage can be applied to the gate terminal of at least one memory cell of the first memory cell string that is not programmed.

[0067] At S1006, in the verification stage, a second verification voltage can be applied to the gate terminal of the selected memory cell of the first memory cell string.

[0068] At S1008 of method 1000, in the verification stage, a second bias voltage can be applied to the gate terminal of at least one memory cell of the first memory cell string that is not programmed, and the second bias voltage is smaller than the first bias voltage.

[0069] In some embodiments, at least one memory cell of the first memory cell string that receives the first bias voltage and the second bias voltage can be positioned between the first adjacent memory cell of the selected memory cell and the TSG transistor of the first memory cell string.

[0070] In some embodiments, at least one memory cell of a first memory cell string that receives a first bias voltage and a second bias voltage can be positioned between a second adjacent memory cell of a selected memory cell and a BSG transistor of the first memory cell string.

[0071] In method 1000, during a pre-verification stage, a first gate voltage can be applied to the gate terminal of a TSG transistor of a second memory cell string. A first pass voltage can be applied to the gate terminal of a first adjacent memory cell of a selected memory cell in a first memory cell string. A first read voltage can be applied to the gate terminal of a second adjacent memory cell of a selected memory cell in a first memory cell string. Further, during a verification stage, a second gate voltage can be applied to the gate terminal of a TSG transistor of a second memory cell string. A second pass voltage can be applied to the gate terminal of a first adjacent memory cell of a selected memory cell in a first memory cell string. A second read voltage can be applied to the gate terminal of a second adjacent memory cell of a selected memory cell in a first memory cell string. Further, at least one of the second pass voltage and the second read voltage can be greater than the second gate voltage.

[0072] FIG. 11 is a simplified block diagram of a memory device 1001 in which various embodiments of the present disclosure may be implemented. The memory device 1001 can include a memory array 1004 arranged in rows and columns. The memory array 1004 can include memory cells (e.g., MC304 in FIG. 3) formed based on a plurality of channel structures (e.g., channel structure 18 in FIG. 2). The channel structure can be formed in a stack of alternating word line layers (e.g., 12 in FIG. 2) and insulating layers (e.g., 14 in FIG. 2). A row decoding circuit 1008 and a column decoding circuit 1010 are provided to decode address signals supplied to the memory device 1001. The address signals are received and decoded to access the memory array 1004. Also, the memory device 1001 can include an input / output (I / O) control circuit to manage the input of commands, addresses, and data to the memory device 1001, and the output of data and status information from the memory device 1001. An address register 1014 is coupled between the I / O control circuit and the row decoding circuit 1008 and the column decoding circuit 1010 to latch the address signal prior to decoding. A command register 1024 is coupled between the I / O control circuit 1012 and the control logic 1016 to latch the incoming commands.

[0073] The control logic 1016 can control access to the memory array 1004 in response to commands and generate status information regarding the external processor 1030. The control logic 1016 is coupled to the row decode circuit 1008 and the column decode circuit 1010 to control the row decode circuit 1008 and the column decode circuit 1010 in response to an address. For example, a bias voltage can be applied to a selected memory cell via the row decode circuit 1008 and the column decode circuit 1010 by the control logic 1016 to operate the selected memory cell, such as reading the memory cell, writing to the memory cell, or erasing the memory cell. Also, the control logic 1016 can be coupled to the sense amplifier and latch circuit 1018 to control the sense amplifier and latch circuit 1018 in response to a command and to generate status information regarding the external processor 1030. The sense amplifier and latch circuit 1018 can be coupled to the memory array 1004 and can latch incoming or outgoing data in the form of an analog voltage level. The sense amplifier and latch circuit 1018 can be configured to read the signal of the memory cell when the memory cell is being operated on.

[0074] Still referring to FIG. 11, a status register 1022 can be coupled between the I / O control circuit 1012 and the control logic 1016 to latch status information regarding the output to the external processor 1030. The memory device 1001 receives control signals at the control logic 1016 on the control link 1032. The control signals can include a chip enable CE#, a command latch enable CLE, an address latch enable ALE, and a write enable WE#. The memory device 1001 can receive a command in the form of a command signal, an address in the form of an address signal, and data in the form of a data signal from the external processor via the multiplexed input / output (I / O) bus 1034, and output data to the external processor via the I / O bus 1034.

[0075] The various embodiments described herein provide several advantages over the methods in related examples for verifying / reading memory cells of a programmed 3D-NAND memory device. In related examples, it is possible for hot carrier injection (HCI) to be generated between a selected memory cell and one of the adjacent memory cells of the selected memory cell, resulting in an edge sum (ESUM) loss. In the present disclosure, it is possible to prevent the edge sum (ESUM) loss induced by hot carrier injection (HCI), and it is possible to reduce the power consumption during verification / reading of memory cells of a 3D-NAND memory device.

[0076] The above outlines the features of some embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will recognize that they may immediately use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments outlined herein. Also, those skilled in the art will understand that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Description of Reference Numerals

[0077] 10 Substrate 12a, 12b, 12c, 12d, 12e, 12f, 12g, 12h, 12i, 12j, 12k, 12l, 12m, 12n, 12o, 12p Word line (WL) layer 12a-1, 12a-2, 12a-3 Lower BSG, lower BSG layer 12p-1, 12p-2, 12p-3 Lower TSG, lower TSG layer 14a, 14b, 14c, 14d, 14e, 14f, 14g, 14h, 14i, 14j, 14k, 14l, 14m, 14n, 14o, 14p, 14q Insulating layer 16 Array common source region 18-channel structure 19 top-channel contact 20a, 20b slit structure 21 bottom-channel contact 22 word-line contact 24 dielectric layer 26, 28 dielectric trench 30, 32 top dielectric trench 100 3D-NAND device 102, 104 plane 106, 108, 110, 112 block 114, 116 cache structure 122 peripheral circuit 200A array region, staircase region 200B, 200C staircase region 300A, 300B memory cell string 302A bottom select transistor (BST), bottom select gate (BSG) transistor 302B bottom select transistor (BST), bottom select gate (BSG) transistor 304A, 304B memory cell (MC) 306A top select transistor (TST), top select gate (TSG) transistor 306B top select transistor (TST), top select gate (TSG) transistor 308A, 308B bit line 1001 memory device 1004 memory array 1008 row decode circuit 1010 column decode circuit 1012 I / O control circuit 1014 address register 1016 control logic 1018 sense amplifier and latch circuit 1022 status register 1024 command register 1030 processor 1032 Control Link 1034 Input / Output (I / O) Bus

Claims

1. 1. A memory device comprising: a first memory cell string including a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series, the memory cells including a selected memory cell and an unselected memory cell, the unselected memory cell including a first adjacent memory cell, a second adjacent memory cell, and a third memory cell, the first adjacent memory cell and the second adjacent memory cell being adjacent to the selected memory cell, and the selected memory cell being programmed and positioned between the first adjacent memory cell and the second adjacent memory cell; word lines respectively coupled to the memory cells; a processing circuit coupled to the word line, applying a first verify voltage to a selected word line to which the selected memory cell is coupled during a pre-verify phase; applying a first bias voltage to a first word line to which the third memory cell is coupled during the pre-verification stage; applying a second verify voltage to the selected word line during a verify phase; applying a first pass voltage to a second word line to which the second adjacent memory cell is coupled during the verify phase; applying a second pass voltage to a third word line to which the first adjacent memory cell is coupled during the verify phase; A second bias voltage is applied to the first word line during the verify step. A processing circuit configured to Including, The memory device, wherein the second bias voltage is less than the first bias voltage, and at least one of the first pass voltage and the second pass voltage is greater than the second bias voltage.

2. 2. The memory device of claim 1, wherein the second bias voltage is 20% to 30% less than the first bias voltage.

3. The memory device of claim 1 , wherein the second bias voltage is less than or equal to 3 volts.

4. 2. The memory device of claim 1, wherein at least one of the first pass voltage and the second pass voltage is greater than the first bias voltage.

5. The memory device of claim 1 , wherein the first verify voltage is greater than the second verify voltage.

6. a second string of memory cells including a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series; The processing circuitry comprises: applying a first gate voltage to a gate terminal of the TSG transistor of the second memory cell string during the pre-verification stage; applying a third pass voltage to a third word line to which the first neighboring memory cell is coupled during the pre-verification stage; applying a fourth pass voltage to a second word line to which the second adjacent memory cell is coupled during the pre-verification stage; applying a bottom bias voltage to gate terminals of the BSG transistors of the first memory cell string during the pre-verification and verification steps; applying a top bias voltage to gate terminals of the TSG transistors of the first memory cell string during the pre-verification and verification stages; applying a second gate voltage to the gate terminal of the TSG transistor of the second memory cell string during the verify phase; The method further comprises:

2. The memory device of claim 1, wherein at least one of the first pass voltage and the second pass voltage is greater than the second gate voltage.

7. 7. The memory device of claim 6, wherein the voltage applied to the first word line is increased from an initial voltage during a first portion of the pre-verification phase, then reduced to the second bias voltage, and equal to the second bias voltage during a second portion of the pre-verification phase.

8. the third pass voltage is increased from the initial voltage to the second pass voltage in the pre-verification stage; the fourth pass voltage is increased from the initial voltage to the first pass voltage in the pre-verification stage; The memory device of claim 7.

9. the first adjacent memory cell is disposed between the TSG transistor and the selected memory cell of the first memory cell string; the third memory cell is positioned between the first adjacent memory cell and the TSG transistor of the first memory cell string; The memory device of claim 8.

10. The processing circuitry includes: During the pre-verification and verification steps, a positive voltage is applied to a fourth word line to which a fourth memory cell is coupled, the fourth memory cell being positioned between the second adjacent memory cell and the BSG transistor of the first string of memory cells. The memory device of claim 9 further configured to:

11. the second adjacent memory cell is disposed between the BSG transistor and the selected memory cell of the first memory cell string; the third memory cell is disposed between the second adjacent memory cell and the BSG transistor of the first memory cell string; The memory device of claim 8.

12. The processing circuitry includes: During the pre-verification and verification steps, a positive voltage is applied to a fourth word line to which a fourth memory cell is coupled, the fourth memory cell being positioned between the second adjacent memory cell and the TSG transistor of the first string of memory cells. The memory device of claim 11 further configured as follows:

13. the bottom bias voltage is increased from the initial voltage to a voltage that is maintained throughout the second portion of the pre-verification phase and the verification phase; the top bias voltage is increased from the initial voltage to a voltage which is maintained throughout the second portion of the pre-verification phase and the verification phase; The memory device of claim 8.

14. 1. A method of operating a memory device, comprising: a first string of memory cells including a bottom select gate (BSG) transistor, memory cells (MCs), and a top select gate (TSG) transistor connected in series, the memory cells including a selected memory cell and an unselected memory cell, the unselected memory cell including a first adjacent memory cell, a second adjacent memory cell, and a third memory cell, the first adjacent memory cell and the second adjacent memory cell being adjacent to the selected memory cell, and the selected memory cell is programmed and positioned between the first adjacent memory cell and the second adjacent memory cell, applying a first verify bias voltage to a selected word line to which the selected memory cell is coupled during a pre-verify phase; applying a first bias voltage to a first word line to which the third memory cell is coupled during the pre-verification phase; applying a second verify voltage to the selected word line during a verify phase; applying a first pass voltage to a second word line to which the second adjacent memory cell is coupled during the verify phase; applying a second pass voltage to a third word line to which the first adjacent memory cell is coupled during the verify phase; applying a second bias voltage to the first word line during the verify phase; Including, The method, wherein the second bias voltage is less than the first bias voltage, and at least one of the first pass voltage and the second pass voltage is greater than the second bias voltage.

15. 15. The method of claim 14, wherein the second bias voltage is 20% to 30% less than the first bias voltage.

16. The method of claim 14 , wherein the second bias voltage is less than or equal to 3 volts.

17. The method of claim 14 , wherein at least one of the first pass voltage and the second pass voltage is greater than the first bias voltage.

18. the first adjacent memory cell is disposed between the TSG transistor and the selected memory cell of the first memory cell string; the third memory cell is positioned between the first adjacent memory cell and the TSG transistor of the first memory cell string; The method of claim 14.

19. the second adjacent memory cell is disposed between the BSG transistor and the selected memory cell of the first memory cell string; the third memory cell is positioned between the second adjacent memory cell and the BSG transistor of the first memory cell string; The method of claim 14.

20. 1. An electronic system comprising:

1. A memory device comprising: a first memory cell string including a bottom select gate (BSG) transistor, a memory cell, and a top select gate (TSG) transistor connected in series, the memory cells including a selected memory cell and an unselected memory cell, the unselected memory cell including a first adjacent memory cell, a second adjacent memory cell, and a third memory cell, the first adjacent memory cell and the second adjacent memory cell being adjacent to the selected memory cell, and the selected memory cell being programmed and positioned between the first adjacent memory cell and the second adjacent memory cell; word lines respectively coupled to the memory cells; a processing circuit coupled to the word line, applying a first verify voltage to a selected word line to which the selected memory cell is coupled during a pre-verify phase; applying a first bias voltage to a first word line to which the third memory cell is coupled during the pre-verification stage; applying a second verify voltage to the selected word line during a verify phase; applying a first pass voltage to a second word line to which the second adjacent memory cell is coupled during the verify phase; applying a second pass voltage to a third word line to which the first adjacent memory cell is coupled during the verify phase; A second bias voltage is applied to the first word line during the verify step. A processing circuit configured to Including, a memory device, the second bias voltage being less than the first bias voltage, and at least one of the first pass voltage and the second pass voltage being greater than the second bias voltage; a processor coupled to the memory device and configured to send commands to the memory device; 2. An electronic system comprising:

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