Semiconductor device

Abstract

To provide a highly reliable semiconductor device which prevents yield deterioration caused by ESD damage.SOLUTION: A semiconductor device has: a gate electrode layer; a gate insulation layer on the gate electrode layer; an oxide insulation layer on the gate insulation layer; an oxide semiconductor layer which contacts a surface of the oxide insulation layer and overlaps the gate electrode layer; and a source electrode layer and a drain electrode layer which are electrically connected with the oxide semiconductor layer. The gate insulation layer is composed to include a nitrogen-containing silicon film; and the oxide insulation layer contains one or a plurality of metal elements selected from constituent elements of the oxide semiconductor layer; and a film thickness of the gate insulation layer is thicker than that of the oxide insulation layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The invention disclosed in this specification and the like relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices are all semiconductor devices. There is.

Background Art

[0003] Techniques for constructing transistors using semiconductor thin films formed on substrates having insulating surfaces have drawn attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials. For example, techniques for manufacturing transistors using zinc oxide or an In-Ga-Zn-based oxide semiconductor as the oxide semiconductor have been disclosed (see Patent Document 1 and Patent Document 2).

[0004]

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the case of mass-producing semiconductor devices using oxide semiconductors (hereinafter abbreviated as mass production), Considering the development cost and development speed, the amorphous Transistor configuration using silicon-based semiconductor materials such as silicon and polycrystalline silicon. It is desirable to utilize process conditions or production equipment, etc.

[0007] However, the carrier generation mechanism of oxide semiconductors is significantly different from that of silicon-based semiconductor materials. The physical properties of oxide semiconductors greatly affect the characteristics and reliability of transistors. It has a significant impact.

[0008] In particular, the gate insulating layer used for silicon-based semiconductor materials is now applicable to oxide semiconductors. In order to achieve this, the interface characteristics with the oxide semiconductor are not sufficiently satisfied. There is a need for a gate insulating layer suitable for semiconductor devices using conductors.

[0009] In addition, transistors using silicon-based semiconductor materials such as amorphous silicon and polycrystalline silicon are being developed. Semiconductor devices composed of 8th generation (2160mm wide x 2460mm long) and above Since it can be used on glass substrates, it has the advantage of high productivity and low cost. When a glass substrate is used, it has high insulation properties and a large surface area, so it is difficult to prevent static electricity. The problem of damage caused by ESD (Electro-Static Discharge) is particularly serious. This problem naturally needs to be taken into consideration when using an oxide semiconductor material.

[0010] In light of the above technical background, one aspect of the present invention is to provide a method for manufacturing a semiconductor device using mass production technology that has been put into practical use. There is little change in the transistor configuration, process conditions, or production equipment, and the like, so the semiconductor device is stable. Another object of the present invention is to provide a highly reliable semiconductor device by imparting good electrical characteristics.

[0011] Another embodiment of the present invention is a semiconductor device that can prevent a decrease in yield due to electrostatic damage. One of the objectives is to provide the following. [Means for solving the problem]

[0012] One embodiment of the disclosed invention is a method for forming a gate electrode layer and an oxide semiconductor layer, the method comprising: a silicon film containing nitrogen and one or more metals selected from the constituent elements of the oxide semiconductor layer; The semiconductor device has a stacked structure including an oxide insulating layer containing an element.

[0013] The silicon film containing nitrogen has a higher dielectric constant than the silicon oxide film, so it has the same capacitance. Therefore, the thickness of the film required to obtain the desired amount of nitrogen is increased. By forming an insulating layer, the gate insulating layer can be physically thickened, which increases the dielectric strength. It is possible to suppress the decrease in the dielectric strength and preferably to improve the dielectric strength. Therefore, electrostatic breakdown of a semiconductor device including a thin insulating layer can be suppressed.

[0014] The thickness of the nitrogen-containing silicon film is preferably 325 nm or more and 550 nm or less. It is more preferable that the thickness is 355 nm or more and 550 nm or less. As the insulating film, a silicon nitride film can be preferably used.

[0015] The nitrogen-containing silicon film is a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon. Since it is also used as a gate insulating layer for semiconductor materials, the process conditions and production equipment can be easily diverted. Therefore, by applying a silicon film containing nitrogen to the gate insulating layer, it is possible to form an oxide semiconductor. It becomes possible to mass-produce transistors using a conductor at low cost.

[0016] Further, by providing an oxide insulating layer of one or more metal elements selected from the constituent elements of the oxide semiconductor layer in contact with the oxide semiconductor layer, the interface between the oxide insulating layer and the oxide semiconductor layer can be kept in a good state and interface deterioration can be prevented. In particular, by suppressing the capture of carriers at the interface between the oxide insulating layer and the oxide semiconductor layer, light deterioration (for example, photo negative bias deterioration) of the transistor can be reduced, and a highly reliable transistor can be obtained. of the metal element, it is possible to keep the state of the interface between the oxide insulating layer and the oxide semiconductor layer good and prevent interface deterioration. In particular, by suppressing the capture of carriers at the interface between the oxide insulating layer and the oxide semiconductor layer, light deterioration (for example, photo negative bias deterioration) of the transistor can be reduced, and a highly reliable transistor can be obtained. That is, according to one aspect of the present invention, while partially utilizing the mass production technology of silicon-based semiconductor materials that have been put into practical use, a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and an oxide semiconductor layer are laminated. By adopting a structure including a structure, it is possible to provide a semiconductor device that exhibits a novel effect different from a semiconductor device using a silicon-based semiconductor material. Specifically, for example, the following configuration can be adopted. bias deterioration) can be reduced, and a highly reliable transistor can be obtained. That is, according to one aspect of the present invention, while partially utilizing the mass production technology of silicon-based semiconductor materials that have been put into practical use, a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and an oxide semiconductor layer are laminated. By adopting a structure including a structure, it is possible to provide a semiconductor device that exhibits a novel effect different from a semiconductor device using a silicon-based semiconductor material. Specifically, for example, the following configuration can be adopted.

[0017] That is, according to one aspect of the present invention, while partially utilizing the mass production technology of silicon-based semiconductor materials that have been put into practical use, a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and an oxide semiconductor layer are laminated. By adopting a structure including a structure, it is possible to provide a semiconductor device that exhibits a novel effect different from a semiconductor device using a silicon-based semiconductor material. Specifically, for example, the following configuration can be adopted. By adopting a structure including a laminated structure of a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and an oxide semiconductor layer, while partially utilizing the mass production technology of silicon-based semiconductor materials that have been put into practical use, a semiconductor device having a novel effect different from that of a semiconductor device using a silicon-based semiconductor material can be provided. Specifically, for example, the following configuration can be adopted. By adopting a structure including a laminated structure of a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and an oxide semiconductor layer, while partially utilizing the mass production technology of silicon-based semiconductor materials that have been put into practical use, a semiconductor device having a novel effect different from that of a semiconductor device using a silicon-based semiconductor material can be provided. Specifically, for example, the following configuration can be adopted. By adopting a structure including a laminated structure of a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and an oxide semiconductor layer, while partially utilizing the mass production technology of silicon-based semiconductor materials that have been put into practical use, a semiconductor device having a novel effect different from that of a semiconductor device using a silicon-based semiconductor material can be provided. Specifically, for example, the following configuration can be adopted. That is, according to one aspect of the present invention, while partially utilizing the mass production technology of silicon-based semiconductor materials that have been put into practical use, a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and an oxide semiconductor layer are laminated. By adopting a structure including a structure, it is possible to provide a semiconductor device that exhibits a novel effect different from a semiconductor device using a silicon-based semiconductor material. Specifically, for example, the following configuration can be adopted. That is, according to one aspect of the present invention, while partially utilizing the mass production technology of silicon-based semiconductor materials that have been put into practical use, a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and an oxide semiconductor layer are laminated. By adopting a structure including a structure, it is possible to provide a semiconductor device that exhibits a novel effect different from a semiconductor device using a silicon-based semiconductor material. Specifically, for example, the following configuration can be adopted.

[0018] One aspect of the present invention has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide insulating layer on the gate insulating layer, an oxide semiconductor layer in contact with the oxide insulating layer and overlapping the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer is composed of a silicon film containing nitrogen, the oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and the thickness of the gate insulating layer is thicker than that of the oxide insulating layer. It is a semiconductor device. One aspect of the present invention has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide insulating layer on the gate insulating layer, an oxide semiconductor layer in contact with the oxide insulating layer and overlapping the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer is composed of a silicon film containing nitrogen, the oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and the thickness of the gate insulating layer is thicker than that of the oxide insulating layer. It is a semiconductor device. One aspect of the present invention has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide insulating layer on the gate insulating layer, an oxide semiconductor layer in contact with the oxide insulating layer and overlapping the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer is composed of a silicon film containing nitrogen, the oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and the thickness of the gate insulating layer is thicker than that of the oxide insulating layer. It is a semiconductor device. One aspect of the present invention has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide insulating layer on the gate insulating layer, an oxide semiconductor layer in contact with the oxide insulating layer and overlapping the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer is composed of a silicon film containing nitrogen, the oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and the thickness of the gate insulating layer is thicker than that of the oxide insulating layer. It is a semiconductor device. One aspect of the present invention has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide insulating layer on the gate insulating layer, an oxide semiconductor layer in contact with the oxide insulating layer and overlapping the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer is composed of a silicon film containing nitrogen, the oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and the thickness of the gate insulating layer is thicker than that of the oxide insulating layer. It is a semiconductor device. One aspect of the present invention has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide insulating layer on the gate insulating layer, an oxide semiconductor layer in contact with the oxide insulating layer and overlapping the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer is composed of a silicon film containing nitrogen, the oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer, and the thickness of the gate insulating layer is thicker than that of the oxide insulating layer. It is a semiconductor device.

[0019] In the above semiconductor device, it is preferable that the ends of the oxide semiconductor layer and the oxide insulating layer coincide. In this specification and the like, coincidence includes approximate coincidence. For example the ends of layer A and layer B of a stacked structure etched using the same mask are considered to coincide .

[0020] In addition to the stacked structure of an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer and a silicon nitride film provided in contact with the lower layer of the oxide semiconductor layer the stacked structure may be provided in contact with the upper layer of the oxide semiconductor layer. By adopting such a configuration stable electrical characteristics can be imparted to the semiconductor device and / or electrostatic breakdown of the semiconductor device can be further prevented .

[0021] That is, another aspect of the present invention is a semiconductor device having a gate electrode layer, a gate insulating layer on the gate electrode layer , a first oxide insulating layer on the gate insulating layer, an oxide semiconductor layer in contact with and overlapping the first oxide insulating layer and the gate electrode layer , a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer , a second oxide insulating layer covering the source electrode layer and the drain electrode layer and in contact with a part of the oxide semiconductor layer , and a protective insulating layer on the second oxide insulating layer, wherein the gate insulating layer and the protective insulating layer are formed including a silicon nitride film , the first oxide insulating layer and the second oxide insulating layer contain one or more metal elements selected from the constituent elements of the oxide semiconductor layer , the film thickness of the gate insulating layer is thicker than the film thickness of the first oxide insulating layer, and the film thickness of the protective insulating layer is thicker than the film thickness of the second oxide insulating layer .

[0022] Also, in the above semiconductor device, it is preferable that the ends of the oxide semiconductor layer and the first oxide insulating layer coincide​​​ is preferably achieved.

[0023] Further, in any one of the above semiconductor devices, the film thickness of the gate insulating layer is 325 nm or more and preferably 550 nm or less. Further, as the gate insulating layer, a silicon nitride film is preferably applied.

[0024] Further, the oxide insulating layer in contact with the oxide semiconductor layer preferably contains a region with more oxygen than the stoichiometric composition (hereinafter referred to as the oxygen-excess region). By the oxide insulating layer in contact with the oxide semiconductor layer containing the oxygen-excess region, it becomes possible to supply oxygen to the oxide semiconductor layer. Oxygen deficiency acts as a donor for the oxide semiconductor and generates electrons that become carriers in the oxide semiconductor. Therefore, by supplying oxygen to the oxide semiconductor layer to compensate for the oxygen deficiency, a highly reliable transistor can be obtained.

Advantages of the Invention

[0025] The semiconductor device provided by one aspect of the present invention is a semiconductor device with stable electrical characteristics and high reliability, manufactured by a manufacturing method with few changes from mass production techniques that have been put into practical use.

[0026] Also, according to one aspect of the present invention, a semiconductor device capable of preventing a decrease in yield due to electrostatic breakdown can be provided.

Brief Description of the Drawings

[0027]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that its form and details can be variously changed. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below.

[0029] In the configuration of the present invention described below, the same parts or parts having the same function are commonly used with the same reference numerals among different drawings, and the repeated description thereof is omitted. In addition, when referring to parts having the same function, the hatching patterns are the same, and there are cases where they are not particularly labeled.

[0030] In each drawing described in this specification, the size, film thickness, or region of each component is clear. ​​It may be exaggerated for the sake of illustration. Therefore, it is not necessarily limited to that scale.

[0031] In addition, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Also, in this specification and the like, it does not indicate a specific name as a matter for specifying the invention .

[0032] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1, 2, 3 , 10, and 11. In this embodiment, as an example of a semiconductor device, a bottom-gate type transistor having an oxide semiconductor layer is shown.

[0033] <Example Configuration 1 of Semiconductor Device> Examples of the configuration of the transistor 300 are shown in FIGS. 1(A) to 1(C). FIG. 1(A) is a plan view of the transistor 300, FIG. 1(B) is a cross-sectional view taken along the dashed line X1 - Y1 in FIG. 1(A), and FIG. 1(C) is a cross-sectional view taken along the dashed line V1 - W1 in FIG. 1(A).

[0034] The transistor 300 includes a gate electrode layer 402 provided on a substrate 400 having an insulating surface, a gate insulating layer 404 on the gate electrode layer 402, an oxide insulating layer 406 on the gate insulating layer 404, an oxide semiconductor layer 408 in contact with the oxide insulating layer 406 and overlapping the gate electrode layer 402, and source electrode layers 410a and drain electrode layers 410b electrically connected to the oxide semiconductor layer 408.

[0035] In the transistor 300, the gate insulating layer 404 includes a silicon film containing nitrogen and is configured ​​​is formed. The silicon nitride film has a higher relative dielectric constant than the silicon oxide film, and since the film thickness required to obtain the same capacitance is large, the gate insulating layer can be physically thickened. Therefore, it is possible to suppress a decrease in the breakdown voltage of the transistor 300 and further improve the breakdown voltage, thereby suppressing electrostatic breakdown of the semiconductor device.

[0036] The film thickness of the gate insulating layer 404 is provided to be at least thicker than the oxide insulating layer 406. It is preferably 325 nm or more and 550 nm or less, and more preferably 355 nm or more and 550 n m or less.

[0037] Examples of the silicon nitride film include a silicon nitride film, a silicon oxynitride film, and a silicon nitride oxide film. Since the higher the nitrogen content, the higher the relative dielectric constant, it is preferable to apply a silicon nitride film. In addition, the energy gap of silicon oxide is 8 eV, whereas the energy gap of silicon nitride is as small as 5.5 eV, and accordingly, the resistivity is also small. Therefore, by using a silicon nitride film, it is possible to impart higher ESD resistance. Furthermore, when forming a silicon nitride film by CVD method, it is not necessary to use N2O gas, which is a greenhouse gas applied when forming a silicon film containing oxygen and nitrogen such as a silicon oxynitride film by CVD method. In this specification, the silicon oxynitride film refers to a film having a higher oxygen content than nitrogen in its composition, and the silicon nitride oxide film refers to a film having a higher nitrogen content than oxygen in its composition.

[0038]

[0038] In the transistor 300, the oxide insulating layer 406 is a constituent element of the oxide semiconductor layer 408. It is composed of one or more selected metal elements. Using such a material for the oxide By forming the insulating layer 406, the interface with the oxide semiconductor layer 408 can be stabilized and it is possible to suppress the trapping of charges at the interface. Therefore, the deterioration of the transistor , especially photo-deterioration, can be prevented, and a highly reliable transistor can be obtained.

[0039] Specifically, as the oxide insulating layer 406, for example, a gallium oxide film (GaO x which may also be denoted as where x is not limited to natural numbers and includes non-natural numbers), a gallium oxide zinc film (Ga2Zn x O y (which may also be denoted as x = 1 to 5), a Ga2O3(Gd2O3) film, an insulating In-Ga-Zn-based oxide film with a high gallium content and a low indium content, etc. are preferably provided. It is preferable to provide an insulating In-Ga-Zn-based oxide film with a high gallium content and a low indium content. It is preferable to provide an insulating In-Ga-Zn-based oxide film with a high gallium content and a low indium content.

[0040] The constituent elements of the oxide insulating layer 406 and the oxide semiconductor layer 408 may be the same, and their compositions may be different. For example, when an In-Ga-Zn-based oxide semiconductor layer is used as the oxide semiconductor layer 408, since the energy gap can be controlled by the ratio of indium (In) to gallium (Ga), if the atomic ratio of the oxide semiconductor layer 408 is In:Ga: Zn = 1:1:1 or In:Ga:Zn = 3:1:2, the atomic ratio of the oxide insulating layer 406 may be set to In:Ga:Zn = 1:3:2. Note that the oxide insulating layer 406 and the oxide semiconductor layer 408 can be formed by sputtering, and containing indium in the sputtering target can reduce the generation of particles during film formation. Therefore, an indium-containing oxide insulating layer 406 and an indium-containing oxide semiconductor layer 408 can be formed. The oxide insulating layer 406 and the oxide semiconductor layer 408 can be formed by sputtering, and containing indium in the sputtering target can reduce the generation of particles during film formation. Therefore, an indium-containing oxide insulating layer 406 and an indium-containing oxide semiconductor layer 408 can be formed. layer 408 can be formed by sputtering, and containing indium in the sputtering target can reduce the generation of particles during film formation. Therefore, an indium-containing oxide insulating layer 406 and an indium-containing oxide semiconductor layer 408 can be formed. target can reduce the generation of particles during film formation. Therefore, an indium-containing oxide insulating layer 406 and an indium-containing oxide semiconductor layer 408 can be formed. Therefore, an indium-containing oxide insulating layer 406 and an indium-containing oxide semiconductor layer 408 can be formed. It is preferable to use the layer 408.

[0041] In the transistor 300 of FIG. 1, an example is shown in which the oxide insulating layer 406 is also processed into an island shape by an etching process when the oxide semiconductor layer 408 is processed into an island shape. Therefore, the ends of the oxide semiconductor layer 408 and the oxide insulating layer 406 coincide. of the etching process, the oxide insulating layer 406 is also processed into an island shape. Therefore, the ends of the oxide semiconductor layer 408 and the oxide insulating layer 406 coincide. oxide semiconductor layer 408 and the oxide insulating layer 406 coincide.

[0042] Hereinafter, the structure of the oxide semiconductor layer will be described.

[0043] The oxide semiconductor layer is roughly classified into a single crystal oxide semiconductor layer and a non-single crystal oxide semiconductor layer. The non single crystal oxide semiconductor layer refers to an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, and the like.

[0044] The amorphous oxide semiconductor layer is an oxide semiconductor layer in which the atomic arrangement in the film is irregular and has no crystal component. It is typical of an oxide semiconductor layer that has no crystal part even in a minute region and the whole film has a complete amorphous structure. oxide semiconductor layer is an oxide semiconductor layer in which the atomic arrangement in the film is irregular and has no crystal component. It is typical of an oxide semiconductor layer that has no crystal part even in a minute region and the whole film has a complete amorphous structure. oxide semiconductor layer is an oxide semiconductor layer in which the atomic arrangement in the film is irregular and has no crystal component. It is typical of an oxide semiconductor layer that has no crystal part even in a minute region and the whole film has a complete amorphous structure.

[0045] The microcrystalline oxide semiconductor layer contains, for example, microcrystals (also called nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor layer has a higher regularity of atomic arrangement than the amorphous oxide semiconductor layer. Therefore, the microcrystalline oxide semiconductor layer is characterized in that the density of defect energy levels is lower than that of the amorphous oxide semiconductor layer. and the like. Therefore, the microcrystalline oxide semiconductor layer has a higher regularity of atomic arrangement than the amorphous oxide semiconductor layer. Therefore, the microcrystalline oxide semiconductor layer is characterized in that the density of defect energy levels is lower than that of the amorphous oxide semiconductor layer. oxide semiconductor layer has a higher regularity of atomic arrangement than the amorphous oxide semiconductor layer. Therefore, the microcrystalline oxide semiconductor layer is characterized in that the density of defect energy levels is lower than that of the amorphous oxide semiconductor layer. oxide semiconductor layer is characterized in that the density of defect energy levels is lower than that of the amorphous oxide semiconductor layer.

[0046] The CAAC-OS film is one of the oxide semiconductor layers having a plurality of crystal parts, and most of the crystal parts have a size that can be accommodated in a cube with a side length of less than 100 nm. Therefore, the CAAC-O The crystal part contained in the S film also includes the case where the size is within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. The CAAC-OS film is characterized by having a lower density of defect energy levels than the microcrystalline oxide semiconductor layer. Hereinafter, the CAAC-OS film will be described in detail. .

[0047] When the CAAC-OS film is observed by a transmission electron microscope (TEM: Transmission Electron Microscope), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary), cannot be confirmed. Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to grain boundaries.

[0048] When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation ), it can be confirmed that in the crystal part, metal atoms are arranged in layers. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0049] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0050] On the other hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation ), it can be seen that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystal parts. None.

[0051] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystal parts of the CAAC-OS film have orientation. This is understandable.

[0052] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) device, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) device, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) device, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) device, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) device, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) device, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface.

[0053] On the other hand, in the analysis of the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°. On the other hand, in the analysis of the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°. On the other hand, in the analysis of the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°. On the other hand, in the analysis of the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°. On the other hand, in the analysis of the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°. On the other hand, in the analysis of the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°. On the other hand, in the analysis of the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor layer of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°.

[0054] From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts. Although it is a rule, it has c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is oriented in a direction. Therefore, each layer of the metal atoms arranged in layers confirmed by the above-described cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

[0055] The crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film.

[0056] Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the surface to be formed. Further, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially.

[0057] In the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. The peak at around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. It is preferable that the CAAC-OS film shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°.

[0058] ​​​​​​​​​​​​​ In addition, in this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system. .

[0059] The transistor using the CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0060] Note that the oxide semiconductor layer 408 may have any structure of, for example, an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a CAAC-OS film, or a mixed film thereof. Alternatively, it may be a laminated film having two or more of these structures.

[0061] Note that the oxide insulating layer 406 may have lower crystallinity than the oxide semiconductor layer 408. The oxide insulating layer 406 may have, for example, an amorphous part or nanocrystals.

[0062] As components of the transistor 300, an oxide insulating layer 412 that covers the source electrode layer 410a and the drain electrode layer 410 b and is in contact with the oxide semiconductor layer 408, and / or a protective insulating layer 414 on the oxide insulating layer 412 may be included.

[0063] As the oxide insulating layer 412, similar to the oxide insulating layer 406, a layer formed by including one or more metal elements selected from the constituent elements of the oxide semiconductor layer 408 is preferably applied. By using such a material, the interface between the oxide insulating layer 412 and the oxide semiconductor layer 408 can be stabilized. Since the oxide insulating layer 412 is an insulating layer in contact with the back channel side of the oxide semiconductor layer 408, charge trapping at the interface between the two layers can be suppressed, and the generation of a parasitic channel can be suppressed. and the generation of a parasitic channel can be suppressed.

[0064] In addition, the oxide semiconductor layer 408 is sandwiched between two oxide semiconductor layers, one of which is selected from the constituent elements of the oxide semiconductor layer. By providing an oxide insulating layer containing one or more metal elements selected from the above, it is possible to prevent the oxide semiconductor from being externally Prevents the diffusion of impurities (such as nitrogen and metal elements) that may affect the body layers. Therefore, the oxide semiconductor layer can be sandwiched between the oxide semiconductor layers or the oxide semiconductor layers can be blocked. By providing the oxide insulating layer so as to surround the oxide semiconductor layer, It is possible to maintain the purity constant and realize a semiconductor device having stable electrical characteristics.

[0065] The protective insulating layer 414 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, a nitride film, or the like. silicon oxide film, silicon oxynitride film, aluminum oxynitride film, or silicon nitride oxide film A membrane or the like can be used.

[0066] <Configuration Example 2 of Semiconductor Device> 2A to 2C show examples of the structure of a transistor 310. 2(B) is a plan view of the resistor 310, and FIG. 2(B) is a cross-sectional view taken along the dashed line X2-Y2 in FIG. 2(A). 2(C) is a cross-sectional view taken along the dashed line V2-W2 in FIG. 2(A).

[0067] The transistor 310 shown in FIG. 2 has an insulating surface, similar to the transistor 300 shown in FIG. A gate electrode layer 402 is provided on a substrate 400, and a gate insulating film is provided on the gate electrode layer 402. A layer 404, an oxide insulating layer 406 on the gate insulating layer 404, and a semiconductor layer 406 on the oxide insulating layer 406. The oxide semiconductor layer 408 overlaps with the gate electrode layer 402, and the oxide semiconductor layer 408 and an The source electrode layer 410a and the drain electrode layer 410b are electrically connected to each other. The source electrode layer 410a and the drain electrode layer 410b are covered by the oxide semiconductor layer 408. The oxide insulating layer 412 and the protective insulating layer 414 on the oxide insulating layer 412 are formed on the transistor 3. It may be 10 components.

[0068] The transistor 310 has a structure in which the gate insulating layer 404 and the oxide semiconductor layer 408 are the same as those of the transistor 310. In the transistor 310, the gate insulating layer 404 is A gate insulating layer 404a in contact with the gate electrode layer 402, and a gate insulating layer 404a and an oxide insulating layer The gate insulating layer 404b is provided between the gate insulating layer 404 and the edge layer 406. In the transistor 310, the oxide semiconductor layer 408 is in contact with the oxide insulating layer 406. The oxide semiconductor layer 408a and the oxide semiconductor layer 408b in contact with the oxide insulating layer 412 are included. Note that in the transistor 310, the gate insulating layer 404 and the oxide semiconductor The configuration other than the layer 408 is the same as that of the transistor 300. The explanation given in the above paragraph can be taken into consideration.

[0069] In the transistor 310, the gate insulating layer 404a and the gate insulating layer 404b are made of nitride. Includes a silicon membrane.

[0070] The gate insulating layer 404a has a thickness greater than that of the gate insulating layer 404b, and thus the defects in the film are reduced. For example, the thickness of the gate insulating layer 404a is set to 300 The wavelength is between 400 nm and 500 nm. In addition, the electron spin resonance method (ESR) The signal that appears at the Nc center (g value is 2.003) in the spin resonance The spin density corresponding to the number is preferably 1×10 17 spins / cm3 Next, a more preferred or 5×10 16 spins / cm 3 or less is applied to the silicon nitride film. In this way by providing a silicon nitride film with reduced defects in the film at a thick film thickness (for example, 300 nm or more), the breakdown voltage of the gate insulating layer 404a can be made, for example, 300 V or more. It is possible.

[0071] In addition, since the gate insulating layer 404b is in contact with the oxide semiconductor layer 408, it is assumed to include a silicon nitride film with a reduced hydrogen concentration, and the hydrogen concentration thereof is at least lower than that of the gate insulating layer 40 4a. For example, when forming the gate insulating layer 404a and the gate insulating layer 404b by plasma CVD, the hydrogen concentration in the supply gas is reduced so that the hydrogen concentration of the gate insulating layer 404b can be reduced compared to the gate insulating layer 404a. Specifically, when forming a silicon nitride film as the gate insulating layer 404a and the gate insulating layer 404b, the ammonia flow rate is reduced compared to the supply gas for forming the gate insulating layer 404a, or the gate insulating layer 404b may be formed without using ammonia.

[0072] In addition, the film thickness of the gate insulating layer 404b is set to be 25 nm or more and 150 nm or less. By providing a silicon nitride film with a reduced hydrogen concentration as the gate insulating layer 404b, the mixing of hydrogen or a hydrogen compound (for example, water) into the oxide insulating layer 406 and the oxide semiconductor layer 408 can be reduced. Hydrogen becomes a factor for generating carriers in the oxide semiconductor and a factor for shifting the threshold voltage of the transistor in the negative direction. Therefore, the reduction of the hydrogen concentration By providing the formed silicon nitride film as the gate insulating layer 404b, the electrical characteristics of the transistor can be stabilized. Further, by providing the silicon nitride film with a reduced hydrogen concentration as the gate insulating layer 404b, it also has the effect of acting as a barrier film to prevent impurities such as hydrogen or hydrogen compounds contained in the gate insulating layer 404a from diffusing into the oxide insulating layer 406 and the oxide semiconductor layer 408. In addition, in the present embodiment, both the gate insulating layer 404a and the gate insulating layer 404b are silicon nitride films, and depending on the material and film formation conditions, the interface between the gate insulating layers may become unclear. Therefore, in FIG. 2, the interface between the gate insulating layer 404a and the gate insulating layer 404b is schematically shown by a dotted line. The same applies to each of the following drawings. The oxide semiconductor layer 408a and the oxide semiconductor layer 408b contained in the oxide semiconductor layer 408 preferably have the same constituent elements and different compositions. When forming an oxide semiconductor layer containing indium and gallium as the oxide semiconductor layer 408a and the oxide semiconductor layer 408b, the content ratio of indium and gallium in the oxide semiconductor layer 408a on the side close to the gate electrode layer 402 (channel side) may be In>Ga. Also, the content ratio of indium and gallium in the oxide semiconductor layer 408b on the side far from the gate electrode layer 402 (back channel side) may be In≦Ga. In an oxide semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction, and increasing the indium content tends to increase the overlap of the s orbitals. Therefore, In>

[0073] In the present embodiment, both the gate insulating layer 404a and the gate insulating layer 404b are silicon nitride films. Depending on the material and film formation conditions, the interface between the gate insulating layers may be unclear. Therefore, in FIG. 2, the interface between the gate insulating layer 404a and the gate insulating layer 404b is schematically shown by a dotted line. The same applies to each of the following drawings. The oxide semiconductor layer 408a and the oxide semiconductor layer 408b contained in the oxide semiconductor layer 408 preferably have the same constituent elements and different compositions. When forming an oxide semiconductor layer containing indium and gallium as the oxide semiconductor layer 408a and the oxide semiconductor layer 408b, the content ratio of indium and gallium in the oxide semiconductor layer 408a on the side close to the gate electrode layer 402 (channel side) may be In>Ga.

[0074] Also, the content ratio of indium and gallium in the oxide semiconductor layer 408b on the side far from the gate electrode layer 402 (back channel side) may be In≦Ga. In an oxide semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction, and increasing the indium content tends to increase the overlap of the s orbitals. Therefore, it is preferable that the content ratio of indium and gallium in the oxide semiconductor layer 408a on the side close to the gate electrode layer 402 (channel side) is In>Ga. Also, the content ratio of indium and gallium in the oxide semiconductor layer 408b on the side far from the gate electrode layer 402 (back channel side) is In≦Ga. In an oxide semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction, and increasing the indium content tends to increase the overlap of the s orbitals. Therefore, when forming an oxide semiconductor layer containing indium and gallium as the oxide semiconductor layer 408a and the oxide semiconductor layer 408b, the content ratio of indium and gallium in the oxide semiconductor layer 408a on the side close to the gate electrode layer 402 (channel side) may be In>Ga.

[0075] In an oxide semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction, and increasing the indium content tends to increase the overlap of the s orbitals. Therefore, by increasing the indium content, the overlap of the s orbitals tends to increase. ​The oxide with a Ga composition has a higher mobility compared to the oxide with a composition of In≦Ga. In addition, Ga has a larger formation energy of oxygen deficiency compared to In, and oxygen deficiency is less likely to occur. Therefore, the oxide with a composition of In≦Ga has characteristics that are more stable compared to the oxide with a composition of In>Ga.

[0076] By applying an oxide semiconductor with a composition of In>Ga to the channel side and an oxide semiconductor with a composition of In≦Ga to the back channel side, the mobility and reliability of the transistor can be further enhanced. For example, the atomic ratio of the oxide semiconductor layer 408a can be In:Ga:Zn = 3:1:2, and the atomic ratio of the oxide semiconductor layer 408b can be In:Ga:Zn = 1 :1:1.

[0077] Note that by making the constituent elements of the oxide insulating layer 406 in contact with the oxide semiconductor layer 408a the same as those of the oxide semiconductor layer 408a and making the composition different to impart insulation to the oxide insulating layer 406, the interface between the two can be made more stable, which is preferable. The same applies to the oxide insulating layer 412 in contact with the oxide semiconductor layer 408b.

[0078] In addition, oxide semiconductors with different crystallinities may be applied to the oxide semiconductor layer 408a and the oxide semiconductor layer 408b. That is, a configuration in which a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a nanocrystal oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS is appropriately combined may also be used. However, an amorphous oxide semiconductor easily absorbs impurities such as hydrogen, and is also prone to oxygen deficiency and is thus easily n-type. For this reason, it is preferable to apply a crystalline oxide semiconductor such as CAAC-OS to the oxide semiconductor layer 408a on the channel side.

[0079] In addition, when an amorphous oxide semiconductor is used for the oxide semiconductor layer 408b on the back channel side, oxygen deficiency occurs due to the etching process during the formation of the source electrode layer 410a and the drain electrode layer 410b, and it is likely to be n-type. Therefore, it is preferable to apply a crystalline oxide semiconductor to the oxide semiconductor layer 408b. Figure 14 is an energy band diagram (schematic diagram) of a structure in which a gate insulating layer GI, oxide insulating layers OI1, oxide semiconductor layers OS1 and OS2, oxide insulating layer OI2, and protective insulating layer Passi are laminated in the transistor of this embodiment. In Figure 14, an ideal situation is assumed where all of the gate insulating layer, oxide insulating layer, oxide semiconductor layer, and protective insulating layer are intrinsic. As the gate insulating layer GI and the protective insulating layer Passi, a silicon nitride film (bandgap Eg is 5 eV) is used, and as the oxide insulating layer OI1 and the oxide insulating layer OI2, an In-Ga-Zn-based oxide insulating layer with In:Ga:Zn = 1:3:2 (bandgap Eg is 3.6 eV) is used. As the oxide semiconductor layer OS1, an In-Ga-Zn-based oxide semiconductor layer with In:Ga:Zn = 3:1:2 (bandgap Eg is 2.8 eV) is used, and as the oxide semiconductor layer OS2, an In-Ga-Zn-based oxide semiconductor layer with In:Ga:Zn = 1:1:1 (bandgap Eg is 3.2 eV) is used. The case is shown. Note that in Figure 14, the relative dielectric constants of the oxide insulating layer OI1, the oxide insulating layer OI2, the oxide semiconductor layer OS1, and the oxide semiconductor layer OS2 are all assumed to be 15. Also, the mobilities of the oxide insulating layer OI1 and the oxide insulating layer OI2 are 4 cm

[0080] Figure 14 is an energy band diagram (schematic diagram) of a structure in which a gate insulating layer GI, oxide insulating layers OI 1, oxide semiconductor layers OS1, OS2, oxide insulating layer OI2, and protective insulating layer Passi are laminated. In Figure 14, an ideal situation is assumed where all of the gate insulating layer, oxide insulating layer, oxide semiconductor layer, and protective insulating layer are intrinsic. As the gate insulating layer GI and the protective insulating layer Passi, a silicon nitride film ( bandgap Eg is 5 eV) is used, and as the oxide insulating layer OI1 and the oxide insulating layer OI2, an In-Ga-Zn-based oxide insulating layer with In:Ga:Zn = 1:3:2 (bandgap Eg is 3.6 eV) is used, and as the oxide semiconductor layer OS1, an In-Ga-Zn-based oxide semiconductor layer with In:Ga:Zn = 3:1:2 is used (bandgap Eg is 2.8 eV), and as the oxide semiconductor layer OS2, an In-Ga-Zn-based oxide semiconductor layer with In:Ga:Zn = 1:1:1 (bandgap Eg is 3.2 eV) is used. The case is shown.

[0081] Note that in Figure 14, the relative dielectric constants of the oxide insulating layer OI1, the oxide insulating layer OI2, the oxide semiconductor layer OS 1, and the oxide semiconductor layer OS2 are all assumed to be 15. Also, the mobilities of the oxide insulating layer OI 1 and the oxide insulating layer OI2 are 4 cm 2 / Vs, and the transition Movement: 25cm 2 / Vs, and the mobility of the oxide semiconductor layer OS2 is 10 cm 2 / Vs and The thickness of the gate insulating layer GI was set to 325 nm, and the thickness of the oxide insulating layer OI1 was set to 3 0 nm, the thickness of the oxide semiconductor layer OS1 is 10 nm, and the thickness of the oxide semiconductor layer OS2 is The thickness of the oxide insulating layer OI2 is set to 30 nm, and the thickness of the protective insulating layer Passi is set to 10 nm. The calculation was performed assuming a thickness of 300 nm.

[0082] As shown in FIG. 14, the oxide semiconductor layer OS1 has an oxide semiconductor layer on the gate electrode side (channel side). There is an energy barrier at the interface between the conductor layer OS1 and the oxide insulating layer OI1. An oxide semiconductor layer O is also formed on the back channel side (opposite side to the gate electrode) of the oxide semiconductor layer OS2. There is an energy barrier at the interface between S2 and the oxide insulating layer OI2. The existence of such an energy barrier at the interface with the insulating layer causes Since the movement of carriers is hindered, the carriers move from the oxide semiconductor layer to the oxide insulating layer. In other words, the oxide semiconductor layer is By forming a layered structure sandwiching the material with a gradually increasing band gap, The carriers move through the oxide semiconductor layer OS1 and the oxide semiconductor layer OS2.

[0083] <Method for Manufacturing Semiconductor Device> An example of a method for manufacturing the transistor 310 will be described below with reference to FIGS.

[0084] First, a gate electrode layer 402 is formed over a substrate 400 having an insulating surface.

[0085] There are no major restrictions on the substrate that can be used for the substrate 400 having an insulating surface, but it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 400. The gate electrode layer 402 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, etc. or an alloy material mainly composed of these. Also, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, a silicide film such as nickel silicide, etc. may be used as the gate electrode layer 402. The gate electrode layer 402 may have a single-layer structure or a laminated structure. The gate electrode layer 402 may have a tapered shape. For example, the taper angle may be 30° or more and 70° or less. Here, the taper angle refers to the angle between the side surface of the layer having the tapered shape and the bottom surface of the layer. Moreover, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be applied as the material of the gate electrode layer 402. For the substrate 400, there are no major restrictions on the substrate that can be used, but it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 400. The gate electrode layer 402 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, etc. or an alloy material mainly composed of these. Also, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, a silicide film such as nickel silicide, etc. may be used as the gate electrode layer 402. The gate electrode layer 402 may have a single-layer structure or a laminated structure. The gate electrode layer 402 may have a tapered shape. For example, the taper angle may be 30° or more and 70° or less. Here, the taper angle refers to the angle between the side surface of the layer having the tapered shape and the bottom surface of the layer. Moreover, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be applied as the material of the gate electrode layer 402. For the substrate 400, there are no major restrictions on the substrate that can be used, but it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 400.

[0086] The gate electrode layer 402 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, etc. or an alloy material mainly composed of these. Also, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, a silicide film such as nickel silicide, etc. may be used as the gate electrode layer 402. The gate electrode layer 402 may have a single-layer structure or a laminated structure. The gate electrode layer 402 may have a tapered shape. For example, the taper angle may be 30° or more and 70° or less. Here, the taper angle refers to the angle between the side surface of the layer having the tapered shape and the bottom surface of the layer. Moreover, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be applied as the material of the gate electrode layer 402. For the substrate 400, there are no major restrictions on the substrate that can be used, but it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 400. The gate electrode layer 402 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, etc. or an alloy material mainly composed of these. Also, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, a silicide film such as nickel silicide, etc. may be used as the gate electrode layer 402. The gate electrode layer 402 may have a single-layer structure or a laminated structure. The gate electrode layer 402 may have a tapered shape. For example, the taper angle may be 30° or more and 70° or less. Here, the taper angle refers to the angle between the side surface of the layer having the tapered shape and the bottom surface of the layer. Moreover, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be applied as the material of the gate electrode layer 402. For the substrate 400, there are no major restrictions on the substrate that can be used, but it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 400. The gate electrode layer 402 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, etc. or an alloy material mainly composed of these. Also, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, a silicide film such as nickel silicide, etc. may be used as the gate electrode layer 402. The gate electrode layer 402 may have a single-layer structure or a laminated structure. The gate electrode layer 402 may have a tapered shape. For example, the taper angle may be 30° or more and 70° or less. Here, the taper angle refers to the angle between the side surface of the layer having the tapered shape and the bottom surface of the layer. Moreover, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be applied as the material of the gate electrode layer 402.

[0087] Moreover, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be applied as the material of the gate electrode layer 402. For the substrate 400, there are no major restrictions on the substrate that can be used, but it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 400. The gate electrode layer 402 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, etc. or an alloy material mainly composed of these. Also, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, a silicide film such as nickel silicide, etc. may be used as the gate electrode layer 402. The gate electrode layer 402 may have a single-layer structure or a laminated structure. The gate electrode layer 402 may have a tapered shape. For example, the taper angle may be 30° or more and 70° or less. Here, the taper angle refers to the angle between the side surface of the layer having the tapered shape and the bottom surface of the layer. Moreover, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be applied as the material of the gate electrode layer 402.

[0088] Alternatively, as the material of the gate electrode layer 402, indium-gallium-zinc oxide containing nitrogen, indium-tin oxide containing nitrogen, indium-gallium oxide containing nitrogen, indium-zinc oxide containing nitrogen, tin oxide containing nitrogen, indium oxide containing nitrogen, metal nitride (such as indium nitride, zinc nitride, tantalum nitride, tungsten nitride, etc.) may be used. Since these materials have a work function of 5 eV or more, by forming the gate electrode layer 402 using these materials, the threshold voltage of the transistor can be made positive, and a normally-off switching transistor can be realized. indium-tin oxide containing nitrogen, indium-gallium oxide containing nitrogen, indium-zinc oxide containing nitrogen, tin oxide containing nitrogen, indium oxide containing nitrogen, metal nitride (such as indium nitride, zinc nitride, tantalum nitride, tungsten nitride, etc.) may be used. Since these materials have a work function of 5 eV or more, by forming the gate electrode layer 402 using these materials, the threshold voltage of the transistor can be made positive, and a normally-off switching transistor can be realized. indium-zinc oxide containing nitrogen, tin oxide containing nitrogen, indium oxide containing nitrogen, metal nitride (such as indium nitride, zinc nitride, tantalum nitride, tungsten nitride, etc.) may be used. Since these materials have a work function of 5 eV or more, by forming the gate electrode layer 402 using these materials, the threshold voltage of the transistor can be made positive, and a normally-off switching transistor can be realized. zinc nitride, tantalum nitride, tungsten nitride, etc.) may be used. Since these materials have a work function of 5 eV or more, by forming the gate electrode layer 402 using these materials, the threshold voltage of the transistor can be made positive, and a normally-off switching transistor can be realized. Since these materials have a work function of 5 eV or more, by forming the gate electrode layer 402 using these materials, the threshold voltage of the transistor can be made positive, and a normally-off switching transistor can be realized. the threshold voltage of the transistor can be made positive, and a normally-off switching transistor can be realized. the threshold voltage of the transistor can be made positive, and a normally-off switching transistor can be realized.

[0089] Next, a gate insulating layer 404 including a gate insulating layer 404a and a gate insulating layer 404b is formed so as to cover the gate electrode layer 402 (see FIG. 3(A)). As the gate insulating layer 404, a silicon film containing nitrogen can be applied. In this embodiment, the gate insulating layer 404a made of a silicon nitride film and the gate insulating layer 404b made of a silicon nitride film are laminated to form the gate insulating layer 404. From the viewpoint of reducing in-plane variation, particle contamination, and film formation tact, it is effective to form the film using the CVD method. Also, the CVD method is effective for film formation on a large-area substrate. Next, a gate insulating layer 404 including a gate insulating layer 404a and a gate insulating layer 404b is formed so as to cover the gate electrode layer 402 (see FIG. 3(A)). As the gate insulating layer 404, a silicon film containing nitrogen can be applied. In this embodiment, the gate insulating layer 404a made of a silicon nitride film and the gate insulating layer 404b made of a silicon nitride film are laminated to form the gate insulating layer 404. From the viewpoint of reducing in-plane variation, particle contamination, and film formation tact, it is effective to form the film using the CVD method. Also, the CVD method is effective for film formation on a large-area substrate. a silicon film containing nitrogen can be applied. In this embodiment, the gate insulating layer 404a made of a silicon nitride film and the gate insulating layer 404b made of a silicon nitride film are laminated to form the gate insulating layer 404. From the viewpoint of reducing in-plane variation, particle contamination, and film formation tact, it is effective to form the film using the CVD method. Also, the CVD method is effective for film formation on a large-area substrate. In this embodiment, the gate insulating layer 404a made of a silicon nitride film and the gate insulating layer 404b made of a silicon nitride film are laminated to form the gate insulating layer 404. From the viewpoint of reducing in-plane variation, particle contamination, and film formation tact, it is effective to form the film using the CVD method. Also, the CVD method is effective for film formation on a large-area substrate. In this embodiment, the gate insulating layer 404a made of a silicon nitride film and the gate insulating layer 404b made of a silicon nitride film are laminated to form the gate insulating layer 404. From the viewpoint of reducing in-plane variation, particle contamination, and film formation tact, it is effective to form the film using the CVD method. Also, the CVD method is effective for film formation on a large-area substrate. From the viewpoint of reducing in-plane variation, particle contamination, and film formation tact, it is effective to form the film using the CVD method. Also, the CVD method is effective for film formation on a large-area substrate. From the viewpoint of reducing in-plane variation, particle contamination, and film formation tact, it is effective to form the film using the CVD method. Also, the CVD method is effective for film formation on a large-area substrate.

[0090] In this embodiment, the gate insulating layer 404a and the gate insulating layer 404b are continuously formed by the plasma CVD method. First, the supply gas is set as a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3) to form a silicon nitride film that becomes the gate insulating layer 404a. Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2). In this embodiment, the gate insulating layer 404a and the gate insulating layer 404b are continuously formed by the plasma CVD method. First, the supply gas is set as a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3) to form a silicon nitride film that becomes the gate insulating layer 404a. Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2). ammonia (NH3) to form a silicon nitride film that becomes the gate insulating layer 404a. Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2). ammonia (NH3) to form a silicon nitride film that becomes the gate insulating layer 404a. Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2). Then, a silicon nitride film that becomes the gate insulating layer 404b is formed.

[0091] The supply gases for the plasma CVD process were silane (SiH4), nitrogen (N2) and ammonia (NH 3) The silicon nitride film is formed by mixing silane (SiH4) and nitrogen gas. It is possible to reduce defects in the film more than silicon nitride films formed using a mixture of nitrogen (N2) and silicon dioxide (N3) gases. Therefore, the gate insulating layer 404a has a larger thickness than the gate insulating layer 404b. The film has reduced defects, and for example, Nc centers are detected by electron spin resonance (ESR). The spin density corresponding to the signal appearing at (g value of 2.003) is preferably 1 × 10 17 s pins / cm 3 , more preferably 5 × 10 16 spins / cm 3 The following can be done: In addition, the silicon nitride film formed by mixing ammonia in the gas mixture can be obtained by silicide gas. This allows for a film with better coverage than a mixture of lanthanum and nitrogen gas, making it possible to As a gate insulating layer in contact with the gate electrode layer 402, a silicon nitride film using the above-mentioned mixed gas is formed. It is effective to provide the gate insulating layer 404a having reduced defects to a thickness of 30 By providing the gate insulating layer 404 with a thickness of 0 nm or more and 400 nm or less, the dielectric strength of the gate insulating layer 404 can be increased to 300 V or more. It can be above.

[0092] On the other hand, the gate insulating layer 404b formed without containing ammonia in the source gas has a gate insulating The hydrogen concentration of the film can be lower than that of the edge layer 404a. The oxide insulating layer 406 and the gate electrode layer 402 are provided with a thickness of 25 nm or more and 150 nm or less. By this, the gate insulating layer 404b is The incorporation of hydrogen can be reduced. Further, the gate insulating layer 404b functions also as a barrier film that suppresses the incorporation of hydrogen or hydrogen compounds contained in the gate insulating layer 4 04a into the oxide insulating layer 406 and the oxide semiconductor layer 408 .

[0093] By laminating a thick film gate insulating layer 404a with reduced defects in the film and a gate insulating layer 404b with reduced hydrogen concentration as the gate insulating layer 404, while improving the breakdown voltage, the diffusion of impurities such as hydrogen into the oxide insulating layer 406 and the oxide semiconductor layer 408 can be suppressed. Therefore, electrostatic breakdown of the transistor including the gate insulating layer 404 can be suppressed, and moreover, the electrical characteristics can be stabilized.

[0094] Next, an oxide insulating layer and an oxide semiconductor layer are formed on the gate insulating layer 404b, and etched to form islands by etching, thereby forming an oxide insulating layer 406 and an oxide semiconductor layer 408 including an oxide semiconductor layer 408a and an acid oxide semiconductor layer 408b (see Fig. 3(B)). Since this etching process can be performed using the same photomask, the oxide insulating layer 406 and the oxide semiconductor layer 408 have the same pattern shape when viewed from the plane, and the ends match.

[0095] As the oxide insulating layer 406, an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer 408 is provided. For example, it is preferable to use an insulating film such as a gallium oxide film, a gallium zinc oxide film, a gallium gadolinium oxide film, or an insulating In-Ga-Zn-based oxide film with a high gallium content and a low indium content.

[0096] The oxide semiconductor layer 408 may have an amorphous structure or a crystalline structure. After film formation when the oxide semiconductor layer is made amorphous, it may be made into a crystalline oxide semiconductor layer 408 by applying heat treatment in a subsequent manufacturing process in this way. The temperature of the heat treatment for crystallizing the amorphous oxide semiconductor layer is 250°C or higher and 700°C or lower, preferably 400°C or higher, more preferably 500°C or higher, and even more preferably 550°C or higher. Note that this heat treatment can also be combined with other heat treatments in the manufacturing process

[0097] The film formation methods for the oxide insulating layer 406 and the oxide semiconductor layer 408 include a sputtering method, MBE (Molecular Beam Epitaxy) method, CVD method, pulsed laser deposition method , ALD (Atomic Layer Deposition) method, etc., which can be appropriately used

[0098] When forming the oxide insulating layer 406 and the oxide semiconductor layer 408, it is preferable to reduce the hydrogen concentration contained in the film as much as possible. To reduce the hydrogen concentration, for example, when film formation is performed using a sputtering method , as the atmosphere gas supplied into the film formation chamber of the sputtering apparatus , high-purity rare gas (typically argon) from which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed, oxygen, and a mixed gas of rare gas and oxygen are appropriately used

[0099] Also, by introducing a sputtering gas from which hydrogen and moisture have been removed while removing the residual moisture in the film formation chamber and performing film formation , the hydrogen concentration of the formed oxide insulating layer and oxide semiconductor layer can be reduced . To remove the residual moisture in the film formation chamber, an adsorption-type vacuum pump, for example ​​​​​, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, a turbo molecular pump with a cold trap added thereto may be used. Since a cryopump has high exhaust capacity for compounds containing hydrogen atoms such as, for example, hydrogen molecules and water (H2O) (more preferably compounds containing carbon atoms as well), the concentration of impurities contained in the film formed in the film formation chamber exhausted using the cryopump can be reduced. In addition, it is preferable that the oxide insulating layer and the oxide semiconductor layer are continuously formed without exposure to the atmosphere. By continuously forming the oxide insulating layer and the oxide semiconductor layer without exposure to the atmosphere, adhesion of hydrogen or a hydrogen compound (for example, adsorbed water, etc.) to the surface of the oxide insulating layer or the surface of the oxide semiconductor layer to be laminated can be prevented, and thus mixing of impurities can be suppressed. When the oxide insulating layer and the oxide semiconductor layer are formed by a sputtering method, the relative density (filling rate) of the metal oxide target used for film formation is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the film to be formed can be made a dense film. In addition, forming the oxide semiconductor layer while maintaining the substrate 400 at a high temperature is also effective in reducing the impurity concentration that may be contained in the oxide semiconductor layer. The temperature for heating the substrate 400 may be 150°C or more and 450°C or less, and preferably the substrate temperature may be 200°C or more and 3

[0100] 50°C or less. Also, by heating the substrate at a high temperature during film formation, a crystalline oxide semiconductor layer can be formed. Furthermore, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, a turbo molecular pump with a cold trap added thereto may be used. Since a cryopump has high exhaust capacity for compounds containing hydrogen atoms such as, for example, hydrogen molecules and water (H2O) (more preferably compounds containing carbon atoms as well), the concentration of impurities contained in the film formed in the film formation chamber exhausted using the cryopump can be reduced. In addition, it is preferable that the oxide insulating layer and the oxide semiconductor layer are continuously formed without exposure to the atmosphere. By continuously forming the oxide insulating layer and the oxide semiconductor layer without exposure to the atmosphere, adhesion of hydrogen or a hydrogen compound (for example, adsorbed water, etc.) to the surface of the oxide insulating layer or the surface of the oxide semiconductor layer to be laminated can be prevented, and thus mixing of impurities can be suppressed. When the oxide insulating layer and the oxide semiconductor layer are formed by a sputtering method, the relative density (filling rate) of the metal oxide target used for film formation is 90% or more and 100% or less, preferably .

[0101] 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the film to be formed can be made a dense film. In addition, forming the oxide semiconductor layer while maintaining the substrate 400 at a high temperature is also effective in reducing the impurity concentration that may be contained in the oxide semiconductor layer. The temperature for heating the substrate 400 may be 150°C or more and 450°C or less, and preferably the substrate temperature may be 200°C or more and 3 50°C or less. Also, by heating the substrate at a high temperature during film formation, a crystalline oxide semiconductor layer can be formed. Furthermore, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, a turbo molecular pump with a cold trap added thereto may be used. Since a cryopump has high exhaust capacity for compounds containing hydrogen atoms such as, for example, hydrogen molecules and water (H2O) (more preferably compounds containing carbon atoms as well), the concentration of impurities contained in the film formed in the film formation chamber exhausted using the cryopump can be reduced.

[0102] In addition, it is preferable that the oxide insulating layer and the oxide semiconductor layer are continuously formed without exposure to the atmosphere. By continuously forming the oxide insulating layer and the oxide semiconductor layer without exposure to the atmosphere, adhesion of hydrogen or a hydrogen compound (for example, adsorbed water, etc.) to the surface of the oxide insulating layer or the surface of the oxide semiconductor layer to be laminated can be prevented, and thus mixing of impurities can be suppressed. When the oxide insulating layer and the oxide semiconductor layer are formed by a sputtering method, the relative density (filling rate) of the metal oxide target used for film formation is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, the film to be formed can be made a dense film. In addition, forming the oxide semiconductor layer while maintaining the substrate 400 at a high temperature is also effective in reducing the impurity concentration that may be contained in the oxide semiconductor layer. The temperature for heating the substrate 400 may be 150°C or more and 450°C or less, and preferably the substrate temperature may be 200°C or more and 3 50°C or less. Also, by heating the substrate at a high temperature during film formation, a crystalline oxide semiconductor layer can be formed.

[0103] When applying a CAAC-OS film as the oxide semiconductor layer 408, as a method for obtaining the CAAC-OS film, for example, there is a method of forming the oxide semiconductor layer with a film formation temperature of 200°C or higher and 450°C or lower, and c-axis orienting it substantially perpendicular to the surface. Or, after forming the oxide semiconductor layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed to c-axis orient it substantially perpendicular to the surface. Or, after forming the first layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed, then the second layer may be formed, and it may be c-axis oriented substantially perpendicular to the surface. When applying a CAAC-OS film as the oxide semiconductor layer 408, as a method for obtaining the CAAC-OS film, for example, there is a method of forming the oxide semiconductor layer with a film formation temperature of 200°C or higher and 450°C or lower, and c-axis orienting it substantially perpendicular to the surface. Or, after forming the oxide semiconductor layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed to c-axis orient it substantially perpendicular to the surface. Or, after forming the first layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed, then the second layer may be formed, and it may be c-axis oriented substantially perpendicular to the surface. When applying a CAAC-OS film as the oxide semiconductor layer 408, as a method for obtaining the CAAC-OS film, for example, there is a method of forming the oxide semiconductor layer with a film formation temperature of 200°C or higher and 450°C or lower, and c-axis orienting it substantially perpendicular to the surface. Or, after forming the oxide semiconductor layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed to c-axis orient it substantially perpendicular to the surface. Or, after forming the first layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed, then the second layer may be formed, and it may be c-axis oriented substantially perpendicular to the surface. When applying a CAAC-OS film as the oxide semiconductor layer 408, as a method for obtaining the CAAC-OS film, for example, there is a method of forming the oxide semiconductor layer with a film formation temperature of 200°C or higher and 450°C or lower, and c-axis orienting it substantially perpendicular to the surface. Or, after forming the oxide semiconductor layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed to c-axis orient it substantially perpendicular to the surface. Or, after forming the first layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed, then the second layer may be formed, and it may be c-axis oriented substantially perpendicular to the surface. When applying a CAAC-OS film as the oxide semiconductor layer 408, as a method for obtaining the CAAC-OS film, for example, there is a method of forming the oxide semiconductor layer with a film formation temperature of 200°C or higher and 450°C or lower, and c-axis orienting it substantially perpendicular to the surface. Or, after forming the oxide semiconductor layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed to c-axis orient it substantially perpendicular to the surface. Or, after forming the first layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed, then the second layer may be formed, and it may be c-axis oriented substantially perpendicular to the surface. When applying a CAAC-OS film as the oxide semiconductor layer 408, as a method for obtaining the CAAC-OS film, for example, there is a method of forming the oxide semiconductor layer with a film formation temperature of 200°C or higher and 450°C or lower, and c-axis orienting it substantially perpendicular to the surface. Or, after forming the oxide semiconductor layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed to c-axis orient it substantially perpendicular to the surface. Or, after forming the first layer with a thin film thickness, a heat treatment at 200°C or higher and 700°C or lower may be performed, then the second layer may be formed, and it may be c-axis oriented substantially perpendicular to the surface.

[0104] The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). In particular, it preferably contains indium and zinc (Zn). Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it preferably has gallium (Ga) in addition to them. Also, as a stabilizer, it preferably has any one or more of tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). In particular, it preferably contains indium and zinc (Zn). Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it preferably has gallium (Ga) in addition to them. Also, as a stabilizer, it preferably has any one or more of tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). In particular, it preferably contains indium and zinc (Zn). Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it preferably has gallium (Ga) in addition to them. Also, as a stabilizer, it preferably has any one or more of tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). In particular, it preferably contains indium and zinc (Zn). Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it preferably has gallium (Ga) in addition to them. Also, as a stabilizer, it preferably has any one or more of tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). In particular, it preferably contains indium and zinc (Zn). Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it preferably has gallium (Ga) in addition to them. Also, as a stabilizer, it preferably has any one or more of tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). In particular, it preferably contains indium and zinc (Zn). Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it preferably has gallium (Ga) in addition to them. Also, as a stabilizer, it preferably has any one or more of tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr).

[0105] Also, as another stabilizer, it may have any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu), which are lanthanoids. Also, as another stabilizer, it may have any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu), which are lanthanoids. Also, as another stabilizer, it may have any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu), which are lanthanoids. Also, as another stabilizer, it may have any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu), which are lanthanoids. Also, as another stabilizer, it may have any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu), which are lanthanoids.

[0106] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn system oxides, In-Mg system oxides, In-Ga system oxides, ternary metal oxides such as In-Ga-Zn system oxides, In-Al-Zn system oxides, In-Sn-Zn system oxides, In-Hf-Zn system oxides, In-La-Zn system oxides, In-Ce-Zn system oxides, In-Pr-Zn system oxides, In-Nd-Zn system oxides, In-Sm-Zn system oxides, In-Eu-Zn system oxides, In-Gd-Zn system oxides, In-Tb-Zn system oxides, In-Dy-Zn system oxides, In-Ho-Zn system oxides, In-Er-Zn system oxides, In-Tm-Zn system oxides, In-Yb-Zn system oxides, In-Lu-Zn system oxides, quaternary metal oxides such as In-Sn-Ga-Zn system oxides, In-Hf-Ga-Zn system oxides, In-Al-Ga-Zn system oxides, In-Sn-Al-Zn system oxides, In-Sn-Hf-Zn system oxides, In-Hf-Al-Zn system oxides can be used. For example, the In-Ga-Zn system oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Further, metal elements other than In, Ga, and Zn may be contained. In addition, as the oxide semiconductor, a material represented by InMO3(ZnO) (m>0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n>0 and n is an integer) may be used. For example, the In-Ga-Zn system oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Further, metal elements other than In, Ga, and Zn may be contained. In addition, as the oxide semiconductor, a material represented by InMO3(ZnO) (m>0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n>0 and n is an integer) may be used. For example, the In-Ga-Zn system oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Further, metal elements other than In, Ga, and Zn may be contained. In addition, as the oxide semiconductor, a material represented by InMO3(ZnO) (m>0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n>0 and n is an integer) may be used. For example, the In-Ga-Zn system oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Further, metal elements other than In, Ga, and Zn may be contained. In addition, as the oxide semiconductor, a material represented by InMO3(ZnO) (m>0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n>0 and n is an integer) may be used. For example, the In-Ga-Zn system oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Further, metal elements other than In, Ga, and Zn may be contained. In addition, as the oxide semiconductor, a material represented by InMO3(ZnO) (m>0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n>0 and n is an integer) may be used.

[0107] For example, the In-Ga-Zn system oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Further, metal elements other than In, Ga, and Zn may be contained. For example, the In-Ga-Zn system oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Further, metal elements other than In, Ga, and Zn may be contained. For example, the In-Ga-Zn system oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Further, metal elements other than In, Ga, and Zn may be contained.

[0108] In addition, as the oxide semiconductor, a material represented by InMO3(ZnO) (m>0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n>0 and n is an integer) may be used. m (m>0, and m is not an integer) In addition, as the oxide semiconductor, a material represented by InMO3(ZnO) (m>0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n>0 and n is an integer) may be used. In addition, as the oxide semiconductor, a material represented by InMO3(ZnO) (m>0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In2SnO5(ZnO) (n>0 and n is an integer) may be used. 5(ZnO) n (n>0, and n is an integer) may be used.

[0109] For example, oxides of the In-Ga-Zn system with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5), or In:Ga:Zn = 3:1:2 (= 1 / 2:1 / 6:1 / 3) and oxides in the vicinity of such compositions can be used. Alternatively, oxides of the In-Sn-Zn system with an atomic ratio of In:Sn:Zn = 1:1:1 (= 1 / 3: 1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2), or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) and oxides in the vicinity of such compositions may be used. However, transistors using indium-containing oxide semiconductors are not limited to these, and those with an appropriate composition may be used according to the required electrical characteristics (such as field-effect mobility, threshold value, variation, etc.). Also, in order to obtain the required electrical characteristics, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. appropriate. For example, in a transistor using an In-Sn-Zn-based oxide semiconductor, a relatively high field-effect mobility can be obtained relatively easily. However, even in a transistor using an In-Ga-Zn-based oxide semiconductor, the field-effect mobility can be increased by reducing the defect density in the bulk. Incidentally, for example, the composition of an oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = a:b:c (a + b + c = 1) and the composition of an oxide with an atomic ratio of In:Ga:Zn = A:B:C (A + B + C

[0110]

[0111]

[0112] ​​​​​​​​​​​= 1), a, b, and c are in the vicinity of the oxide composition (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 It means that the following condition is satisfied. For example, r can be set to 0.05. The same is true for other oxides.

[0113] In addition, the oxide insulating layer 406 and / or the oxide semiconductor layer 408 may be formed by Heat treatment is carried out to remove excess hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation). The temperature of the heat treatment is preferably 300° C. or higher and 700° C. or lower, or lower than the distortion point of the substrate. The heat treatment can be carried out under reduced pressure or in a nitrogen atmosphere. It is possible to remove hydrogen, an impurity that gives the mold its electrical conductivity.

[0114] Note that the heat treatment for dehydration or dehydrogenation is performed after the oxide insulating layer and / or the oxide semiconductor layer The step may be performed at any time in the manufacturing process of the transistor as long as it is performed after the film formation. The heat treatment for dehydration or dehydrogenation may be carried out multiple times or may be carried out in combination with other heat treatments. .

[0115] Note that in the case where the oxide insulating layer includes an oxygen excess region, the heat treatment for dehydration or dehydrogenation is When the oxide insulating layer and the oxide semiconductor layer are processed into islands, the oxide insulating layer This is preferable because it is possible to prevent oxygen from being released by the heat treatment.

[0116] In heat treatment, nitrogen or rare gases such as helium, neon, argon, water, hydrogen, etc. It is preferable that the nitrogen, helium, or neon introduced into the heat treatment device is not included. , the purity of noble gases such as argon should be 6N (99.9999%) or higher, preferably 7N (99. 99999%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). This is preferred.

[0117] Also, after heating the oxide semiconductor layer 408 by heat treatment, the heating temperature is maintained, or the same furnace is gradually cooled from the heating temperature while introducing high-purity oxygen gas, high-purity nitrous oxide gas, or ultra-dry air (the moisture content measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method is 20 ppm or lower (dew point conversion -55 °C), preferably 1 ppm or lower, more preferably 10 ppb or lower of air). It is preferable that oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Or, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment apparatus should be 6N or higher, preferably 7N or higher (i.e., the impurity concentration in the oxygen gas or nitrous oxide gas is 1 ppm or lower, preferably 0.1 ppm or lower). By supplying oxygen, which is the main component material constituting the oxide semiconductor and has simultaneously decreased due to the elimination process of impurities by dehydration or dehydrogenation treatment, the oxide semiconductor layer can be made highly pure and i-type (intrinsic). This is preferred. Due to the action of oxygen gas or nitrous oxide gas, the main component material constituting the oxide semiconductor, which is oxygen, is simultaneously decreased due to the elimination process of impurities by dehydration or dehydrogenation treatment. By supplying oxygen, the oxide semiconductor layer can be made highly pure and i-type (intrinsic). This can be achieved.

[0118] Also, since there is a possibility that oxygen, which is the main component material constituting the oxide semiconductor, is simultaneously desorbed and decreased due to dehydration or dehydrogenation treatment, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film.

[0119] Oxygen is introduced into the oxide semiconductor layer that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film, by which the oxide semiconductor layer can be purified to high purity and made intrinsic (i-type). A transistor having a high-purity and intrinsic (i-type) oxide semiconductor has suppressed fluctuations in electrical characteristics and is electrically stable.

[0120] When introducing oxygen into the oxide semiconductor layer 408, it may be directly introduced into the oxide semiconductor layer 408, or it may be introduced into the oxide semiconductor layer 408 through an insulating layer formed later. As a method for introducing oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions), ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, etc. can be used. Also, for the oxygen introduction treatment, a gas containing oxygen can be used. As the gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. Further, in the oxygen introduction treatment, a rare gas may be included in the gas containing oxygen.

[0121] For example, when implanting oxygen ions into the oxide semiconductor layer 408 by the ion implantation method, the dose amount should be 1×10 13 ions / cm 2 or more and 5×10 16 ions / cm 2 or less.

[0122] Alternatively, the oxide insulating layer 406 in contact with the oxide semiconductor layer is made into a layer containing an oxygen-excess region, and by performing heat treatment in a state where the oxide insulating layer 406 and the oxide semiconductor layer 408 are in contact, oxygen excessively contained in the oxide insulating layer 406 is diffused into the oxide semiconductor layer 408, and the oxide semi- conductor layer 408 is made intrinsic (i-type). Oxygen may be supplied to the conductor layer 408. This heat treatment can also be combined with other heat treatments in the manufacturing process of the transistor.

[0123] To provide an oxygen-excess region in the oxide insulating layer 406, for example, the oxide insulating layer may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the oxide insulating layer after film formation to form an oxygen-excess region in the oxide insulating layer 406.

[0124] The supply of oxygen to the oxide insulating layer 406 or the oxide semiconductor layer 408 is not particularly limited as long as it is after the film formation of the oxide insulating layer or the oxide semiconductor layer. Also, the introduction of oxygen may be performed multiple times.

[0125] Next, a conductive film is formed on the oxide semiconductor layer 408 and processed to form a source electrode layer 410a and a drain electrode layer 410b (see Fig. 3(C)).

[0126] As the source electrode layer 410a and the drain electrode layer 410b, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Also, a configuration in which a high melting point metal film such as Ti, Mo, W or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) of these is laminated on one or both of the lower side and the upper side of a metal film such as Al, Cu may be used. Further, the source electrode layer 410a and the drain electrode layer 410b may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ) Indium tin oxide (In2O3 - SnO2), indium zinc oxide (In 2O3 - ZnO), or a material in which silicon oxide is added to these metal oxide materials can be used. This is possible.

[0127] Also, as the source electrode layer 410a and the drain electrode layer 410b, an In - Ga - Zn - O film containing nitrogen, an In - Sn - O film containing nitrogen, an In - Ga - O film containing nitrogen, an I n - Zn - O film containing nitrogen, an Sn - O film containing nitrogen, an In - O film containing nitrogen, etc., that is, a metal nitride film can be used. Since these films contain the same constituent elements as the oxide semiconductor layer 408, the interface with the oxide semiconductor layer 408 can be stabilized. For example, as the source electrode layer 410a and the drain electrode layer 410b, a laminated structure of an In - Ga - Zn - O film containing nitrogen and a tungsten film can be applied from the side in contact with the oxide semiconductor layer 408. This is possible.

[0128] Next, an oxide insulating layer 412 is formed so as to cover the source electrode layer 410a, the drain electrode layer 410b, and the exposed oxide semiconductor layer 4 08. The oxide insulating layer 412 can be formed by the same material and the same manufacturing method as the oxide insulating layer 406. This is possible.

[0129] Thereafter, a protective insulating layer 414 is formed on the oxide insulating layer 412 (see Fig. 3(D)).

[0130] As the protective insulating layer 414, it can be formed by plasma CVD method or sputtering method, and a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, an oxynitride silicon film, an oxynitride aluminum film, or a silicon oxynitride film, etc., can be used. However, the protective insulating layer 414 is preferably a silicon film containing nitrogen, more preferably a silicon nitride film. This is possible. By using a layer containing this, it is possible to further reduce electrostatic breakdown during the manufacturing process of the semiconductor device or for the formed semiconductor device, which is preferable.

[0131] As described above, the transistor 310 of the present embodiment can be formed.

[0132] <Example Configuration 3 of Semiconductor Device> Examples of the configuration of the transistor 320 are shown in FIGS. 10(A) to 10(C). FIG. 10(A) is a plan view of the transistor 320, FIG. 10(B) is a cross-sectional view taken along the dashed line X3 - Y3 in FIG. 10(A), and FIG. 10(C) is a cross-sectional view taken along the dashed line V3 - W3 in FIG. 10(A).

[0133] Similar to the transistor 300 in FIG. 1, the transistor 320 shown in FIG. 10 includes a gate electrode layer 402 provided on a substrate 400 having an insulating surface, a gate insulating layer 404 on the gate electrode layer 402, an oxide insulating layer 406 on the gate insulating layer 404, an oxide semiconductor layer 408 in contact with and overlapping the gate electrode layer 402 on the oxide insulating layer 406, and a source electrode layer 410a and a drain electrode layer 410b electrically connected to the oxide semiconductor layer 408. Further, an oxide insulating layer 412 covering the source electrode layer 410a and the drain electrode layer 410b and in contact with the oxide semiconductor layer 408, and a protective insulating layer 414 on the oxide insulating layer 412 may be components of the transistor 320. The transistor 320 is different from the transistor 300 in the structure of the gate insulating layer 404 and the oxide semiconductor layer 408. That is, in the transistor 320, the gate insulating layer 404

[0134] ​​​​​​​​The gate insulating layer 404c in contact with the gate electrode layer 402, and the gate insulating layer 404a on the gate insulating layer 404c, and the gate insulating layer 404b provided between the gate insulating layer 404a and the oxide insulating layer 406. Further, in the transistor 320, the oxide semiconductor layer 408 is composed of an oxide semiconductor layer 408a in contact with the oxide insulating layer 406 and an oxide semiconductor layer 408b in contact with the oxide insulating layer 412, similar to the transistor 310.

[0135] Note that, in the transistor 320, the configurations other than the gate insulating layer 404 and the oxide semiconductor layer 408 are the same as those of the transistor 300, and the description of the transistor 300 can be referred to.

[0136] Also, the configuration of the oxide semiconductor layer 408 included in the transistor 320 is the same as that of the transistor 310, and the description of the transistor 310 can be referred to. However, in the transistor 320, in the oxide semiconductor layer 408b, the thickness of the region in contact with the oxide insulating layer 412 is smaller than the thickness of the region in contact with the source electrode layer 410a and the drain electrode layer 410b. This is exemplified. The region with a small thickness is formed by partially etching during the processing of the conductive film that becomes the source electrode layer 410a and the drain electrode layer 410b, or by performing an etching process on the exposed region of the oxide semiconductor layer 408b after forming the source electrode layer 410a and the drain electrode layer 410b. The region with a small thickness is a region that functions as the channel formation region of the transistor 320. By reducing the thickness of the channel formation region, the source electrode layer 410a and the drain electrode layer 410 ​​​​​​​​​​​​​The resistance of the region in contact with b can be reduced as compared with the channel formation region. Thus, it is possible to reduce the contact resistance with the source electrode layer 410a and the drain electrode layer 410b. The gate insulating layer 404 included in the transistor 320 includes a gate insulating layer 404c in contact with the gate electrode layer 402, a gate insulating layer 404a in contact with the gate insulating layer 404c, and a gate insulating layer 404b in contact with the oxide insulating layer 406. It is possible.

[0137] In this embodiment, silicon nitride films are used as the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 404b, and each gate insulating layer is continuously formed by plasma CVD. First, after forming a silicon nitride film that becomes the gate insulating layer 404c using a mixed gas of silane (SiH4) and nitrogen (N2) as the supply gas, the supply gas is switched to a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3) to form a silicon nitride film that becomes the gate insulating layer 404a. Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2) to form a silicon nitride film that becomes the gate insulating layer 404b. The gate insulating layer 404c formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) can reduce ammonia in the film formation atmosphere and in the film as compared with the gate insulating layer 404a formed by supplying at least a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3). Ammonia becomes a ligand of a metal complex due to the action of the lone pair electrons on the nitrogen atom. Thus, for example, when copper is used as the gate electrode layer 402, ammonia It is configured to include.

[0138] In this embodiment, silicon nitride films are used as the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 404b, and each gate insulating layer is continuously formed by plasma CVD. First, after forming a silicon nitride film that becomes the gate insulating layer 404c using a mixed gas of silane (SiH4) and nitrogen (N2) as the supply gas, the supply gas is switched to a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3) to form a silicon nitride film that becomes the gate insulating layer 404a. Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2) to form a silicon nitride film that becomes the gate insulating layer 404b. First, a silicon nitride film that becomes the gate insulating layer 404c is formed using a mixed gas of silane (SiH4) and nitrogen (N2) as the supply gas. After that, the supply gas is switched to a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3) to form a silicon nitride film that becomes the gate insulating layer 404a. Then, the supply gas is switched to a mixed gas of silane (SiH4) and nitrogen (N2) to form a silicon nitride film that becomes the gate insulating layer 404b. The gate insulating layer 404c formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) can reduce ammonia in the film formation atmosphere and in the film as compared with the gate insulating layer 404a formed by supplying at least a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3). Ammonia becomes a ligand of a metal complex due to the action of the lone pair electrons on the nitrogen atom. Thus, for example, when copper is used as the gate electrode layer 402, ammonia It is possible to reduce the contact resistance with the source electrode layer 410a and the drain electrode layer 410b.

[0139] The gate insulating layer 404c formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) can reduce ammonia in the film formation atmosphere and in the film as compared with the gate insulating layer 404a formed by supplying at least a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3). Ammonia becomes a ligand of a metal complex due to the action of the lone pair electrons on the nitrogen atom. Thus, for example, when copper is used as the gate electrode layer 402, ammonia The gate insulating layer 404c formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) can reduce ammonia in the film formation atmosphere and in the film as compared with the gate insulating layer 404a formed by supplying at least a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3). Ammonia becomes a ligand of a metal complex due to the action of the lone pair electrons on the nitrogen atom. Thus, for example, when copper is used as the gate electrode layer 402, ammonia The gate insulating layer 404c formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) can reduce ammonia in the film formation atmosphere and in the film as compared with the gate insulating layer 404a formed by supplying at least a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3). Ammonia becomes a ligand of a metal complex due to the action of the lone pair electrons on the nitrogen atom. Thus, for example, when copper is used as the gate electrode layer 402, ammonia The gate insulating layer 404c formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) can reduce ammonia in the film formation atmosphere and in the film as compared with the gate insulating layer 404a formed by supplying at least a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3). Ammonia becomes a ligand of a metal complex due to the action of the lone pair electrons on the nitrogen atom. Thus, for example, when copper is used as the gate electrode layer 402, ammonia The gate insulating layer 404c formed by supplying a mixed gas of silane (SiH4) and nitrogen (N2) can reduce ammonia in the film formation atmosphere and in the film as compared with the gate insulating layer 404a formed by supplying at least a mixed gas of silane (SiH4), nitrogen (N2), and ammonia (NH3). Ammonia becomes a ligand of a metal complex due to the action of the lone pair electrons on the nitrogen atom. Thus, for example, when copper is used as the gate electrode layer 402, ammonia When a gate insulating layer with a high ammonia content is provided in a manner that contacts the gate electrode layer, copper may diffuse into the gate insulating layer due to the reaction shown in the following formula ( 1).

[0140]

Equation

[0141] In the transistor 320 shown in FIG. 10, at least a gate insulating layer 404c with an ammonia content lower than that of the gate insulating layer 404a is provided in a manner that contacts the gate electrode layer 402. By doing so, diffusion of the material (e.g., copper) of the gate electrode layer 402 into the gate insulating layer 404 can be suppressed. That is, the gate insulating layer 404c can function as a barrier film against the metal material constituting the gate electrode layer 402. By providing the gate insulating layer 404c, the reliability of the transistor can be further improved.

[0142] Note that in the gate insulating layer 404 included in the transistor 320, the configurations of the gate insulating layer 404 a and the gate insulating layer 404b can be the same as those of the transistor 310. By including a gate insulating layer having the above-described configuration, electrostatic breakdown of the transistor can be prevented, and stable electrical characteristics can be imparted to the transistor, making it possible to obtain a highly reliable semiconductor device.

[0143] The film thickness of the gate insulating layer 404c is 30 nm or more and 100 nm or less, preferably 30 nm or more and 50 nm or less. Also, as described above, the film thickness of the gate insulating layer 404a provided as a countermeasure against electrostatic breakdown of the transistor is preferably 300 nm or more and 400 nm or less, and oxidation ​​​The gate insulating layer 404 that functions as a barrier film to prevent the diffusion of hydrogen into the oxide semiconductor layer 408 The film thickness of b is preferably 25 nm or more and 150 nm or less. However, the gate insulating layer 4 04 (the total film thickness of the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 404b is preferably adjusted as appropriate so that the film thickness is 355 nm or more and 550 nm or less.

[0144] 〈Configuration Example 4 of Semiconductor Device〉 Configuration examples of the transistor 330 are shown in FIGS. 11(A) to 11(C). FIG. 11(A) is a plan view of the transistor 330, FIG. 11(B) is a cross-sectional view taken along the dashed line X4 - Y4 in FIG. 11(A), and FIG. 11(C) is a cross-sectional view taken along the dashed line V4 - W4 in FIG. 11(A).

[0145] The transistor 330 shown in FIG. 11 includes a gate electrode layer 402 provided on a substrate 400 having an insulating surface, a gate insulating layer 404 on the gate electrode layer 402, an oxide insulating layer 406 on the gate insulating layer 404, an oxide semiconductor layer 408 in contact with and overlapping the gate electrode layer 402 on the oxide insulating layer 406, a source electrode layer 410a and a drain electrode layer 410b electrically connected to the oxide semiconductor layer 408, an oxide insulating layer 412 covering the source electrode layer 410a and the drain electrode layer 410b and in contact with the oxide semiconductor layer 408, and a protective insulating layer 414 on the oxide insulating layer 412.

[0146] In the transistor 330, the protective insulating layer 414 has a laminated structure of a protective insulating layer 414a in contact with the oxide insulating layer 412 and a protective insulating layer 414b on the protective insulating layer 414a, and silicon nitride films can be applied to each of them. ​​​​​​​​​​

[0147] As the protective insulating layer 414a, the same configuration as the gate insulating layer 404b of the transistor 310 can be adopted. By providing the protective insulating layer 414a, it is possible to suppress the incorporation of hydrogen or hydrogen compounds into the oxide insulating layer 412 and the oxide semiconductor layer 408, so that the electrical characteristics of the transistor can be further stabilized.

[0148] As the protective insulating layer 414b, the same configuration as the gate insulating layer 404a of the transistor 310 can be adopted. By providing the protective insulating layer 414b, it becomes possible to further reduce electrostatic breakdown of the semiconductor device during the manufacturing process or after formation.

[0149] In addition, other components of the transistor 330 can have the same configuration as the transistor 310, and the description of the transistor 310 can be referred to.

[0150] Although the transistors shown in FIGS. 1, 2, 10, and 11 each have a partially different configuration, one aspect of the present invention is not particularly limited, and various combinations are possible.

[0151] The transistor shown in this embodiment includes a thick silicon film containing nitrogen (for example, 325 nm or more and 550 nm or less) as a gate insulating layer, and one or more metal elements selected from the constituent elements of the oxide semiconductor layer are included between the gate insulating layer and the oxide semiconductor layer. It is configured to include an oxide insulating layer formed. The silicon film containing nitrogen can be formed by applying a mass production technology that has been put into practical use. Also, by providing the silicon film containing nitrogen as a thick film, the gate insulating layer is physically thickened, and a decrease in the breakdown voltage of the transistor is suppressed. , Furthermore, the breakdown voltage can be improved to suppress electrostatic breakdown of the semiconductor device. Also , by including an oxide insulating layer, the interface with the oxide semiconductor layer can be stabilized, and trapping of charges at the interface can be suppressed. Therefore, deterioration of the transistor can be prevented, and a highly reliable transistor can be obtained.

[0152] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0153] (Embodiment 2) A semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistor shown in Embodiment 1. Also, part or all of the drive circuit including the transistor can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0154] In FIG. 4(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the substrate 4001, and is sealed by the substrate 4006. In FIG. 4(A) , an IC chip, or a scanning line drive circuit 4004 and a signal line drive circuit 4003 formed of a single-crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate are mounted in a region different from the region surrounded by the sealing material 4005 on the substrate 4001. Also, various signals and potentials applied to the pixel portion 4002 through the signal line drive circuit 4003 and the scanning line drive circuit 4004 are supplied from FPC (Flexible printed circuit) 4018a, 4 018b.

[0155] In FIGS. 4(B) and 4(C), the pixel portion 4002 provided on the substrate 4001 and the scanning A sealing material 4005 is provided so as to surround the wiring inspection drive circuit 4004. Also, a substrate 4006 is provided on the pixel portion 4002 and the scanning line drive circuit 4004. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the display element by the substrate 4001, the sealing material 4005, and the substrate 4006. In FIGS. 4(B) and 4(C), in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, an IC chip, or a single-crystal semiconductor film or a polycrystalline semiconductor film formed on a separately prepared substrate is mounted with a signal line drive circuit 4003. In FIGS. 4(B) and 4(C), various signals and potentials supplied to the pixel portion 4002 through the signal line drive circuit 4003 and the scanning line drive circuit 4004 are supplied from the FPC 4018. Also, in FIGS. 4(B) and 4(C), an example is shown in which the signal line drive circuit 4003 is separately formed and mounted on the substrate 4001, but the present invention is not limited to this configuration. The scanning line drive circuit may be separately formed and mounted, or only a part of the signal line drive circuit or only a part of the scanning line drive circuit may be separately formed and mounted. In addition, the connection method of the separately formed drive circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method, etc. can be used. FIG. 4(A) is an example of mounting the signal line drive circuit 4003 and the scanning line drive circuit 4004 by the COG method,

[0156] FIG. 4(B) is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 4(C is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 4(C is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 4(C is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 4(C

[0157] Note that the connection method of the separately formed drive circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method, etc. can be used. FIG. 4(A) is an example of mounting the signal line drive circuit 4003 and the scanning line drive circuit 4004 by the COG method, FIG. 4(B) is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 4(C is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 4(C is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 4(C is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 4(C ) is an example of implementing the signal line driving circuit 4003 by the TAB method.

[0158] Note that the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted thereon. That is, the display device described in this specification refers to an image display device, a display device, or a light source (including a lighting device). In addition, not only the panel in a state where the display element is sealed, but also a module to which a connector, for example, an FPC or a TCP is attached, a module in which a printed wiring board is provided at the tip of the TCP or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG method shall all be included in the display device.

[0159] In addition, the pixel portion and the scanning line driving circuit provided on the substrate have a plurality of transistors, and the transistors shown in Embodiment 1 can be applied.

[0160] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element ( also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. In addition, a display medium such as an electronic ink display device (electronic paper) whose contrast changes by an electric action can also be applied.

[0161] One form of the semiconductor device will be described with reference to FIGS. 4 to 6. FIG. 6 corresponds to a cross-sectional view taken along line M-N in FIG. 4(B). -N.

[0162] ​As shown in FIGS. 4 and 6, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 4016. The connection terminal electrodes 4015 and the terminal electrodes 4016 are electrically connected to the terminals of the FPCs 4018 and 4018b via an anisotropic conductive layer 4019.

[0163] The connection terminal electrode 4015 is formed of the same conductive layer as the first electrode layer 4034, and the terminal electrode 4 016 is formed of the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011.

[0164] Also, the pixel portion 4002 provided on the substrate 4001 and the scanning line driving circuit 4004 have a plurality of transistors. In FIG. 6, the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scanning line driving circuit 4004 are illustrated. In FIG. 6(A ), an oxide insulating layer 4030 and a protective insulating layer 40 32 are provided on the transistors 4010 and 4011. In FIG. 6(B), an insulating layer 40 21 that functions as a planarization insulating layer is further provided.

[0165] As the transistors 4010 and 4011, the transistors shown in Embodiment 1 can be applied. In this embodiment, an example of applying a transistor having the same structure as the transistor 300 shown in Embodiment 1 is shown. The transistors 4010 and 4011 are transistors having a bottom gate structure.

[0166] The transistors 4010 and 4011 include, as an insulating layer in contact with the oxide semiconductor layer, an oxide insulating layer 4020b and an oxide insulating layer 4030, which are selected from the constituent elements of the oxide semiconductor layer. An oxide insulating layer containing one or more metal elements is applied, and a gate insulating layer 4020a and The silicon film has a thick film (for example, a film thickness of 325 nm or more and 550 nm or less) containing nitrogen. Therefore, the transistors 4010 and 4011 are transistors in which fluctuations in electrical characteristics are suppressed. The electrical resistance is controlled and electrostatic damage is suppressed.

[0167] In addition, the oxide semiconductor layer of the transistor 4011 for the driver circuit overlaps with a channel formation region of the oxide semiconductor layer. A conductive layer may be further provided at a position overlapping with the channel formation region of the oxide semiconductor layer. By providing the transistor 4011 at a position closer to the threshold voltage, the amount of change in the threshold voltage of the transistor 4011 can be further reduced. In addition, the conductive layer can be electrically connected to the gate electrode layer of the transistor 4011. It may be the same or different and may also function as the second gate electrode layer. The potential of the conductive layer may be in a floating state.

[0168] The conductive layer also shields the external electric field, i.e., prevents the external electric field from reaching the internal (including the transistor) It also has a function (particularly an electrostatic shielding function against static electricity) to prevent the electrical resistance of the device from acting on other components (including the circuitry). The shielding function of the conductive layer prevents the transistor from being electrically damaged by external electric fields such as static electricity. Fluctuations in characteristics can be prevented.

[0169] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display an image. can be used.

[0170] FIG. 6(A) shows an example of a liquid crystal display device using a liquid crystal element as a display element. Here, the liquid crystal element 4013 includes a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer 4008. Insulating layers 4 038 and 4033 that function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the substrate 4006 side , and the first electrode layer 4034 and the second electrode layer 4031 are laminated via the liquid crystal layer 4008 to form a structure.

[0171] Also, the spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Note that spherical spacers may be used.

[0172] When using a liquid crystal element as a display element, thermotropic liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials may be low molecular weight compounds or high molecular weight compounds . These liquid crystal materials (liquid crystal compositions) may exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

[0173] Also, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008 . In this case, the liquid crystal layer 4008, the first electrode layer 4034, and the second electrode layer 4031 have a contact structure. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. The blue phase can be expressed using a liquid crystal composition in which a liquid crystal and a chiral agent are mixed. Also, in order to widen the temperature range in which the blue phase appears, a polymerizable monomer is added to the liquid crystal composition that exhibits the blue phase It is also possible to form a liquid crystal layer by adding a polymerization initiator or the like and performing a process of polymer-stabilizing it. This can be achieved. A liquid crystal composition that exhibits a blue phase has a short response time and is optically isotropic, so no alignment treatment is required and the viewing angle dependence is small. Also, since there is no need to provide an alignment film, no rubbing treatment is required either, so it is possible to prevent electrostatic breakdown caused by the rubbing treatment, and reduce defects and breakage of the liquid crystal display device during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0174] Also, the resistivity of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. Note that the resistivity value in this specification is the value measured at 20°C.

[0175] The size of the holding capacitance provided in the liquid crystal display device is set so as to be able to hold charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion and the like. The size of the holding capacitance can be set in consideration of the off-current of the transistor and the like. By using the transistor having an oxide semiconductor layer disclosed in this specification, it is sufficient to provide a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel.

[0176] The transistor using the oxide semiconductor layer disclosed in this specification can control the current value in the off state ( off-current value) to be low. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the writing interval can also be set longer. Therefore, the frequency of the refresh operation ​​​Since it can be reduced, it has the effect of suppressing power consumption.

[0177] In addition, the transistor using the oxide semiconductor layer disclosed in this specification has a relatively high field effect mobility, so it can be driven at high speed. For example, by using such a transistor in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the drive circuit portion can be formed on the same substrate. Also, in the pixel portion as well, by using such a transistor, a high-quality image can be provided.

[0178] Liquid crystal display devices can use TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS (Fringe Field Swit ching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq uid Crystal) mode, etc.

[0179] In addition, it may be a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode. As the vertical alignment mode, several examples can be mentioned, for example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode 、ASV (Advanced Super View) mode, etc. can be used ​ Moreover, it can also be applied to VA-type liquid crystal display devices. A VA-type liquid crystal display device is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. A VA-type liquid crystal display device is a method in which liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. Moreover, pixels can be divided into several regions (sub-pixels), and a method called multi-domain or multi-domain design, which is devised to tilt the molecules in different directions, can be used.

[0180] In addition, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an anti-reflection member are appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source.

[0181] In addition, as the display method in the pixel portion, a progressive method, an interlace method, etc. can be used. Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white), or RGB with one or more additional colors such as yellow, cyan, and magenta. Note that the size of the display area may be different for each dot of the color elements. However, the disclosed invention is not limited to color display devices, and can also be applied to monochrome display devices.

[0182] In addition, as the display element included in the display device, a light-emitting element that utilizes electroluminescence can be applied. A light-emitting element that utilizes electroluminescence is a light-emitting material ​​​​​​​It is distinguished according to whether it is an organic compound or an inorganic compound. Generally, the former is an organic E L element, and the latter is called an inorganic EL element.

[0183] In an organic EL element, by applying a voltage to a light-emitting element, electrons and holes are respectively injected into a layer containing a light-emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine to form an excited state of the light-emitting organic compound and emit light when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. In the present embodiment, an example of using an organic EL element as a light-emitting element is shown.

[0184] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. A dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder and its light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, an organic EL element is used for explanation as the light-emitting element.

[0185] For a light-emitting element, at least one of a pair of electrodes may be light-transmissive in order to extract light emission. Thus, there are light-emitting elements with an upper surface emission structure in which a transistor and a light-emitting element are formed on a substrate and light emission is extracted from the surface opposite to the substrate, a lower surface emission structure in which light emission is extracted from the surface on the substrate side, and a double-sided emission structure in which light emission is extracted from the surface on the substrate side and the surface opposite to the substrate. Any light-emitting element with any emission structure can be applied. ​​​It is possible to

[0186] Figs. 5(A) and (B) and Fig. 6(B) show examples of a light-emitting device using a light-emitting element as a display element. 。

[0187] Fig. 5(A) is a plan view of the light-emitting device, and the cross-sections taken along the one-dot chain lines S1-T1, S2-T2 , and S3-T3 in Fig. 5(A) correspond to Fig. 5(B). In the plan view of Fig. 5(A), the electroluminescent layer 542 and the second electrode layer 543 are omitted and not shown.

[0188] The light-emitting device shown in Fig. 5 has a transistor 510, a capacitor element 520, and a wiring layer with an intersection 530 on a substrate 500, and the transistor 510 is electrically connected to the light-emitting element 540. Note that Fig. 5 shows a bottom-emission type light-emitting device that extracts light from the light-emitting element 540 through the substrate 500.

[0189] As the transistor 510, the transistor shown in Embodiment 1 can be applied. In this embodiment, an example of applying a transistor having the same structure as the transistor 300 shown in Embodiment 1 is shown. The transistor 510 is a transistor with a bottom gate structure.

[0190] The transistor 510 includes a gate electrode layer 511a, 511b, a gate insulating layer 502, an oxide insulating layer 512, an oxide semiconductor layer 514, and a conductive layer 513a, 513b that functions as a source electrode layer or a drain electrode layer.

[0191] The transistor 510 has an oxide insulating layer 51 2, which is an insulating layer in contact with the oxide semiconductor layer 514, and contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer 514. An oxide insulating layer is applied, and as the gate insulating layer 502, it includes a silicon film containing nitrogen with a thick film thickness (for example, a film thickness of 32 5 nm or more and 550 nm or less). By adopting such a configuration, the trapping of charges at the interface between the oxide semiconductor layer 514 and the oxide insulating layer 512 can be suppressed, and the electrical characteristics of the transistor 510 can be improved. Also, the electrostatic breakdown of the transistor 51 0 can be prevented. Therefore, it becomes possible to provide a highly reliable semiconductor device with a high yield. Note that, as the insulating layer 524 in contact with the oxide semiconductor layer 514, it is preferable to apply an oxide insulating layer having the same configuration as the oxide insulating layer 512. Also, as the insulating layer 525 in contact with the insulating layer 524, it is preferable to apply an insulating layer having the same configuration as the gate insulating layer 502.

[0192] The capacitor element 520 includes conductive layers 521a, 521b, a gate insulating layer 502, an oxide insulating layer 52 2, an oxide semiconductor layer 526, and a conductive layer 523. A capacitor is formed by sandwiching the gate insulating layer 502, the oxide insulating layer 522, and the oxide semiconductor layer 526 between the conductive layers 521a, 521b and the conductive layer 5 23.

[0193] The wiring layer intersection 530 is the intersection of the gate electrode layers 511a, 511b and the conductive layer 533. The gate electrode layers 511a, 511b and the conductive layer 533 intersect with each other with the gate insulating layer 502 interposed therebetween.

[0194] In this embodiment, a titanium film with a thickness of 30 nm is used as the gate electrode layer 511a and the conductive layer 521a, and a copper thin film with a thickness of 200 nm is used as the gate electrode layer 511b and the conductive layer 521b. Therefore, the gate electrode layer has a laminated structure of a titanium film and a copper thin film.

[0195] As the oxide semiconductor layers 514 and 526, an In-Ga-Zn-O film with a thickness of 25 nm is used. .

[0196] An interlayer insulating layer 504 is formed over the transistors 510, the capacitive elements 520, and the wiring layer intersection 530. A color filter layer 505 is provided in a region that overlaps with the light-emitting element 540 over the interlayer insulating layer 504. An insulating layer 506 that functions as a planarizing insulating layer is provided over the interlayer insulating layer 504 and the color filter layer 505. An insulating layer 506 that functions as a planarizing insulating layer is provided over the interlayer insulating layer 504 and the color filter layer 505. An insulating layer 506 that functions as a planarizing insulating layer is provided over the interlayer insulating layer 504 and the color filter layer 505.

[0197] A light-emitting element 540 including a stacked structure in which a first electrode layer 541, a light-emitting layer 542, and a second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The light-emitting element 540 and the transistor 510 are electrically connected by contact between the first electrode layer 541 and the conductive layer 513a at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening. A light-emitting element 540 including a stacked structure in which a first electrode layer 541, a light-emitting layer 542, and a second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The light-emitting element 540 and the transistor 510 are electrically connected by contact between the first electrode layer 541 and the conductive layer 513a at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening. A light-emitting element 540 including a stacked structure in which a first electrode layer 541, a light-emitting layer 542, and a second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The light-emitting element 540 and the transistor 510 are electrically connected by contact between the first electrode layer 541 and the conductive layer 513a at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening. A light-emitting element 540 including a stacked structure in which a first electrode layer 541, a light-emitting layer 542, and a second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The light-emitting element 540 and the transistor 510 are electrically connected by contact between the first electrode layer 541 and the conductive layer 513a at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening. A light-emitting element 540 including a stacked structure in which a first electrode layer 541, a light-emitting layer 542, and a second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The light-emitting element 540 and the transistor 510 are electrically connected by contact between the first electrode layer 541 and the conductive layer 513a at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening. A light-emitting element 540 including a stacked structure in which a first electrode layer 541, a light-emitting layer 542, and a second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The light-emitting element 540 and the transistor 510 are electrically connected by contact between the first electrode layer 541 and the conductive layer 513a at an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening.

[0198] As the insulating layer 506, a photosensitive acrylic film with a thickness of 1500 nm can be used, and as the partition wall 507, a photosensitive polyimide film with a thickness of 1500 nm can be used. As the insulating layer 506, a photosensitive acrylic film with a thickness of 1500 nm can be used, and as the partition wall 507, a photosensitive polyimide film with a thickness of 1500 nm can be used.

[0199] As the color filter layer 505, for example, a colored light-transmitting resin can be used. As the colored light-transmitting resin, a photosensitive or non-photosensitive organic resin can be used, but using a photosensitive organic resin layer can reduce the number of resist masks, so the process is simplified and preferable. As the colored light-transmitting resin, a photosensitive or non-photosensitive organic resin can be used, but using a photosensitive organic resin layer can reduce the number of resist masks, so the process is simplified and preferable. As the colored light-transmitting resin, a photosensitive or non-photosensitive organic resin can be used, but using a photosensitive organic resin layer can reduce the number of resist masks, so the process is simplified and preferable. As the colored light-transmitting resin, a photosensitive or non-photosensitive organic resin can be used, but using a photosensitive organic resin layer can reduce the number of resist masks, so the process is simplified and preferable.

[0200] Colors other than achromatic colors such as black, gray, and white are chromatic colors, and the color filter layer is formed of a material that transmits only the colored chromatic light. As chromatic colors, red, green, blue, etc. can be used. Also, cyan, magenta, yellow (amber), etc. may be used. Transmitting only the colored chromatic light means that the transmitted light in the color filter layer has a peak at the wavelength of the chromatic light. The color filter layer may appropriately control the optimal film thickness in consideration of the relationship between the concentration of the coloring material to be included and the light transmittance. For example, the film thickness of the color filter layer 505 may be 1500 nm or more and 2000 nm or less. In the light-emitting device shown in FIG. 6(B), the light-emitting element 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The configuration of the light-emitting element 4513 is a stacked structure of the first electrode layer 4034, the electroluminescent layer 4511, and the second electrode layer 4031, but is not limited to the shown

[0201] configuration. The configuration of the light-emitting element 4513 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4513, etc. The partition walls 4510 and 507 are formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form openings on the first electrode layers 4034 and 541, and to form the side walls of the openings as inclined surfaces having a continuous curvature. The electroluminescent layers 4511 and 542 may be configured by a single layer or may be configured by laminating a plurality of layers. To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting elements 4513 and 540, a second

[0202] The partition walls 4510 and 507 are formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form openings on the first electrode layers 4034 and 541, and to form the side walls of the openings as inclined surfaces having a continuous curvature. The electroluminescent layers 4511 and 542 may be configured by a single layer or may be configured by laminating a plurality of layers.

[0203] The electroluminescent layers 4511 and 542 may be configured by either a single layer or a structure in which a plurality of layers are laminated. It doesn't matter which one.

[0204] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting elements 4513 and 540, a second A protective film may be formed on the electrode layers 4031 and 543 and the partition walls 4510 and 507. The protective film may be formed of a silicon nitride film, a silicon oxynitride film, a DLC film, or the like. .

[0205] Further, a layer containing an organic compound that covers the light-emitting elements 4513 and 540 may be formed by vapor deposition so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting elements 4513 and 540. .

[0206] Further, a filling material 4514 is provided and sealed in the space sealed by the substrates 4001, the substrate 4006, and the sealing material 4005. In this way, it is highly airtight so as not to be exposed to the outside air, and it is preferable to package (encase) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. .

[0207] As the filling material 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), an acrylic resin, poly imide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate copolymer) can be used. For example, nitrogen can be used as the filling material. .

[0208] Further, if necessary, a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or other optical films may be appropriately provided on the light-emitting surface of the light-emitting element. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, an antiglare treatment can be performed to diffuse reflected light due to surface irregularities and reduce reflection. .

[0209] Also, as a display device, it is also possible to provide electronic paper that drives electronic ink. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantages of being as easy to read as paper, having lower power consumption than other display devices, and being thin and light in shape.

[0210] Although various forms of electrophoretic display devices can be considered, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0211] The above microcapsules dispersed in a solvent are called electronic ink. Color display is also possible by using color filters or particles having dyes.

[0212] In FIGS. 4 to 6, as the substrates 4001, 500, and 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having translucency can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, if translucency is not required, a metal substrate (metal film) such as aluminum or stainless steel can be used. ​ This is also acceptable. For example, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can also be used.

[0213] In addition, the insulating layers 4021 and 506 that function as a planarization insulating layer can be made of heat-resistant organic materials such as acrylic resin, polyimide, benzocyclobutene-based resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (low-k materials) such as siloxane-based resin, PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass) can also be used. Note that the insulating layers 4021 and 506 can be formed by laminating a plurality of insulating layers formed of these materials.

[0214] The method for forming the insulating layers 4021 and 506 is not particularly limited, and depending on the material, sputtering, spin coating, dipping, spray coating, droplet discharge method (inkjet method), screen printing, offset printing, etc. can be used.

[0215] The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 can be made of conductive materials having translucency such as indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium, indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and graphene.

[0216] In addition, the first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 are made of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium ( V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver ( Ag), or other metals, or alloys thereof, or one or more metal nitrides thereof can be used to form.

[0217] In this embodiment, since the light-emitting device shown in FIG. 5 is a bottom emission type, the first electrode layer 541 has translucency, and the second electrode layer 543 has reflectivity. Therefore, when a metal film is used for the first electrode layer 541, the film thickness is made thin enough to maintain translucency, and when a conductive layer having translucency is used for the second electrode layer 543, a conductive layer having reflectivity may be laminated. When using a conductive layer having translucency for the second electrode layer 543, a conductive layer having reflectivity may be laminated. In addition, the first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 can be formed using a conductive composition containing a highly conductive molecule (also referred to as a conductive polymer). As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example,

[0218] polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers composed of two or more of aniline, pyrrole, and thiophene or their derivatives can be used. derivatives, or copolymers composed of two or more of aniline, pyrrole, and thiophene or their derivatives, or copolymers composed of two or more of aniline, pyrrole, and thiophene or their derivatives, etc. can be mentioned.

[0219] A protection circuit for protecting the drive circuit may also be provided. The protection circuit is preferably configured using a non-linear element. configured using a non-linear element.

[0220] By applying the transistor shown in Embodiment 1 as described above, a semiconductor device having various functions can be provided. provided.

[0221] The configurations, methods, etc. shown in this embodiment can be appropriately combined with those shown in other embodiments and used together. It can be used in combination.

[0222] (Embodiment 3) Using the transistor shown in Embodiment 1, a semiconductor device having an image sensor function for reading information on an object can be manufactured. It can be manufactured.

[0223] FIG. 7(A) shows an example of a semiconductor device having an image sensor function. FIG. 7(A) is an equivalent circuit of a photosensor, and FIG. 7(B) is a cross-sectional view showing a part of the photosensor. It is a cross-sectional view showing a part of the photosensor.

[0224] One electrode of the photodiode 602 is electrically connected to the photodiode reset signal line 658, and the other electrode is electrically connected to the gate of the transistor 640. One of the source or drain of the transistor 640 is electrically connected to the photosensor reference signal line 672, and the other of the source or drain is electrically connected to one of the source or drain of the transistor 656. One of the source or drain of the transistor 640 is electrically connected to the photosensor reference signal line 672, and the other of the source or drain is electrically connected to one of the source or drain of the transistor 656. One of the source or drain of the transistor 640 is electrically connected to the photosensor reference signal line 672, and the other of the source or drain is electrically connected to one of the source or drain of the transistor 656. The gate of the transistor 656 is electrically connected to the gate signal line 659, and the other of the source or drain is electrically connected to the photosensor output signal line 671. The gate of the transistor 656 is electrically connected to the gate signal line 659, and the other of the source or drain is electrically connected to the photosensor output signal line 671.

[0225] In the circuit diagrams in this specification, as can be clearly determined, the symbol of the transistor using the oxide semiconductor layer is described as "OS". In FIG. 7(A), the transistors 640 and 656 can be the transistors shown in Embodiment 1 and are transistors using an oxide semiconductor layer. In FIG. 7(A), the transistors 640 and 656 can be the transistors shown in Embodiment 1 and are transistors using an oxide semiconductor layer. In this embodiment, the transistors have the same structure as the transistor 300 shown in Embodiment 1 and are transistors using an oxide semiconductor layer. In this embodiment, the transistors have the same structure as the transistor 300 shown in Embodiment 1. An example of application is shown. The transistor 640 is a transistor with a bottom gate structure.

[0226] FIG. 7(B) is a cross-sectional view showing the photodiode 602 and the transistor 640 in the photosensor, wherein a photodiode 602 and a transistor 640 that function as sensors are provided on a substrate 601 (element substrate) having an insulating surface. On the photodiode 602 and the transistor 640, a substrate 613 is provided using an adhesive layer 608.

[0227] An insulating layer 631, an insulating layer 632, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided on the transistor 640. The photodiode 602 is formed on the interlayer insulating layer 633. An electrode layer 641b, a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c laminated in this order on the electrode layer 641b, and an electrode layer 642 provided on the interlayer insulating layer 634 and electrically connected to the electrode layer 641b through the first to third semiconductor films. And an electrode layer 641a provided in the same layer as the electrode layer 641b and electrically connected to the electrode layer 642.

[0228] The electrode layer 641b is electrically connected to a conductive layer 643 formed in the interlayer insulating layer 634, and the electrode layer 642 is electrically connected to a conductive layer 645 through the electrode layer 641a. The conductive layer 645 is electrically connected to the gate electrode layer of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640.

[0229] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity type, and the second semiconductor film As the high-resistance semiconductor film (i-type semiconductor film) 606b and the third semiconductor film 606c, a pin-type photodiode in which semiconductor films having an n-type conductivity type are laminated is exemplified.

[0230] The first semiconductor film 606a is a p-type semiconductor film and can be formed of an amorphous silicon film containing an impurity element that imparts a p-type. For the formation of the first semiconductor film 606a, a semiconductor material gas containing a group 13 impurity element (for example, boron (B)) is used, and it is formed by plasma CVD method . Silane (SiH4) may be used as the semiconductor material gas. Or, S i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Also , after forming an amorphous silicon film not containing an impurity element, an impurity element may be introduced into the amorphous silicon film by a diffusion method or an ion implantation method. After introducing an impurity element by an ion implantation method or the like, heating or the like may be performed to diffuse the impurity element. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor growth method, or a sputtering method or the like may be used. The film thickness of the first semiconductor film 606a is preferably formed to be 10 nm or more and 5 0 nm or less.

[0231] The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is formed of an amorphous silicon film. For the formation of the second semiconductor film 606b, an amorphous silicon film is formed by plasma CVD method using a semiconductor material gas. As the semiconductor material gas, silane (SiH4) may be used. Or, Si2H6, SiH2Cl2, SiHCl3, S iCl4, SiF4, etc. may also be used. The formation of the second semiconductor film 606b is by an LPCVD method, The second semiconductor film 606b may be formed by vapor deposition, sputtering, or the like. It is preferable to form the film so that the thickness is 00 nm or more and 1000 nm or less.

[0232] The third semiconductor film 606c is an n-type semiconductor film, and is an amorphous film containing an impurity element that imparts n-type conductivity. The third semiconductor film 606c is formed of a fast silicon film. It is formed by the plasma CVD method using a semiconductor material gas containing silicon (e.g. phosphorus (P)). Silane (SiH4) can be used as the semiconductor material gas. SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain elements, the material is then doped with silicon using diffusion or ion implantation. An impurity element may be introduced into the amorphous silicon film by ion implantation or the like. After the element is introduced, the impurity element may be diffused by heating or the like. The method for forming the amorphous silicon film includes the LPCVD method, the vapor phase growth method, or the sputtering method. The thickness of the third semiconductor film 606c is 20 nm or more and 200 nm or less. It is preferable to form it so that the bottom is facing downward.

[0233] The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are Instead of an amorphous semiconductor, a polycrystalline semiconductor may be used. Semiconductor Amorphous Semiconductor (SAS) It may be formed using a conductor.

[0234] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so Photodiodes exhibit better characteristics when the p-type semiconductor film side is used as the light receiving surface. From the surface of the substrate 601 on which the in-type photodiode is formed, the photodiode 602 This example shows how the light received by the semiconductor film is converted into an electrical signal. Since light from the semiconductor film side having the pattern becomes disturbance light, the electrode layer uses a conductive layer with light blocking properties. In addition, the n-type semiconductor film side can be used as the light receiving surface.

[0235] The transistor 640 includes an oxide insulating layer 621 which is an insulating layer in contact with the oxide semiconductor layer 623. The oxide semiconductor layer 623 may be formed of an oxide semiconductor material having a thickness of 100 nm or more. Therefore, a charge is generated at the interface between the oxide semiconductor layer 623 and the oxide insulating layer 621. This can suppress trapping of the ions, thereby stabilizing the electrical characteristics of the transistor 640. In addition, the transistor 640 has a thick gate insulating layer 620 (for example, The film thickness is 325 nm to 550 nm. It is possible to prevent electrostatic damage to the transistor 640. As a result, highly reliable semiconductor devices can be provided with a high yield.

[0236] The insulating layer 631, the insulating layer 632, the interlayer insulating layer 633, and the interlayer insulating layer 634 are made of insulating materials. Depending on the material, sputtering, plasma CVD, spin coating, Dip, spray coating, droplet ejection method (inkjet method), screen printing, offset The insulating layer 11 can be formed by using inkjet printing or the like.

[0237] Note that the insulating layer 631 in contact with the oxide semiconductor layer 623 has the same structure as the oxide semiconductor layer 623. It is preferable to apply an oxide insulating layer containing one or more metal elements selected from constituent elements. Further, as the insulating layer 632 in contact with the insulating layer 631, it is preferable to provide a silicon film containing nitrogen.

[0238] As the interlayer insulating layers 633 and 634, an insulating layer that functions as a planarizing insulating layer to reduce surface irregularities is preferable. As the interlayer insulating layers 633 and 634, for example, organic insulating materials having heat resistance such as polyimide, acrylic resin, benzocyclobutene-based resin, polyamide, and epoxy resin can be used. In addition to the above organic insulating materials, single layers or laminates of low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. By detecting the light 622 incident on the photodiode 602, information on the object to be detected can be read. Note that a light source such as a backlight can be used when reading information on the object to be detected.

[0239]

[0240] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0241] (Embodiment 4) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, audio playback devices, and gaming machines. ​​​​​​​​​​​​Examples include game cabinets such as pachinko machines and slot machines. Specific examples of these electronic devices are shown in FIG. 8.

[0242] FIG. 8(A) shows a table 9000 having a display unit. The table 9000 has a display unit 9003 incorporated in a housing 9001, and the display unit 9003 can display an image. Note that a configuration is shown in which the housing 9001 is supported by four legs 9002. The housing 9001 also has a power cord 9005 for power supply.

[0243] The semiconductor device shown in any of the above embodiments can be used for the display unit 9003 and can impart high reliability to an electronic device.

[0244] The display unit 9003 has a touch input function. By touching a display button 9004 displayed on the display unit 9003 of the table 9000 with a finger or the like, screen operations and information input can be performed, and communication with other household appliances or control can be enabled, so that it may also be used as a control device for controlling other household appliances by screen operations. For example, by using the semiconductor device having the image sensor function

[0245] shown in Embodiment 3, the display unit 9003 can be provided with a touch input function. Also, the screen of the display unit 9003 can be set perpendicular to the floor

[0246] by a hinge provided on the housing 9001, and it can also be used as a televisionFIG. 8B shows a television device 9100. The television device 9100 includes: A display unit 9103 is incorporated in the housing 9101, and an image is displayed on the display unit 9103. In this example, the case 9101 is supported by a stand 9105. This shows the composition of the

[0247] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by the remote control operation device 9110. The channel and volume can be controlled by the 9109, and the display 9103 shows In addition, the remote control unit 9110 can control the image displayed on the remote control unit 9110. A display unit 9107 for displaying information output from 9110 may be provided.

[0248] A television device 9100 shown in FIG. 8(B) includes a receiver, a modem, and the like. The vision device 9100 can receive general television broadcasts using a receiver, and further By connecting to a wired or wireless communication network via a modem, Information from sender to receiver) or bidirectional (between sender and receiver, or between receivers) It is also possible to carry out communication.

[0249] The semiconductor device shown in any of the above embodiments can be used for the display portions 9103 and 9107. This makes it possible to provide high reliability to the television device and the remote control device. Cut.

[0250] FIG. 8C shows a computer, which includes a main body 9201, a housing 9202, a display unit 9203, and a keyboard. It includes a board 9204, an external connection port 9205, a pointing device 9206, etc.

[0251] The semiconductor device shown in any of the above embodiments can be used for the display unit 9203, and can provide high reliability to a computer.

[0252] FIGS. 9(A) and 9(B) are foldable tablet terminals. FIG. 9(A) shows the open state, and the tablet terminal includes a housing 9630, a display unit 9631a, a display unit 963 1b, a display mode switch 9034, a power switch 9035, a power saving mode switch 9036, a fastener 9033, and an operation switch 9038.

[0253] The semiconductor device shown in any of the above embodiments can be used for the display unit 9631a and the display unit 9631b, and can be made into a highly reliable tablet terminal.

[0254] A part of the display unit 9631a can be made into a touch panel area 9632a, and data can be input by touching the displayed operation keys 9638. Note that in the display unit 963 1a, as an example, a configuration in which half of the area has only a display function and the other half of the area has a touch panel function is shown, but it is not limited to this configuration. It is also possible to configure the entire area of the display unit 963 1a to have a touch panel function. For example, the entire surface of the display unit 96 31a can be made to display keyboard buttons to serve as a touch panel, and the display unit 9631b can be used as a display screen.

[0255] Also, in the display unit 9631b, similar to the display unit 9631a, a part of the display unit 9631b can be made into a touch panel area 9632b. Also, the keyboard of the touch panel By touching the position where the switching button 9639 is displayed with a finger or a stylus, etc., keyboard buttons can be displayed on the display unit 9631b.

[0256] Also, simultaneous touch input can be performed on the touch panel area 9632a and the touch panel area 9632b.

[0257] Also, the display mode switching switch 9034 can select switching of the display orientation such as vertical display or horizontal display, switching between black and white display and color display, etc. The power saving mode switching switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built into the tablet terminal during use. The tablet terminal can incorporate not only the optical sensor but also other detection devices such as sensors for detecting inclination such as gyroscopes and acceleration sensors.

[0258] Also, in FIG. 9(A), an example where the display areas of the display unit 9631b and the display unit 9631a are the same is shown, but it is not particularly limited, and the size of one and the size of the other may be different, and the quality of the display may also be different. For example, one may be a display panel that can perform higher-definition display than the other.

[0259] FIG. 9(B) shows a closed state, and the tablet terminal includes a housing 9630, a solar cell 963 3, and a charge / discharge control circuit 9634. In FIG. 9(B), a configuration having a battery 9635 and a DCDC converter 9636 as an example of the charge / discharge control circuit 9634 is shown

[0260] Since the tablet terminal can be folded in two, when not in use, the housing 9630 is in a closed state. ​​​​​​​​This is possible. Therefore, since the display units 9631a and 9631b can be protected, a tablet terminal with excellent durability and reliability from the perspective of long-term use can be provided.

[0261] In addition, the tablet terminal shown in FIGS. 9(A) and 9(B) can also have functions such as displaying various types of information ( still images, moving images, text images, etc.), a function of displaying a calendar, date, or time on a display unit, a touch input function of touching or editing the information displayed on the display unit, a function of controlling processing by various software (programs), and so on.

[0262] Power can be supplied to a touch panel, a display unit, a video signal processing unit, etc. by a solar cell 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 can be provided on one side or both sides of the housing 9630, and can efficiently charge the battery 9635. As the battery 9635, using a lithium-ion battery has advantages such as enabling miniaturization.

[0263] Also, regarding the configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 9(B), a block diagram is shown in FIG. 9(C) and will be described. FIG. 9(C) shows the solar cell 9633, the battery 9635, the DCDC converter 9636, the converter 9637, the switches SW1 to SW3, and the display unit 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 correspond to the parts of the charge / discharge control circuit 963 4 shown in FIG. 9(B).

[0264] First, an example of the operation when power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell is made into a voltage for charging the battery 9635 by the DCD C converter 9636. When the power from the solar cell 9633 is used for the operation of the display unit 9631, the switch SW1 is turned on, and the converter 96 37 steps up or down the voltage to the voltage required for the display unit 9631. Also, when the display on the display unit 96 31 is not performed, SW1 may be turned off and SW2 may be turned on to charge the battery 96 35.

[0265] Note that the solar cell 9633 is shown as an example of a power generation means, but it is not particularly limited, and the battery 9635 may be charged by other power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). For example, a contactless power transmission module that wirelessly (non - contact) transmits and receives power for charging, or a configuration that combines other charging means may be used. and performs charging, or a configuration that combines other charging means may be used.

[0266] The configurations, methods, etc. shown in this embodiment can be appropriately combined with the configurations, methods, etc. shown in other embodiments and used.

Example

[0267] In this example, the evaluation results of the film quality of a silicon nitride film formed by the plasma CVD method will be described. Specifically, the results of ESR measurement of a silicon nitride film formed using a mixed gas of silane and nitrogen as the supply gas, and a silicon nitride film formed using a mixed gas of silane, nitrogen, and ammonia as the supply gas are shown.

[0268] In the present embodiment, the method for preparing the samples used in the ESR measurements will be described below.

[0269] For the ESR measurement, samples 1 and 2 were prepared by depositing a silicon nitride film with a thickness of 300 nm on a quartz substrate. The silicon nitride film was formed by placing a quartz substrate in the deposition chamber of a plasma CVD apparatus. The pressure in the deposition chamber was controlled to 100 Pa, and the temperature was increased to 2000 Hz with a 27.12 MHz high frequency power source. A power of 1000 W was supplied to the substrate. The substrate temperature was set to 350° C. The plasma CVD apparatus was Electrode area is 6000cm 2 The sample 1 is a parallel plate type plasma CVD apparatus. The supply gas was a mixture of silane and nitrogen. The gas mixture was a mixture of nitrogen and ammonia. The deposition conditions for each sample are shown in Table 1 below.

[0270] [Table 1]

[0271] The ESR measurements were performed on the prepared samples 1 to 5 under the following conditions: The measurement temperature was -170°C, and the 9.2GHz high-frequency power (microwave power) was The magnetic field was set to 1 mW, and the direction of the magnetic field was set parallel to the surfaces of the silicon nitride films of the samples 1 to 5. , which corresponds to the signal appearing at g=2.003 originating from the Nc center contained in the silicon nitride film. The detection limit for the spin density is 8.1×10 15 spins / cm 3 It is.

[0272] The results of the ESR measurement are shown in Fig. 12(A). The spin density of the Nc center in sample 1 is 2.7×10 17 spins / cm 3 It was confirmed that it is a silicon nitride film with many defects in the film. On the other hand, in Samples 2 to 5 containing ammonia in the supply gas, the spin density derived from the Nc center is 5.1 ×10 ×10 16 spins / cm 3 (Sample 2), 5.2×10 16 spins / cm 3 (Sample 3), 6.0×10 16 spins / cm 3 (Sample 4), 5.5×10 16 spins / cm 3 (Sample 5), showing a uniformly low value regardless of the ammonia flow rate, and it was confirmed that it is a silicon nitride film with reduced defects in the film.

[0273] Also, the first derivative curve obtained by ESR measurement is shown in FIG. 12(B). From FIG. 12(B), at a g value of 2.003, a signal derived from defects (Nc center) in the film was detected with strong intensity in Sample 1. On the other hand, in Samples 2 to 5, it was confirmed that the signal intensity at a g value of 2.003 is small.

[0274] From the above, by using a mixed gas of silane, nitrogen, and ammonia as the supply gas when forming a silicon nitride film by the plasma CVD method, it was shown that it is possible to form a silicon nitride film with reduced defects in the film. By using the silicon nitride film as a gate insulating layer, it is possible to realize a gate insulating layer with good breakdown voltage, and it is suggested that it is possible to make a transistor including the gate insulating layer have good ESD resistance.

Example

[0275] In this example, the characteristics of the silicon nitride film formed by the plasma CVD method as a barrier film The evaluation results are shown in Figure 13. The evaluation method was Thermal Desorption Spectroscopy (TDS) Used.

[0276] In this example, a silicon nitride film was formed on a quartz substrate by plasma CVD. Evaluations were performed using Samples 1 to 8. The methods for preparing the samples are described below.

[0277] The silicon nitride film was formed by placing a quartz substrate in the deposition chamber of a plasma CVD apparatus. The pressure is controlled to 100 Pa, and 2000 W of power is supplied by a 27.12 MHz high frequency power source. The substrate temperature was set to 350° C. The plasma CVD apparatus had an electrode area of ​​60 00cm 2 This is a parallel plate type plasma CVD device.

[0278] For sample 6, the supply gas was a mixture of silane, nitrogen and ammonia (SiH4 flow rate 200 scc m: N2 flow rate 2000sccm: NH3 flow rate 2000sccm) and the film thickness was 300nm. A silicon nitride film was formed.

[0279] For sample 7, the supply gas was a mixture of silane, nitrogen and ammonia (SiH4 flow rate 200 scc m: N2 flow rate 2000sccm: NH3 flow rate 2000sccm) and the film thickness was 275nm. After the first silicon nitride film was formed, the supply gas was changed to a mixture of silane and nitrogen in the same deposition chamber. Gas (SiH4 flow rate 200sccm:N2 flow rate 5000sccm) with a film thickness of 50nm A second silicon nitride film was formed.

[0280] For sample 8, the supply gas was a mixture of silane, nitrogen and ammonia (SiH4 flow rate 200 scc (with an N2 flow rate of 2000 sccm and an NH3 flow rate of 2000 sccm), a first silicon nitride film with a film thickness of 275 nm was formed, and then, in the same film formation chamber, the flow rate of ammonia was reduced to a SiH4 flow rate of 200 sccm, an N2 flow rate of 2000 sccm, and an NH3 flow rate of 100 sccm to form a second silicon nitride film with a film thickness of 50 nm.

[0281] Fig. 13 shows the evaluation results of the TDS measurement at M / z = 2 (H2) for each sample. Fig. 13(A ) shows the evaluation results of the TDS measurement at M / z = 2 (H2) for Sample 6 and Sample 7 fabricated in this example, and Fig. 13(B) shows the evaluation results of the TDS measurement at M / z = 2 (H2) for Sample 6 and Sample 8.

[0282] From Fig. 13(A) and Fig. 13(B), in Sample 6 where a single layer of a silicon nitride film with a high hydrogen concentration in the film was provided, hydrogen release was confirmed by heat treatment. On the other hand, in Sample 7 and Sample 8 where a silicon nitride film with a reduced hydrogen concentration in the film was laminated on the upper layer, hydrogen release was not observed around 450 °C at which hydrogen release was confirmed in Sample 6, and even after further heat treatment, it was confirmed that the hydrogen release was extremely reduced.

[0283] Therefore, it was shown that by providing a silicon nitride film with a reduced hydrogen concentration on the upper layer in contact with a silicon nitride film with a high hydrogen concentration, a hydrogen blocking effect (barrier effect) is achieved.

[0284] As shown in Example 1, a silicon nitride film formed by plasma CVD using silane, nitrogen, and ammonia as supply gases is a film with high dielectric breakdown voltage with reduced defects in the film. Thus, ​​​Then, a silicon nitride film with reduced defects in the film and a silicon nitride film with reduced hydrogen concentration are laminated. The structure in which they are laminated can reduce the release of hydrogen that can be a donor of the oxide semiconductor layer while maintaining high ESD resistance, so it can be preferably applied as a gate insulating layer of a transistor.

Explanation of symbols

[0285] 300 Transistor 310 Transistor 320 Transistor 330 Transistor 400 Substrate 402 Gate electrode layer 404 Gate insulating layer 404a Gate insulating layer 404b Gate insulating layer 404c Gate insulating layer 406 Oxide insulating layer 408 Oxide semiconductor layer 408a Oxide semiconductor layer 408b Oxide semiconductor layer 410a Source electrode layer 410b Drain electrode layer 412 Oxide insulating layer 414 Protection insulating layer 414a Protection insulating layer 414b Protection insulating layer 500 Substrate 502 Gate insulating layer 504 Interlayer insulating layer 505 Color filter layer 506 Insulating layer 507 Partition wall 510 Transistor 511a Gate electrode layer 511b Gate electrode layer 512 Oxide insulating layer 513a Conductive layer 513b Conductive layer 514 Oxide semiconductor layer 520 Capacity Element 521a Conductive Layer 521b Conductive Layer 522 Oxide Insulating Layer 523 Conductive Layer 524 Insulating Layer 525 Insulating Layer 526 Oxide Semiconductor Layer 530 Wiring Layer Intersection 533 Conductive Layer 540 Light Emitting Element 541 Electrode Layer 542 Electroluminescent Layer 543 Electrode Layer 601 Substrate 602 Photodiode 606a Semiconductor Film 606b Semiconductor Film 606c Semiconductor Film 608 Adhesive Layer 613 Substrate 620 Gate Insulating Layer 621 Oxide Insulating Layer 622 Light 623 Oxide Semiconductor Layer 631 Insulating Layer 632 Insulating Layer 633 Interlayer Insulating Layer 634 Interlayer Insulating Layer 640 Transistor 641a Electrode Layer 641b Electrode Layer 642 Electrode Layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode Reset Signal Line 659 Gate Signal Line 671 Photo Sensor Output Signal Line 672 Photo Sensor Reference Signal Line 4001 Substrate 4002 Pixel Section 4003 Signal Line Driving Circuit 4004 Scanning Line Driving Circuit 4005 Sealing Material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020a Gate insulating layer 4020b Oxide insulating layer 4021 Insulating layer 4030 Oxide insulating layer 4031 Electrode layer 4032 Protective insulating layer 4033 Insulating layer 4034 Electrode layer 4035 Spacer 4038 Insulating layer 4510 Partition wall 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9000 Table 9001 Housing 9002 Leg 9003 Display unit 9004 Display button 9005 Power cord 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9100 Television device 9101 Housing 9103 Display unit 9105 Stand 9107 Display unit 9109 Operation key 9110 Remote control operation unit 9201 Main body 9202 Housing 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Pointing Device 9630 Housing 9631 Display Unit 9631a Display Unit 9631b Display Unit 9632a Area 9632b Area 9633 Solar Cell 9634 Charge and Discharge Control Circuit 9635 Battery 9636 DCDC Converter 9637 Converter 9638 Operation Key 9639 Button

Claims

1. a gate electrode layer on a substrate; a first silicon nitride film on the gate electrode layer; a first oxide layer on the first silicon nitride film; a second oxide layer on the first oxide layer; and a third oxide layer on the second oxide layer; and a source or drain electrode layer on the third oxide layer; a fourth oxide layer on the source electrode layer and on the drain electrode layer; a second silicon nitride film on the fourth oxide layer; the fourth oxide layer has a region in contact with the third oxide layer between the source electrode layer and the drain electrode layer, the fourth oxide layer has a region in contact with the source electrode layer, a region in contact with the drain electrode layer, a region in contact with the second oxide layer, and a region in contact with the first oxide layer, the source electrode layer and the drain electrode layer have a structure in which a film containing Al or Cu and a film containing any of Ti, Mo, and W are stacked, the second oxide layer contains In, Ga, and Zn, and the content ratios of In and Ga are In>Ga; the third oxide layer contains In, Ga, and Zn, and the contents of In and Ga are in a range of In≦Ga; the second oxide layer is composed of nanocrystals; A semiconductor device, wherein the third oxide layer is composed of c-axis oriented crystals and nanocrystals.

2. a gate electrode layer on a substrate; a first silicon nitride film on the gate electrode layer; a first oxide layer on the first silicon nitride film; a second oxide layer on the first oxide layer; and a third oxide layer on the second oxide layer; and a source or drain electrode layer on the third oxide layer; a fourth oxide layer on the source electrode layer and on the drain electrode layer; a second silicon nitride film on the fourth oxide layer; the fourth oxide layer has a region in contact with the third oxide layer between the source electrode layer and the drain electrode layer, the fourth oxide layer has a region in contact with the source electrode layer, a region in contact with the drain electrode layer, a region in contact with the second oxide layer, and a region in contact with the first oxide layer, the source electrode layer and the drain electrode layer have a structure in which a film containing Al or Cu and a film containing any of Ti, Mo, and W are stacked, the second oxide layer contains In, Ga, and Zn, and the content ratios of In and Ga are In>Ga; the third oxide layer contains In, Ga, and Zn, and the contents of In and Ga are in a range of In≦Ga; the second oxide layer having nanocrystals; The third oxide layer has higher crystallinity than the second oxide layer and has c-axis oriented crystals.

3. a gate electrode layer on a substrate; a first silicon nitride film on the gate electrode layer; a first oxide layer on the first silicon nitride film; a second oxide layer on the first oxide layer; and a third oxide layer on the second oxide layer; and a source or drain electrode layer on the third oxide layer; a fourth oxide layer on the source electrode layer and on the drain electrode layer; a second silicon nitride film on the fourth oxide layer; the fourth oxide layer has a region in contact with the third oxide layer between the source electrode layer and the drain electrode layer, the fourth oxide layer has a region in contact with the source electrode layer, a region in contact with the drain electrode layer, a region in contact with the second oxide layer, and a region in contact with the first oxide layer, the source electrode layer and the drain electrode layer have a structure in which a film containing Al or Cu and a film containing any of Ti, Mo, and W are stacked, the second oxide layer contains In, Ga, and Zn, and the content ratios of In and Ga are In>Ga; the third oxide layer contains In, Ga, and Zn, and the contents of In and Ga are in a range of In≦Ga; the second oxide layer having nanocrystals; The third oxide layer has a higher degree of atomic order than the second oxide layer and has c-axis oriented crystals.

4. In any one of claims 1 to 3, The nanocrystals are crystals having a size of 1 nm or more and less than 10 nm.

5. In any one of claims 1 to 4, A semiconductor device, wherein the second oxide layer and / or the third oxide layer contains one or more of tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr).

Images