Indicating device

Abstract

To provide a display device capable of a problem that, as the display device becomes higher definition, the number of pixels increases, the number of gate lines, and the number of signal lines increase, and as the number of gate lines and signal lines increases, it becomes difficult to mount an IC chip that has a drive circuit to drive them by bonding or the like, resulting in an increase of manufacturing costs.SOLUTION: At least a part of a circuit of the drive circuit that has a pixel part and a drive circuit that drives the pixel part on an identical substrate is composed of a thin film transistor using an oxide semiconductor sandwiched between the gate electrodes on the top and bottom. The manufacturing cost is reduced by providing the pixel part and the drive circuit on the identical substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

Background Art

[0002] As represented by a liquid crystal display device, thin film transistors formed on a flat plate such as a glass substrate are made of amorphous silicon or polycrystalline silicon. Although thin film transistors using amorphous silicon have a low field effect mobility, they can respond to the enlargement of the area of the glass substrate. On the other hand, thin film transistors using polycrystalline silicon have a high field effect mobility, but require a crystallization process such as laser annealing and do not necessarily adapt to the enlargement of the area of the glass substrate. have characteristics such as not necessarily being suitable for the enlargement of the area of the glass substrate.

[0003] On the other hand, a technique of manufacturing a thin film transistor using an oxide semiconductor and applying it to an electronic device or an optical device has attracted attention. For example, a technique of manufacturing a thin film transistor using zinc oxide or an In-G a-Zn-O based oxide semiconductor as an oxide semiconductor film and using it for a switching element of an image display device is disclosed in Patent Document 1 and Patent Document 2.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] A thin-film transistor having a channel formation region provided in an oxide semiconductor has a higher field-effect mobility than a thin-film transistor using amorphous silicon. The oxide semiconductor film can be formed at a temperature of 300°C or lower by a sputtering method or the like, and the manufacturing process is simpler than that of a thin-film transistor using polycrystalline silicon.

[0006] Using such an oxide semiconductor, a thin-film transistor is formed on a glass substrate, a plastic substrate, or the like, and application to a display device such as a liquid crystal display, an electroluminescence display, or an electronic paper is expected.

[0007] In addition, when the display area of the display device is increased, the number of pixels increases, and the number of gate lines and signal lines increases. Furthermore, with the increase in the high definition of the display device, the number of pixels increases, and the number of gate lines and signal lines increases. When the number of gate lines and signal lines increases, it becomes difficult to mount an IC chip having a driving circuit for driving them by bonding or the like, and the manufacturing cost increases.

[0008] Therefore, one of the problems is to use a thin-film transistor using an oxide semiconductor for at least a part of the circuit of the driving circuit that drives the pixel portion to reduce the manufacturing cost.

[0009] When using a thin-film transistor using an oxide semiconductor for at least a part of the circuit of the driving circuit that drives the pixel portion, the thin-film transistor is required to have high dynamic characteristics (on characteristics and frequency characteristics (referred to as f characteristics)). One of the problems is to provide a thin-film transistor having high dynamic characteristics (on characteristics) and a driving circuit that can drive at high speed.

[0010] ​​​​​​​​​In addition, one aspect of the present invention uses an oxide semiconductor layer for a channel, and aims to provide a semiconductor device including a highly reliable thin film transistor.

Means for Solving the Problems

[0011] Gate electrodes are provided above and below the oxide semiconductor layer to improve the on characteristics and reliability of the thin film transistor.

[0012] In addition, by controlling the gate voltage applied to the upper and lower gate electrodes, the threshold voltage can be controlled. The upper and lower gate electrodes may be made conductive to have the same potential, or the upper and lower gate electrodes may be connected to separate wirings to have different potentials. For example, the threshold voltage can be made zero or close to zero, and the driving voltage can be reduced to lower the power consumption. Also, the threshold voltage can be made positive to function as an enhancement type transistor. Further, the threshold voltage can be made negative to function as a depletion type transistor.

[0013] For example, an inverter circuit (hereinafter referred to as an EDMOS circuit) can be configured by combining an enhancement type transistor and a depletion type transistor, and can be used for a driving circuit. The driving circuit includes at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the above EDMOS circuit. Also, for the switch section or the buffer section, it is preferable to use a thin film transistor capable of flowing a large on-current, and a depletion type transistor or a thin film transistor having gate electrodes above and below the oxide semiconductor layer is used.

[0014] ​​​​​​​​​​​​​​Fabricate thin film transistors with different structures on the same substrate without significantly increasing the number of processes. This is also possible. For example, for a driving circuit that requires high-speed driving, an EDMOS circuit can be configured using a thin film transistor having gate electrodes above and below an oxide semiconductor layer, and for the pixel portion, a thin film transistor having a gate electrode only below the oxide semiconductor layer may be used.

[0015] When the threshold voltage of an n-channel TFT is positive, it is defined as an enhancement-type transistor, and when the threshold voltage of an n-channel TFT is negative, it is defined as a depletion-type transistor, and this definition shall be followed throughout this specification.

[0016] In addition, the material of the gate electrode provided above the oxide semiconductor layer is not particularly limited as long as it is a conductive film, and elements selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), or alloys containing the above-described elements are used. Further, the gate electrode is not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used.

[0017] In addition, as the material of the gate electrode provided above the oxide semiconductor layer, the same material as the pixel electrode (such as a transparent conductive film in the case of a transmissive display device) can be used. For example, in the pixel portion, the gate electrode provided above the oxide semiconductor layer can be formed in the same process as the process of forming the pixel electrode that is electrically connected to the thin film transistor. By doing so, a thin film transistor having gate electrodes above and below the oxide semiconductor layer can be formed without significantly increasing the number of processes. ​​​​​​​​​​​​​In addition, by providing a gate electrode above the oxide semiconductor layer, Bias-thermal stress test (hereinafter referred to as BT test) for investigating the reliability of thin-film transistors In the BT test, the change in the threshold voltage of thin-film transistors before and after the test is reduced. That is, by providing a gate electrode above the oxide semiconductor layer, This can improve reliability.

[0018] The configuration of the invention disclosed in this specification includes a first gate electrode on an insulating surface; A first insulating layer is provided above the first insulating layer, and a source electrode or a drain electrode is provided above the first insulating layer. an oxide semiconductor layer above the first electrode and the drain electrode; a second insulating layer covering the oxide semiconductor layer; A second gate electrode is formed above the second insulating layer, and an oxide semiconductor layer is formed above the first insulating layer. The first gate electrode and the second gate electrode overlap each other. At least a portion of the oxide semiconductor layer is connected to a source electrode. The second gate electrode is disposed between the oxide semiconductor layer and the first gate electrode. The semiconductor device is characterized in that the first and second poles overlap each other.

[0019] The above configuration solves at least one of the above problems.

[0020] In the above structure, the width of the second gate electrode is wider than the width of the first gate electrode. Thus, a voltage can be applied to the entire oxide semiconductor layer from the second gate electrode.

[0021] Alternatively, in the above configuration, the width of the first gate electrode is narrower than the width of the second gate electrode. By doing so, the area overlapping with the source electrode or drain electrode is reduced, thereby reducing the parasitic capacitance. Furthermore, the width of the second gate electrode can be set to be equal to or smaller than the width between the source electrode and the drain electrode. By making it narrower than the gap, it may be configured to further reduce the parasitic capacitance so as not to overlap with the source electrode or the drain electrode. The capacitance can be further reduced.

[0022] Also, the manufacturing method of the above configuration has features. The manufacturing method forms a first gate electrode on an insulating surface, forms a first insulating layer on the first gate electrode, forms a source electrode or a drain electrode on the first insulating layer, performs plasma treatment on the first insulating layer, the source electrode, and the drain electrode, then forms an oxide semiconductor layer on the source electrode and the drain electrode, forms a second insulating layer covering the oxide semiconductor layer, and forms a second gate electrode on the second insulating layer. This is a method for manufacturing a semiconductor device. In this manufacturing method, by manufacturing the second gate electrode using the same material and the same mask as the pixel electrode, it can be manufactured without significantly increasing the number of processes. A first insulating layer is formed on the first gate electrode, a source electrode or a drain electrode is formed on the first insulating layer, plasma treatment is performed on the first insulating layer, the source electrode, and the drain electrode, an oxide semiconductor layer is formed on the source electrode and the drain electrode, a second insulating layer covering the oxide semiconductor layer is formed, and a second gate electrode is formed on the second insulating layer. A semiconductor device manufacturing method. After performing plasma treatment on the first insulating layer, the source electrode, and the drain electrode, an oxide semiconductor layer is formed on the source electrode and the drain electrode, a second insulating layer covering the oxide semiconductor layer is formed, and a second gate electrode is formed on the second insulating layer. An oxide semiconductor layer is formed on the source electrode and the drain electrode, a second insulating layer covering the oxide semiconductor layer is formed, and a second gate electrode is formed on the second insulating layer. A semiconductor device manufacturing method. In this manufacturing method, by manufacturing the second gate electrode using the same material and the same mask as the pixel electrode, it can be manufactured without significantly increasing the number of processes. It can be manufactured.

[0023] Also, the configuration of another invention has a pixel portion and a driving circuit. The pixel portion has a first thin film transistor having at least a first oxide semiconductor layer, and the driving circuit has an EDMOS circuit having a second thin film transistor having at least a second oxide semiconductor layer and a third thin film transistor having a third oxide semiconductor layer. The third thin film transistor has a first gate electrode below the third oxide semiconductor layer and a second gate electrode above the third oxide semiconductor layer. At least a part of the third oxide semiconductor layer is disposed between the source electrode and the drain electrode, and the second gate electrode overlaps the third oxide semiconductor layer and the first gate electrode. A semiconductor device having a first thin film transistor having at least a first oxide semiconductor layer. The driving circuit has an EDMOS circuit having a second thin film transistor having at least a second oxide semiconductor layer and a third thin film transistor having a third oxide semiconductor layer. The third thin film transistor has a first gate electrode below the third oxide semiconductor layer and a second gate electrode above the third oxide semiconductor layer. At least a part of the third oxide semiconductor layer is disposed between the source electrode and the drain electrode, and the second gate electrode overlaps the third oxide semiconductor layer and the first gate electrode. A semiconductor device having a third oxide semiconductor layer disposed between the source electrode and the drain electrode. The second gate electrode overlaps the third oxide semiconductor layer and the first gate electrode. A semiconductor device.

[0024] In the above configuration, the first thin film transistor in the pixel portion is electrically connected to the pixel electrode. The electrode can be made of the same material as the second gate electrode of the driving circuit without increasing the number of manufacturing steps. It can be manufactured.

[0025] In the above configuration, the first thin film transistor in the pixel portion is electrically connected to the pixel electrode, and the pixel electrode is made of a material different from that of the second gate electrode of the driving circuit. For example, the pixel electrode is a transparent conductive film and the second gate electrode is an aluminum film, so that the resistance of the second gate electrode of the driving circuit can be reduced.

[0026] Also, the third oxide semiconductor layer of the driving circuit overlaps with the first gate electrode via the first insulating layer and also overlaps with the second gate electrode via the second insulating layer, which is a so-called dual gate structure structure.

[0027] In addition, as a semiconductor device having a driving circuit, in addition to a liquid crystal display device, a light emitting display device using a light emitting element and a display device also called an electronic paper using an electrophoretic display element are exemplified including.

[0028] Note that the display device in this specification refers to an image display device, a light emitting device, or a light source (including a lighting device). Also, a connector, for example, an FPC (Flexible printed circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached Module, a module provided with a printed wiring board at the tip of the TAB tape or TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method are all included in the display device.

[0029] ​​​In a light-emitting display device using a light-emitting element, the pixel portion has a plurality of thin film transistors, and in the pixel portion, there is a location where the gate electrode of a certain thin film transistor is electrically connected to the source wiring or the drain wiring of another transistor. Moreover, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor.

[0030]

[0031] The oxide semiconductor used in this specification forms a thin film represented by InMO3(ZnO) (m>0), and a thin film transistor using the thin film as a semiconductor layer is manufactured. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, there may be cases where other metal elements such as Ga and Ni or Ga and Fe are included. In the above oxide semiconductor, in addition to the metal elements included as M, there are those containing Fe, Ni, other transition metal elements, or oxides of the transition metals as impurity elements. In this specification, this thin film is also referred to as an In-Ga-Zn-O-based non-single crystal film. m

[0032] After forming the In-Ga-Zn-O-based non-single crystal film by sputtering, annealing is performed at 200°C to 500°C, typically 300°C to 400°C for 10 minutes to 100 minutes. Note that the In-Ga-Zn-O-based non-single crystal film has an amorphous structure as observed by XRD analysis.

[0033] Oxide semiconductors typified by In-Ga-Zn-O-based non-single crystal films are materials with a wide energy gap ( Eg), so even if two gate electrodes are provided above and below the oxide semiconductor layer, the increase in off current can be suppressed.

[0034] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate unique names as matters specific to identifying the invention in this specification.

Advantages of the Invention

[0035] By forming a peripheral circuit such as a gate line driving circuit or a source line driving circuit, or a pixel portion, with a thin film transistor using an oxide semiconductor sandwiched between two gate electrodes above and below, the manufacturing cost can be reduced.

[0036] Also, by using a thin film transistor using an oxide semiconductor sandwiched between two gate electrodes above and below, in the BT test, the amount of change in the threshold voltage of the thin film transistor before and after the BT test can be reduced. That is, the reliability can be improved by using a thin film transistor using an oxide semiconductor sandwiched between two gate electrodes above and below.

Brief Description of the Drawings

[0037]

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Best Mode for Carrying Out the Invention

[0038] This embodiment will be described below. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the content of the embodiments shown below. It will be easily understood by those skilled in the art. Therefore, the present invention should not be construed as being limited to the content of the embodiments shown below. It will be easily understood by those skilled in the art. Therefore, the present invention should not be construed as being limited to the content of the embodiments shown below. It will not be construed as being limited to the content of the embodiments shown below.

[0039] (Embodiment 1) FIG. 1(A) shows an example in which a first thin film transistor 430 used for a driving circuit and a second thin film transistor 170 used for a pixel portion are provided on the same substrate. Note that FIG. 1(A) is an example of a cross-sectional view of a display device. The pixel portion and the driving circuit are formed on the same substrate. In the pixel portion, the on / off switching of voltage application to the pixel electrode 110 is switched using a second thin film transistor 170 which is an enhancement type transistor arranged in a matrix. The second thin film transistor 170 arranged in this pixel portion uses an oxide semiconductor layer 103, and the electrical characteristics of the second thin film transistor have an on / off ratio of 10 or more at a gate voltage of ±20 V, so that the contrast of the display can be improved, and further, since the leakage current is small, low power consumption driving can be realized. The on / off ratio is the ratio of the off current to the on current (Ioff / Ion), and it is an example of a cross-sectional view of a display device.

[0040] The pixel portion and the driving circuit are formed on the same substrate. In the pixel portion, the on / off switching of voltage application to the pixel electrode 110 is switched using a second thin film transistor 170 which is an enhancement type transistor arranged in a matrix. The second thin film transistor 170 arranged in this pixel portion uses an oxide semiconductor layer 103, and the electrical characteristics of the second thin film transistor have an on / off ratio of 10 or more at a gate voltage of ±20 V, so that the contrast of the display can be improved, and further, since the leakage current is small, low power consumption driving can be realized. The second thin film transistor 170 arranged in this pixel portion uses an oxide semiconductor layer 103, and the electrical characteristics of the second thin film transistor have an on / off ratio of 10 or more at a gate voltage of ±20 V, so that the contrast of the display can be improved, and further, since the leakage current is small, low power consumption driving can be realized. The second thin film transistor 170 arranged in this pixel portion uses an oxide semiconductor layer 103, and the electrical characteristics of the second thin film transistor have an on / off ratio of 10 or more at a gate voltage of ±20 V, so that the contrast of the display can be improved, and further, since the leakage current is small, low power consumption driving can be realized. The electrical characteristics of the second thin film transistor have an on / off ratio of 10 or more at a gate voltage of ±20 V, so that the contrast of the display can be improved, and further, since the leakage current is small, low power consumption driving can be realized. 9 or more, so that the contrast of the display can be improved, and further, since the leakage current is small, low power consumption driving can be realized. The electrical characteristics of the second thin film transistor have an on / off ratio of 10 or more at a gate voltage of ±20 V, so that the contrast of the display can be improved, and further, since the leakage current is small, low power consumption driving can be realized. The on / off ratio is the ratio of the off current to the on current (I ON / I OFF ) and It can be said that the larger it is, the better the switching characteristics are, which contributes to improving the contrast of the display. Note that the on-current refers to the current flowing between the source electrode and the drain electrode when the transistor is in the on state. Also, the off-current refers to the current flowing between the source electrode and the drain electrode when the transistor is in the off state. For example, in the case of an n-type transistor, it is the current flowing between the source electrode and the drain electrode when the gate voltage is lower than the threshold voltage of the transistor. As described above, in order to achieve high contrast and low power consumption driving, it is preferable to use an enhancement-type transistor in the pixel portion. In the driving circuit, at least one thin film transistor 430 having a first gate electrode 401 below the oxide semiconductor layer 405 and a second gate electrode 470 above the oxide semiconductor layer 405 is used. This second gate electrode 470 can also be called a back gate electrode. By forming the back gate electrode, the change amount of the threshold voltage of the thin film transistor in the bias-temperature stress test (hereinafter referred to as the BT test) before and after the BT test can be reduced. The structure of this thin film transistor 430 will be described with reference to FIG. 1(A). The first gate electrode 401 provided on the substrate 400 having an insulating surface is covered with the first gate insulating layer 403, and the first wiring 409 or the second wiring 410 is provided on the first gate insulating layer 403 overlapping the first gate electrode 401. The first wiring 409 or the second wiring 410 functioning as a source electrode or a drain electrode has an oxide semiconductor layer 405 thereon.

[0041]

[0042] It has a second gate insulating layer 412 that covers the layer 405. Also, on the second gate insulating layer 412 it has a second gate electrode 470.

[0043] Also, the first gate electrode 401 and the second gate electrode 470 may be electrically connected to have the same potential. When they have the same potential, a gate voltage can be applied from above and below the oxide semiconductor layer, so that the current flowing in the on state can be increased.

[0044] Also, a control signal line for shifting the threshold voltage to minus is electrically connected to either the first gate electrode 401 or the second gate electrode 470, thereby making it a depletion-type TFT.

[0045] Also, a control signal line for shifting the threshold voltage to plus is electrically connected to either the first gate electrode 401, or the second gate electrode 470, thereby making it an enhancement-type TFT.

[0046] Also, the combination of two thin film transistors used in the drive circuit is not particularly limited. A thin film transistor having one gate electrode may be used as a depletion-type TFT, and a thin film transistor having two gate electrodes may be used as an enhancement-type TFT. In that case, as the thin film transistor in the pixel portion, it has a structure in which gate electrodes are respectively provided above and below the oxide semiconductor layer.

[0047] Also, as the thin film transistor in the pixel portion, it has a structure in which gate electrodes are respectively provided above and below the oxide semiconductor layer, and as the enhancement-type TFT in the drive circuit, the gate electrode is made of oxide semiconductor. Structures respectively provided above and below the layer, and the gate as a depletion-type TFT of the drive circuit The structure may be such that the gate electrodes are respectively provided above and below the oxide semiconductor layer. In that case, a control signal line for controlling the threshold voltage is electrically connected to one of the upper or lower gate electrodes, and the connected gate electrode controls it.

[0048] In FIG. 1(A), the second gate electrode 470 is made of the same material as the pixel electrode 110 in the pixel portion. For example, in a transmissive liquid crystal display device, the number of processes is reduced by using a transparent conductive film, but it is not particularly limited. Also, the width of the second gate electrode 470 is wider than the width of the first gate electrode 40 1 and is further wider than the width of the oxide semiconductor layer. Although an example is shown, it is not particularly limited.

[0049] An example in which the material and width of the second gate electrode are different from those in FIG. 1(A) is shown in FIG. 1(B). Also, FIG. 1 (B) is an example of a display device having a thin film transistor 170 connected to an organic light emitting element or an inorganic light emitting element in the pixel portion.

[0050] In FIG. 1(B), the electrode 471 that functions as the second gate electrode of the thin film transistor 432 is made of a metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (N d), scandium (Sc), an element selected therefrom, or an alloy containing the above-described elements) is used, and the width of the electrode 471 in the cross section is narrower than the second gate electrode 470 in FIG. 1(A). Also, the width of the electrode 471 is narrower than the width of the oxide semiconductor layer. By narrowing the width, the area where the first wiring 409 and the second wiring 410 overlap via the second gate insulating layer 412 is reduced. It can be reduced, and the parasitic capacitance can be decreased.

[0051] The light-emitting element has at least a first electrode 472, a light-emitting layer 475, and a second electrode 474. In FIG. 1(B), the electrode 471 uses the same material as the first electrode 472 of the pixel portion, for example, , aluminum or the like, to reduce the number of processes, but it is not particularly limited. Also, in FIG. 1( B), the insulating layer 473 functions as a partition wall for insulating from the first electrodes of adjacent pixels.

[0052] Also, an example in which the material and width of the second gate electrode are different from those in FIG. 1(A) is shown in FIG. 1(C). In FIG. 1 (C), the material of the electrode 47 6 that functions as the second gate electrode of the thin-film transistor 433 is a metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd) , an element selected from scandium (Sc), or an alloy containing the above-described elements as components), and the width of the second gate electrode in the cross section is narrower than that in FIG. 1(B). By making the width even narrower than that in FIG. 1(B), the first wiring 409, and the second wiring 410 and the second gate insulating layer 412 can be prevented from overlapping, and the parasitic capacitance can be further decreased. The width of the electrode 476 shown in FIG. 1(C) is narrower than the interval between the first wiring 409 and the second wiring 410. When forming the electrode 476 with such a narrow width, it is preferable to use wet etching or the like to make the both ends of the electrode 476 located inside the resist mask end portion. However, in FIG. 1(C), since a metal material different from the pixel electrode 110 is used, The photolithography process for forming the electrode 476 is increased by one time, and one additional mask is added. This will be the case.

[0053] For a peripheral circuit such as a gate line drive circuit or a source line drive circuit used in a liquid crystal display device, a light-emitting display device, or an electronic paper, or for a pixel portion, a thin-film transistor using an oxide semiconductor sandwiched between two gate electrodes above and below is used, and high-speed driving and low power consumption can be achieved. In addition, without significantly increasing the number of processes, both a pixel portion and a drive circuit can be provided on the same substrate. By providing various circuits other than the pixel portion on the same substrate, the manufacturing cost of the display device can be reduced.

[0054] (Embodiment 2) In Embodiment 1, one thin-film transistor was described as the thin-film transistor of the drive circuit. Here, an example of configuring the inverter circuit of the drive circuit using two n-channel type thin-film transistors will be described below. Since the thin-film transistor shown in FIG. 2(A) is the same as the thin-film transistor 430 shown in FIG. 1(A) of Embodiment 1, the same parts will be described using the same reference numerals.

[0055] The drive circuit for driving the pixel portion is configured using an inverter circuit, a capacitor, a resistor, etc. When forming an inverter circuit by combining two n-channel type TFTs, there are cases of combining an enhancement type transistor and a depletion type transistor (hereinafter referred to as an EDMOS circuit), and cases of forming with enhancement type TFTs (hereinafter referred to as an EEMOS circuit).

[0056] The cross-sectional structure of the inverter circuit of the drive circuit is shown in Fig. 2(A). Note that the thin film transistors 430 and the second thin film transistor 431 are bottom gate type thin film transistors and are examples of thin film transistors in which wiring is provided under the semiconductor layer.

[0057] In Fig. 2(A), a first gate electrode 401 and a gate electrode 402 are provided on a substrate 400. The materials of the first gate electrode 401 and the gate electrode 402 can be formed as a single layer or laminated using metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or alloy materials mainly composed of these.

[0058] For example, as a two-layer laminated structure of the first gate electrode 401 and the gate electrode 402, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. As a three-layer laminated structure, it is preferable to form a laminate of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer.

[0059] Further, a first wiring 409 and a second wiring 410 are provided on a first gate insulating layer 403 covering the first gate electrode 401 and the gate electrode 402. The second wiring 410 is directly connected to the gate electrode 402 through a contact hole 404 formed in the first gate insulating layer 403.

[0060] ​​​​​​​​​ An oxide semiconductor layer 405 is provided on the first wiring 409 and the second wiring 410. A second oxide semiconductor layer 407 is provided over the third wiring 411 .

[0061] The thin film transistor 430 includes a first gate electrode 401 and a first gate insulating layer 403. The first gate electrode 401 and the oxide semiconductor layer 405 overlap each other. The first wiring 409 This power supply line is a power supply line to which a negative voltage VDL is applied (negative power supply line). It may also be a power line (ground power line).

[0062] The second thin film transistor 431 includes a gate electrode 402 and a first gate insulating layer 40 a second oxide semiconductor layer 407 overlapping the gate electrode 402 via a third wiring 4 Reference numeral 11 denotes a power supply line (positive power supply line) to which a positive voltage VDH is applied.

[0063] FIG. 2C shows a top view of the inverter circuit of the driver circuit. The cross section taken along line Z1-Z2 corresponds to FIG. 2(A).

[0064] The equivalent circuit of the EDMOS circuit is shown in Fig. 2(B). 2(B), the thin film transistor 430 is an enhancement type n-channel transistor. The second thin film transistor 431 is a depletion type n-channel transistor. This is an example of a sta.

[0065] In order to make the thin film transistor 430 an enhancement-type n-channel transistor, In this embodiment, a second gate insulating layer 412 is formed over the oxide semiconductor layer 405. A second gate electrode 470 is provided on the gate insulating layer 412, and a voltage is applied to the second gate electrode 470. The threshold value of the thin film transistor 430 is controlled by the voltage applied thereto.

[0066] Further, the second gate insulating layer 412 also functions as a protective layer covering the second oxide semiconductor layer 407. functions.

[0067] In FIGS. 2(A) and 2(C), an example is shown in which the second wiring 410 is directly connected to the gate electrode 402 through the contact hole 404 formed in the first gate insulating layer 403. However, it is not particularly limited, and a connection electrode may be separately provided to electrically connect the second wiring 410 and the gate electrode 402. However, it is not particularly limited, and a connection electrode may be separately provided to electrically connect the second wiring 410 and the gate electrode 402. electrically connected.

[0068] Further, the present embodiment can be freely combined with Embodiment 1.

[0069] (Embodiment 3) In the present embodiment, a display device will be described with reference to a block diagram and the like.

[0070] FIG. 3(A) shows an example of a block diagram of an active matrix type liquid crystal display device. FIG. 3 (A) shows a pixel portion 301 having a plurality of pixels each including a display element on a substrate 300, a scanning line driving circuit 302 for controlling scanning lines connected to the gate electrodes of the respective pixels, 301, a scanning line driving circuit 302 that controls scanning lines connected to the gate electrodes of the respective pixels, and a signal line driving circuit 303 that controls the input of a video signal to the selected pixels.

[0071] FIG. 3(B) shows an example of a block diagram of an active matrix type light emitting display device. FIG. 3 (B) shows a pixel portion 311 having a plurality of pixels each including a display element on a substrate 310, a first scanning line driving circuit 31 311 and a second scanning line driving circuit 313 that control scanning lines connected to the gate electrodes of the respective pixels, and a control circuit that controls the input of a video signal to the selected pixels. 2 and a second scanning line driving circuit 313, and controls the input of a video signal to the selected pixels. It has a signal line driving circuit 314 and a switching TFT (Thin Film Transistor) and a current control TFT arranged in one pixel. When two TFTs, a switching TFT and a current control TFT, are arranged in one pixel, in the light-emitting display device shown in FIG. 3(B), a signal input to the gate electrode of the switching TFT is generated by the first scanning line driving circuit 312, and a signal input to the second scanning line connected to the gate electrode of the current control TFT is generated by the second scanning line driving circuit 313. However, the signal input to the first scanning line and the signal input to the second scanning line may be generated by one scanning line driving circuit. Also, for example, depending on the number of TFTs of the switching element, the first scanning line used to control the operation of the switching element may be provided in plurality for each pixel. In this case, the signals input to the plurality of first scanning lines may all be generated by one scanning line driving circuit, or a plurality of scanning line driving circuits may be provided and each of them may generate the signals. Here, the form of fabricating the scanning line driving circuit 302, the first scanning line driving circuit 312, the second scanning line driving circuit 313, and the signal line driving circuits 303 and 314 in the display device is shown. However, a part of the scanning line driving circuit 302, the first scanning line driving circuit 312, or the second scanning line driving circuit 313 may be mounted with a semiconductor device such as an IC. Also, a part of the signal line driving circuits 303 and 314 may be mounted with a semiconductor device such as an IC. FIG. 4 is a diagram for explaining the positional relationship of a signal input terminal 321, a scanning line, a signal line, a protection circuit including a non-linear element, and a pixel portion that constitute a display device. On a substrate 320 having an insulating surface, a scanning line 323 and a signal line 324 are arranged to intersect, and a pixel portion 327 is formed.

[0072] Here, the form of fabricating the scanning line driving circuit 302, the first scanning line driving circuit 312, the second scanning line driving circuit 313, and the signal line driving circuits 303 and 314 in the display device is shown. However, a part of the scanning line driving circuit 302, the first scanning line driving circuit 312, or the second scanning line driving circuit 313 may be mounted with a semiconductor device such as an IC. Also, a part of the signal line driving circuits 303 and 314 may be mounted with a semiconductor device such as an IC. FIG. 4 is a diagram for explaining the positional relationship of a signal input terminal 321, a scanning line, a signal line, a protection circuit including a non-linear element, and a pixel portion that constitute a display device. On a substrate 320 having an insulating surface, a scanning line 323 and a signal line 324 are arranged to intersect, and a pixel portion 327 is formed.

[0073] FIG. 4 is a diagram for explaining the positional relationship of a signal input terminal 321, a scanning line, a signal line, a protection circuit including a non-linear element, and a pixel portion that constitute a display device. On a substrate 320 having an insulating surface, a scanning line 323 and a signal line 324 are arranged to intersect, and a pixel portion 327 is formed. That is, the scanning line 323 and the signal line 324 are arranged to intersect on the substrate 320 having an insulating surface, and the pixel portion 327 is formed. Oh, the pixel section 327 corresponds to the pixel section 301 and the pixel section 311 shown in FIG. 3.

[0074] The pixel section 301 is connected to the signal line driving circuit 303 by a plurality of signal lines S 1 to Sm (not shown) extending in the column direction, and is connected to the scanning line driving circuit 302 by a plurality of scanning lines G1 to Gn (not shown) extending in the row direction from the scanning line driving circuit 302 and has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. And each pixel is a signal line Sj ( any one of the signal lines S1 to Sm), and is connected to a scanning line Gi (any one of the scanning lines G1 to Gn ). )

[0075] The pixel section 327 is configured by arranging a plurality of pixels 328 in a matrix. Pixel 32 8 includes a pixel TFT 329 connected to the scanning line 323 and the signal line 324, a holding capacitor section 330, and a pixel electrode 331.

[0076] In the pixel configuration shown here, in the holding capacitor section 330, one electrode is connected to the pixel TFT 329 and the other electrode is connected to the capacitor line 332. Also, the pixel electrode 331 constitutes one electrode for driving a display element (liquid crystal element, light emitting element, contrast medium (electronic ink), etc.). The other electrode of these display elements is connected to the common terminal 333 .

[0077] The protection circuit is disposed between the pixel section 327 and the signal line input terminal 322. Also, it is disposed between the scanning line driving circuit and the pixel section 327. In the present embodiment, a plurality of protections ​A circuit is arranged so that a surge voltage is applied to the scanning line 323, the signal line 324, and the capacitance bus line 337 due to static electricity or the like, and the pixel TFT 329 and the like are not damaged. Therefore, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. Thus, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. Thus, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. Thus, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied.

[0078] In this embodiment, an example is shown in which a protection circuit 334 is arranged on the scanning line 323 side, a protection circuit 335 is arranged on the signal line 324 side, and a protection circuit 336 is arranged on the capacitance bus line 337. However, the arrangement position of the protection circuit is not limited to this. Further, when the scanning line driving circuit is not implemented by a semiconductor device such as an IC, the protection circuit 334 may not be provided on the scanning line 323 side. In this embodiment, an example is shown in which a protection circuit 334 is arranged on the scanning line 323 side, a protection circuit 335 is arranged on the signal line 324 side, and a protection circuit 336 is arranged on the capacitance bus line 337. However, the arrangement position of the protection circuit is not limited to this. Further, when the scanning line driving circuit is not implemented by a semiconductor device such as an IC, the protection circuit 334 may not be provided on the scanning line 323 side. In this embodiment, an example is shown in which a protection circuit 334 is arranged on the scanning line 323 side, a protection circuit 335 is arranged on the signal line 324 side, and a protection circuit 336 is arranged on the capacitance bus line 337. However, the arrangement position of the protection circuit is not limited to this. Further, when the scanning line driving circuit is not implemented by a semiconductor device such as an IC, the protection circuit 334 may not be provided on the scanning line 323 side. In this embodiment, an example is shown in which a protection circuit 334 is arranged on the scanning line 323 side, a protection circuit 335 is arranged on the signal line 324 side, and a protection circuit 336 is arranged on the capacitance bus line 337. However, the arrangement position of the protection circuit is not limited to this. Further, when the scanning line driving circuit is not implemented by a semiconductor device such as an IC, the protection circuit 334 may not be provided on the scanning line 323 side.

[0079] By using the TFTs shown in Embodiment 1 or Embodiment 2 for each of these circuits, there are the following advantages. By using the TFTs shown in Embodiment 1 or Embodiment 2 for each of these circuits, there are the following advantages.

[0080] The driving circuit is roughly classified into a logic circuit section and a switch section or a buffer section. The TFT provided in the logic circuit section is preferably configured to be able to control the threshold voltage. On the other hand, the TFT provided in the switch section or the buffer section preferably has a large on-current. By providing a driving circuit having the TFTs shown in Embodiment 1 or Embodiment 2, it becomes possible to control the threshold voltage of the TFT provided in the logic circuit section, and it becomes possible to increase the on-current of the TFT provided in the switch section or the buffer section. Furthermore, it contributes to reducing the area occupied by the driving circuit and making the bezel narrower. The driving circuit is roughly classified into a logic circuit section and a switch section or a buffer section. The TFT provided in the logic circuit section is preferably configured to be able to control the threshold voltage. On the other hand, the TFT provided in the switch section or the buffer section preferably has a large on-current. By providing a driving circuit having the TFTs shown in Embodiment 1 or Embodiment 2, it becomes possible to control the threshold voltage of the TFT provided in the logic circuit section, and it becomes possible to increase the on-current of the TFT provided in the switch section or the buffer section. Furthermore, it contributes to reducing the area occupied by the driving circuit and making the bezel narrower. The driving circuit is roughly classified into a logic circuit section and a switch section or a buffer section. The TFT provided in the logic circuit section is preferably configured to be able to control the threshold voltage. On the other hand, the TFT provided in the switch section or the buffer section preferably has a large on-current. By providing a driving circuit having the TFTs shown in Embodiment 1 or Embodiment 2, it becomes possible to control the threshold voltage of the TFT provided in the logic circuit section, and it becomes possible to increase the on-current of the TFT provided in the switch section or the buffer section. Furthermore, it contributes to reducing the area occupied by the driving circuit and making the bezel narrower. The driving circuit is roughly classified into a logic circuit section and a switch section or a buffer section. The TFT provided in the logic circuit section is preferably configured to be able to control the threshold voltage. On the other hand, the TFT provided in the switch section or the buffer section preferably has a large on-current. By providing a driving circuit having the TFTs shown in Embodiment 1 or Embodiment 2, it becomes possible to control the threshold voltage of the TFT provided in the logic circuit section, and it becomes possible to increase the on-current of the TFT provided in the switch section or the buffer section. Furthermore, it contributes to reducing the area occupied by the driving circuit and making the bezel narrower. The driving circuit is roughly classified into a logic circuit section and a switch section or a buffer section. The TFT provided in the logic circuit section is preferably configured to be able to control the threshold voltage. On the other hand, the TFT provided in the switch section or the buffer section preferably has a large on-current. By providing a driving circuit having the TFTs shown in Embodiment 1 or Embodiment 2, it becomes possible to control the threshold voltage of the TFT provided in the logic circuit section, and it becomes possible to increase the on-current of the TFT provided in the switch section or the buffer section. Furthermore, it contributes to reducing the area occupied by the driving circuit and making the bezel narrower. The driving circuit is roughly classified into a logic circuit section and a switch section or a buffer section. The TFT provided in the logic circuit section is preferably configured to be able to control the threshold voltage. On the other hand, the TFT provided in the switch section or the buffer section preferably has a large on-current. By providing a driving circuit having the TFTs shown in Embodiment 1 or Embodiment 2, it becomes possible to control the threshold voltage of the TFT provided in the logic circuit section, and it becomes possible to increase the on-current of the TFT provided in the switch section or the buffer section. Furthermore, it contributes to reducing the area occupied by the driving circuit and making the bezel narrower. The driving circuit is roughly classified into a logic circuit section and a switch section or a buffer section. The TFT provided in the logic circuit section is preferably configured to be able to control the threshold voltage. On the other hand, the TFT provided in the switch section or the buffer section preferably has a large on-current. By providing a driving circuit having the TFTs shown in Embodiment 1 or Embodiment 2, it becomes possible to control the threshold voltage of the TFT provided in the logic circuit section, and it becomes possible to increase the on-current of the TFT provided in the switch section or the buffer section. Furthermore, it contributes to reducing the area occupied by the driving circuit and making the bezel narrower.

[0081] Next, the shift register circuit constituting the scanning line driving circuit will be described below.

[0082] The shift register circuit shown in FIG. 5 has a plurality of flip-flop circuits 351 and control signals line 352, control signal lines 353, 354, 355, 356 , and a reset line 357.

[0083] As shown in the shift register circuit of FIG. 5, in the flip-flop circuit 351, a start pulse SSP is input to the input terminal IN of the first stage via the control signal line 352, and the output signal terminal S of the previous flip-flop circuit 351 is connected to the input terminal IN of the subsequent stages . Also, the reset terminal RES of the Nth stage (N is a natural number) is connected to the output signal terminal S of the flip-flop circuit of the (N + 3)th stage via the reset line 357. Assuming that a first clock signal CLK1 is input to the clock terminal CLK of the flip-flop circuit 351 of the Nth stage via the control signal line 35 OUT 3, a second clock signal CLK2 is input to the clock terminal CLK of the flip-flop circuit 351 of the (N + 1)th stage via the control signal line 354 . Also, a third clock signal CLK3 is input to the clock terminal CLK of the flip-flop circuit 351 of the (N + 2)th stage via the control signal line 355 . Also, a fourth clock signal CLK4 is input to the clock terminal CLK of the flip-flop circuit 351 of the (N + 3)th stage via the control signal line 356 out . Then, a first clock signal CLK1 is input to the clock terminal CLK of the flip-flop circuit 351 of the (N + 4)th stage via the control signal line 353 . Also, the flip-flop circuit 351 of the Nth stage outputs the output SRoutN of the flip-flop circuit of the Nth stage from the gate output terminal G . out ​​​​​​​​​​

[0084] Although the connection between the flip-flop circuit 351 and the power supply and the power supply line is not shown, the power supply potential Vdd and the power supply potential GND are supplied to each flip-flop circuit 351 via a power supply line. Supplied.

[0085] Note that the power supply potential described in this specification corresponds to the potential difference when the reference potential is 0V. Therefore, the power supply potential may also be referred to as the power supply voltage, or the power supply voltage may be referred to as the power supply potential. Therefore, the power supply potential may also be referred to as the power supply voltage, or the power supply voltage may be referred to as the power supply potential. There is also.

[0086] In this specification, when A and B are connected, it means that not only A and B are directly connected, but also those that are electrically connected are included. Here, when A and B are electrically connected, it means that when there is an object having some electrical action between A and B, and A and B become substantially the same node through the object. Specifically, when A and B are connected via a switching element such as a TFT, and A and B become substantially the same potential due to the conduction of the switching element, or when A and B are connected via a resistance element, and the potential difference generated at both ends of the resistance element does not affect the operation of the circuit including A and B, etc., it means a state where A and B can be regarded as the same node without problem when considering the circuit operation. In this specification, when A and B are connected, it means that not only A and B are directly connected, but also those that are electrically connected are included. Here, when A and B are electrically connected, it means that when there is an object having some electrical action between A and B, and A and B become substantially the same node through the object. In this specification, when A and B are connected, it means that not only A and B are directly connected, but also those that are electrically connected are included. Here, when A and B are electrically connected, it means that when there is an object having some electrical action between A and B, and A and B become substantially the same node through the object. In this specification, when A and B are connected, it means that not only A and B are directly connected, but also those that are electrically connected are included. Here, when A and B are electrically connected, it means that when there is an object having some electrical action between A and B, and A and B become substantially the same node through the object. Specifically, when A and B are connected via a switching element such as a TFT, and A and B become substantially the same potential due to the conduction of the switching element, or when A and B are connected via a resistance element, and the potential difference generated at both ends of the resistance element does not affect the operation of the circuit including A and B, etc., it means a state where A and B can be regarded as the same node without problem when considering the circuit operation. Specifically, when A and B are connected via a switching element such as a TFT, and A and B become substantially the same potential due to the conduction of the switching element, or when A and B are connected via a resistance element, and the potential difference generated at both ends of the resistance element does not affect the operation of the circuit including A and B, etc., it means a state where A and B can be regarded as the same node without problem when considering the circuit operation. Specifically, when A and B are connected via a switching element such as a TFT, and A and B become substantially the same potential due to the conduction of the switching element, or when A and B are connected via a resistance element, and the potential difference generated at both ends of the resistance element does not affect the operation of the circuit including A and B, etc., it means a state where A and B can be regarded as the same node without problem when considering the circuit operation. Specifically, when A and B are connected via a switching element such as a TFT, and A and B become substantially the same potential due to the conduction of the switching element, or when A and B are connected via a resistance element, and the potential difference generated at both ends of the resistance element does not affect the operation of the circuit including A and B, etc., it means a state where A and B can be regarded as the same node without problem when considering the circuit operation. Specifically, when A and B are connected via a switching element such as a TFT, and A and B become substantially the same potential due to the conduction of the switching element, or when A and B are connected via a resistance element, and the potential difference generated at both ends of the resistance element does not affect the operation of the circuit including A and B, etc., it means a state where A and B can be regarded as the same node without problem when considering the circuit operation.

[0087] Next, FIG. 6 shows one form of the flip-flop circuit 351 included in the shift register circuit shown in FIG. 5. The flip-flop circuit 351 shown in FIG. 6 has a logic circuit section 361 and a switch section 362. The logic circuit section 361 has TFTs 363 to 368. Next, FIG. 6 shows one form of the flip-flop circuit 351 included in the shift register circuit shown in FIG. 5. The flip-flop circuit 351 shown in FIG. 6 has a logic circuit section 361 and a switch section 362. Next, FIG. 6 shows one form of the flip-flop circuit 351 included in the shift register circuit shown in FIG. 5. The flip-flop circuit 351 shown in FIG. 6 has a logic circuit section 361 and a switch section 362. It also has TFTs 369 to 372. Note that the logic circuit section is a circuit for switching the signal output to the switch section, which is the subsequent circuit, according to the signal input from the outside. The switch section is a circuit for switching on or off the TFT that serves as a switch according to the signals input from the outside and the control circuit section, and outputting a current according to the size and structure of the TFT. In the flip-flop circuit 351, the input terminal in is connected to the gate terminals of TFT 364 and TFT 367. The reset terminal RES is connected to the gate terminal of TFT 363. The clock terminal CLK is connected to the first terminals of TFT 369 and TFT 371. The power supply line to which the power supply potential Vdd is supplied is connected to the first terminal of TFT 364, and the gate terminal and the second terminal of TFT 366. The power supply line to which the power supply potential GND is supplied is connected to the second terminals of TFT 363, TFT 365, TFT 367, TFT 368, TFT 370, and TFT 372. Also, the first terminal of TFT 363, the second terminal of TFT 364, the first terminal of TFT 365, the gate terminal of TFT 368, the gate terminal of TFT 369, and the gate terminal of TFT 371 are connected to each other. Also, the first terminal of TFT 366 is connected to the gate terminals of TFT 365, TFT 367, the first terminal of TFT 368, the gate terminal of TFT 370, and the gate terminal of TFT 372. Further, the gate output terminal G is connected to the second terminal of TFT 369 and the first terminal of TFT 370. The output signal terminal S

[0088] out ​​​​​​​​​​​​​​​​out is connected to the second terminal of TFT371 and the first terminal of TFT37 2.

[0089] Here, an explanation will be given for the case where all of TFT363 to TFT372 are N-type TFTs.

[0090] Note that a TFT is an element having at least three terminals including a gate, a drain, and a source, has a channel formation region between a drain region and a source region, and can pass a current through the drain region, the channel formation region, and the source region. Here, since the source and the drain may be interchanged depending on the structure and operating conditions of the TFT, etc., it is difficult to specify which is the source and which is the drain. Therefore, the regions functioning as the source and the drain are not called the source or the drain, but are denoted as the first terminal and the second terminal, respectively. Also, in this case, the terminal functioning as the gate is denoted as the gate terminal. Next, an example of the layout diagram of the flip-flop circuit 351 shown in FIG. 6 is shown in FIG. 7.

[0091] Next, an example of the layout diagram of the flip-flop circuit 351 shown in FIG. 6 is shown in FIG. 7.

[0092] The flip-flop circuit in FIG. 7 has a power supply line 381 to which a power supply potential Vdd is supplied, a reset line 382, control signal lines 353, 354, 355, 356 , control signal line 383, a power supply line 384 to which a power supply potential GND is supplied, a logic circuit section 361, and a switch section 362. The logic circuit section 361 has TFTs 363 to 368. Also, the switch section 362 has TFTs 369 to 372. Also, in FIG. 7, the gate output terminal G outThe wiring connected to it, output signal terminal S out Connected to The wiring is also shown.

[0093] In FIG. 7, the semiconductor layer 385, the first wiring layer 386, the second wiring layer 387, the third wiring layer 388, and the contact hole 389 are shown. Note that the first wiring layer 386 is formed by the layer forming the gate electrode, the second wiring layer 387 is formed by the layer forming the source electrode or drain electrode of the TFT, and the third wiring layer 388 may be formed by the layer forming the pixel electrode in the pixel portion. However, it is not limited to this. For example, the third wiring layer 388 may be formed as a wiring layer different from the layer forming the pixel electrode.

[0094] Note that the connection relationship between each circuit element in FIG. 7 is as described in FIG. 6. Note that in FIG. 7 since the flip-flop circuit to which the first clock signal is input is shown, the connection to the control signal lines 354 to 356 is not shown.

[0095] In the layout diagram of the flip-flop circuit in FIG. 7, by controlling the threshold voltage of the TFT 366 or TFT367 included in the logic circuit section 361, the EDMOS circuit 373 can be configured. Typically, the EDMOS circuit 373 is configured with the TFT366 being of the depletion type and the TFT36 7 being of the enhancement type, and the TFTs 369 to 372 included in the switch section 362 being dual-gate type TFTs, or depletion type TFTs. Note that in FIG. 6, the TFTs 366 and T FT367 in the EDMOS circuit 373 have different connection positions of the gate electrodes of the depletion type TFTs from those of the EDMOS circuit shown in FIG. 2.

[0096] Form TFT366 or TFT367 with dual - gate type TFTs, and control the potential of the back - gate electrode to make it a depletion - type TFT or an enhancement - type TFT.

[0097] In FIG. 7, a control signal line 390 with the same potential as the back - gate electrode for controlling the threshold voltage of TFT366 is separately provided to make it a depletion - type. TFT366 is a dual - gate type TFT, and the potential of the back - gate electrode is different from the potential of the power supply line 381 to which the power supply potential V dd is supplied.

[0098] In FIG. 7, TFT369 - 372 are examples of dual - gate type TFTs where the back - gate electrode and the gate electrode have the same potential. The potential of the back - gate electrode is the same as the potential of the power supply line to which the power supply potential Vdd applied to the gate electrode is supplied.

[0099] In this way, the TFTs arranged in the pixel portion and the driving circuit of the display device can be formed only with n - channel type TFTs using an oxide semiconductor layer

[0100] Also, TFT366 in the logic circuit section 361 is a TFT for flowing current according to the power supply potential Vdd. By making the dual - gate type TFT or TFT366 a depletion - type TFT and increasing the flowing current, the miniaturization of the TFT can be achieved without degrading the performance.

[0101] Also, in the TFTs constituting the switch section 362, by increasing the amount of current flowing through the TFT ​​​​​, and since it can switch between on and off at high speed, without degrading performance the area occupied by the TFT can be reduced. Therefore, the circuit constituted by the TFT can also reduce the area it occupies. Note that the TFTs 369 to TFT 372 in the switch section 362 may be laid out so as to sandwich the semiconductor layer 385 between the first wiring layer 386 and the third wiring layer 388 to form a dual-gate type TFT.

[0102] Also, in FIG. 7, an example is shown in which a dual-gate type TFT is formed by sandwiching the semiconductor layer 385 between the first wiring layer 386 and , the third wiring layer 388 that is connected to the first wiring layer 386 through the contact hole 389 and has the same potential, but it is not limited to this configuration. For example, a separate control signal line may be provided for the third wiring layer 388, and the potential of the third wiring layer 388 may be controlled independently from the first wiring layer 386.

[0103] Note that in the layout diagram of the flip-flop circuit shown in FIG. 7, the shapes of the channel formation regions of the TFTs 363 to T FT 372 may be U-shaped (C-shaped or horseshoe-shaped). Also in FIG. 7, the sizes of the respective TFTs are made equal, but depending on the magnitude of the load in the subsequent stage, the output force signal terminal S out or the sizes of the respective TFTs connected to the gate output terminal G out may be appropriately changed.

[0104] Next, the operation of the shift register circuit shown in FIG. 5 will be described using the timing chart shown in FIG. 8. FIG. 8 shows the control signal lines 352 to 356 shown in FIG. 5, respectively to which the start pulse SSP, the first clock signal CLK1 to the fourth clock are respectively supplied The signal CLK4 and the output signal terminals S of the flip-flop circuits of the first to fifth stages out and Sout1 to Sout5 output therefrom are shown. In the description of FIG. 8, the reference numerals attached to each element in FIGS. 6 and 7 are used.

[0105] Note that FIG. 8 is a timing chart when each of the TFTs included in the flip-flop circuit is an N-type TFT. Also, the first clock signal CLK1 and the fourth clock signal CLK4 are shifted by 1 / 4 wavelength (one section divided by a dotted line) as shown in the figure and have such a configuration.

[0106] First, in period T1, a start pulse SSP is input to the first-stage flip-flop circuit at the H level, and the logic circuit section 361 turns on the TFTs 369 and 371 of the switch section and turns off the TFTs 370 and 372. At this time, since the first clock signal CLK1 is at the L level, Sout1 is at the L level.

[0107] Note that in period T1, since no signal is input to the IN terminal of the flip-flop circuits of the second stage and subsequent stages, they output the L level without operating. In the initial state, each flip-flop circuit of the shift register circuit is described as outputting the L level.

[0108] Next, in period T2, in the first-stage flip-flop circuit, similar to period T1, the logic circuit section 361 controls the switch section 362. In period T2, since the first clock signal C LK1 becomes the H level, Sout1 becomes the H level. Also, in period T2, the second ​​​In the eye flip-flop circuit, when Sout1 is at the H level and input to the IN terminal, the logic circuit section 361 turns on the TFTs 369 and 371 of the switch section and turns off the TFTs 370 and TF T372. At this time, since the second clock signal CLK2 is at the L level, S out2 is at the L level.

[0109] Note that in period T2, since no signal is input to the IN terminal of the flip-flop circuits after the third stage, they output the L level without operating.

[0110] Next, in period T3, in the first-stage flip-flop circuit, the logic circuit section 361 controls the switch section 362 to hold the state of period T2. Therefore, in period T3 , the first clock signal CLK1 is at the H level and Sout1 becomes the H level. Also, in period T3, in the second-stage flip-flop circuit, the logic circuit section 361 controls the switch section 362 in the same manner as in period T2. In period T3, since the second clock signal CLK2 is at the H level, Sout2 is at the H level. Also, in the third-stage flip - flop circuit of period T3, Sout2 is input to the IN terminal at the H level, and the logic circuit section 361 turns on the TFTs 369 and 371 of the switch section and turns off the TFTs 370 and 372. At this time, since the third clock signal CLK3 is at the L level, Sout3 is at the L level .

[0111] Note that in period T3, since no signal is input to the IN terminal of the flip-flop circuits after the fourth stage, they output the L level without operating.

[0112] Next, in period T4, in the first flip-flop circuit, the logic circuit unit 361 controls the switch unit 362 to hold the state in period T3. Therefore, in period T4, the first clock signal CLK1 is at the L level, and Sout1 becomes the L level. Also, in period T4, in the second flip-flop circuit, the logic circuit unit 361 controls the switch unit 362 to hold the state in period T3. Therefore, in period T4, the second clock signal CLK2 is at the H level, and Sout2 becomes the H level. Further, in period T4, in the third flip-flop circuit, similar to period T3, the logic circuit unit 361 controls the switch unit 362. In period T4, since the third clock signal CLK3 is at the H level, Sout3 is at the H level. Also, in the fourth flip-flop circuit in period T4, Sout3 at the H level is input to the IN terminal, and the logic circuit unit 361 turns on the TFT369 and TFT371 of the switch unit 362 and turns off the TFT370 and TFT372. At this time, since the fourth clock signal CLK4 is at the L level, Sout4 is at the L level. The logic circuit unit 361 controls the switch unit 362 to do so. Therefore, in period T4, the first clock signal CLK1 is at the L level, and Sout1 becomes the L level. Also, in period T4, in the second flip-flop circuit, the logic circuit unit 361 controls the switch unit 362 to hold the state in period T3. The logic circuit unit 361 controls the switch unit 362 to do so. Therefore, in period T4, the second clock signal CLK2 is at the H level, and Sout2 becomes the H level. Also, in period T4, in the third flip-flop circuit, similar to period T3, the logic circuit unit 361 controls the switch unit 362. In period T4, the third clock signal CLK3 is at the H level, so Sout3 is at the H level. Also, in the fourth flip-flop circuit in period T4, Sout3 at the H level is input to the IN terminal, and the logic circuit unit 361 turns on the TFT369 and TFT371 of the switch unit 362 and turns off the TFT370 and TFT37 2. At this time, since the fourth clock signal CLK4 is at the L level, Sou t4 is at the L level.

[0113] Note that in period T4, in the flip-flop circuits from the fifth stage onwards, since no signal is input to the IN terminal, they output the L level without operating.

[0114] Next, in period T5, in the second flip-flop circuit, the logic circuit unit 361 controls the switch unit 362 to hold the state in period T3. The logic circuit unit 361 controls the switch unit 362 to do so. Therefore, in period T5, the second clock signal CLK2 is at the L level, and Sout2 becomes the L level. Also, ​In period T5, in the third flip-flop circuit, the state in period T4 is held. The logic circuit section 361 controls the switch section 362 in such a manner. Therefore, in period T5 , the third clock signal CLK3 is at the H level, and Sout3 becomes the H level. Also, In the fourth flip-flop circuit in period T5, similar to period T4, the logic circuit section 3 61 controls the switch section 362. In period T5, since the fourth clock signal CLK4 is at the H level, Sout4 is at the H level. Also, for the flip-flop circuits after the fifth stage , the wiring relationship is the same as that of the flip-flop circuits of the first to fourth stages, and the timing of the input signals is also the same, so the description is omitted.

[0115] As shown in the shift register circuit of FIG. 5, Sout4 also serves as the reset signal for the first-stage flip-flop circuit. In period T5, Sout4 becomes the H level, and this signal is input to the reset terminal RES of the first-stage flip-flop circuit. When the reset signal is input , the TFTs 369 and 371 of the switch section 362 are turned off, and the TFTs 3 70 and 372 are turned on. Then, Sout1 of the first-stage flip-flop circuit outputs the L level until the next start pulse SSP is input.

[0116] Through the operations described above, even in the flip-flop circuits after the second stage, the logic circuit section is reset based on the reset signal output from the subsequent flip-flop circuit, and a shift register circuit that outputs a signal having a waveform shifted by 1 / 4 wavelength of the clock signal as shown in Sout1 to Sout5 can be obtained.

[0117] ​​​​​In addition, the logic circuit section is divided into enhancement and depletion types as flip-flop circuits. The switch section is equipped with a dual-gate TFT and an EDMOS TFT. By adopting this configuration, the amount of current flowing through the TFT constituting the logic circuit section 361 can be increased. It is possible to reduce the area occupied by the TFT and the amount of light generated by the TFT without degrading the performance. In addition, the area occupied by the circuitry configured by the switch unit 362 can be reduced. In TFTs, the amount of current flowing through the TFT is increased, enabling the device to switch between on and off quickly. This allows the area occupied by the TFT and the size of the TFT to be reduced without compromising performance. The area occupied by the circuit formed by T can be reduced. It is possible to achieve reduced edge size, miniaturization, and high performance.

[0118] In addition, a latch circuit, a level shifter circuit, and the like may be provided in the signal line driver circuit shown in FIG. A buffer section is provided at the final stage of sending signals from the signal line driver circuit to the pixel section, and the amplified signals are The signal is sent from the signal line driver circuit to the pixel section. T, typically a dual-gate TFT or a depletion-type TFT Therefore, it is possible to reduce the area of ​​the TFT and the area occupied by the signal line driving circuit. Therefore, it is possible to realize a display device with a narrower frame, smaller size, and higher performance. The shift register, which is part of the signal line driver circuit, is required to operate at high speed. It is preferable to mount the display device using C or the like.

[0119] This embodiment mode can be freely combined with the first embodiment mode or the second embodiment mode. Cut.

[0120] (Embodiment 4) In this embodiment, a display device including the second thin film transistor 170 shown in Embodiment 1 will be described with reference to FIGS. 9 to 16 in terms of its manufacturing process.

[0121] In FIG. 9(A), a glass substrate such as barium borosilicate glass or aluminum borosilicate glass can be used as the light-transmissive substrate 100.

[0122] Next, after forming a conductive layer over the entire surface of the substrate 100, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wirings and electrodes (gate wiring including the gate electrode 101, the capacitor wiring 108, and the first terminal 121). At this time, etching is performed such that at least the end portions of the gate electrode 101 have a tapered shape. A cross-sectional view at this stage is shown in FIG. 9(A). Note that a top view at this stage corresponds to FIG. 11 .

[0123] The gate wiring including the gate electrode 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion are desirably formed of a low-resistance conductive material such as aluminum (Al) or copper (Cu). However, since Al alone has problems such as poor heat resistance and easy corrosion, it is formed in combination with a heat-resistant conductive material . As the heat-resistant conductive material, titanium (Ti), tantalum (Ta) , tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc) selected from the elements, or an alloy containing the above-described elements as components, or an alloy film combining the above-described elements, or a nitride containing the above-described elements as components is used.

[0124] Next, a gate insulating layer 102 is formed over the entire surface of the gate electrode 101. The gate insulating layer 10 2 is formed by a sputtering method or the like to have a film thickness of 50 to 400 nm. When giving priority to the yield of the thin film transistor, it is preferable that the film thickness of the gate insulating layer 102 is thicker.

[0125] For example, a silicon oxide film is used as the gate insulating layer 102 by a sputtering method and formed to have a thickness of 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film, and other insulating films such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, and a tantalum oxide film may be used, and may be formed as a single layer or a laminated structure made of these materials. Further, when a silicon oxynitride film, a silicon nitride film, or the like is used as the gate insulating layer 102, impurities from the glass substrate, for example, sodium, can be blocked from diffusing and entering the oxide semiconductor formed later.

[0126] Next, a second photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form a contact hole reaching a wiring or electrode made of the same material as the gate electrode. This contact hole is provided to be directly connected to a conductive film formed later. For example, in a drive circuit portion, a contact hole is formed when forming a thin film transistor directly contacting the gate electrode and the source electrode or the drain electrode, or a terminal electrically connected to the gate wiring of the terminal portion. Here, an example of forming a contact hole for directly connecting to a conductive film formed later by performing a second photolithography process has been shown, but particularly ​​​​​​​​​​​​not limited thereto, and the gate electrode may be formed in the same process as the contact hole for connection to the pixel electrode later to reach the layer, and an electrical connection may be made using the same material as the pixel electrode If an electrical connection is made using the same material as the pixel electrode, the number of masks can be reduced by one possible.

[0127] Next, a conductive film made of a metal material is formed on the gate insulating layer 102 by sputtering or vacuum evaporation Here, a three-layer structure of a Ti film, an aluminum film containing Nd, and a Ti film is used. As the material of the conductive film include elements selected from Al, Cr, Ta, Ti, Mo, W, or alloys containing the above-mentioned elements as components, or alloy films combining the above-mentioned elements, etc. Also, the conductive film may have a two-layer structure, or a titanium film may be laminated on an aluminum film. Also the conductive film may have a single-layer structure of an aluminum film containing silicon or a single-layer structure of a titanium film is also possible.

[0128] Next, a third photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the source electrode layer 105a, the drain electrode layer 105b, and the connection electrode 120. As the etching method at this time, wet etching or dry etching is used. Here, ammonia peroxide (hydrogen peroxide : ammonia: water = 5:2:2) is used as the etchant for the Ti film, and a solution mixed with phosphoric acid, acetic acid, and nitric acid is used for etching the aluminum film containing Nd respectively. By this wet etching the conductive film in which the Ti film, the Al-Nd film, and the Ti film are sequentially laminated is etched to form the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in FIG. 9(B ​) as shown in

[0129] In the terminal portion, the connection electrode 120 is directly connected to the first terminal 121 of the terminal portion through a contact hole formed in the gate insulating layer. Although not shown here, the source wiring or drain wiring of the thin film transistor of the driving circuit and the gate electrode are directly connected through the same process as the above-described process.

[0130] Next, after removing the resist mask, it is preferable to perform plasma treatment to remove dust and the like adhering to the surfaces of the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in FIG. 9(C). Here, argon gas is introduced and reverse sputtering is performed to generate plasma by an RF power source, and plasma treatment is performed on the exposed gate insulating layer.

[0131] Next, after the plasma treatment, an oxide semiconductor film is formed. Forming the oxide semiconductor film without exposing it to the atmosphere is useful in that dust and the like are not adhered to the interface between the gate insulating layer and the oxide semiconductor film. Here, an oxide semiconductor target (In2O3:Ga2O3:ZnO = 1:1:1) containing indium (In), gallium (Ga), and zinc (Zn) with a diameter of 8 inches is used, and the distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa, the DC power source is 0.5 kW, and the film is formed in an argon or oxygen atmosphere. Using a pulsed DC power source is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm.

[0132] Next, a fourth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the oxide semiconductor layer 103. Here, wet etching using ITO07N (manufactured by Kansai Chemical Co., Ltd.) is used to remove the unnecessary portions to form the oxide semiconductor layer 103. Note that the etching here is not limited to wet etching, and dry etching may be used. Then, the resist mask is removed. Moreover, in this fourth photolithography process, the second terminal 122, which is made of the same material as the source electrode layer or drain electrode layer 105a, 105b, is left at the terminal portion. Note that the second terminal 122 is electrically connected to the source wiring (source wiring including the source electrode layer or drain electrode layer 105a, 105b). Next, it is preferable to perform heat treatment at 200°C to 600°C, typically 300°C to 500°C. For example, the substrate is placed in a furnace and heat treatment is performed at 350°C for 1 hour in a nitrogen atmosphere or an air atmosphere. With the above processes, the thin film transistor 170 having the oxide semiconductor layer 103 as the channel formation region can be fabricated. The cross-sectional view at this stage is shown in FIG. 10(A). Note that the top view at this stage corresponds to FIG. 13. Note that the timing of the heat treatment is not particularly limited as long as it is after the formation of the oxide semiconductor film. For example, it may be performed after the formation of the protective insulating film. Furthermore, oxygen radical treatment may be performed on the surface of the exposed oxide semiconductor layer 103. By performing oxygen radical treatment, the thin film transistor can be made normally-off. Also, by performing radical treatment, the etching resistance of the oxide semiconductor layer 103 can be improved.

[0133]

[0134]

[0135] Damage can be recovered. The radical treatment contains O2, N2O, preferably oxygen It is preferably carried out in an atmosphere of N2, He, or Ar. Also, Cl2 and CF4 can be added to the above atmosphere and the treatment can be carried out in the resulting atmosphere. Note that the radical treatment is preferably carried out without bias

[0136] Next, a protective insulating layer 107 that covers the second thin film transistor 170 is formed. The protective insulating layer 107 can be a single layer such as a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, a tantalum oxide film, etc., obtained by using a sputtering method or the like, or a laminate thereof. In some thin film transistors of the driving circuit, this protective insulating layer 107 functions as the second gate insulating layer, and a second gate electrode is formed thereon. The protective insulating layer 107 has a film thickness of 50 to 400 nm When giving priority to the yield of the thin film transistor, the film thickness of the protective insulating layer 107 is preferably thicker Also, when using a silicon oxynitride film or a silicon nitride film as the protective insulating layer 107, impurities that adhere for some reason after the formation of the protective insulating layer 107, such as sodium, etc., can be blocked from diffusing and entering the oxide semiconductor

[0137] Next, a fifth photolithography process is performed to form a resist mask, and a contact hole 125 that reaches the drain electrode layer 105b is formed by etching the protective insulating layer 1 07. Also, a contact hole 12 7 that reaches the second terminal 122 and a contact hole 126 that reaches the connection electrode 120 are also formed by the etching here. A cross-sectional view at this stage is shown in FIG. 10(B)

[0138] ​​​​​​ Next, after removing the resist mask, a transparent conductive film is formed. As the material for the transparent conductive film are indium oxide (In2O3), indium tin oxide alloy (In2O3―SnO 2, abbreviated as ITO), etc., which are formed by using a sputtering method, a vacuum evaporation method, or the like. The etching treatment of such materials is performed with a hydrochloric acid-based solution. However, especially for the etching of ITO residue is likely to occur, so indium zinc oxide alloy (In2O3―ZnO) may be used to improve the etching processability.

[0139] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode 110 in the pixel portion. In this sixth photolithography process, in the driving circuit, an electrode layer (back gate electrode) for controlling the threshold value is formed on the oxide semiconductor layer using the same material as the pixel electrode 110 for a part of the circuit . Note that since the thin film transistor having the back gate electrode is shown in FIG. 1(A) and Embodiment 1 , a detailed description thereof is omitted here. . Since it is shown in FIG. 1(A) and Embodiment 1, a detailed description thereof is omitted here.

[0140] Also, in this sixth photolithography process, using the gate insulating layer 10 2 and the protective insulating layer 107 as dielectrics, a holding capacitor is formed by the capacitor wiring 108 and the pixel electrode 110. Here, an example in which the gate insulating layer 102 and the protective insulating layer 107 are used as dielectrics to form a holding capacitor by the capacitor wiring 108 and the pixel electrode 110 is shown, but it is not particularly limited and an electrode made of the same material as the source electrode or the drain electrode is provided above the capacitor wiring , and a capacitor is configured with that electrode, the capacitor wiring, and the gate insulating layer 102 as a dielectric therebetween It may be configured to form a holding capacitance and electrically connect its electrode and the pixel electrode.

[0141] Also, in this sixth photolithography process, the first terminal and the second terminal are covered with a resist mask to leave the transparent conductive films 128 and 129 formed on the terminal portion. The transparent conductive films 128 and 129 become electrodes or wirings used for connection with the FPC. The transparent conductive film 128 formed on the connection electrode 120 directly connected to the first terminal 121 becomes a connection terminal electrode that functions as an input terminal of the gate wiring. The transparent conductive film 129 formed on the second terminal 122 is a connection terminal electrode that functions as an input terminal of the source wiring.

[0142] Next, the resist mask is removed, and a cross-sectional view at this stage is shown in FIG. 10(C). Note that the top view at this stage corresponds to FIG. 14.

[0143] Also, FIGS. 15(A1) and 15(A2) respectively show a top view and a cross-sectional view of the gate wiring terminal portion at this stage. FIG. 15(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 15(A2). In FIG. 15(A1), the transparent conductive film 155 formed on the protective insulating film 154 is a connection terminal electrode that functions as an input terminal. Also, in FIG. 15(A1), at the terminal portion, the first terminal 151 formed of the same material as the gate wiring and the connection electrode 153 formed of the same material as the source wiring overlap and are directly connected through the gate insulating layer 152 to be electrically connected. Also, the connection electrode 153 and the transparent conductive film 155 are directly connected and electrically connected through a contact hole provided in the protective insulating film 154.

[0144] ​​​​​​​​In addition, FIGS. 15(B1) and 15(B2) show a top view and a cross-sectional view of the source wiring terminal portion, respectively. Also, FIG. 15(B1) corresponds to a cross-sectional view taken along line D1-D2 in FIG. 15(B2). In FIG. 15(B1), the transparent conductive film 155 formed on the protective insulating film 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 15(B1), in the terminal portion, an electrode 156 formed of the same material as the gate wiring overlaps via a gate insulating layer 152 below a second terminal 150 that is electrically connected to the source wiring. The electrode 156 is not electrically connected to the second terminal 150. If the electrode 156 is set to a potential different from that of the second terminal 150, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 150 is electrically connected to the transparent conductive film 155 via the protective insulating film 154. are shown respectively. Also, FIG. 15(B1) corresponds to a cross-sectional view taken along line D1-D2 in FIG. 15(B2). In FIG. 15(B1), the transparent conductive film 155 formed on the protective insulating film 154 is a terminal electrode for connection that functions as an input terminal. In FIG. 15(B1), the transparent conductive film 155 formed on the protective insulating film 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 15(B1), In FIG. 15(B1), the transparent conductive film 155 formed on the protective insulating film 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 15(B1), in the terminal portion, an electrode 156 formed of the same material as the gate wiring overlaps via a gate insulating layer 152 below a second terminal 150 that is electrically connected to the source wiring. in the terminal portion, an electrode 156 formed of the same material as the gate wiring overlaps via a gate insulating layer 152 below a second terminal 150 that is electrically connected to the source wiring. The electrode 156 is not electrically connected to the second terminal 150. If the electrode 156 is set to a potential different from that of the second terminal 150, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 15 such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 15 0 is electrically connected to the transparent conductive film 155 via the protective insulating film 154.

[0145] A plurality of gate wirings, source wirings, and capacitor wirings are provided according to the pixel density. Also, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitor wiring, etc. are arranged side by side. The number of each terminal can be set to any number, and the implementer can appropriately determine it. terminal can be set to any number, and the implementer can appropriately determine it.

[0146] Thus, by six photolithography processes, using six photomasks, a second thin film transistor 170, which is a bottom gate type n-channel thin film transistor, and a holding capacitor can be completed. Then, by arranging these in a matrix corresponding to individual pixels to form a pixel portion, an active matrix type display device can be manufactured. capacitor can be completed. Then, by arranging these in a matrix corresponding to individual pixels to form a pixel portion, an active matrix type display device can be manufactured for can be used as one of the substrates. For the sake of convenience in this specification, such a substrate is called an active matrix substrate.

[0147] Also, when configured to be electrically connected to the gate wiring using the same material as the pixel electrode, the third photolithography process can be omitted. Therefore, compared with five photolithography processes using five photomasks, a bottom-gate type n-channel thin-film transistor which is the second thin-film transistor and the holding capacitor can be completed.

[0148] Also, as shown in FIG. 1(C), when the material of the second gate electrode is made different from that of the pixel electrode, one more photolithography process is added and one more photomask is increased.

[0149] When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. A common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided at the terminal portion. This fourth terminal is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc.

[0150] Also, it is not limited to the pixel configuration of FIG. 14, and an example of a top view different from FIG. 14 is shown in FIG. 16. In FIG. 16, a capacitance wiring is not provided, and an example of forming a holding capacitor by overlapping a pixel electrode with the gate wiring of adjacent pixels through a protective insulating film and a gate insulating layer. In this case, the capacitance wiring and the third terminal connected to the capacitance wiring can be omitted. In FIG. 16, the same parts as in FIG. 14 ​​The same reference numerals will be used for the description in each minute.

[0151] In an active matrix type liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, whereby optical modulation of a liquid crystal layer disposed between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by an observer as a display pattern.

[0152] In video display of a liquid crystal display device, since the response of the liquid crystal molecules themselves is slow, there are problems such as afterimages and blurring of video. In order to improve the video characteristics of the liquid crystal display device, there is a driving technique called so-called black insertion in which all-black display is performed every other frame.

[0153] Also, there is a driving technique called so-called double-speed driving in which video characteristics are improved by making the normal vertical period 1.5 times or 2 times or more.

[0154] Also, in order to improve the video characteristics of the liquid crystal display device, a surface light source is configured using a plurality of LED (light emitting diode) light sources or a plurality of EL light sources as a backlight, and there is also a driving technique in which each light source constituting the surface light source is independently driven to blink within one frame period. As the surface light source, three or more types of LEDs may be used, or white light emitting LEDs may be used. Since a plurality of LEDs can be independently controlled, the light emission timing of the LEDs can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. Since this driving technique can turn off the LEDs partially, particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. ​​​​​​​​​​​​​

[0155] By combining these driving techniques, display characteristics such as the video characteristics of the liquid crystal display device can be improved more than before.

[0156] The n-channel type transistor obtained in this embodiment uses an In-Ga-Zn-O based non-single crystal crystal film in the channel formation region and has good driving characteristics, so these driving techniques can be combined.

[0157] Also, when manufacturing a light-emitting display device, one electrode (also called the cathode) of the organic light-emitting element is set to a low power supply potential, for example, GND, 0V, etc. Therefore, a fourth terminal for setting the cathode to a low power supply potential, for example, GND, 0V, etc. is provided at the terminal portion. Also, when manufacturing a light-emitting display device, a power supply line is provided in addition to the source wiring and the gate wiring. Accordingly, a fifth terminal that is electrically connected to the power supply line is provided at the terminal portion.

[0158] Forming with a thin film transistor using an oxide semiconductor in a gate line driving circuit or a source line driving circuit reduces the manufacturing cost. And by directly connecting the gate electrode of the thin film transistor used in the driving circuit to the source wiring or the drain wiring, the number of contact holes can be reduced, and a display device capable of reducing the occupied area of the driving circuit can be provided. Accordingly, according to this embodiment, a display device with high electrical characteristics can be provided at low cost.

[0159] Therefore, according to this embodiment, a display device with high electrical characteristics can be provided at low cost.

[0160] Also, this embodiment can be freely combined with Embodiment 1, Embodiment 2, or Embodiment 3. ​​​

[0161] (Embodiment 5) In this embodiment, an example of an electronic paper is shown as a semiconductor device.

[0162] FIG. 17 shows an active matrix type electronic paper as an example of a semiconductor device different from a liquid crystal display device. As the thin film transistor 581 used in the pixel portion of the semiconductor device, it can be manufactured in the same manner as the thin film transistor of the pixel portion shown in Embodiment 4, and is a thin film transistor including an In-Ga-Zn-O based non-single crystal film as a semiconductor layer. Further, as shown in Embodiment 1, the pixel portion and the drive circuit can be manufactured on the same substrate, and an electronic paper with reduced manufacturing cost can be realized.

[0163] The electronic paper in FIG. 17 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer that are used as display elements, and causing a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0164] The thin film transistor 581 is a thin film transistor having a bottom gate structure, and the source electrode layer or the drain electrode layer is in contact with and electrically connected to the first electrode layer 587 through openings formed in the insulating layers 583, 584, and 585. Between the first electrode layer 587 and the second electrode layer 588, there are a black region 590a and a white region 590b, and spherical particles 589 including a cavity 594 filled with liquid around them are provided between a pair of substrates 580 and 596. The periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 17).

[0165] ​​​​​​ Also, it is possible to use an electrophoretic element instead of the twist ball. A transparent liquid encapsulates white microparticles charged positively and black microparticles charged negatively, and microcapsules with a diameter of about 10 μm to 20 0 μm are used. The microcapsules provided between the first electrode layer and the second electrode layer are such that when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move in opposite directions, and white or black can be displayed. A display element applying this principle is an electrophoretic display element, which is also called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required, and moreover, the power consumption is small, and it is possible to recognize the display portion even in a dim place. Also, even when no power is supplied to the display portion, it is possible to hold the image once displayed, so that even when the semiconductor device with a display function (also simply called a display device or a semiconductor device including the display device) is kept away from a radio wave transmission source, it is possible to save the displayed image. Through the above steps, it is possible to fabricate electronic paper with reduced manufacturing cost as a semiconductor device.

[0166]

[0167] This embodiment can be implemented in appropriate combination with the configurations described in Embodiment 1 or Embodiment 2.

[0168] (Embodiment 6) In this embodiment, an example of a light-emitting display device as a semiconductor device is shown. As the display element of the display device, here, a light-emitting element using electroluminescence is shown. Light-emitting devices that utilize electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL device, and the latter is called an inorganic EL device. When a voltage is applied to the light-emitting device, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, respectively, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. From such a mechanism, such a light-emitting device is called a current-excited type light-emitting device.

[0169]

[0170] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL device is used as the light-emitting device for explanation.

[0171] Figure 18 is a diagram showing an example of a pixel configuration to which digital time-division driving can be applied as an example of a semiconductor device.

[0172] The configuration and operation of a pixel to which digital time-division driving can be applied will be described. Here, an n-channel MOS transistor using an oxide semiconductor layer (In-Ga-Zn-O-based non-single crystal film) in the channel formation region is used. An example of using two channel-type transistors in one pixel is shown.

[0173] Pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitive element 6403. The switching transistor 64 01 has its gate connected to the scanning line 6406, and its first electrode (either the source electrode or the drain electrode) is connected to the signal line 6405, and its second electrode (the other of the source electrode and the drain electrode) is connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitive element 6403, its first electrode connected to the power supply line 640 7, and its second electrode connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408.

[0174] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential lower than the high power supply potential set for the power supply line 6407 and satisfies the low power supply potential < high power supply potential. For example, GND, 0V, etc. may be set as the low power supply potential. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light. Therefore, the potential difference between the high power supply potential and the low power supply potential is set so as to be equal to or greater than the forward threshold voltage of the light-emitting element 6404. Each potential is set accordingly.

[0175] Note that the capacitive element 6403 can also be omitted by substituting for the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, the channel region ​A capacitance may be formed between the gate electrode and the like.

[0176] Here, in the case of the voltage input voltage driving method, to the gate of the driving transistor 6402, a video signal is input such that the driving transistor 6402 has two states of being fully on or off. That is, the driving transistor 6402 operates in the linear region. To make the driving transistor 6402 operate in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. In addition, to the signal line 6405, a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied. (Power supply line voltage + Vth of the driving transistor 6402) or higher voltage is applied.

[0177] Also, when performing analog gradation driving instead of digital time gradation driving, by changing the signal input, the same pixel configuration as in FIG. 18 can be used.

[0178] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 64 04 refers to the voltage for a desired luminance and includes at least the forward threshold voltage. In addition, by inputting a video signal such that the driving transistor 6402 operates in the saturation region, current can flow through the light emitting element 6404. To make the driving transistor 64 02 operate in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 64 02. By making the video signal analog, a current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed.

[0179]

[0179] Note that the pixel configuration shown in FIG. 18 is not limited to this. For example, a switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added to the pixel shown in FIG. 18.

[0180] Next, the configuration of the light-emitting element will be described with reference to FIGS. 19(A), 19(B), and 19(C). Here, the case where the driving TFT is the thin-film transistor 170 shown in FIG. 1(B) will be taken as an example to describe the cross-sectional structure of the pixel. The driving TFTs TFT7001, 7011, and 7021 used in the semiconductor devices of FIGS. 19(A), 19(B), and 19(C) can be manufactured in the same manner as the thin-film transistor 170 shown in Embodiment 1, and are thin-film transistors having high electrical characteristics including an In-Ga-Zn-O-based non-single-crystalline film as a semiconductor layer.

[0181] For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, a top emission type that forms a thin-film transistor and a light-emitting element on a substrate and extracts light from the surface opposite to the substrate, a bottom emission type that extracts light from the surface on the substrate side, and a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate exist, and the pixel configuration shown in FIG. 18 can be applied to any emission structure of the light-emitting element.

[0182] The top emission type light-emitting element will be described with reference to FIG. 19(A).

[0183] FIG. 19(A) shows a cross-sectional view of a pixel in the case where the driving TFT, TFT7001, is the thin-film transistor 170 shown in FIG. 1(B) and the light emitted from the light-emitting element 7002 passes through to the anode 7005 side. In FIG. 19(A), the cathode 7003 of the light-emitting element 7002 and the driving TFT The TFT 7001, which is T, is electrically connected, and a light-emitting layer 7004 is formed on the cathode 7003, and an anode 7005 are sequentially laminated. The cathode 7003 has a low work function and can reflect light. Any material can be used as long as it is a conductive film. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. The light-emitting layer 7004 can be composed of a single layer or a plurality of layers laminated. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003. It is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or other light-transmitting conductive films can be used. The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 19(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow.

[0184]

[0185] Note that the second gate electrode provided on the oxide semiconductor layer in the driving circuit is preferably formed of the same material as the cathode 7003 because the process can be simplified.

[0186] Next, a light-emitting element with a bottom emission structure will be described with reference to Fig. 19(B). The driving TFT 7 ​​​​​​011 is the thin film transistor 170 shown in FIG. 1A, and the light emitting element 7012 emits light. FIG. 19B shows a cross-sectional view of a pixel in the case where the light emitted from the driving A light-emitting element is formed on a light-transmitting conductive film 7017 electrically connected to the moving TFT 7011. A cathode 7013 of 7012 is formed, and a light-emitting layer 7014 and an anode 70 In addition, when the anode 7015 is transparent, the anode 7015 is covered with the insulating film 15. As shown in FIG. 1, a shielding film 7016 for reflecting or shielding light may be formed. As in the case of FIG. 19(A), various conductive materials with small work functions can be used. However, the thickness of the film should be such that it transmits light (preferably 5 nm to 3 For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013. The light-emitting layer 7014 can be a single layer, as in FIG. The anode may be configured as a single layer or as a laminate of multiple layers. 7015 does not need to transmit light, but as in FIG. 19(A), it is a conductive material having light-transmitting properties. The shielding film 7016 can be formed of, for example, a light-reflecting metal or the like. However, it is not limited to a metal film. For example, a resin containing a black pigment may be used. You can also be there.

[0187] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 19B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0188] Note that a second gate electrode provided over the oxide semiconductor layer in the driver circuit is a cathode 7013. It is preferable to form with the same material because the process can be simplified.

[0189] Next, a light-emitting element having a double-sided injection structure will be described with reference to FIG. 19(C). FIG. 19(C) shows that on a light-transmissive conductive film 7027 electrically connected to the driving TFT 7021, the cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 and the anode 7025 are sequentially laminated on the cathode 7023. The cathode 7023, similar to the case of FIG. 19(A), can use various materials as long as they are conductive materials with a small work function. However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024, similar to FIG. 19(A), can be composed of a single layer or can be configured such that a plurality of layers are laminated. The anode 70 25, similar to FIG. 19(A), can be formed using a light-transmissive conductive material that transmits light.

[0190] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in FIG. 19(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0191] Note that the second gate electrode provided on the oxide semiconductor layer in the driving circuit is preferably formed of the same material as the conductive film 7027 because the process can be simplified. Also, the second gate electrode provided on the oxide semiconductor layer in the driving circuit is laminated using the same material as the conductive film 7027 and the cathode 7023, which not only simplifies the process but also reduces the wiring resistance by lamination. ​It can be lowered, which is preferable.

[0192] Here, although the organic EL element has been described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element. L element.

[0193] In this embodiment, an example in which a thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically connected has been shown. However, a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used.

[0194] The semiconductor device shown in this embodiment is not limited to the configuration shown in FIGS. 19(A), 19(B), and 19(C), and various modifications based on the disclosed technical idea are possible.

[0195] Next, the upper surface and cross-section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIGS. 20(A) and 20(B). FIG. 20(A) is a top view of the panel in which the thin film transistors and light-emitting elements formed on the first substrate are sealed with a sealing material between the second substrate, and FIG. 20(B) corresponds to a cross-sectional view taken along H-I of FIG. 20(A).

[0196] A sealing material 4505 is provided so as to surround the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b. Thus, the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 45 04a and 4504b​​​​​​​​​​​ 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. This seals the filling material 4507 together. High-performance, low-outgassing protective film (lamination film, UV-curable resin film, etc.) It is preferable to package (enclose) the product in a cover material.

[0197] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 20B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0198] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O non-single crystal films as semiconductor layers. As a result, the highly reliable thin film transistor described in Embodiment 1 can be applied. In addition, the thin film transistor 4509 is a thin film transistor having a semiconductor layer as shown in Embodiment 1 and FIG. The gate electrodes are disposed above and below the gate electrode.

[0199] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The first electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The light emitting element 4511 is not rotated in accordance with the direction of the light to be extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0200] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. Particularly, using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side wall of the opening is preferably formed to be an inclined surface having a continuous curvature.

[0201] The electroluminescent layer 4512 may be configured with a single layer or multiple layers laminated thereon. Either is acceptable.

[0202] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, a protective film may be formed on the second electrode layer 4513 and the partition wall 4520. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0203] Also, various signals and potentials supplied to the signal line driving circuits 4503a, 4503b, the scanning line driving circuits 4504a, 4504b or the pixel portion 4502 are supplied from the FPCs 4518a, 4518 b.

[0204] In this embodiment, the connection terminal electrode 4515 is formed from the same conductive film as the first electrode layer 4 517 of the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4509, 4 510.

[0205] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a via an anisotropic conductive film 4519.

[0206] On the substrate located in the light extraction direction from the light-emitting element 4511, the second substrate is not translucent It is necessary. In that case, a material having translucency such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

[0207] In addition, as the filler 4507, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used.

[0208] Further, if necessary, a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. may be appropriately provided on the light emitting surface of the light emitting element. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, anti-glare treatment can be performed to diffuse reflected light due to surface irregularities and reduce reflection.

[0209] The signal line drive circuits 4503a and 4503b and the scan line drive circuits 4504a and 4504b may be mounted on a separately prepared single crystal semiconductor substrate or a drive circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on an insulating substrate. Further, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or only a part thereof may be separately formed and mounted, and the present embodiment is not limited to the configurations of FIGS. 20(A) and 20(B).

[0210] By the above steps, a light emitting display device (display panel) with reduced manufacturing cost can be manufactured.

[0211] This embodiment is appropriately combined with the configurations described in Embodiment 1 or Embodiment 2. It is possible to implement.

[0212] (Embodiment 7) In this embodiment, the upper surface and cross-section of a liquid crystal display panel corresponding to one form of a semiconductor device will be described with reference to FIGS. 21(A1), 21(A2), and 21(B). FIG. 21(A1) , FIG. 21(A2) show thin film transistors 4010, 4011, including an In-Ga-Zn-O based polycrystalline film formed on the first substrate 4001 as a semiconductor layer, and a liquid crystal element 4013, which are sealed with a sealing material 4005 between the second substrate 4006, and is a top view of the panel. FIG. 21(B) corresponds to a cross-sectional view taken along M-N in FIGS. 21(A1) and 21(A2).

[0213] A sealing material 4005 is provided so as to surround the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is mounted. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 21(A1)

[0214] is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 21(A2) is an example of mounting the signal line driving circuit 4003 by the wire bonding method, or the like. is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 21(A2) is This is an example of implementing the signal line driving circuit 4003 by the TAB method.

[0215] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of thin film transistors. In FIG. 21(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. Insulating layers 4020 and 402 1 are provided on the thin film transistors 4010 and 4011.

[0216] The thin film transistors 4010 and 4011 can be applied to the thin film transistors shown in Embodiment 1 including an In-Ga-Zn-O based non-single crystal film as a semiconductor layer. The thin film trans istors 4011 correspond to the thin film transistors having the back gate electrodes shown in FIG. 2(A) of Embodiment 2.

[0217] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The overlapping portion of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0218] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, ​​​​, FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Alternatively, you can use aluminum foil with a PVF film or polyester film. A sheet having a structure sandwiched between films can also be used.

[0219] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 40 to the conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0220] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to It is short at 100μs, has optical isotropy so no alignment treatment is required, and has small viewing angle dependency. stomach.

[0221] Although the present embodiment is an example of a transmissive liquid crystal display device, a semi-transmissive liquid crystal display device may also be used. It can also be applied to a liquid crystal display device.

[0222] In addition, in the liquid crystal display device of this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and on the inside, an example is shown in which a colored layer and an electrode layer used for the display element are provided in this order. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the colored layer. Further, a light-shielding film that functions as a black matrix may be provided.

[0223] In addition, in this embodiment, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor obtained in Embodiment 1 is covered with an insulating layer (insulating layer 4020, insulating layer 4021) that functions as a protective film or a planarizing insulating film. The protective film is for preventing the intrusion of contaminants such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferable. The protective film may be formed as a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film using a sputtering method. In this embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited, and it may be formed by various methods such as a PCVD method. In a part of the drive circuit, this protective film functions as a second gate insulating layer, and includes a thin film transistor having a back gate on the second gate insulating layer.

[0224] Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, a silicon oxide film is formed as the first layer of the insulating layer 4020 using a sputtering method. The silicon oxide film as the protective film ​ Using is effective in preventing hillocks in the aluminum films used as the source electrode layer and the drain electrode layer.

[0225] Also, an insulating layer is formed as the second layer of the protective film. Here, as the second layer of the insulating layer 4020, a silicon nitride film is formed using a sputtering method. When a silicon nitride film is used as the protective film, it is possible to suppress ions such as sodium from entering the semiconductor region and changing the electrical characteristics of the TFT.

[0226] Also, after forming the protective film, annealing (300 °C to 400 °C) of the semiconductor layer may be performed. Also, a back gate is formed after forming the protective film.

[0227] Also, an insulating layer 4021 is formed as the planarization insulating film. As the insulating layer 4021, heat-resistant organic materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials.

[0228] The siloxane-based resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group.

[0229] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, , spin coating, dipping, spray coating, droplet ejection methods (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When forming the insulating layer 4021 using a material liquid, annealing of the semiconductor layer (300 °C to 400 °C) may be performed simultaneously in the baking process. By combining the baking process of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.

[0230] The pixel electrode layer 4030 and the counter electrode layer 4031 can be made of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or other conductive materials having translucency. can be used.

[0231] Also, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Also, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

[0232] As the conductive polymer, so-called π - electron conjugated system conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or Examples thereof include a derivative thereof, or a copolymer of two or more of these.

[0233] Also, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4 002 are supplied from the FPC 4018.

[0234] In the present embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 40 30 included in the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4010, 40 11.

[0235] The connection terminal electrode 4015 is electrically connected to the terminal included in the FPC 4018 via the anisotropic conductive film 4019.

[0236] Also, in FIGS. 21(A1) and 21(A2), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001. However, the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or only a part of the scanning line driving circuit may be separately formed and mounted.

[0237] FIG. 22 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600.

[0238] FIG. 22 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, a coloring layer 2605, and a polarizing plate 2606 are provided therebetween to form a display region. ​​​​。The coloring layer 2605 is necessary when performing color display. In the case of the RGB system, coloring layers corresponding to each of the red, green, and blue colors are provided corresponding to each pixel. Outside the TFT substrate 2600 and the opposing substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, it may be laminated in a state having a retardation plate between the polarizing plate and the liquid crystal layer.

[0239] In the liquid crystal display module, a TN (Twisted Nematic) mode, an IPS (I n-Plane-Switching) mode, an FFS (Fringe Field S witching) mode, an MVA (Multi-domain Vertical A lignment) mode, a PVA (Patterned Vertical Alig nment), an ASM (Axially Symmetric aligned Mic ro-cell) mode, an OCB (Optical Compensated Bire fringence) mode, an FLC (Ferroelectric Liquid C rystal) mode, an AFLC (AntiFerroelectric Liquid Crystal), etc. can be used.

[0240] Through the above steps, a liquid crystal display panel with reduced manufacturing cost as a semiconductor device can be fabricated.

[0241] This embodiment can be implemented in appropriate combination with the configurations described in Embodiment 1, Embodiment 2, or Embodiment 3. It can be implemented in appropriate combination with the configurations described in Embodiment 1, Embodiment 2, or Embodiment 3.

[0242] (Embodiment 8) The semiconductor device according to the disclosed invention can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large gaming machines such as pachinko machines. are included.

[0243] FIG. 23(A) shows an example of a portable information terminal device 9200. The portable information terminal device 9 200 incorporates a computer and can perform various data processes. Such a portable information terminal device 9200 includes a PDA (Personal Digital Assistant).

[0244] The portable information terminal device 9200 is composed of two housings, a housing 9201 and a housing 9203. The housing 9201 and the housing 9203 are connected by a connecting portion 9207 so as to be foldable. A display portion 9202 is incorporated in the housing 9201, and the housing 9203 is provided with a keyboard 9205. Of course, the configuration of the portable information terminal device 9200 is not limited to the above, and any configuration having at least a thin film transistor with a back gate electrode is acceptable, and other accessory equipment can be appropriately provided. A drive circuit on the same substrate is acceptable, and a configuration with other accessory equipment appropriately provided can be adopted. A drive circuit ​​By forming a pixel portion, the manufacturing cost can be reduced, and a thin film transistor with high electrical characteristics can be obtained. A portable information terminal device having the same can be realized.

[0245] Figure 23(B) shows an example of a digital video camera 9500. The digital video camera 9500 has a display portion 9503 incorporated in a housing 9501, and various operation portions are provided therein. Note that the configuration of the digital video camera 9500 is not particularly limited, and it may be a configuration including at least a thin film transistor having a back gate electrode, and other attached equipment may be appropriately provided. By forming a drive circuit and a pixel portion on the same substrate, the manufacturing cost can be reduced, and a digital video camera having a thin film transistor with high electrical characteristics can be realized. By forming a drive circuit and a pixel portion on the same substrate, the manufacturing cost can be reduced, and a digital video camera having a thin film transistor with high electrical characteristics can be realized.

[0246] Figure 23(C) shows an example of a mobile phone 9100. The mobile phone 9100 is composed of two housings, a housing 9102 and a housing 9101, and is connected by a connecting portion 9103 so as to be foldable. A display portion 9104 is incorporated in the housing 9102, and operation keys 9106 are provided in the housing 9101. Note that the configuration of the mobile phone 9100 is not particularly limited, and it may be a configuration including at least a thin film transistor having a back gate electrode, and other attached equipment may be appropriately provided. By forming a drive circuit and a pixel portion on the same substrate, the manufacturing cost can be reduced, and a mobile phone having a thin film transistor with high electrical characteristics can be realized. and other attached equipment may be appropriately provided. By forming a drive circuit and a pixel portion on the same substrate, the manufacturing cost can be reduced, and a mobile phone having a thin film transistor with high electrical characteristics can be realized.

[0247] Figure 23(D) shows an example of a portable computer 9400. The computer 9400 includes a housing 9401 and a housing 9404 that are connected so as to be openable and closable. The housing 94​​ 01 is incorporated with a display unit 9402, and the housing 9404 is provided with a keyboard 9403 and the like. Note that the configuration of the computer 9400 is not particularly limited, and it may be a configuration including at least a thin film transistor having a back gate electrode, and other attached equipment may be provided as appropriate. By forming a drive circuit and a pixel portion on the same substrate, the manufacturing cost can be reduced, and a computer having a thin film transistor with high electrical characteristics can be realized. FIG. 24(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. An image can be displayed by the display unit 9603. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown.

[0248] FIG. 24(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. An image can be displayed by the display unit 9603. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate channels and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be provided with a display unit 9607 for displaying information output from the remote control unit 9610. The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate channels and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be provided with a display unit 9607 for displaying information output from the remote control unit 9610.

[0249] The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate channels and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be provided with a display unit 9607 for displaying information output from the remote control unit 9610. The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate channels and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be provided with a display unit 9607 for displaying information output from the remote control unit 9610. The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate channels and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be provided with a display unit 9607 for displaying information output from the remote control unit 9610. The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate channels and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be provided with a display unit 9607 for displaying information output from the remote control unit 9610. The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate channels and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote control unit 9610 may be provided with a display unit 9607 for displaying information output from the remote control unit 9610.

[0250] Note that the television device 9600 has a configuration including a receiver, a modem, and the like. The receiver can receive general television broadcasts, and further, by connecting to a communication network via a modem, either wired or wirelessly, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication can also be performed. Note that the television device 9600 has a configuration including a receiver, a modem, and the like. The receiver can receive general television broadcasts, and further, by connecting to a communication network via a modem, either wired or wirelessly, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication can also be performed. Note that the television device 9600 has a configuration including a receiver, a modem, and the like. The receiver can receive general television broadcasts, and further, by connecting to a communication network via a modem, either wired or wirelessly, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication can also be performed. (Between sender and receiver, or between receivers) information communication can also be performed.

[0251] Figure 24(B) shows an example of the digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and by displaying the image data taken with, for example, a digital camera, it can function in the same way as a normal photo frame.

[0252] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (such as USB terminals and terminals connectable to various cables such as USB cables), a recording medium insertion part, etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface as it improves the design. For example, by inserting a memory storing the image data taken with a digital camera into the recording

[0253] medium insertion part of the digital photo frame, the image data can be captured and the captured image data can be displayed on the display unit 9703.

[0254] Figure 25(A) shows an example of another mobile phone 1000 different from the mobile phone in Fig. 23(C). The mobile phone 1000 includes, in addition to a display unit 1002 incorporated in a housing 1001, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc.

[0255] The mobile phone 1000 shown in Fig. 25(A) can be operated by touching the Information can be input. Also, operations such as making a phone call or sending an email can be performed by touching the display unit 1002 with a finger or the like.

[0256] The screen of the display unit 1002 mainly has three modes. The first is the display mode mainly for displaying images The second is the input mode mainly for inputting information such as characters. The third is the display + input mode in which two modes of the display mode and the input mode are mixed. For example, when making a phone call or creating an email, the display unit 1002 can be set to the character input mode mainly for character input, and an input operation on the characters displayed on the screen can be performed. In this

[0257] case, it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000 to detect the inclination, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched.

[0258] Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of the image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0259] Also, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected, and the table

[0260] Also, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected, and the table ​​​​When there is no input by touch operation on the display unit 1002 for a certain period, the screen mode may be controlled to switch from the input mode to the display mode. It may be controlled to switch from the input mode to the display mode when there is no input by touch operation on the display unit 1002 for a certain period.

[0261] The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 10 02, it is possible to perform personal authentication by imaging palm prints, fingerprints, etc. In addition, if a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, it is also possible to image finger veins, palm veins, etc. It is also possible to image finger veins, palm veins, etc.

[0262] FIG. 25(B) is also an example of a mobile phone. The mobile phone in FIG. 25(B) includes a display device 9410 including a housing 9411, a display unit 9412, and operation buttons 9413, and a communication device 9400 including operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting unit 9406 that emits light when there is an incoming call, provided on a housing 9401. The display device 9410 having a display function is detachably attached to the communication device 9400 having a telephone function in two directions indicated by arrows. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Further, when only a display function is required, the display device 9410 can be removed from the communication device 9400, and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange image or input information by wireless communication or wired communication, and each has a rechargeable battery. or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Further, when only a display function is required, the display device 9410 can be removed from the communication device 9400, and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange image or input information by wireless communication or wired communication, and each has a rechargeable battery. or wired communication, and each has a rechargeable battery.

[0263] (Embodiment 9) Here, a second oxide semiconductor layer is provided between the source wiring (or drain wiring) and the semiconductor layer (n+ An example of a display device having a thin film transistor configured to have an n-layer is shown in FIG. 26. Note that in FIG. 26, the same reference numerals are used for the same parts as in FIG. 1(A) for explanation.

[0264] The first thin film transistor 480 shown in FIG. 26 is a thin film transistor used in a driving circuit and is an example in which an n-layer 406a is provided between the oxide semiconductor layer 405 and the first wiring 409, and an n-layer 406b is provided between the oxide semiconductor layer 405 and the second wiring 410. The first thin film transistor 480 has a first gate electrode 401 below the oxide semiconductor layer 405 and a second gate electrode 470 above the oxide semiconductor layer 405. + layer 406a and an n-layer 406b are provided between the oxide semiconductor layer 405 and the second wiring 410. The first thin film transistor 480 has a first gate electrode 401 below the oxide semiconductor layer 405 and a second gate electrode 470 above the oxide semiconductor layer 405. body layer 405 and the second wiring 410, an n-layer 406b is provided. The first thin film transistor 480 has a first gate electrode 401 below the oxide semiconductor layer 405 and a second gate electrode 470 above the oxide semiconductor layer 405. + layer 406b is provided. The first thin film transistor 480 has a first gate electrode 401 below the oxide semiconductor layer 405 and a second gate electrode 470 above the oxide semiconductor layer 405. thin film transistor 480 has a first gate electrode 401 below the oxide semiconductor layer 405 and a second gate electrode 470 above the oxide semiconductor layer 405. oxide semiconductor layer 405 and a second gate electrode 470 above the oxide semiconductor layer 405.

[0265] Also, the second thin film transistor 481 is a thin film transistor used in a pixel portion, and n-layers 104a and 104b are provided between the oxide semiconductor layer 103 and the source electrode layer or drain electrode layers 105a and 105b, respectively, as an example. oxide semiconductor layer 103 and the source electrode layer or drain electrode layers 105a, 105b, n-layers 104a, 104b are provided, respectively, as an example. + layers 104a, 104b are provided, respectively, as an example.

[0266] n + layers are oxide semiconductor layers having lower resistance than the oxide semiconductor layer 405 and the oxide semiconductor layer 103, and function as source regions or drain regions. oxide semiconductor layer 405 and the oxide semiconductor layer 103, and function as source regions or drain regions.

[0267] n + layers are formed using a target with In2O3:Ga2O3:ZnO = 1:1:1. The film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced for sputter film formation. Despite intentionally using a target with In2O3:Ga2O3:ZnO = 1:1:1, immediately after film formation, the size is 1 n conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced for sputter film formation. Despite intentionally using a target with In2O3:Ga2O3:ZnO = 1:1:1, immediately after film formation, the size is 1 n flow rate 40 sccm is introduced for sputter film formation. Despite intentionally using a target with In2O3:Ga2O3:ZnO = 1:1:1, immediately after film formation, the size is 1 n 1:1:1 and, immediately after film formation, the size is 1 n An In-Ga-Zn-O based polycrystalline film containing crystal grains of m~10nm may be formed. . Note that the component ratio of the target, the film formation pressure (0.1 Pa to 2.0 Pa), the power (250 W to 3000 W: 8-inch φ), the temperature (room temperature to 100 °C), the film formation conditions of reactive sputtering, etc. By appropriately adjusting, it can be said that the presence or absence of crystal grains, the density of crystal grains, and the diameter size can be adjusted in the range of 1 nm to 10 nm. The film thickness of the second In-Ga-Zn-O based polycrystalline film is 5 nm to 20 nm. Of course, when crystal grains are contained in the film, the size of the contained crystal grains does not exceed the film thickness. In this embodiment, the film thickness of the second In-Ga-Zn-O based polycrystalline film is 5 nm.

[0268] The semiconductor device of this embodiment has a configuration with an n + layer between the wiring and the semiconductor layer, so compared with the Schottky junction of Embodiment 1, it has a thermally stable operation.

[0269] Also, by laminating the conductive film that becomes the source electrode layer or drain electrode layer 105a, 105b and the n + layer oxide semiconductor film by sputtering without exposing it to the atmosphere, it is possible to prevent the source electrode layer or drain electrode layer from being exposed and dust from adhering during the manufacturing process.

[0270] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. .

Explanation of Reference Numerals

[0271] 100 Substrate 101 Gate electrode 102 Gate insulating layer 103 Oxide semiconductor layer 104a, 104b n + layer 105a source electrode layer 105b drain electrode layer 107 protective insulating layer 108 capacitive wiring 109 oxide semiconductor film 110 pixel electrode 111 oxide semiconductor film 120 connection electrode 121 terminal 122 terminal 125 contact hole 126 contact hole 127 contact hole 128 transparent conductive film 129 transparent conductive film 131 resist mask 132 conductive film 150 terminal 151 terminal 152 gate insulating layer 153 connection electrode 154 protective insulating film 155 transparent conductive film 156 electrode 170 second thin film transistor 400 substrate 401 first gate electrode 402 gate electrode 403 first gate insulating layer 404 contact hole 405 oxide semiconductor layer 407 oxide semiconductor layer 409 wiring 410 wiring 411 wiring 412 second gate insulating layer 430 thin film transistor 431 thin film transistor 432 thin film transistor 433 thin film transistor 440 substrate 441 gate electrode 442 gate electrode 443 gate insulating layer 444 Contact hole 445 Oxide semiconductor layer 447 Oxide semiconductor layer 449 First wiring 450 Second wiring 451 Third wiring 452 Protective layer 453 Connection wiring 460 Thin film transistor 461 Thin film transistor 470 Second gate electrode 471 Electrode 472 First electrode 473 Insulating layer 474 Second electrode 475 Light emitting layer 476 Electrode 581 Thin film transistor 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material

Claims

1. A pixel portion and a scanning line driver circuit are included. the scanning line driving circuit includes first to fifth transistors, one of a source electrode or a drain electrode of the first transistor is always electrically connected to one of a source electrode or a drain electrode of the fifth transistor and a first wiring; a first conductive layer having a function as a gate electrode of the first transistor is always electrically connected to a third conductive layer having a function as a gate electrode of the second transistor through a second conductive layer having a function as one of a source electrode or a drain electrode of the third transistor and a function as one of a source electrode or a drain electrode of the fourth transistor; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a gate electrode of the third transistor; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a second wiring; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the second wiring; a gate electrode of the third transistor is always electrically connected to a gate electrode of the fifth transistor; the second transistor has a first semiconductor layer including a channel formation region overlapping the third conductive layer; the first wiring has a function of transmitting a signal output from the scanning line driver circuit to the pixel portion; the pixel portion includes a sixth transistor, the sixth transistor includes a fourth conductive layer having a function as a gate electrode, and a second semiconductor layer including a channel formation region overlapping the fourth conductive layer; A display device in which, in a plan view, the entire periphery of the second semiconductor layer overlaps with the fourth conductive layer.

2. A pixel portion and a scanning line driver circuit are included. the scanning line driving circuit includes first to fifth transistors, one of a source electrode or a drain electrode of the first transistor is always electrically connected to one of a source electrode or a drain electrode of the fifth transistor and a first wiring; a first conductive layer having a function as a gate electrode of the first transistor is always electrically connected to a third conductive layer having a function as a gate electrode of the second transistor through a second conductive layer having a function as one of a source electrode or a drain electrode of the third transistor and a function as one of a source electrode or a drain electrode of the fourth transistor; one of a source electrode and a drain electrode of the second transistor is always electrically connected to a gate electrode of the third transistor; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a second wiring; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to the second wiring; a gate electrode of the third transistor is always electrically connected to a gate electrode of the fifth transistor; the second transistor has a first semiconductor layer including a channel formation region overlapping the third conductive layer; the first wiring has a function of transmitting a signal output from the scanning line driver circuit to the pixel portion; the pixel portion includes a sixth transistor, the sixth transistor includes a fourth conductive layer having a function as a gate electrode, a second semiconductor layer including a channel formation region overlapping the fourth conductive layer, a fifth conductive layer having a function as one of a source electrode and a drain electrode, and a sixth conductive layer having a function as the other of the source electrode and the drain electrode; an entire periphery of the second semiconductor layer overlaps with the fourth conductive layer in a plan view; A display device, in a plan view, wherein the fifth conductive layer has an area sandwiched between the sixth conductive layers.

Images