Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device in which destruction of a gate insulating film associated with electric field concentration can be suppressed.SOLUTION: A silicon carbide semiconductor device includes: a gate insulating film 81; and a gate trench 5 which is defined by a side face 3 leading to a drift region while penetrating a source region 13 and a body region 12 and a bottom face 4 communicated with the side face, and which extends along a virtual straight line parallel to a first principal surface 1. The side face includes: a first side face 31; a second side face 32; and a third side face. The gate insulating film includes: a first portion 71 which is in contact with a first region 51 communicated with the first side face, and has a first thickness T1; a second part 72 which is in contact with a second region 52 communicated with the second side face, and has a second thickness T2; and a third portion which is in contact with a third region communicated with a third side face, and has a third thickness. The third thickness is larger than the first thickness and the second thickness.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device.

Background Art

[0002] As one of silicon carbide semiconductor devices, a trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which a gate trench is formed in a silicon carbide substrate and a gate electrode is provided in the gate trench via a gate insulating film has been disclosed (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to a conventional trench gate type MOSFET, although the intended purpose is achieved, an electric field concentrates in the gate insulating film in the vicinity of the upper end of the gate trench, and there is a risk that the gate insulating film may be damaged.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of suppressing the breakdown of a gate insulating film due to electric field concentration.

Means for Solving the Problems

[0006] The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, and a contact region provided on the body region and having the second conductivity type. The first main surface is defined by a side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface continuous with the side surface. A gate trench extending along a virtual straight line parallel to the first main surface is provided, and further includes a gate insulating film in contact with the side surface, the bottom surface, and the first main surface. The side surface includes a first side surface extending along the virtual straight line, a second side surface extending along the virtual straight line and separated from the first side surface in a direction parallel to the first main surface, and a third side surface continuous with the first side surface and the second side surface. The gate insulating film includes a first portion in contact with a first region continuous with the first side surface of the first main surface and having a first thickness, a second portion in contact with a second region continuous with the second side surface of the first main surface and having a second thickness, and a third portion in contact with a third region continuous with the third side surface of the first main surface and having a third thickness. The third thickness is greater than the first thickness and the second thickness.

Advantages of the Invention

[0007] According to the present disclosure, breakdown of the gate insulating film due to electric field concentration can be suppressed.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Embodiments for carrying out the invention will be described below.

[0010] [Description of Embodiments of the Present Disclosure] Embodiments of the present disclosure will be listed and described first. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated. In the crystallographic description in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Also, a negative crystallographic index is usually expressed by attaching "-" (bar) above the number, but in this specification, a negative sign is attached before the number. Further, in the present disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are assumed to be mutually orthogonal directions. The plane including the X1-X2 direction and the Y1-Y2 direction is described as the XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is described as the YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is described as the ZX plane. For convenience, the Z1-Z2 direction is taken as the vertical direction, the Z1 side is the upper side, and the Z2 side is the lower side. Also, a plan view means viewing an object from the Z1 side, and a planar shape means the shape of an object viewed from the Z1 side.

[0011] 〔1〕 The silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, and a contact region provided on the body region and having the second conductivity type. On the first main surface, there is defined by a side surface that penetrates the source region and the body region and reaches the drift region and a bottom surface continuous with the side surface. A gate trench extending along a virtual straight line parallel to the first main surface is provided, and further includes a gate insulating film in contact with the side surface, the bottom surface, and the first main surface. The side surface has a first side surface extending along the virtual straight line, a second side surface extending along the virtual straight line and separated from the first side surface in a direction parallel to the first main surface, and a third side surface continuous with the first side surface and the second side surface. The gate insulating film has a first portion in contact with a first region continuous with the first side surface of the first main surface and having a first thickness, a second portion in contact with a second region continuous with the second side surface of the first main surface and having a second thickness, and a third portion in contact with a third region continuous with the third side surface of the first main surface and having a third thickness. The third thickness is larger than the first thickness and the second thickness.

[0012] Since the third thickness of the third portion of the gate insulating film is larger than the first thickness of the first portion and the second thickness of the second portion, breakdown of the gate insulating film in the third portion can be suppressed, and excellent reliability can be ensured. Although it is also possible to suppress breakdown of the gate insulating film by increasing the overall thickness of the gate insulating film, in that case, the gate insulating film on the body region may become excessively thick due to alignment deviation or the like during the formation of the gate insulating film. On the other hand, in this silicon carbide semiconductor device, even if alignment deviation or the like occurs, it is possible to suppress the gate insulating film on the body region from becoming excessively thick in the vicinity of the first portion and the second portion. Therefore, variations in characteristics such as channel resistance and threshold voltage due to variations in the thickness of the gate insulating film can be suppressed.

[0013] [2] In [1], the third side surface may have a first region that is connected to the bottom surface and inclined at a first angle with respect to a plane parallel to the first main surface, and a second region that connects the first region and the first main surface and inclined at a second angle smaller than the first angle with respect to a plane parallel to the first main surface. In this case, electric field concentration in the third portion is easily alleviated.

[0014] [3] In [1] or [2], the side surface may have a fourth side surface continuing to the first side surface and the second side surface on a side opposite to the third side surface, and the gate insulating film may have a fourth portion having a fourth thickness in contact with a fourth region continuing to the fourth side surface of the first main surface, the fourth thickness being greater than the first thickness and the second thickness. In this case, breakdown of the gate insulating film in the fourth portion may be suppressed, and excellent reliability may be ensured.

[0015] [4] In [3], the third side surface may have a first surface connected to the bottom surface and inclined at a first angle with respect to a plane parallel to the first main surface, and the fourth side surface may have a third surface connected to the bottom surface and inclined at a third angle with respect to a plane parallel to the first main surface, the first angle being greater than the third angle, and the third thickness being greater than the fourth thickness. Although an electric field is more likely to concentrate in the third portion than in the fourth portion, breakdown of the gate insulating film can be suppressed because the third thickness is greater than the fourth thickness.

[0016] [5] In [4], the first main surface may be a surface of the {000-1} plane of the silicon carbide substrate inclined by an angle θ toward the direction in which the virtual straight line extends, and the difference between the first angle and the third angle may be 2θ. By using a silicon carbide substrate having an off-angle of angle θ, it is easy to grow an epitaxial layer with good crystallinity. In addition, by forming a gate trench by thermal etching of such a silicon carbide substrate, it is easy to obtain good side surfaces with little damage. In this case, the difference between the first angle and the third angle is 2θ.

[0017] 〔6〕In [1] to [5], a plurality of the gate trenches may be provided so as to overlap the virtual straight line at regular intervals. In this case, a region for relaxing the electric field concentration in the silicon carbide substrate can be provided through the spaces between the gate trenches.

[0018] 〔7〕In [1] to [6], it has a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the silicon carbide substrate, and in a plan view from a direction perpendicular to the first main surface, the gate electrode may be provided between the first portion and the second portion and separated from the first portion and the second portion. In this case, the breakdown of the gate insulating film can be suppressed by avoiding the electric field concentration at the first portion and the second portion.

[0019] 〔8〕In [1] to [7], the first side surface and the second side surface of the gate trench may include the {0-33-8} plane. In this case, good mobility can be obtained on the side surface of the gate trench, and the channel resistance can be reduced.

[0020] [Embodiments of the present disclosure] Embodiments of the present disclosure relate to a so-called vertical MOSFET (silicon carbide semiconductor device). FIG. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a diagram showing the configuration of the first main surface in a silicon carbide semiconductor device according to an embodiment. FIGS. 3 to 5 are cross-sectional views showing the configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIGS. 1 and 2. FIG. 4 corresponds to a cross-sectional view taken along line VI-VI in FIGS. 1 and 2. FIG. 5 corresponds to a cross-sectional view taken along line V-V in FIGS. 1 and 2.

[0021] As shown in FIGS. 1 to 5, the MOSFET 100 according to this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 63, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains, for example, an n-type impurity such as nitrogen (N) and has an n-type (first conductivity type).

[0022] The first main surface 1 is a {0001} plane or a plane in which the {0001} plane is inclined by an off-angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane in which the (000-1) plane is inclined by an off-angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more, or 2° or more. The off-angle may be 6° or less, or 4° or less.

[0023] The silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, an electric field relaxation region 16, a connection region 17, and a contact region 18.

[0024] The drift region 11 is provided on the silicon carbide single crystal substrate 50. The drift region 11 is on the first main surface 1 side of the silicon carbide single crystal substrate 50. The drift region 11 may be continuous with the silicon carbide single crystal substrate 50. The drift region 11 contains, for example, an n-type impurity such as nitrogen or phosphorus (P) and has an n-type conductivity type. The drift region 11 mainly has, for example, a third region 11C, a fourth region 11D, and a fifth region 11E.

[0025] The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity type (second conductivity type). The body region 12 is on the first main surface 1 side (Z1 side) of the drift region 11. The drift region 11 is on the second main surface 2 side (Z2 side) of the body region 12. The body region 12 is in contact with the drift region 11.

[0026] The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity type. The source region 13 is on the first main surface 1 side of the body region 12. The body region 12 is on the second main surface 2 side of the source region 13. The source region 13 is in contact with the body region 12. The source region 13 constitutes the first main surface 1. The source region 13 is covered by the gate insulating film 81. The source region 13 is in direct contact with the gate insulating film 81.

[0027] The contact region 18 contains p-type impurities such as aluminum and has a p-type conductivity type. The effective concentration of the p-type impurities in the contact region 18 is higher than that of the p-type impurities in the body region 12, for example. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 constitutes the first main surface 1. The contact region 18 mainly has, for example, a first region 18A and a second region 18B.

[0028] A gate trench 5 defined by a side surface 3 and a bottom surface 4 is provided on the first main surface 1. The side surface 3 penetrates the source region 13, the body region 12, and the drift region 11 and reaches the drift region 11. The bottom surface 4 is continuous with the side surface 3. The source region 13, the body region 12, and the drift region 11 are in contact with the side surface 3. The bottom surface 4 is located in the drift region 11. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. Details of the gate trench 5 will be described later.

[0029] In particular, as shown in FIGS. 1 and 2, in a plan view, that is, when viewed from a direction perpendicular to the first main surface 1, the gate trench 5 overlaps with a virtual straight line L1 extending in the Y1 - Y2 direction (first direction) parallel to the first main surface 1. In the plan view, the gate trench 5 is on the virtual straight line L1. A plurality of gate trenches 5 are provided at regular intervals on the virtual straight line L1. For example, a plurality of gate trenches 5 are provided to overlap with the virtual straight line L1 at a first period F1. Also, in the plan view, a plurality of gate trenches 5 are provided at regular intervals in the X1 - X2 direction (second direction) perpendicular to the Y1 - Y2 direction. A plurality of gate trenches 5 may be provided, for example, in an array shape.

[0030] The electric field relaxation region 16 contains a p - type impurity such as aluminum, for example, and has a p - type conductivity type. The electric field relaxation region 16 is between the bottom surface 4 of the gate trench 5 and the second main surface 2. That is, the electric field relaxation region 16 is away from the bottom surface 4 of the gate trench 5. The electric field relaxation region 16, similar to the gate trench 5, overlaps with the virtual straight line L1 in the plan view. In the plan view, the electric field relaxation region 16 is on the virtual straight line L1. On the virtual straight line L1, the electric field relaxation region 16 may be provided in common for a plurality of gate trenches 5. Also, in the plan view, a plurality of electric field relaxation regions 16 are provided at regular intervals in the X1 - X2 direction. A plurality of electric field relaxation regions 16 may be provided in a stripe shape.

[0031] The fifth region 11E of the drift region 11 is on the side of the second main surface 2 rather than the electric field relaxation region 16. The fifth region 11E is in contact with the electric field relaxation region 16. The fifth region 11E is on the side of the first main surface 1 rather than the silicon carbide single - crystal substrate 50. The fifth region 11E may be sandwiched between the electric field relaxation region 16 and the silicon carbide single - crystal substrate 50. The fifth region 11E may be continuous with the silicon carbide single - crystal substrate 50. A buffer layer containing an n - type impurity such as nitrogen, for example, and having an n - type conductivity type may be provided between the silicon carbide single - crystal substrate 50 and the fifth region 11E.

[0032] The fourth region 11D is on the first main surface 1 side rather than the fifth region 11E. The fourth region 11D is continuous with the fifth region 11E. The fourth region 11D is in contact with the electric field relaxation region 16 in the X1-X2 direction. The fourth region 11D and the electric field relaxation region 16 may be located in the same plane parallel to the second main surface 2.

[0033] The third region 11C is on the second main surface 2 side rather than the body region 12, and on the first main surface 1 side rather than the electric field relaxation region 16 and the fourth region 11D. The third region 11C is continuous with the fourth region 11D. The third region 11C is sandwiched between the body region 12, and the electric field relaxation region 16 and the fourth region 11D. The third region 11C is in contact with each of the body region 12, the electric field relaxation region 16, and the fourth region 11D. The upper end surface of the third region 11C includes, for example, the bottom surface 4 of the gate trench 5.

[0034] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is composed of a material containing, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with each of the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 and the contact region 18 on the first main surface 1. Details of the gate insulating film 81 will be described later.

[0035] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is composed of, for example, polysilicon (poly-Si) containing a conductive impurity. The gate electrode 82 is disposed inside the gate trench 5. Details of the gate electrode 82 will be described later.

[0036] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0037] The interlayer insulating film 83 overlaps with the virtual straight line L1 in plan view, similar to the gate trench 5 and the electric field relaxation region 16. On the virtual straight line L1, the interlayer insulating film 83 may be provided in common for a plurality of gate trenches 5. In plan view, contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the X1-X2 direction. The contact holes 90 are provided such that a gate trench 5 is positioned between adjacent contact holes 90 in the X1-X2 direction in plan view. The contact holes 90 extend in the Y1-Y2 direction. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0038] In particular, as shown in FIGS. 1 and 2, the first region 18A of the contact region 18 extends in the X1-X2 direction through between adjacent gate trenches 5 in the Y1-Y2 direction and intersects the virtual straight line L1. A part of the first region 18A may be covered by the interlayer insulating film 83 between adjacent gate trenches 5 in the Y1-Y2 direction. The gate insulating film 81 and the gate electrode 82 may be sandwiched between the first region 18A and the interlayer insulating film 83 in the Z1-Z2 direction. Another part of the first region 18A may be exposed from the interlayer insulating film 83 through the contact holes 90 between two adjacent virtual straight lines L1 in the X1-X2 direction.

[0039] The second region 18B is exposed from the interlayer insulating film 83 through the contact hole 90. The second region 18B is provided between adjacent gate trenches 5 in the X1-X2 direction. The second region 18B is provided on both sides of the gate trench 5 in the X1-X2 direction. A part (narrow portion) of the source region 13 is sandwiched between the gate trench 5 and the second region 18B in the X1-X2 direction. The second region 18B extends from each first region 18A to the Y1 side and the Y2 side. Between two adjacent first regions 18A in the Y1-Y2 direction, a part of the source region 13 is exposed from the interlayer insulating film 83 through the contact hole 90 between the second region 18B extending from one first region 18A to the Y1 side and the second region 18B extending from the other first region 18A to the Y2 side.

[0040] In particular, as shown in FIG. 1, the first region 18A, the second region 18B, and the source region 13 are exposed from the interlayer insulating film 83 through the contact hole 90. The portion (narrow portion) of the source region 13 sandwiched between the gate trench 5 and the second region 18B is covered with the interlayer insulating film 83. That is, in plan view, the narrow portion of the source region 13 is away from the source electrode 60.

[0041] The connection region 17 contains p-type impurities such as aluminum and has a p-type conductivity type. The connection region 17 electrically connects the first region 18A of the contact region 18 and the electric field relaxation region 16. The connection region 17 contacts the electric field relaxation region 16 on the virtual straight line L1. The connection region 17 may extend in the X1-X2 direction, similar to the first region 18A. The connection region 17 may be provided between adjacent gate trenches 5 in the Y1-Y2 direction in plan view. The connection region 17 contacts the first region 18A or the body region 12. The connection region 17 may contact each of the body region 12 and the first region 18A. The connection region 17 may directly contact the first region 18A. The body region 12 may directly contact the first region 18A, and the connection region 17 may directly contact the body region 12. The connection region 17 is between the electric field relaxation region 16 and the first region 18A in the Z1-Z2 direction. The connection region 17 is on the second main surface 2 side of the first region 18A. The connection region 17 is on the first main surface 1 side of the electric field relaxation region 16. For example, the connection region 17 may contact each of the first region 18A and the electric field relaxation region 16. When the connection region 17 is between the electric field relaxation region 16 and the first region 18A in the Z1-Z2 direction and contacts each of the first region 18A and the electric field relaxation region 16, the series resistance between the first region 18A and the electric field relaxation region 16 is reduced.

[0042] Assuming that a plurality of gate trenches 5 arranged in the Y1-Y2 direction are regarded as one gate trench aggregate, it can be considered that the gate trench aggregate is divided into a plurality of gate trenches 5 by the first region 18A and the connection region 17.

[0043] The barrier metal film 84 covers the upper surface and the side surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with each of the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is composed of a material containing, for example, titanium nitride (TiN).

[0044] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the first region 18A and the second region 18B of the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The contact electrode 61 is ohmically joined to the source region 13 and the first region 18A and the second region 18B of the contact region 18. The source wiring 62 covers the upper surface and the side surface of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with each of the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0045] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide or silicon nitride.

[0046] The drain electrode 63 is in contact with the second main surface 2. The drain electrode 63 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 63 is electrically connected to the drift region 11. The drain electrode 63 is made of a material containing, for example, nickel silicide. The drain electrode 63 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 63 is ohmically joined to the silicon carbide single crystal substrate 50.

[0047] Here, the gate trench 5, the gate insulating film 81, and the gate electrode 82 will be described in detail. FIGS. 6 and 7 are cross-sectional views showing the gate trench, the gate insulating film, and the gate electrode. In FIGS. 6 and 7, the interlayer insulating film 83 and the source electrode 60 are omitted. FIG. 6 corresponds to a partial enlarged view of FIG. 3, and FIG. 7 corresponds to a partial enlarged view of FIG. 5.

[0048] The bottom surface 4 is a plane substantially parallel to the first main surface 1 of the silicon carbide substrate 10. The side surface 3 of the gate trench 5 has a first side surface 31, a second side surface 32, a third side surface 33, and a fourth side surface 34. The first side surface 31 is on the X1 side of the bottom surface 4 and extends in the Y1 - Y2 direction along the virtual straight line L1. The second side surface 32 is on the X2 side of the bottom surface 4 and extends in the Y1 - Y2 direction along the virtual straight line L1. The first side surface 31 and the second side surface 32 are separated from each other in the X1 - X2 direction. The third side surface 33 is on the Y1 side of the bottom surface 4 and is continuous with the first side surface 31 and the second side surface 32. In plan view, the third side surface 33 is curved so as to be convex on the side away from the bottom surface 4 (Y1 side). The fourth side surface 34 is on the Y2 side of the bottom surface 4 and is continuous with the first side surface 31 and the second side surface 32. In plan view, the fourth side surface 34 is curved so as to be convex on the side away from the bottom surface 4 (Y2 side). The third side surface 33 and the fourth side surface 34 are separated from each other in the Y1 - Y2 direction.

[0049] The first side surface 31 has a first bottom - side region 31A that is continuous with the bottom surface 4 and is inclined at an angle θ11 with respect to a plane parallel to the first main surface 1, and a first top - side region 31B that connects the first bottom - side region 31A and the first main surface 1 and is inclined at an angle θ12 smaller than the angle θ11 with respect to a plane parallel to the first main surface 1. The first boundary 31C between the first bottom - side region 31A and the first top - side region 31B is located in the source region 13. In other words, the first boundary 31C is located between the body region 12 and the first main surface 1. The first bottom - side region 31A is formed by the source region 13, the body region 12, and the drift region 11. The first top - side region 31B is formed by the source region 13.

[0050] The angle θ11 is, for example, 45° or more and 65° or less. The angle θ11 may be, for example, 50° or more. The angle θ11 may be, for example, 60° or less. The first bottom - side region 31A preferably has a {0 - 33 - 8} plane. The {0 - 33 - 8} plane is a crystal plane from which excellent mobility can be obtained.

[0051] The second side surface 32 is continuous with the bottom surface 4 and has a second bottom-side region 32A that is inclined at an angle θ21 with respect to a plane parallel to the first main surface 1, and a second top-side region 32B that connects the second bottom-side region 32A and the first main surface 1 and is inclined at an angle θ22 smaller than the angle θ21 with respect to a plane parallel to the first main surface 1. The second boundary 32C between the second bottom-side region 32A and the second top-side region 32B is located in the source region 13. In other words, the second boundary 32C is located between the body region 12 and the first main surface 1. The second bottom-side region 32A is formed by the source region 13, the body region 12, and the drift region 11. The second top-side region 32B is formed by the source region 13.

[0052] The angle θ21 is, for example, 45° or more and 65° or less. The angle θ21 may be, for example, 50° or more. The angle θ21 may be, for example, 60° or less. The second bottom-side region 32A preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane on which excellent mobility can be obtained.

[0053] The third side surface 33 is continuous with the bottom surface 4 and has a third bottom-side region 33A that is inclined at an angle θ31 with respect to a plane parallel to the first main surface 1, and a third top-side region 33B that connects the third bottom-side region 33A and the first main surface 1 and is inclined at an angle θ32 smaller than the angle θ31 with respect to a plane parallel to the first main surface 1. The third boundary 33C between the third bottom-side region 33A and the third top-side region 33B is located in the source region 13. In other words, the third boundary 33C is located between the body region 12 and the first main surface 1. The third bottom-side region 33A is formed by the source region 13, the body region 12, and the drift region 11. The third top-side region 33B is formed by the source region 13. The third bottom-side region 33A is an example of a first surface, and the angle θ31 is an example of a first angle. The third top-side region 33B is an example of a 3 surface, and the angle θ32 is an example of a 3 angle.

[0054] The fourth side surface 34 is connected to the bottom surface 4 and has a fourth bottom-side region 34A that is inclined at an angle θ41 with respect to a plane parallel to the first main surface 1, and a fourth top-side region 34B that connects the fourth bottom-side region 34A and the first main surface 1 and is inclined at an angle θ42 smaller than the angle θ41 with respect to a plane parallel to the first main surface 1. The fourth boundary 34C between the fourth bottom-side region 34A and the fourth top-side region 34B is located in the source region 13. In other words, the fourth boundary 34C is located between the body region 12 and the first main surface 1. The fourth bottom-side region 34A is formed by the source region 13, the body region 12, and the drift region 11. The fourth top-side region 34B is formed by the source region 13. The angle θ31 is larger than the angle θ41. The fourth bottom-side region 34A is the 2 an example of a surface, and the angle θ41 is the 2 an example of an angle.

[0055] The gate insulating film 81 has a first portion 71, a second portion 72, a third portion 73, and a fourth portion 74. The first portion 71 is in contact with a first region 51 that is continuous with the first side surface 31 of the first main surface 1 and has a first thickness T1. The second portion 72 is in contact with a second region 52 that is continuous with the second side surface 32 of the first main surface 1 and has a second thickness T2. The third portion 73 is in contact with a third region 53 that is continuous with the third side surface 33 of the first main surface 1 and has a third thickness T3. The fourth portion 74 is in contact with a fourth region 54 that is continuous with the fourth side surface 34 of the first main surface 1 and has a fourth thickness T4. For example, the first region 51, the second region 52, the third region 53, and the fourth region 54 are included in the source region 13.

[0056] The third thickness T3 is larger than the first thickness T1 and the second thickness T2. The first thickness T1 and the second thickness T2 may be equal. The fourth thickness T4 may be equal to the first thickness T1 and the second thickness T2.

[0057] The gate electrode 82 is provided on the gate insulating film 81 even between the gate trenches 5 adjacent in the Y1 - Y2 direction. That is, the gate electrode 82 is provided on the third portion 73 and the fourth portion 74 even between the gate trenches 5 adjacent in the Y1 - Y2 direction. Also, in the X1 - X2 direction, the gate electrode 82 is preferably provided inside the gate trench 5, separated from the first portion 71 and the second portion 72 of the gate insulating film 81. That is, it is preferable that the upper surfaces of the first portion 71 and the second portion 72 are in contact with the interlayer insulating film 83 without contacting the gate electrode 82.

[0058] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. FIGS. 8 to 21 are cross-sectional views showing the method for manufacturing the MOSFET 100 according to the embodiment. FIGS. 8 to 16 show the changes in the cross-section shown in FIG. 3. FIGS. 17 to 21 show the changes in the cross-section shown in FIG. 5.

[0059] First, as shown in FIG. 8, a silicon carbide single crystal substrate 50 is prepared. For example, a silicon carbide ingot (not shown) manufactured by the sublimation method is sliced to prepare the silicon carbide single crystal substrate 50. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer can be formed, for example, by a Chemical Vapor Deposition (CVD) method using a mixed gas of silane (SiH4) and propane (C3H8) as a source gas and, for example, hydrogen (H2) as a carrier gas. During the epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

[0060] Next, as also shown in FIG. 8, a first epitaxial layer 21 is formed. For example, a mixed gas of silane and propane is used as a source gas, and the first epitaxial layer 21 is formed on a silicon carbide single crystal substrate 50 by a CVD method using, for example, hydrogen as a carrier gas. During epitaxial growth, an n-type impurity such as nitrogen is introduced into the first epitaxial layer 21. The first epitaxial layer 21 has an n-type conductivity type. The effective concentration of the n-type impurity in the first epitaxial layer 21 may be lower than the effective concentration of the n-type impurity in the buffer layer.

[0061] Next, as shown in FIG. 9, an electric field relaxation region 16 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the electric field relaxation region 16 is to be formed. Next, p-type impurity ions capable of imparting a p-type, such as aluminum ions, are implanted into the first epitaxial layer 21. Thereby, the electric field relaxation region 16 is formed.

[0062] Next, as also shown in FIG. 9, a fourth region 11D is formed. For example, a mask layer (not shown) having an opening is formed on the region where the fourth region 11D is to be formed, that is, on the region on the side of the electric field relaxation region 16 in a direction parallel to the second main surface 2. Next, n-type impurity ions capable of imparting an n-type, such as nitrogen, are implanted into the first epitaxial layer 21. Thereby, the fourth region 11D is formed. Of the first epitaxial layer 21, the portion on the side of the silicon carbide single crystal substrate 50 from the electric field relaxation region 16 and the portion on the side of the silicon carbide single crystal substrate 50 from the fourth region 11D become a fifth region 11E.

[0063] Next, as shown in FIG. 10, a second epitaxial layer 22 is formed. For example, a mixed gas of silane and propane is used as a source gas, and the second epitaxial layer 22 is formed on the first epitaxial layer 21 by a CVD method using, for example, hydrogen as a carrier gas. During epitaxial growth, an n-type impurity such as nitrogen is introduced into the second epitaxial layer 22. The second epitaxial layer 22 has an n-type conductivity type.

[0064] Next, as shown in FIGS. 11 and 17, a connection region 17 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the connection region 17 is to be formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the second epitaxial layer 22. Thereby, the connection region 17 is formed.

[0065] Next, as also shown in FIGS. 11 and 17, a body region 12 is formed. For example, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted over the entire surface of the second epitaxial layer 22. Thereby, the body region 12 is formed.

[0066] Next, as also shown in FIGS. 11 and 17, a source region 13 is formed. For example, n-type impurity ions capable of imparting n-type, such as phosphorus, are implanted over the entire surface of the second epitaxial layer 22. Thereby, the source region 13 is formed.

[0067] Next, as also shown in FIGS. 11 and 17, a contact region 18 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the contact region 18 is to be formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the second epitaxial layer 22. Thereby, the contact region 18 is formed. The contact region 18 includes a first region 18A and a second region 18B.

[0068] Next, activation annealing is performed to activate the impurity ions implanted into the silicon carbide substrate 10. The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere of the activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

[0069] Next, as shown in FIGS. 12 and 18, a gate trench 5 is formed. For example, a mask layer (not shown) having an opening is formed on the first main surface 1 composed of the source region 13 and the contact region 18 at a position where the gate trench 5 is to be formed. Using the mask layer, a part of the source region 13, a part of the body region 12, and a part of the drift region 11 are removed by etching. As the etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixed gas of SF6 and oxygen (O2) as a reaction gas can be used. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion continuously provided with the side portion and substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0070] Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more halogen atoms with a mask layer formed on the first main surface 1. The at least one or more halogen atoms include at least either a chlorine (Cl) atom or a fluorine (F) atom. The atmosphere contains, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and setting the heat treatment temperature to, for example, 800°C or higher and 900°C or lower. Note that the reaction gas may contain a carrier gas in addition to the chlorine gas and oxygen gas described above. As the carrier gas, for example, nitrogen gas, argon gas, or helium gas can be used.

[0071] By the above thermal etching, a gate trench 5 is formed on the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. By changing the reaction gas during the thermal etching, a first side surface 31 including a first bottom side region 31A and a first top side region 31B, a second side surface 32 including a second bottom side region 32A and a second top side region 32B, a third side surface 33 including a third bottom side region 33A and a third top side region 33B, and a fourth side surface 34 including a fourth bottom side region 34A and a fourth top side region 34B are formed. Next, the mask layer is removed from the first main surface 1.

[0072] Next, as shown in FIGS. 13 and 19, a gate insulating film 81 is formed. Details of the method for forming the gate insulating film 81 will be described later. When the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in subsequent processes, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 are slightly shifted at the interface between the thermally oxidized gate insulating film 81 and the silicon carbide substrate 10.

[0073] Next, heat treatment (NO annealing) may be performed on the silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100°C or higher and 1400°C or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface levels in the interface region is suppressed, and the channel mobility can be improved.

[0074] Next, as shown in FIGS. 14 and 20, a gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, and the drift region 11.

[0075] Next, as shown in FIG. 15, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by a CVD method. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0076] Next, as also shown in FIG. 15, a barrier metal film 84, a contact electrode 61, and a drain electrode 63 are formed. For example, etching is performed so that contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81, whereby the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 in the contact holes 90. Next, a barrier metal film 84 that covers the upper surface and the side surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81 is formed. The barrier metal film 84 is composed of a material containing, for example, titanium nitride. The barrier metal film 84 is formed, for example, by film formation by a sputtering method and reactive ion etching (RIE). Next, a metal film (not shown) for the contact electrode 61 is formed in contact with the portions of the source region 13 and the contact region 18 that are exposed from the contact holes 90 on the first main surface 1. The metal film for the contact electrode 61 is formed, for example, by a sputtering method. The metal film for the contact electrode 61 is composed of a material containing, for example, nickel. Next, a metal film (not shown) for the drain electrode 63 is formed in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The metal film for the drain electrode 63 is formed, for example, by a sputtering method. The metal film for the drain electrode 63 is composed of a material containing, for example, nickel.

[0077] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 63 are held at a temperature of, for example, 900°C or higher and 1100°C or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 and at least a part of the metal film for the drain electrode 63 react with silicon included in the silicon carbide substrate 10 to form silicide. Thereby, a contact electrode 61 that forms an ohmic contact with the source region 13 and the contact region 18, and a drain electrode 63 that forms an ohmic contact with the silicon carbide single crystal substrate 50 are formed. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 63 may be made of a material containing titanium, aluminum, and silicon.

[0078] Next, as shown in FIGS. 16 and 21, a source wiring 62 is formed. Specifically, a source wiring 62 that covers the contact electrode 61 and the barrier metal film 84 is formed. The source wiring 62 is formed, for example, by film formation using a sputtering method and RIE. The source wiring 62 is made of a material containing, for example, aluminum. In this way, a source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0079] Next, as also shown in FIGS. 16 and 21, a passivation film 85 is formed. Specifically, a passivation film 85 that covers the source wiring 62 is formed. The passivation film 85 is made of a material containing, for example, polyimide or silicon nitride. The passivation film 85 is formed, for example, by a coating method. The passivation film 85 may be formed by plasma CVD.

[0080] In this way, the MOSFET 100 according to the embodiment is completed.

[0081] Here, the method for forming the gate insulating film 81 will be described in detail. FIGS. 22 to 25 are cross-sectional views showing the method for forming the gate insulating film.

[0082] First, as shown in FIG. 22, a silicon oxide film 91 is formed on the first main surface 1, on the side surface 3, and on the bottom surface 4 by a deposition method such as CVD method.

[0083] Next, as shown in FIG. 23, an etching mask 92 is formed on the first main surface 1. The etching mask 92 covers the region where the third portion 73 of the gate insulating film 81 is to be formed, and the other regions of the silicon oxide film 91 are exposed from the etching mask 92. The etching mask 92 is, for example, a photoresist mask.

[0084] Next, as shown in FIG. 24, the portion of the silicon oxide film 91 exposed from the etching mask 92 is removed by wet etching. Then, the etching mask 92 is removed.

[0085] Next, as shown in FIG. 25, the gate insulating film 81 is formed so as to incorporate the silicon oxide film 91. Specifically, the silicon carbide substrate 10 is heated in an atmosphere containing oxygen at a temperature of, for example, 1300°C or higher and 1400°C or lower. In this way, the gate insulating film 81 is formed. The boundary between the bottom surface 4 and the side surface 3 may be curved. The portion of the gate insulating film 81 other than the silicon oxide film 91 may be formed by a deposition method such as CVD method.

[0086] In this way, the shape of the gate insulating film 81 is formed.

[0087] Next, the operation and effect of the MOSFET according to this embodiment will be described.

[0088] In this embodiment, the third thickness T3 of the third portion 73 of the gate insulating film 81 is greater than the first thickness T1 of the first portion 71 and the second thickness T2 of the second portion 72. Therefore, breakdown of the gate insulating film 81 in the third portion 73 can be suppressed, and excellent reliability can be ensured. Although it is also possible to suppress breakdown of the gate insulating film 81 by increasing the overall thickness of the gate insulating film 81, in that case, the gate insulating film 81 on the body region 12 may become excessively thick due to alignment deviation or the like during the formation of the gate insulating film 81. In contrast, in this embodiment, even if alignment deviation or the like occurs, it is possible to suppress the gate insulating film 81 on the body region 12 from becoming excessively thick in the vicinity of the first portion 71 and the second portion 72. Therefore, variations in characteristics such as channel resistance and threshold voltage due to variations in the thickness of the gate insulating film 81 can be suppressed.

[0089] Further, the third side surface 33 has a third bottom side region 33A and a third top side region 33B, and the angle θ32 is smaller than the angle θ31. Therefore, it is easy to relieve the electric field concentration in the third portion 73. The angle θ32 is preferably smaller than the angles θ11 and θ21.

[0090] Also, a first region 18A of the contact region 18 is provided overlapping a virtual straight line L1 between adjacent gate trenches 5 in the Y1 - Y2 direction. Therefore, it is easy to electrically connect the contact region 18 and the electric field relaxation region 16, and it is easy to obtain a shielding effect.

[0091] Also, the gate electrode 82 is provided, in a plan view, between the first portion 71 and the second portion 72 of the gate insulating film 81 and separated from the first portion 71 and the second portion 72. Therefore, breakdown of the gate insulating film 81 can be suppressed by avoiding electric field concentration in the first portion 71 and the second portion 72.

[0092] Further, the fourth thickness T4 of the fourth portion 74 of the gate insulating film 81 may be greater than the first thickness T1 of the first portion 71 and the second thickness T2 of the second portion 72. In this case, the breakdown of the gate insulating film 81 in the fourth portion 74 can be suppressed, and excellent reliability can be ensured. The angle θ31 of the third bottom-side region 33A of the third side surface 33 and the angle θ41 of the fourth bottom-side region 34A of the fourth side surface 34 may be different. For example, the angle θ31 of the third bottom-side region 33A of the third side surface 33 may be greater than the angle θ41 of the fourth bottom-side region 34A of the fourth side surface 34. In this case, it is preferable that the third thickness T3 of the third portion 73 is greater than the fourth thickness T4 of the fourth portion 74. From the viewpoint of the shape of the gate trench 5, the electric field is likely to concentrate in the third portion 73 rather than the fourth portion 74. However, since the third thickness T3 is greater than the fourth thickness T4, the breakdown of the gate insulating film 81 can be suppressed.

[0093] The first main surface 1 is a surface obtained by inclining the {000-1} plane of the silicon carbide substrate 10 by an angle θ in the direction (Y1-Y2 direction) in which the virtual straight line L1 extends, and the difference between the angle θ31 and the angle θ41 may be 2θ. By using the silicon carbide substrate 10 having an off-angle of the angle θ, the first epitaxial layer 21 and the second epitaxial layer 22 can be easily grown well. Further, by forming the gate trench 5 by thermal etching such a silicon carbide substrate 10, it is easy to obtain a good side surface 3 with less damage. In this case, the difference between the angle θ31 and the angle θ41 is 2θ.

[0094] [Modification Example] Next, a modification example of the embodiment will be described. The modification example is mainly different from the embodiment in terms of the shape of the gate trench. FIG. 26 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to a modification example of the embodiment. FIG. 26 shows a cross-section similar to the cross-section along the line III-III in FIGS. 1 and 2.

[0095] As shown in FIG. 26, in the MOSFET 110 according to the modified example, the gate trench 5 is a vertical trench. That is, the angle θ11 of the first bottom side region 31A of the first side surface 31 and the angle θ21 of the second bottom side region 32A of the second side surface 32 with respect to the plane including the bottom surface 4 may be 90°. Other configurations are the same as those in the embodiment.

[0096] Even with such a modified example, the same effects as those in the embodiment can be obtained.

[0097] Although the embodiments have been described in detail above, the present invention is not limited to specific embodiments, and various modifications and changes are possible within the scope described in the claims.

Description of Reference Numerals

[0098] 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 11C Third region 11D Fourth region 11E Fifth region 12 Body region 13 Source region 16 Electric field relaxation region 17 Connection region 18 Contact region 18A First region 18B Second region 21 First epitaxial layer 22 Second epitaxial layer 31 First side surface 31A First bottom side region 31B First top side region 31C First boundary 32 Second side surface 32A Second bottom side region 32B Second top side region 32C Second boundary 33 Third side surface 33A Third bottom region 33B Third top region 33C Third boundary 34 Fourth side surface 34A Fourth bottom region 34B Fourth top region 34C Fourth boundary 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 51 First region 52 Second region 53 Third region 54 Fourth region 60 Source electrode 61 Contact electrode 62 Source wiring 63 Drain electrode 71 First part 72 Second part 73 Third part 74 Fourth part 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Passivation film 90 Contact hole 91 Silicon oxide film 92 Etching mask 100, 110 MOSFET L1 Virtual straight line

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is provided, The silicon carbide substrate, A drift region having a first conductivity type, A body region provided on the drift region and having a second conductivity type different from the first conductivity type, A source region provided on the body region so as to be separated from the drift region and having the first conductivity type, A contact region provided on the body region and having the second conductivity type, And having, On the first main surface, a gate trench is provided which is defined by a side surface that penetrates the source region and the body region and reaches the drift region and a bottom surface continuous with the side surface, and extends along a virtual straight line parallel to the first main surface, Further having a gate insulating film in contact with the side surface, the bottom surface and the first main surface, The side surface, A first side surface extending along the virtual straight line, A second side surface extending along the virtual straight line and separated from the first side surface in a direction parallel to the first main surface, A third side surface continuous with the first side surface and the second side surface, A fourth side surface continuous with the first side surface and the second side surface on the opposite side of the third side surface, And having, The gate insulating film, A first portion having a first thickness and in contact with a first region continuous with the first side surface of the first main surface, A second portion having a second thickness and in contact with a second region continuous with the second side surface of the first main surface, A third portion having a third thickness and in contact with a third region continuous with the third side surface of the first main surface, A fourth portion having a fourth thickness and in contact with a fourth region continuous with the fourth side surface of the first main surface, And having, The third thickness is larger than the first thickness and the second thickness, The fourth thickness is greater than the first thickness and the second thickness. The third side surface has a first surface that is continuous with the bottom surface and is inclined at a first angle with respect to a plane parallel to the first main surface. The fourth side surface has a second surface that is continuous with the bottom surface and is inclined at a second angle with respect to a plane parallel to the first main surface. The first angle is greater than the second angle. A silicon carbide semiconductor device in which the third thickness is greater than the fourth thickness.

2. The silicon carbide semiconductor device according to claim 1, wherein the third side surface has a third surface that connects the first surface and the first main surface and is inclined at a third angle smaller than the first angle with respect to a plane parallel to the first main surface.

3. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the fourth side surface has a fourth surface that connects the second surface and the first main surface and is inclined at a fourth angle smaller than the second angle with respect to a plane parallel to the first main surface.

4. The first main surface is a surface in which the {000 - 1} plane of the silicon carbide substrate is inclined by an angle θ in the direction in which the virtual straight line extends. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the difference between the first angle and the second angle is 2θ.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein a plurality of the gate trenches are provided overlapping the virtual straight line at regular intervals.

6. It has a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between the silicon carbide substrate. In a plan view from a direction perpendicular to the first main surface, the gate electrode is provided between the first portion and the second portion and away from the first portion and the second portion. The silicon carbide semiconductor device according to any one of claims 1 to 5.

7. The first side surface and the second side surface of the gate trench are the silicon carbide semiconductor device according to any one of claims 1 to 6 including a {0-33-8} plane.

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