Semiconductor device

Abstract

To prevent an overheat state of a power semiconductor element and an error in an overcurrent detection notification to a host control device.SOLUTION: A logical circuit 10 includes an oscillation signal generation circuit 30 that generates an oscillation signal when an input signal for indicating an ON operation of a power semiconductor element and an overcurrent detection signal from an overcurrent detection circuit 160 are simultaneously inputted, a pulse generation circuit 40 that generates a pulse when an input signal is inputted, a gated latch circuit 50 that holds an overcurrent detection state when the pulse is inputted, an overcurrent mode switch circuit 60 that outputs a counter input signal obtained by inversion or noninversion switching of the oscillation signal generated by the oscillation signal generation circuit 30 according to the overcurrent detection state held by the gated latch circuit 50, and an inversion signal obtained by inverting the oscillation signal, and a timing determination circuit 70 that divides the frequency of the counter input signal to generate a plurality of frequency divided signals, and outputs an output signal for periodically turning on the power semiconductor element from the inversion signal and the frequency divided signals.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a power semiconductor device which is a voltage-driven power control element and a circuit for driving and protecting the power semiconductor device.

Background Art

[0002] Automobiles are often equipped with semiconductor devices for switching control of loads such as motors. As such in-vehicle semiconductor devices, an IPS (Intelligent Power Switch) in which a power semiconductor element for supplying power to a load and its control circuit are integrated on the same chip is used. As this IPS, particularly in the application of automotive electrical components, a high-side type IPS arranged and used between a power supply and a load is common from the viewpoint of safety during maintenance of the load.

[0003] In semiconductor products used in the automotive field, a design that does not break under any circumstances is required. In a high-side type IPS, when the load is in an overcurrent state, an excessive current greater than that during normal operation flows through the load, which may cause failures in the power semiconductor element and peripheral circuits.

[0004] When an overcurrent state is detected, techniques have been proposed to control so as to limit the current or adjust the overcurrent detection threshold to be limited (see, for example, Patent Document 1). In particular, the overcurrent protection circuit of Patent Document 1 is described as a technique that achieves both ensuring the instantaneous current during normal operation and overcurrent protection according to the load.

[0005] Next, although different from the overcurrent protection circuit of Patent Document 1, the specific operation when a general high-side type IPS and the high-side type IPS detect an overcurrent state will be described. This general high-side type IPS is based on the configuration described in Non-Patent Document 1.

[0006] FIG. 9 is a diagram showing a configuration example of a conventional IPS, FIG. 10 is a block diagram showing an example of the function of a logic circuit at the time of overcurrent detection, and FIG. 11 is a diagram showing an example of a timing determination circuit. FIG. 12 is a time chart of a first operation example of the timing determination circuit, where (A) shows the case where an overcurrent is detected during the on operation, and (B) shows the case where the overcurrent detection state exists before the on operation. FIG. 13 is a waveform diagram of a first operation example when an overcurrent is detected, where (A) shows the case where an overcurrent is detected during the on operation, and (B) shows the case where the overcurrent detection state exists before the on operation. FIG. 14 is a time chart of a second operation example of the timing determination circuit, where (A) shows the case where an overcurrent is detected during the on operation, and (B) shows the case where the overcurrent detection state exists before the on operation. FIG. 15 is a waveform diagram of a second operation example when an overcurrent is detected, where (A) shows the case where an overcurrent is detected during the on operation, and (B) shows the case where the overcurrent detection state exists before the on operation. In the description of FIG. 9, the terminal names and the voltages, signals, etc. at those terminals may use the same reference signs.

[0007] As shown in FIG. 9, the conventional IPS 100 includes a main MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 110, a logic circuit 120, and a driver circuit 130. Note that the main MOSFET 110 may be a circuit combining an IGBT (Insulated Gate Bipolar Transistor), which is a voltage-driven power control element, and an FWD (Free Wheeling Diode). The IPS 100 also includes a low voltage detection circuit 140, a short circuit detection circuit 150, an overcurrent detection circuit 160, an overheat detection circuit 170, an N-channel MOSFET 180, a constant current circuit 182, an operational amplifier 190, and gain setting resistors 191, 192, 193, 194.

[0008] The IPS100 has an IN terminal, a VCC terminal, an OUT terminal, an IN+ terminal, an IN- terminal, an AMP terminal, and a GND terminal. The IN terminal and the AMP terminal of the IPS100 are connected to a microcomputer 200 which is a host control device. The microcomputer 200 generates a signal for turning the main MOSFET 110 on and off based on the load current obtained from the AMP terminal of the IPS100 and supplies it to the IN terminal of the IPS100. In the illustrated example, the signal for turning the main MOSFET 110 on has a potential of 5 volts (V), and the signal for turning the main MOSFET 110 off has a potential of 0 V.

[0009] The IN terminal of the IPS100 is connected to the input terminal of a logic circuit 120. The output terminal of the logic circuit 120 is connected to the input terminal of a driver circuit 130 having a level shift function. The output terminal of the driver circuit 130 is connected to the gate terminal of the main MOSFET 110. The drain terminal of the main MOSFET 110 is connected to the VCC terminal, and the VCC terminal is connected to the positive terminal of a power supply 210. The negative terminal of the power supply 210 is connected to a reference potential (GND). The source terminal of the main MOSFET 110 is connected to the OUT terminal, and the OUT terminal is connected to one terminal of a load 220. The other terminal of the load 220 is connected to one terminal of a shunt resistor 230, and the other terminal of the shunt resistor 230 is connected to the reference potential. One terminal of the shunt resistor 230 is also connected to the IN+ terminal of the IPS100, and the other terminal is connected to the IN- terminal. The GND terminal of the IPS100 is connected to the reference potential.

[0010] The VCC terminal of the IPS100 is connected to the input terminal of the low-voltage detection circuit 140, and the output terminal of the low-voltage detection circuit 140 is connected to the logic circuit 120. The VCC terminal of the IPS100 is connected to one input terminal of the short-circuit detection circuit 150, the other input terminal of the short-circuit detection circuit 150 is connected to the OUT terminal, and the output terminal of the short-circuit detection circuit 150 is connected to the logic circuit 120. The VCC terminal of the IPS100 is connected to the drain terminal of the MOSFET 180, and the gate terminal of the MOSFET 180 is connected to the output terminal of the driver circuit 130. The source terminal of the MOSFET 180 is connected to one terminal of the constant-current circuit 182 and one input terminal of the overcurrent detection circuit 160, the other input terminal of the overcurrent detection circuit 160 is connected to the OUT terminal, and the output terminal of the overcurrent detection circuit 160 is connected to the logic circuit 120. The output terminal of the overheat detection circuit 170 is connected to the logic circuit 120. The IN+ terminal of the IPS100 is connected to one terminal of the gain-setting resistor 191, and the other terminal of the gain-setting resistor 191 is connected to one terminal of the gain-setting resistor 192 and the non-inverting input terminal of the operational amplifier 190. The other terminal of the gain-setting resistor 192 is connected to the GND terminal. The IN- terminal of the IPS100 is connected to one terminal of the gain-setting resistor 193, and the other terminal of the gain-setting resistor 193 is connected to one terminal of the gain-setting resistor 194 and the inverting input terminal of the operational amplifier 190. The output terminal of the operational amplifier 190 is connected to the other terminal of the gain-setting resistor 194 and the AMP terminal of the IPS100.

[0011] The low-voltage detection circuit 140 monitors whether the voltage VCC of the VCC terminal is equal to or higher than a predetermined voltage that enables the IPS100 to operate. When the voltage VCC drops below the predetermined voltage, the low-voltage detection circuit 140 notifies the logic circuit 120 of the abnormal drop in the voltage VCC. When notified of the abnormal drop in the voltage VCC, the logic circuit 120 outputs a signal to the driver circuit 130 to stop the operation of the main MOSFET 110 and the MOSFET 180 so that the IPS100 does not operate abnormally.

[0012] The short-circuit detection circuit 150 detects a short circuit of the load 220 from the difference between the voltage VCC of the VCC terminal and the voltage of the OUT terminal when the main MOSFET 110 is on. When the short-circuit detection circuit 150 detects a short-circuit state of the load 220, it notifies the logic circuit 120, and the logic circuit 120 that has received the notification outputs a signal for lowering the gate voltages of the main MOSFET 110 and the MOSFET 180 to the driver circuit 130.

[0013] The overcurrent detection circuit 160 allows a constant current to flow through the constant current circuit 182 when the MOSFET 180 is on, and detects an overcurrent from the potential difference due to the on-resistances of the main MOSFET 110 and the MOSFET 180 when the main MOSFET 110 and the MOSFET 180 are on. When the overcurrent detection circuit 160 detects an overcurrent state of the load 220, it notifies the logic circuit 120. When the logic circuit 120 is notified of the overcurrent state of the load 220, it stops the operations of the main MOSFET 110 and the MOSFET 180 and controls to periodically turn on the main MOSFET 110 and the MOSFET 180 only for a short time. This control to periodically turn on the main MOSFET 110 and the MOSFET 180 only for a short time is for detecting whether the load 220 has returned to the normal state after the overcurrent detection. During this operation, the logic circuit 120 outputs a signal for stopping the operations of the main MOSFET 110 and the MOSFET 180. Note that the threshold value of the load current at which the overcurrent detection circuit 160 determines an overcurrent is set lower than the threshold value of the load current at which the short-circuit detection circuit 150 determines a short circuit.

[0014] The overheat detection circuit 170 detects the temperature of the main MOSFET 110 or the IPS 100, and when the temperature of the main MOSFET 110 or the IPS 100 becomes equal to or higher than a predetermined temperature, it notifies the logic circuit 120 of the overheat state of the main MOSFET 110 or the IPS 100. When the logic circuit 120 is notified of the overheat state, in order to prevent a failure of the IPS 100, it outputs a signal for stopping the operations of the main MOSFET 110 and the MOSFET 180 to the driver circuit 130.

[0015] The operational amplifier 190 and the gain setting resistors 191, 192, 193, 194 constitute a current detection circuit that detects the value of the current flowing through the load 220 and notifies the microcomputer 200. The current flowing through the load 220 is converted into a voltage by the shunt resistor 230, and the operational amplifier 190 amplifies the voltage and supplies it to the AMP terminal. At this time, the gain of the operational amplifier 190 is set by the gain setting resistors 191, 192, 193, 194.

[0016] As shown in the function at the time of overcurrent detection in FIG. 10, the logic circuit 120 includes an input circuit 121, an oscillation signal generation circuit 122, and a timing determination circuit 123. The input circuit 121 is a circuit that inputs an input signal IN for turning on and off the main MOSFET 110 received at the IN terminal. The output terminal of the input circuit 121 is connected to the first input terminal of the oscillation signal generation circuit 122, and the second input terminal of the oscillation signal generation circuit 122 is connected to the output terminal of the overcurrent detection circuit 160. The output terminal of the oscillation signal generation circuit 122 is connected to the input terminal of the timing determination circuit 123.

[0017] The input circuit 121 shapes the waveform of the input input signal IN and supplies it to the oscillation signal generation circuit 122. When the oscillation signal generation circuit 122 receives an overcurrent detection signal from the overcurrent detection circuit 160 while receiving the input signal IN for turning on the main MOSFET 110 from the input circuit 121, or when the oscillation signal generation circuit 122 receives the input signal IN for turning on the main MOSFET 110 from the input circuit 121 while receiving the overcurrent detection signal from the overcurrent detection circuit 160, the oscillation signal generation circuit 122 creates an oscillation signal signal1 and supplies this created signal signal1 to the timing determination circuit 123. The timing determination circuit 123 outputs a signal output that determines the timing for periodically turning on the main MOSFET 110 for a short time from the signal signal1.

[0018] As shown in FIG. 11, the timing determination circuit 123 includes T flip-flops TFF1, TFF2, TFF3, NOR circuits NOR1, NOR2, and a NAND circuit NAND1. The input terminal of the timing determination circuit 123 that receives signal signal1 is connected to the input terminal of T flip-flop TFF1 and one input terminal of NOR circuit NOR1. The output terminal of T flip-flop TFF1 is connected to the input terminal of T flip-flop TFF2 and the other input terminal of NOR circuit NOR1. The output terminal of T flip-flop TFF2 is connected to the input terminal of T flip-flop TFF3 and one input terminal of NOR circuit NOR2. The output terminal of T flip-flop TFF3 is connected to the other input terminal of NOR circuit NOR2. The output terminal of NOR circuit NOR1 is connected to one input terminal of NAND circuit NAND1, the output terminal of NOR circuit NOR2 is connected to the other input terminal of NAND circuit NAND1, and the output terminal of NAND circuit NAND1 constitutes the output terminal of the timing determination circuit 123.

[0019] When the timing determination circuit 123 receives signal signal1 from the oscillation signal generation circuit 122, signal signal1 is sequentially divided by a down-counter circuit composed of three-stage T flip-flops TFF1, TFF2, and TFF3. That is, T flip-flop TFF1 outputs signal signal2 with a period twice that of signal signal1, T flip-flop TFF2 outputs signal signal3 with a period twice that of signal signal2, and T flip-flop TFF3 outputs signal signal4 with a period twice that of signal signal3. NOR circuit NOR1 receives signals signal1 and signal2 and outputs a high (H) level signal when both are at the low (L) level. NOR circuit NOR2 receives signals signal3 and signal4 and outputs a high (H) level signal when both are at the L level. NAND circuit NAND1 outputs a low (L) level signal output only when it receives high (H) level signals from NOR circuits NOR1 and NOR2. Thus, the timing determination circuit 123 has the function of outputting a low (L) level signal output at the timing when all of signals signal1, signal2, signal3, and signal4 are at the L level. This low (L) level signal output is logically inverted when input to the driver circuit 130 during the period when an overcurrent is detected, and becomes a signal that periodically turns on the main MOSFET 110 for a short time.

[0020] The above timing determination circuit 123 operates based on signal signal1 supplied from the oscillation signal generation circuit 122, but the timing of signal signal1 may be different depending on whether it is created by an overcurrent detection signal from the overcurrent detection circuit 160 or an input signal IN. That is, the oscillation signal generation circuit 122 may set signal signal1 to a signal that rises in synchronization with the overcurrent detection signal or input signal IN (first operation example) or a signal that rises with a half-cycle delay from the input of the overcurrent detection or input signal IN (second operation example). First, the operation of the timing determination circuit 123 and the IPS 100 in the first operation example will be described.

[0021] Figures 12(A) and 13(A) show the case where the overcurrent detection timing by the overcurrent detection circuit 160 is during the input of the input signal IN. In Fig. 12(A), from top to bottom, the input signal IN, the overcurrent detection state of the overcurrent detection circuit 160, signals signal1, signal2, signal3, signal4, and the signal output by the timing determination circuit 123 are shown respectively. Fig. 13(A) shows, from top to bottom, the input signal IN, the output signal OUT of the OUT terminal, the load current IL, and the signal AMP of the AMP terminal respectively.

[0022] First, as shown in Fig. 12(A), when the input signal IN of H level is input and the main MOSFET 110 is in the on state, the overcurrent detection circuit 160 has not yet detected an overcurrent state, so it outputs a signal of L level. At this time, the oscillation signal generation circuit 122 outputs a signal signal1 of L level, and the T flip-flops TFF1, TFF2, TFF3 of the timing determination circuit 123 are in the reset state, so they output signals signal2, signal3, signal4 of L level. Therefore, the timing determination circuit 123 outputs a signal output of L level, and the driver circuit 130 maintains the output of the signal for turning on the main MOSFET 110.

[0023] When the main MOSFET 110 is in the on state, as shown in Fig. 13(A), an output signal OUT is output to the OUT terminal. As a result, a load current IL starts to flow through the load 220, and the signal AMP of the AMP terminal has a signal waveform corresponding to the load current IL.

[0024] Next, during the on operation of the main MOSFET 110, when the overcurrent detection circuit 160 detects an overcurrent state and outputs an overcurrent detection signal of H level, the oscillation signal generation circuit 122 outputs a signal signal1 that rises in synchronization with the rising edge of the signal of H level. In the timing determination circuit 123, with the input of the signal signal1 of H level, the remaining signals signal2, signal3, signal4 also become H level. As a result, the timing determination circuit 123 outputs a signal output of H level.

[0025] When the overcurrent detection circuit 160 detects an overcurrent, as shown in Fig. 13(A), the main MOSFET 110 turns off, so the output signal OUT at the OUT terminal drops to almost 0V. As a result, the load current IL flowing through the load 220 decreases, and the signal AMP at the AMP terminal also decreases accordingly. At this time, since the load current IL does not drop immediately, the signal AMP at the AMP terminal also drops to almost 0V with a delay from the overcurrent detection. Thus, the microcomputer 200 will know that the overcurrent detection circuit 160 has detected an overcurrent with a delay from the actual overcurrent detection.

[0026] When the overcurrent detection circuit 160 detects an overcurrent, the oscillation signal generation circuit 122 and the timing determination circuit 123 operate to periodically output the signal output. That is, as shown in Fig. 12(A), the signal signal1 is sequentially divided, and during the output valid interval of output where all the signals signal1, signal2, signal3, signal4 are at the L level, the signal output is at the L level. Each time this L-level signal output is output, the main MOSFET 110 turns on, so an output signal OUT is output at the OUT terminal, and during that time, the load current IL flows. Thus, the IPS100 periodically checks whether the state of the load 220 has returned to the normal state after the overcurrent detection.

[0027] The example shown in Fig. 13(A) shows the case where the overcurrent state of the load 220 has been released when the third signal output is output from the overcurrent detection. In this case, normal power supply to the load 220 is resumed. At this time, a signal AMP with a magnitude corresponding to the load current IL is output at the AMP terminal after a delay in the overcurrent recovery.

[0028] Finally, when the input signal IN becomes the L level, the main MOSFET 110 turns off, so the output signal OUT at the OUT terminal drops to almost 0V. As a result, the load current IL of the load 220 starts to decrease, and the signal AMP at the AMP terminal also starts to decrease.

[0029] Next, with reference to FIGS. 12(B) and 13(B), a case where the detection timing of the overcurrent by the overcurrent detection circuit 160 is before the input of the input signal IN will be described. In FIG. 12(B), from top to bottom, the input signal IN, the overcurrent detection state of the overcurrent detection circuit 160, the signals signal1, signal2, signal3, signal4, and the signal output output by the timing determination circuit 123 are shown respectively. FIG. 13(B) shows, from top to bottom, the input signal IN, the output signal OUT of the OUT terminal, the load current IL, and the signal AMP of the AMP terminal respectively.

[0030] When a high-level input signal IN is input in a state where an overcurrent detection signal is being output, the oscillation signal generation circuit 122 outputs a signal signal1 that rises at the timing when the input signal IN is input. After the high-level signal signal1 is output, the timing determination circuit 123 operates in the same manner as in the case of FIG. 12(A).

[0031] When a high-level input signal IN is input in a state where an overcurrent is detected, as shown in FIG. 13(B), first, the main MOSFET 110 turns on, and the output signal OUT is output to the OUT terminal. At this time, the load current IL starts to flow through the load 220, and the signal AMP at the AMP terminal also outputs a signal AMP having a magnitude corresponding to the load current IL.

[0032] At the timing when the high-level input signal IN is input, since it is already in the overcurrent detection state, immediately after that timing, the main MOSFET 110 turns off, and the output signal OUT at the OUT terminal drops to almost 0V. Immediately after this, the load current IL drops, and the signal AMP at the AMP terminal also drops immediately. When the signal AMP drops to almost 0V, the microcomputer 200 will know that the overcurrent detection circuit 160 has detected an overcurrent with a delay from the timing when the high-level input signal IN was input.

[0033] During the period when the subsequent input signal IN at the H level is being input, the signal output by the periodic signal output for checking whether the overcurrent state of the load 220 has returned to normal and the operation after the overcurrent of the load 220 is released are the same as those shown in FIG. 13(A).

[0034] Next, the operation of the timing determination circuit 123 and the IPS 100 in the second operation example in which the oscillation signal generation circuit 122 sets the signal signal1 to a signal that rises with a half-cycle delay from the detection of the overcurrent or the input of the input signal IN will be described.

[0035] FIGS. 14(A) and 15(A) show the case where the overcurrent detection timing by the overcurrent detection circuit 160 is during the input of the input signal IN. In FIG. 14(A), from the top, the input signal IN, the overcurrent detection state of the overcurrent detection circuit 160, the signals signal1, signal2, signal3, signal4, and the signal output output by the timing determination circuit 123 are shown respectively. FIG. 15(A) shows, from the top, the input signal IN, the output signal OUT of the OUT terminal, the load current IL, and the signal AMP of the AMP terminal respectively.

[0036] First, as shown in FIG. 14(A), when the input signal IN at the H level is input and the main MOSFET 110 turns on, the overcurrent detection circuit 160 outputs an L-level signal because it has not yet detected an overcurrent state. At this time, the oscillation signal generation circuit 122 outputs an L-level signal signal1, the timing determination circuit 123 outputs an L-level signal output, and the driver circuit 130 outputs a signal to turn on the main MOSFET 110.

[0037] At this time, as shown in FIG. 15(A), when the main MOSFET 110 turns on, an output signal OUT is output to the OUT terminal. As a result, a load current IL starts to flow through the load 220, and the signal AMP of the AMP terminal has a signal waveform corresponding to the load current IL.

[0038] Next, when the overcurrent detection circuit 160 detects an overcurrent state and outputs an H-level overcurrent detection signal, the oscillation signal generation circuit 122 outputs a signal signal1 that rises with a half-cycle delay from the rising edge of the H-level signal of the overcurrent detection signal. After the H-level signal signal1 is output, it operates in the same manner as in the first operation example shown in FIGS. 12(A) and 13(A).

[0039] Next, with reference to FIGS. 14(B) and 15(B), the case where the overcurrent detection timing by the overcurrent detection circuit 160 is before the input of the input signal IN will be described. In FIG. 14(B), from the top, the input signal IN, the overcurrent detection state of the overcurrent detection circuit 160, the signals signal1, signal2, signal3, signal4, and the signal output by the timing determination circuit 123 are shown respectively. FIG. 15(B) shows, from the top, the input signal IN, the output signal OUT of the OUT terminal, the load current IL, and the signal AMP of the AMP terminal respectively.

[0040] When an H-level input signal IN is input while the overcurrent detection signal is being output, the oscillation signal generation circuit 122 creates a signal signal1 that starts at the L level from the timing when the input signal IN is input. Therefore, since signal1 rises to the H level after a half cycle, until then, the signal output by the timing determination circuit 123 becomes valid, and the main MOSFET 110 will perform an on operation. After signal1 first becomes H level, it operates in the same manner as in the cases of FIGS. 14(A) and 15(A).

[0041] Note that in FIGS. 12 and 14, when the input signal IN is at the L level, the signal output is at the H level. This is because a circuit (not shown) is configured such that when the input signal IN is at the L level, the signal output becomes H level.

Prior Art Documents

Patent Documents

[0042]

Patent Document 1

Non-Patent Document

[0043]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0044] However, in the first operation example, particularly when an overcurrent is detected before the input signal IN is input, as shown in Fig. 13(B), the main MOSFET 110 turns on and off immediately after the input signal IN at the H level is input. For this reason, since the width of the signal AMP at the AMP terminal is short, the microcomputer 200 receiving the signal AMP may not be able to detect the load current IL due to instructing the on operation of the main MOSFET 110 and may not be able to know that an overcurrent is detected. On the other hand, in the second operation example, when an overcurrent is detected after the input signal IN is input, as shown in Fig. 15(A), there is a period during which an overcurrent flows in addition to the normal load current flowing. For this reason, the main MOSFET 110 is likely to be in an overheated state and may lead to a failure.

[0045] The present invention has been made in view of such points, and an object thereof is to provide a semiconductor device in which the main power semiconductor element is less likely to be in an overheated state and there is no error in the overcurrent detection notification to the upper control device.

Means for Solving the Problems

[0046] To solve the above problems, there is provided a semiconductor device including a power semiconductor element, an overcurrent detection circuit, and a logic circuit having a function of periodically turning on the power semiconductor element for a short time when the overcurrent detection circuit detects an overcurrent. The logic circuit includes an oscillation signal creation circuit that creates an oscillation signal when an input signal instructing the on operation of the power semiconductor element and an overcurrent detection signal from the overcurrent detection circuit are input simultaneously, a pulse generation circuit that generates a pulse when the input signal is input, a gated latch circuit that holds the overcurrent detection state of the overcurrent detection circuit when the pulse is input, and an overcurrent mode switching circuit that outputs a counter input signal obtained by switching the oscillation signal created by the oscillation signal creation circuit in an inverted or non-inverted manner according to the overcurrent detection state held by the gated latch circuit and an inverted signal obtained by inverting the oscillation signal, and a timing determination circuit that divides the counter input signal into a plurality of divided signals and outputs an output signal that periodically turns on the power semiconductor element from the inverted signal and the divided signals.

Advantages of the Invention

[0047] When an overcurrent is detected while the power semiconductor element is in the on operation, the semiconductor device having the above configuration immediately turns off the power semiconductor element, so that it is possible to prevent the power semiconductor element from reaching a heat generation state. Further, when an overcurrent is detected at least during the period in which the pulse generation circuit outputs a pulse, by outputting an on signal to the power semiconductor element for a predetermined period, it is possible to sufficiently secure the period of notifying the overcurrent detection to the upper control device and prevent notification errors.

[0048] The above and other objects, features, and advantages of the present invention will become apparent from the following description in connection with the accompanying drawings showing preferred embodiments of the present invention by way of example.

Brief Description of the Drawings

[0049]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings by taking the case of applying it to a high-side type IPS as an example. Note that since the basic configuration of the high-side type IPS is the same as the basic configuration described above with reference to FIG. 9, for the description of other components except the logic circuit which is a characteristic part of the present invention, reference may be made to FIG. 9.

[0051] FIG. 1 is a block diagram showing a configuration example of the logic circuit of the high-side type IPS according to the present invention, FIG. 2 is a circuit diagram showing an example of an input circuit and a pulse generation circuit, FIG. 3 is a circuit diagram showing an example of a gated latch circuit, FIG. 4 is a circuit diagram showing an example of an overcurrent mode switching circuit, and FIG. 5 is a circuit diagram showing an example of a timing determination circuit. In the description of the figures, the same reference signs may be used for terminal names and voltages, signals, etc. at those terminals.

[0052] As shown in FIG. 1, the logic circuit 10 of the high-side type IPS according to the present invention includes an input circuit 20, an oscillation signal creation circuit 30, a pulse generation circuit 40, a gated latch circuit 50, an overcurrent mode switching circuit 60, and a timing determination circuit 70.

[0053] The input circuit 20 has its input terminal connected to the IN terminal of the high-side type IPS, and the output terminal of the input circuit 20 is connected to the first input terminal of the oscillation signal creation circuit 30 and the input terminal of the pulse generation circuit 40, respectively. The second input terminal of the oscillation signal creation circuit 30 is connected to the output terminal of the overcurrent detection circuit 160. The output terminal of the pulse generation circuit 40 is connected to the enable terminal of the gated latch circuit 50. The other input terminal of the gated latch circuit 50 is connected to the output terminal of the overcurrent detection circuit 160, and the output terminal of the gated latch circuit 50 is connected to the input terminal for the switching signal input of the overcurrent mode switching circuit 60. The overcurrent mode switching circuit 60 also has its input terminal for the oscillation signal input connected to the output terminal of the oscillation signal creation circuit 30. The output terminal of the overcurrent mode switching circuit 60 is connected to the input terminal of the timing determination circuit 70. The timing determination circuit 70 is configured to also receive the first overcurrent detection signal OCDS1 output by the overcurrent detection circuit 160.

[0054] As shown in FIG. 2, the input circuit 20 includes a non-inverting Schmitt trigger circuit 21. The input terminal of the Schmitt trigger circuit 21 is connected to the IN terminal of the high-side type IPS, and the output terminal of the Schmitt trigger circuit 21 is connected to the input terminal of the pulse generation circuit 40. The input circuit 20 can shape the waveform of the input signal IN including noise supplied from the microcomputer 200.

[0055] The pulse generation circuit 40 includes inverter circuits INV11, INV12, INV13, a NAND circuit NAND11, a P-channel MOSFET 41, N-channel MOSFETs 42 and 43, and a capacitor 44. Note that the MOSFET 42 is a depletion-type MOSFET.

[0056] The input terminal of the pulse generation circuit 40 is connected to the input terminal of the inverter circuit INV11 and one input terminal of the NAND circuit NAND11. The output terminal of the inverter circuit INV11 is connected to the gate terminals of the MOSFETs 41 and 43. The source terminal of the MOSFET 41 is connected to the power supply line, and the source terminal of the MOSFET 43 is connected to the ground line. The drain terminal of the MOSFET 41 is connected to the drain terminal of the MOSFET 42. The gate terminal and the source terminal of the MOSFET 42 are connected to the drain terminal of the MOSFET 43, one terminal of the capacitor 44, and the input terminal of the inverter circuit INV12. The other terminal of the capacitor 44 is connected to the ground line. The output terminal of the inverter circuit INV12 is connected to the other input terminal of the NAND circuit NAND11. The output terminal of the NAND circuit NAND11 is connected to the input terminal of the inverter circuit INV13. The output terminal of the inverter circuit INV13 constitutes the output terminal of this pulse generation circuit 40.

[0057] When an L-level input signal is input to the input terminal of this pulse generation circuit 40, the L-level input signal is inverted to an H level by the inverter circuit INV11. As a result, the MOSFETs 41 and 43 have an H-level gate voltage applied to their gate terminals. The MOSFET 41 is turned off and the MOSFET 43 is turned on, so the charge of the capacitor 44 is discharged by the MOSFET 43. At this time, the inverter circuit INV12 outputs an H-level signal and applies it to the other input terminal of the NAND circuit NAND11. An L-level input signal input to the pulse generation circuit 40 is applied to one input terminal of the NAND circuit NAND11. Therefore, the NAND circuit NAND11 outputs an H-level signal, and this H-level signal is inverted to an L level by the inverter circuit INV13 and supplied to the output terminal of the pulse generation circuit 40.

[0058] When an H-level input signal is input to the input terminal of the pulse generation circuit 40, the H-level input signal is inverted to an L level by the inverter circuit INV11. As a result, the MOSFETs 41 and 43 have an L-level gate voltage applied to their gate terminals. The MOSFET 41 is turned on and the MOSFET 43 is turned off. At this time, a constant current that flows when the gate-source voltage of the depletion-type MOSFET 42 is 0V flows, charging the capacitor 44. At the start of charging, since the voltage of the capacitor 44 has not reached the threshold voltage of the inverter circuit INV12, the inverter circuit INV12 outputs an H-level signal. Therefore, since H-level signals are applied to both input terminals of the NAND circuit NAND11, the NAND circuit NAND11 outputs an L-level signal, and this L-level signal is inverted to an H level by the inverter circuit INV13 and supplied to the output terminal of the pulse generation circuit 40.

[0059] Thereafter, when the charging voltage of the capacitor 44 being charged at a constant current by the MOSFET 42 reaches the threshold voltage of the inverter circuit INV12, the inverter circuit INV12 outputs an L-level signal. For this reason, when the other input terminal of the NAND circuit NAND11 becomes the L level, the NAND circuit NAND11 outputs an H-level signal, and this H-level signal is inverted to the L level by the inverter circuit INV13 and supplied to the output terminal of the pulse generation circuit 40.

[0060] That is, when an input signal IN instructing the ON operation of the main MOSFET 110 is input to the IN terminal, the pulse generation circuit 40 generates and outputs an H-level pulse for a fixed time determined by the depletion-type MOSFET 42, the capacitor 44, and the inverter circuit INV12.

[0061] As shown in FIG. 3, the gated latch circuit 50 includes NAND circuits NAND12 and NAND13 that constitute a gate circuit, and NAND circuits NAND14 and NAND15 that constitute a latch circuit. One input terminal of the NAND circuit NAND12 is connected to the set terminal S of the gated latch circuit 50, one input terminal of the NAND circuit NAND13 is connected to the reset terminal R of the gated latch circuit 50, and the other input terminals of the NAND circuits NAND12 and NAND13 are connected to the enable terminal E of the gated latch circuit 50. The output terminal of the NAND circuit NAND12 is connected to one input terminal of the NAND circuit NAND14, and the output terminal of the NAND circuit NAND13 is connected to one input terminal of the NAND circuit NAND15. The other input terminal of the NAND circuit NAND14 is connected to the output terminal of the NAND circuit NAND15, and the other input terminal of the NAND circuit NAND15 is connected to the output terminal of the NAND circuit NAND14. The output terminal of the NAND circuit NAND14 is connected to the output terminal Q of the gated latch circuit 50, and the output terminal of the NAND circuit NAND15 is connected to the inverted output terminal NQ of the gated latch circuit 50.

[0062] The set terminal S of the gated latch circuit 50 receives a first overcurrent detection signal OCDS1 from the overcurrent detection circuit 160, and the reset terminal R of the gated latch circuit 50 receives a second overcurrent detection signal OCDS2 from the overcurrent detection circuit 160. In this embodiment, the first overcurrent detection signal OCDS1 is a signal that becomes high level when the overcurrent detection circuit 160 detects an overcurrent, and the second overcurrent detection signal OCDS2 is a signal obtained by inverting the first overcurrent detection signal OCDS1. The enable terminal E of the gated latch circuit 50 is connected to the output terminal of the pulse generation circuit 40.

[0063] When the gated latch circuit 50 receives a high-level pulse from the pulse generation circuit 40 at the enable terminal E, it latches the first overcurrent detection signal OCDS1 at the set terminal S and the second overcurrent detection signal OCDS2 at the reset terminal R, and holds the overcurrent detection state of the overcurrent detection circuit 160. When not in the overcurrent detection state, the overcurrent detection circuit 160 outputs a low-level first overcurrent detection signal OCDS1 and a high-level second overcurrent detection signal OCDS2. Also, when in the overcurrent detection state, the overcurrent detection circuit 160 outputs a high-level first overcurrent detection signal OCDS1 and a low-level second overcurrent detection signal OCDS2.

[0064] When the gated latch circuit 50 receives a high-level pulse and is not in the overcurrent detection state, it holds the low-level first overcurrent detection signal OCDS1 and outputs a low-level first switching signal SWS1 to the output terminal Q, and holds the high-level second overcurrent detection signal OCDS2 and outputs a high-level second switching signal SWS2 to the inverted output terminal NQ. When the gated latch circuit 50 receives a high-level pulse and is in the overcurrent detection state, it holds the high-level first overcurrent detection signal OCDS1 and outputs a high-level first switching signal SWS1 to the output terminal Q, and holds the low-level second overcurrent detection signal OCDS2 and outputs a low-level second switching signal SWS2 to the inverted output terminal NQ.

[0065] As shown in FIG. 4, the overcurrent mode switching circuit 60 includes inverter circuits INV14, INV15, INV16 and transmission gates 61, 62 that constitute a switch circuit. The overcurrent mode switching circuit 60 has an input terminal that receives the signal signal created by the oscillation signal creation circuit 30, and an input terminal that receives the first switching signal SWS1 and the second switching signal SWS2 output by the gated latch circuit 50. The overcurrent mode switching circuit 60 also has an output terminal that outputs signals signal0 and signal1 generated based on the signal signal.

[0066] The input terminal of the signal signal is connected to the first terminal of the transmission gate 61 and the input terminal of the inverter circuit INV14. The output terminal of the inverter circuit INV14 is connected to the first terminal of the transmission gate 62 and the output terminal of the signal signal1. The second terminals of the transmission gate 61 and the transmission gate 62 are connected to the input terminal of the inverter circuit INV15. The output terminal of the inverter circuit INV15 is connected to the input terminal of the inverter circuit INV16, and the output terminal of the inverter circuit INV16 is connected to the output terminal of the signal signal0. The input terminal that receives the first switching signal SWS1 is connected to the inversion control terminal of the transmission gate 61 and the control terminal of the transmission gate 62. The input terminal that receives the second switching signal SWS2 is connected to the control terminal of the transmission gate 61 and the inversion control terminal of the transmission gate 62.

[0067] When the overcurrent detection circuit 160 is not in the overcurrent detection state, the first switching signal SWS1 received from the gated latch circuit 50 is at the L level, and the second switching signal SWS2 is at the H level. At this time, in the overcurrent mode switching circuit 60, the transmission gate 61 is conductive and the transmission gate 62 is non-conductive. Therefore, the signal signal created when the input signal IN is input is output as a signal signal0 in phase with the signal signal through the transmission gate 61 and the inverter circuits INV15 and INV16. At this time, since the signal signal also passes through the inverter circuit INV14, the signal signal1 is out of phase with the signal signal.

[0068] On the other hand, when the overcurrent detection circuit 160 is in the overcurrent detection state, since the first switching signal SWS1 received from the gated latch circuit 50 is at the H level and the second switching signal SWS2 is at the L level, the transmission gate 61 is non-conductive and the transmission gate 62 is conductive. Here, when the input signal IN is input and the signal signal is input from the oscillation signal generation circuit 30, signals obtained by inverting the signal signal are output as the signals signal0 and signal1.

[0069] As shown in FIG. 5, the timing determination circuit 70 includes T flip-flops TFF11, TFF12, TFF13, NOR circuits NOR11, NOR12, NAND circuits NAND16, NAND17, and an inverter circuit INV17. The input terminal for receiving signal signal0 is connected to the input terminal of T flip-flop TFF11. The input terminal for receiving signal signal1 is connected to one input terminal of NOR circuit NOR1. The input terminal for receiving the first overcurrent detection signal OCDS1 is connected to one input terminal of NAND circuit NAND17. The output terminal of T flip-flop TFF11 is connected to the input terminal of T flip-flop TFF12 and the other input terminal of NOR circuit NOR11. The output terminal of T flip-flop TFF12 is connected to the input terminal of T flip-flop TFF13 and one input terminal of NOR circuit NOR12. The output terminal of T flip-flop TFF13 is connected to the other input terminal of NOR circuit NOR12. The output terminal of NOR circuit NOR11 is connected to one input terminal of NAND circuit NAND16. The output terminal of NOR circuit NOR12 is connected to the other input terminal of NAND circuit NAND16. The output terminal of NAND circuit NAND16 is connected to the other input terminal of NAND circuit NAND17. The output terminal of NAND circuit NAND17 is connected to the input terminal of inverter circuit INV17. The output terminal of inverter circuit INV17 constitutes the output terminal of timing determination circuit 70. Note that NOR circuits NOR11, NOR12 and NAND circuit NAND16 constitute the first logic operation circuit, and NAND circuit NAND17 and inverter circuit INV17 constitute the second logic operation circuit.

[0070] When the timing determination circuit 70 receives the signal signal0 from the overcurrent mode switching circuit 60, the signal signal0 is sequentially divided by a down-counter circuit composed of three-stage T flip-flops TFF11, TFF12, and TFF13. That is, the T flip-flop TFF11 outputs a signal signal2 with a period twice that of the signal signal0, the T flip-flop TFF12 outputs a signal signal3 with a period twice that of the signal signal2, and the T flip-flop TFF13 outputs a signal signal4 with a period twice that of the signal signal3. The NOR circuit NOR11 receives the signals signal1 and signal2 and outputs a high-level signal when both are at the low level. The NOR circuit NOR12 receives the signals signal3 and signal4 and outputs a high-level signal when both are at the low level. The NAND circuit NAND16 outputs a low-level signal (match signal) only when high-level signals are input from both of the NOR circuits NOR11 and NOR12. The low-level signal output by this NAND circuit NAND16 becomes a signal that periodically turns on the main MOSFET110 for a short time.

[0071] However, immediately after the high-level input signal IN is input when the overcurrent detection circuit 160 is not detecting an overcurrent, the signal signal1 remains at the high level, so the NAND circuit NAND16 outputs a high-level signal. Therefore, despite the high-level input signal IN being input, the NAND circuit NAND16 cannot output a low-level signal that turns on the main MOSFET110.

[0072] Therefore, the timing determination circuit 70 is provided with a NAND circuit NAND17 and an inverter circuit INV17. When the overcurrent detection circuit 160 does not detect an overcurrent, it outputs an L-level signal that turns on the main MOSFET 110 in synchronization with the input signal IN. That is, the output signal of the NAND circuit NAND16 and the first overcurrent detection signal OCDS1 are input to the NAND circuit NAND17. When the L-level first overcurrent detection signal OCDS1 that does not detect an overcurrent is input, the NAND circuit NAND17 outputs an H-level signal regardless of the logic level of the output signal of the NAND circuit NAND16, and the inverter circuit INV17 outputs an L-level signal output. That is, the NAND circuit NAND17 becomes effective when the NAND circuit NAND16 outputs a match signal or when the first overcurrent detection signal OCDS1 is at the L level, and the main MOSFET 110 is turned on only during the output effective interval of the output.

[0073] Next, the operation of the logic circuit 10 will be described with reference to FIGS. 6 to 8. FIG. 6 is a time chart showing the operation of the logic circuit when it enters the overcurrent detection state after the input signal is input, FIG. 7 is a time chart showing the operation of the logic circuit when it enters the overcurrent detection state before the input signal is input, and FIG. 8 is a time chart showing the operation of the logic circuit when it enters the overcurrent detection state during the period when the pulse generation circuit outputs a pulse. In FIGS. 6 to 8, from top to bottom, the input signal IN, the pulse generation circuit output, the first overcurrent detection signal OCDS1, the second overcurrent detection signal OCDS2, the first switching signal SWS1, the second switching signal SWS2, the signal signal, the signal signal0, the signal signal1, the signal signal2, the signal signal3, the signal signal4, and the signal output are shown respectively.

[0074] First, as shown in FIG. 6, when the H-level input signal IN is input, the pulse generation circuit 40 generates a pulse that rises in synchronization with the rising edge of the input signal IN. At this time, since the overcurrent detection circuit 160 does not detect an overcurrent, it outputs an L-level first overcurrent detection signal OCDS1 and an H-level second overcurrent detection signal OCDS2.

[0075] When the gated latch circuit 50 receives a pulse from the pulse generation circuit 40, it latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2. The gated latch circuit 50 outputs the L level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the H level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0076] The overcurrent mode switching circuit 60 places the transmission gate 61 in the conducting state and the transmission gate 62 in the non-conducting state according to the first switching signal SWS1 and the second switching signal SWS2.

[0077] After that, when the overcurrent detection circuit 160 detects an overcurrent, the first overcurrent detection signal OCDS1 becomes the H level and the second overcurrent detection signal OCDS2 becomes the L level. However, at this time, the generation of the pulse has ended and the gated latch circuit 50 is in the disabled state, and its holding state does not change, so the logic levels of the first switching signal SWS1 and the second switching signal SWS2 do not change either.

[0078] When the overcurrent detection circuit 160 detects an overcurrent, the oscillation signal generation circuit 30 outputs a signal signal that rises in synchronization with the rising edge of the first overcurrent detection signal OCDS1. At this time, since the overcurrent mode switching circuit 60 does not switch the overcurrent mode, the signal signal passes through the transmission gate 61 and the inverter circuits INV15 and INV16, and is output as a signal signal0 that is in the same phase as the signal signal. Also, the signal signal passes through the inverter circuit INV14 and is output as a signal signal1 that is in the opposite phase to the signal signal.

[0079] In the timing determination circuit 70, when a signal signal0 and a signal signal1 at the H level are input, the NAND circuit NAND16 outputs a signal at the H level. At this time, since the first overcurrent detection signal OCDS1 is at the H level, the NAND circuit NAND17 outputs a signal at the L level, and the inverter circuit INV17 outputs a signal output at the H level.

[0080] After that, in the timing determination circuit 70, upon receiving the signal signal0, signals signal2, signal signal3, and signal signal4 are sequentially generated. And each time a match signal is output from the NAND circuit NAND16, the output of the NAND circuit NAND16 becomes the L level, so the output of the NAND circuit NAND17 becomes the H level, and the inverter circuit INV17 outputs a signal output at the L level. This signal output turns on the main MOSFET 110 only during the output valid interval when it is at the L level.

[0081] In this way, when the input signal IN is input and an overcurrent detection state occurs, the output valid interval of the signal output immediately ends at that timing, so the main MOSFET 110 can be safely protected against overheating due to overcurrent.

[0082] Next, as shown in FIG. 7, when the overcurrent detection circuit 160 detects an overcurrent at the L level before the input signal IN is input, the overcurrent detection circuit 160 outputs a first overcurrent detection signal OCDS1 at the H level and outputs a second overcurrent detection signal OCDS2 at the L level.

[0083] After that, when the input signal IN at the H level is input, the pulse generation circuit 40 generates a pulse that rises in synchronization with the rising edge of the input signal IN and supplies it to the gated latch circuit 50.

[0084] When the gated latch circuit 50 receives a pulse from the pulse generation circuit 40, it latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2. The gated latch circuit 50 outputs the H level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the L level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0085] The overcurrent mode switching circuit 60 places the transmission gate 61 in the non-conducting state and the transmission gate 62 in the conducting state according to the first switching signal SWS1 and the second switching signal SWS2. Therefore, the signal signal created in synchronization with the rising edge of the input signal IN passes through the inverter circuit INV14, the transmission gate 62, and the inverter circuits INV15 and INV16 to become the signal signal0. The signal signal also passes through the inverter circuit INV14 to become the signal signal1. These signal signal0 and signal signal1 are out of phase with the signal signal.

[0086] In the timing determination circuit 70, when the signal signal0 is received, since the signals signal1, signal signal2, signal signal3, and signal signal4 are at the L level, the NAND circuit NAND16 outputs a matching signal at the L level. Therefore, the NAND circuit NAND17 outputs a signal at the H level, and the inverter circuit INV17 outputs a signal output at the L level. Only during the valid interval of the output, the main MOSFET 110 is turned on.

[0087] After that, the down-counter circuit sequentially generates the signals signal2, signal signal3, and signal signal4 with a half-cycle delay from the signal signal. Each time the NAND circuit NAND16 outputs a matching signal at the L level, the main MOSFET 110 is turned on.

[0088] In this way, when the input signal IN is input while in the overcurrent detection state, the timing of starting the count of the counter circuit for generating the signal output is delayed by half a cycle of the signal signal. As a result, since the output valid section of the signal output is surely set by half a cycle of the signal signal from the timing when the input signal IN is input, the microcomputer 200 can secure sufficient time to receive the signal AMP at the time of overcurrent detection.

[0089] Note that it is desirable that the output valid section at the time of input of the input signal IN, that is, the period of half a cycle of the signal signal output by the oscillation signal generation circuit 30, is longer than the period during which the pulse generation circuit 40 outputs a pulse. Thus, regardless of whether an overcurrent is detected at the time when the input signal IN is input, during at least the period when the pulse generation circuit 40 outputs a pulse, the logic circuit 10 outputs an on signal for the main MOSFET 110.

[0090] Next, as shown in FIG. 8, when the input signal IN at the H level is input, the pulse generation circuit 40 outputs a pulse. At this time, since the overcurrent detection circuit 160 is not detecting an overcurrent, it outputs the first overcurrent detection signal OCDS1 at the L level. Therefore, in the timing determination circuit 70, since the NAND circuit NAND17 receives the first overcurrent detection signal OCDS1 at the L level, the NAND circuit NAND17 outputs a signal at the H level, and the inverter circuit INV17 outputs a signal output at the L level.

[0091] If the overcurrent detection circuit 160 detects an overcurrent during the period when the pulse generation circuit 40 outputs a pulse, in the overcurrent detection circuit 160, the first overcurrent detection signal OCDS1 changes to the H level, and the second overcurrent detection signal OCDS2 changes to the L level.

[0092] At this time, since the gated latch circuit 50 is still receiving a pulse from the pulse generation circuit 40, it latches the first overcurrent detection signal OCDS1 and the second overcurrent detection signal OCDS2 whose logic levels have changed. The gated latch circuit 50 outputs the H level of the latched first overcurrent detection signal OCDS1 as the first switching signal SWS1, and outputs the L level of the latched second overcurrent detection signal OCDS2 as the second switching signal SWS2.

[0093] The overcurrent mode switching circuit 60 places the transmission gate 61 in the non-conducting state and the transmission gate 62 in the conducting state according to the first switching signal SWS1 and the second switching signal SWS2. For this reason, the signal signal created in synchronization with the rising edge of the first overcurrent detection signal OCDS1 passes through the inverter circuit INV14, the transmission gate 62, and the inverter circuits INV15 and INV16 to become the signal signal0. Also, the signal signal passes through the inverter circuit INV14 to become the signal signal1. The signal signal0 and the signal signal1 are out of phase with the signal signal.

[0094] In the timing determination circuit 70, immediately after the H-level input signal IN is input, since the first overcurrent detection signal OCDS1 is at the L level, the NAND circuit NAND17 outputs a H-level signal, and the inverter circuit INV17 outputs a L-level signal output. Immediately after the overcurrent detection circuit 160 detects an overcurrent and the first overcurrent detection signal OCDS1 becomes H level, the signal signal output by the oscillation signal generation circuit 30 becomes H level. As a result, the signals signal0, signal signal1, signal signal2, signal signal3, and signal signal4 all become L level. For this reason, since the NAND circuit NAND16 outputs a L-level coincidence signal, the NAND circuit NAND17 outputs a H-level signal, and the inverter circuit INV17 continues to output a L-level signal output.

[0095] After the output valid interval elapses with a half-cycle delay from the signal, the down-counter circuit sequentially generates signal2, signal3, and signal4. Each time the NAND circuit NAND16 outputs an L-level coincidence signal, the output valid interval becomes valid, and the main MOSFET 110 is turned on.

[0096] In this way, in the timing determination circuit 70, when the overcurrent detection circuit 160 detects an overcurrent, the counter circuit starts counting with a delay of half a cycle of the signal from that timing. Since the output valid interval extends until the start of counting, the microcomputer 200 can secure sufficient time to receive the signal AMP at the time of overcurrent detection.

[0097] In FIGS. 6 to 8, when the input signal IN is at the L level, the signal output indicates the H level. This is because, by a circuit not shown, when the input signal IN is at the L level, the signal output is configured to be at the H level.

[0098] In the above embodiment, the oscillation signal generation circuit 30 uses the signal signal that rises when both the input signal IN and the first overcurrent detection signal OCDS1 are at the H level, but it is not limited to this. For example, a signal signal starting from the L level can be created when both the input signal IN and the first overcurrent detection signal OCDS1 are at the H level. In the overcurrent mode switching circuit 60, the input positions of the first switching signal SWS1 and the second switching signal SWS2 may be interchanged with those in the case of FIG. 4. Also, the timing determination circuit 70 is configured with a three-stage T flip-flop TFF11, TFF12, TFF13, but it is not limited to this number of stages. Also, instead of the MOSFET 42 in the pulse generation circuit 40, a resistor or a diode-connected MOSFET can be used. Furthermore, a configuration using a NOR circuit instead of the NAND circuit can also be adopted. Also, the gated latch circuit 50 is configured with a NAND circuit, but a configuration using a NOR circuit can also be adopted.

[0099] The above is merely illustrative of the principles of the present invention. Further, numerous modifications and variations are possible for those skilled in the art, and the present invention is not limited to the exact configurations and application examples shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and their equivalents.

Description of Reference Numerals

[0100] 10 Logic circuit 20 Input circuit 21 Schmitt trigger circuit 30 Oscillation signal generation circuit 40 Pulse generation circuit 41, 42, 43 MOSFET 44 Capacitor 50 Gate latch circuit 60 Overcurrent mode switching circuit 61, 62 Transmission gate 70 Timing determination circuit 160 Overcurrent detection circuit INV11, INV12, INV13, INV14, INV15, INV16, INV17 Inverter circuit NAND11, NAND12, NAND13, NAND14, NAND15, NAND16, NAND17 NAND circuit NOR11, NOR12 NOR circuit TFF11, TFF12, TFF13 T flip-flop

Claims

1. A semiconductor device including a power semiconductor element, an overcurrent detection circuit, and a logic circuit having a function of periodically turning on the power semiconductor element for a short period of time when the overcurrent detection circuit detects an overcurrent, The logic circuit includes: an oscillation signal generating circuit that generates an oscillation signal when an input signal instructing an ON operation of the power semiconductor element and an overcurrent detection signal from the overcurrent detection circuit are simultaneously input; a pulse generating circuit that generates a pulse when the input signal is input; a gated latch circuit that holds the overcurrent detection state of the overcurrent detection circuit when the pulse is input; an overcurrent mode switching circuit that outputs a counter input signal obtained by switching the oscillation signal generated by the oscillation signal generating circuit to an inverted or non-inverted state in response to the overcurrent detection state held by the gated latch circuit, and an inverted signal obtained by inverting the oscillation signal; a timing determination circuit that divides the counter input signal into a plurality of divided signals and outputs an output signal for periodically turning on the power semiconductor element based on the inverted signal and the divided signals; The semiconductor device comprises:

2. 2. The semiconductor device according to claim 1, wherein said pulse generating circuit generates said pulse which continues for a fixed period of time set at the time when said input signal is input.

3. 2. The semiconductor device according to claim 1, wherein the gated latch circuit has a gate circuit that captures the overcurrent detection state of the overcurrent detection circuit when the pulse is input, and a latch circuit that holds the overcurrent detection state captured by the gate circuit, and the overcurrent mode switching circuit outputs a switching signal that switches the oscillation signal between inversion and non-inversion depending on the holding state of the latch circuit.

4. 4. The semiconductor device according to claim 3, wherein the overcurrent mode switching circuit comprises: an inverter circuit that outputs an inverted signal obtained by inverting the oscillation signal; and a switch circuit that selects the oscillation signal or the inverted signal based on the switching signal output by the gated latch circuit and sets the selected signal as the counter input signal.

5. 5. The semiconductor device according to claim 4, wherein said switch circuit is constituted by a transmission gate.

6. 2. The semiconductor device according to claim 1, wherein said timing determination circuit comprises: a counter circuit for dividing said counter input signal; and a logic operation circuit for outputting said output signal when all logical states of said inverted signal and said divided signal match.

7. 2. The semiconductor device according to claim 1, wherein said timing decision circuit comprises: a counter circuit which divides said counter input signal; a first logic operation circuit which outputs a match signal when the logical states of said inverted signal and said divided signal all match; and a second logic operation circuit which receives said overcurrent detection signal and said match signal, and outputs said output signal synchronized with said input signal when said overcurrent detection circuit is not detecting an overcurrent at the time when said input signal is input.

8. 8. The semiconductor device according to claim 6, wherein said counter circuit is composed of a plurality of T flip-flops.

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