Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device comprising: a semiconductor substrate; an interlayer insulation film that has a contact hole and is provided above the semiconductor substrate; a first alloy layer that is provided below the contact hole and on the upper surface of the semiconductor substrate; an oxide layer that is provided in the contact hole and on the upper surface of the first alloy layer; a conductive barrier metal layer that is provided in the contact hole and above the oxide layer; and a plug layer that is provided in the contact hole and above the barrier metal layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 describes a semiconductor device in which a "silicide layer" is provided in a "contact hole". [Prior Art Document] [Patent Document] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-318396 Patent Document 2: Japanese Patent Application Laid-Open No. 2007-335554 Patent Document 3: Japanese Patent Application Laid-Open No. 2002-334850 Problems to be Solved

[0003] It is preferable to improve the reliability on the front side of the semiconductor device. General Disclosure

[0004] In a first aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate, an interlayer insulating film having a contact hole and provided above the semiconductor substrate, a first alloy layer provided on the upper surface of the semiconductor substrate below the contact hole, an oxide layer provided on the upper surface of the first alloy layer in the contact hole, a conductive barrier metal layer provided above the oxide layer in the contact hole, and a plug layer provided above the barrier metal layer in the contact hole.

[0005] The oxide layer may be provided in contact with the first alloy layer and the barrier metal layer.

[0006] In any of the semiconductor devices described above, the first alloy layer and the barrier metal layer may contain a predetermined first metal. The oxide layer may contain an oxide of the first metal.

[0007] Any of the above semiconductor devices may include a drift region of a first conductivity type provided on the semiconductor substrate, a first conductivity type region of the first conductivity type provided on the front surface of the semiconductor substrate and having a higher doping concentration than the drift region, and a second conductivity type region of the second conductivity type provided on the front surface of the semiconductor substrate. The film thickness of the oxide layer may be thinner above the second conductivity type region than above the first conductivity type region.

[0008] In any of the above semiconductor devices, the oxide layer may not be provided above the second conductivity type region.

[0009] Any of the above semiconductor devices may include a polycrystalline layer provided above the semiconductor substrate or in the semiconductor substrate, and a front surface side metal layer electrically connected to the polycrystalline layer through a contact hole provided above the polycrystalline layer.

[0010] In any of the above semiconductor devices, the barrier metal layer may be provided on the upper surface of the oxide layer and the sidewall of the interlayer insulating film in the contact hole.

[0011] In any of the above semiconductor devices, the barrier metal layer may include a conductive first barrier metal portion provided on the sidewall of the interlayer insulating film, and a conductive second barrier metal portion laminated on the first barrier metal portion in the contact hole. The first barrier metal portion may be denser than the second barrier metal portion.

[0012] In any of the above semiconductor devices, the second barrier metal portion may be provided in contact with the first barrier metal portion and the oxide layer.

[0013] Any of the above semiconductor devices may have the contact hole and include a trench contact portion extending in the depth direction of the semiconductor substrate from the front surface of the semiconductor substrate.

[0014] In any of the semiconductor devices described above, the first alloy layer may be provided in contact with the side wall and the upper surface of the semiconductor substrate in the trench contact portion. The oxide layer may be provided in contact with the upper surface and the side surface of the first alloy layer in the trench contact portion.

[0015] In any of the semiconductor devices described above, the barrier metal layer may be provided in contact with the oxide layer provided on the side wall of the semiconductor substrate.

[0016] Any of the semiconductor devices described above may include a transistor portion and a diode portion.

[0017] Any of the semiconductor devices described above may include a front surface side lifetime control region provided closer to the front surface side than the center of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0018] In any of the semiconductor devices described above, the front surface side lifetime control region may be formed by irradiating the semiconductor substrate with a particle beam.

[0019] Any of the semiconductor devices described above may include a back surface side metal layer provided in contact with the back surface of the semiconductor substrate.

[0020] In a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming an interlayer insulating film having contact holes above a semiconductor substrate; forming a first alloy layer on the upper surface of the semiconductor substrate below the contact holes; forming an oxide layer on the upper surface of the first alloy layer in the contact holes; forming a conductive barrier metal layer above the oxide layer in the contact holes; and forming a plug layer above the barrier metal layer in the contact holes.

[0021] The step of forming the oxide layer may include a step of wet etching the upper surface of the first alloy layer after forming the first alloy layer on the upper surface of the semiconductor substrate.

[0022] In the method for manufacturing any of the semiconductor devices described above, the step of wet etching the upper surface of the first alloy layer may include a step of wet etching using hydrogen peroxide or buffered hydrofluoric acid.

[0023] In the method for manufacturing any of the semiconductor devices described above, the step of forming the oxide layer may include a step of annealing the semiconductor substrate in an oxygen atmosphere.

[0024] Note that the above summary of the invention does not list all the features of the present invention. Also, sub - combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0025]

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Embodiments for Carrying Out the Invention

[0026] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0027] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction during mounting of the semiconductor device.

[0028] In this specification, when explaining technical matters, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis may be used. The orthogonal coordinate axes only specify the relative positions of the components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without indicating positive or negative, it means the directions parallel to the +Z-axis and -Z-axis.

[0029] In this specification, orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are defined as the X-axis and the Y-axis. Also, an axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Also, in this specification, including the X-axis and the Y-axis, the directions parallel to the upper surface and the lower surface of the semiconductor substrate may sometimes be referred to as the horizontal direction.

[0030] In this specification, when described as P+ type or N+ type, it means that the doping concentration is higher than that of the P type or N type, and when described as P- type or N- type, it means that the doping concentration is lower than that of the P type or N type.

[0031] FIG. 1A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 in this example is a semiconductor chip including a transistor portion 70. The semiconductor device 100 is not limited to a transistor as long as it is a semiconductor element having a MOS gate structure on the semiconductor substrate 10.

[0032] The transistor portion 70 is an area obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor portion 70 includes a transistor such as an IGBT. In this example, the transistor portion 70 is an IGBT. Note that the transistor portion 70 may be another transistor such as a MOSFET.

[0033] In this figure, an area around the active portion of the semiconductor device 100 is shown, and other areas are omitted. For example, an edge termination structure portion may be provided in the negative side region of the semiconductor device 100 of this example in the Y-axis direction. The edge termination structure portion alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion has, for example, a guard ring, a field plate, RESURF, and a structure combining these. Note that in this example, for the sake of convenience, the edge on the negative side in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0034] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, may be a silicon carbide substrate, may be a gallium nitride substrate, may be a diamond substrate, or may be other substrates. The semiconductor substrate 10 of this example is a silicon substrate. Note that when simply referred to as a top view in this specification, it means viewing from the upper surface side of the semiconductor substrate 10. As will be described later, the semiconductor substrate 10 has a front surface 21 and a back surface 23.

[0035] In the semiconductor device 100 of this example, on the front surface 21 of the semiconductor substrate 10, there are provided a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are examples of the front surface side metal layer 53 described later. The gate trench portion 40 is an example of a MOS gate structure included in the semiconductor device 100. Note that the semiconductor device 100 of this example is a transistor having a MOS gate structure, but may be a diode having a MOS gate structure.

[0036] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Further, the gate metal layer 50 is provided above the connection portion 25 and the well region 17.

[0037] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a part of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). At least a part of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal layer formed of titanium or a titanium compound or the like under a region formed of aluminum or the like. The barrier metal layer will be described later. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0038] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film 38 therebetween. The interlayer insulating film 38 is omitted in FIG. 1A. Contact holes 54, 55, and 56 penetrate the interlayer insulating film 38.

[0039] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. A plug layer formed of tungsten or the like may be formed inside the contact hole 55. The plug layer will be described later.

[0040] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. A plug layer formed of tungsten or the like may be formed inside the contact hole 56.

[0041] The connection portion 25 is connected to the front-side metal layer 53 such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 in this example extends in the X-axis direction and may be electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connection portion 25 in this example is polysilicon doped with N-type impurities (N+). The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0042] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined extending direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The gate trench portions 40 in this example may have two extending portions 41 extending along an extending direction (the Y-axis direction in this example) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting portion 43 connecting the two extending portions 41.

[0043] At least a part of the connecting portion 43 is preferably formed in a curved shape. By connecting the ends of the two extending portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extending portions 41 can be alleviated. In the connecting portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connecting portion 25.

[0044] The dummy trench portion 30 is an example of a plurality of trench portions extending in a predetermined extending direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example), similar to the gate trench portions 40. The dummy trench portion 30 in this example has an I-shaped configuration on the front surface 21 of the semiconductor substrate 10, but may have a U-shaped configuration on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extending portions extending along the extending direction and a connecting portion connecting the two extending portions.

[0045] The transistor portion 70 in this example has a structure in which two gate trench portions 40 and two dummy trench portions 30 are repeatedly arranged. That is, the transistor portion 70 in this example has the gate trench portions 40 and the dummy trench portions 30 in a 1:1 ratio. For example, the transistor portion 70 has one dummy trench portion 30 between two extending portions 41.

[0046] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be larger than the ratio of the dummy trench portion 30, or the ratio of the dummy trench portion 30 may be larger than the ratio of the gate trench portion 40. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. Also, the transistor portion 70 may not have a dummy trench portion 30 and may have all the trench portions as the gate trench portion 40.

[0047] The well region 17 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10 rather than the drift region 18 described later. The well region 17 is an example of a well region provided on the peripheral side of the active portion 120. The active portion 120 will be described later. The well region 17 is, for example, of P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. A part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottoms of the ends in the extending direction of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0048] The contact hole 54 is formed above each of the emitter region 12 and the contact region 15 in the transistor portion 70. The contact hole 54 is not formed above the well region 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be formed to extend in the extending direction.

[0049] The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom portion of each trench portion. The extended portion of each trench portion may be regarded as one trench portion. That is, the region sandwiched between two extended portions may be regarded as the mesa portion.

[0050] In the transistor portion 70, the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are alternately provided in the extending direction.

[0051] The base region 14 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, of P-type. The base region 14 may be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0052] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. The emitter region 12 in this example is, for example, of N+ type. An example of the dopant of the emitter region 12 is arsenic (As). The emitter region 12 is provided in contact with the gate trench portion 40 on the front surface 21 of the mesa portion 71. The emitter region 12 may extend in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0053] Also, the emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 in this example is in contact with the dummy trench portion 30.

[0054] The contact region 15 is provided above the base region 14 and is a region of the second conductivity type having a higher doping concentration than the base region 14. The contact region 15 in this example is of P+ type as an example. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0055] FIG. 1B shows an example of the a-a' cross section in FIG. 1A. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor portion 70. The semiconductor device 100 in this example has, in the a-a' cross section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24. The collector electrode 24 is an example of a back surface side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0056] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. The drift region 18 in this example is of N- type as an example. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0057] The buffer region 20 is a region of a first conductivity type provided on the back surface 23 side of the semiconductor substrate 10 rather than the drift region 18. The buffer region 20 in this example is N-type as an example. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. Note that the buffer region 20 may be omitted.

[0058] The collector region 22 is provided below the buffer region 20 in the transistor portion 70. The collector region 22 has a second conductivity type. The collector region 22 in this example is P+-type as an example.

[0059] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0060] The base region 14 is a region of a second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0061] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0062] The accumulation region 16 is a region of a first conductivity type provided on the front surface 21 side of the semiconductor substrate 10 rather than the drift region 18. The accumulation region 16 in this example is N+-type as an example. However, the accumulation region 16 may not be provided.

[0063] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose amount of ion implantation in the accumulation region 16 is 1.0E+12 cm -2 or more and 1.0E+13 cm -2 or less. Also, the dose amount of ion implantation in the accumulation region 16 may be 3.0E+12 cm -2 or more and 6.0E+12 cm -2 or less. By providing the accumulation region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0064] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In the region where at least any one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion penetrates these regions and reaches the drift region 18. The fact that the trench portion penetrates the doping region is not limited to the case where the trench portion is formed in the order of forming the doping region and then the trench portion. Even in the case where the doping region is formed between the trench portions after the trench portions are formed, it is included in the case where the trench portion penetrates the doping region.

[0065] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered by an interlayer insulating film 38 on the front surface 21.

[0066] The gate conductive portion 44 includes a region facing the base region 14 adjacent on the mesa portion 71 side with the gate insulating film 42 interposed therebetween in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 in contact with the gate trench.

[0067] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy trench portion 30 may be covered by an interlayer insulating film 38 on the front surface 21.

[0068] The interlayer insulating film 38 is provided above the semiconductor substrate 10. The interlayer insulating film 38 in this example is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or a plurality of contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10 are provided in the interlayer insulating film 38. Similarly, the contact hole 55 and the contact hole 56 may also be provided to penetrate the interlayer insulating film 38. The film thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited thereto.

[0069] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a BPSG (Boro-phospho Silicate Glass) film, a BSG (borosilicate glass) film, or a PSG (Phosphosilicate glass) film. The interlayer insulating film 38 may include a high-temperature silicon oxide (HTO: High Temperature Oxide) film.

[0070] The back-side lifetime control region 151 may be provided in the transistor portion 70. However, the back-side lifetime control region 151 may be omitted. The back-side lifetime control region 151 is a region where a lifetime killer is intentionally formed by implanting impurities into the inside of the semiconductor substrate 10 or the like. In one example, the back-side lifetime control region 151 is formed by implanting helium into the semiconductor substrate 10. The back-side lifetime control region 151 may be formed by implanting protons. By providing the back-side lifetime control region 151, the turn-off time can be reduced, and the tail current can be suppressed, thereby reducing the loss during switching.

[0071] The lifetime killer is a recombination center of carriers. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a complex defect of these and the elements constituting the semiconductor substrate 10, or a dislocation. Also, the lifetime killer may be a noble gas element such as helium or neon, or a metal element such as platinum. An electron beam or protons may be used to form the lattice defect.

[0072] The lifetime killer concentration is the recombination center concentration of carriers. The lifetime killer concentration may be the lattice defect concentration. For example, the lifetime killer concentration may be the vacancy concentration such as a vacancy or a divacancy, the complex defect concentration of these vacancies and the elements constituting the semiconductor substrate 10, or the dislocation concentration. Also, the lifetime killer concentration may be the chemical concentration of a noble gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0073] The back-side lifetime control region 151 is provided on the back surface 23 side of the semiconductor substrate 10 rather than at the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The back-side lifetime control region 151 in this example is provided in the buffer region 20. The back-side lifetime control region 151 in this example is provided over the entire surface of the semiconductor substrate 10 in the XY plane and can be formed without using a mask. The back-side lifetime control region 151 may be provided on a part of the semiconductor substrate 10 in the XY plane. The dose amount of impurities for forming the back-side lifetime control region 151 is 0.5E+10 cm -2 or more and 1.0E+14 cm -2 or less, or 5.0E+10 cm -2 or more and 1.0E+13 cm -2 or less may be sufficient.

[0074] The back-side lifetime control region 151 may be formed by implantation from the back surface 23 side. This makes it easier to avoid the influence on the front surface 21 side of the semiconductor device 100. For example, the back-side lifetime control region 151 is formed by irradiating helium or protons from the back surface 23 side. Here, whether the back-side lifetime control region 151 is formed by implantation from the front surface 21 side or by implantation from the back surface 23 side can be determined by obtaining the state of the front surface 21 side through the SR method or measurement of leakage current.

[0075] FIG. 2A shows a top view of a modified example of the semiconductor device 100. In this example, only some members of the semiconductor device 100 are shown, and some members are omitted.

[0076] The semiconductor substrate 10 has side edges 102 in a top view. The semiconductor substrate 10 in this example has two sets of side edges 102 facing each other in a top view. In this example, the X axis and the Y axis are parallel to any one of the side edges 102.

[0077] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region where a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode 52 is provided above the active portion 120, but is omitted in this figure.

[0078] At least one of a transistor portion 70 including transistor elements such as IGBTs and a diode portion 80 including diode elements such as a freewheeling diode (FWD) is provided in the active portion 120. In the example of FIG. 2A, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 of the semiconductor substrate 10. In other examples, only one of the transistor portion 70 and the diode portion 80 may be provided in the active portion 120.

[0079] In this example, the region where the transistor portion 70 is arranged is marked with the symbol "I", and the region where the diode portion 80 is arranged is marked with the symbol "F". The transistor portion 70 and the diode portion 80 may each have a length in the extending direction. That is, the length of the transistor portion 70 in the Y-axis direction is larger than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is larger than the width in the X-axis direction. The extending direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.

[0080] The diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 will be described later. On the back surface 23 of the semiconductor substrate 10, a P+-type collector region 22 may be provided in a region other than the cathode region 82. In this specification, the extended region 85 obtained by extending the diode portion 80 in the Y-axis direction up to the gate wiring described later may also be included in the diode portion 80. A collector region 22 may be provided on the back surface 23 of the extended region 85.

[0081] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 in this example has a gate pad 112. The semiconductor device 100 may have pads such as an anode pad and a cathode pad. Each pad is disposed in the vicinity of the end side 102. The vicinity of the end side 102 refers to the region between the end side 102 in a top view and the emitter electrode 52. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via a wiring such as a wire.

[0082] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion 40. In FIG. 2A, the gate wiring is hatched with oblique lines.

[0083] The gate wiring in this example has an outer peripheral gate wiring 130 and an inter-active portion gate wiring 131. The gate wiring may be configured by appropriately combining either one or both of the gate metal layer 50 and the connection portion 25. The outer peripheral gate wiring 130 and the inter-active portion gate wiring 131 may have the same configuration or different configurations. The outer peripheral gate wiring 130 is disposed between the active portion 120 and the end side 102 of the semiconductor substrate 10 in a top view. The outer peripheral gate wiring 130 in this example surrounds the active portion 120 in a top view. The region surrounded by the outer peripheral gate wiring 130 in a top view may be regarded as the active portion 120. Further, the outer peripheral gate wiring 130 is connected to the gate pad 112. The outer peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The outer peripheral gate wiring 130 may be constituted by the gate metal layer 50 and the connection portion 25.

[0084] The inter-active region gate wiring 131 is provided between a plurality of active regions 120. In FIG. 2A, two active regions 120 are arranged side by side in the Y-axis direction. By providing the inter-active region gate wiring 131 between the plurality of active regions 120 inside the semiconductor substrate 10, the variation in the wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

[0085] The inter-active region gate wiring 131 is connected to the gate trench portion of the active region 120. The inter-active region gate wiring 131 is disposed above the semiconductor substrate 10. The inter-active region gate wiring 131 in this example is composed of a gate metal layer 50 and a connection portion 25. The gate metal layer 50 may be a metal layer containing aluminum or the like.

[0086] The inter-active region gate wiring 131 may be connected to the outer peripheral gate wiring 130. The inter-active region gate wiring 131 in this example is provided to extend in the X-axis direction so as to cross the active region 120 from one outer peripheral gate wiring 130 to the other outer peripheral gate wiring 130 at approximately the center in the Y-axis direction. When the active region 120 is divided by the inter-active region gate wiring 131, the transistor portions 70 and the diode portions 80 may be alternately arranged in the X-axis direction in each divided region.

[0087] The edge termination structure portion 140 is provided on the front surface 21 of the semiconductor substrate 10. The edge termination structure portion 140 is provided between the active region 120 and the end side 102 in a top view. The edge termination structure portion 140 in this example is disposed between the outer peripheral gate wiring 130 and the end side 102. The edge termination structure portion 140 relaxes the electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure portion 140 may include at least one of a guard ring, a field plate, and RESURF provided annularly surrounding the active region 120.

[0088] FIG. 2B shows a top view of a modified example of the semiconductor device 100. The semiconductor device 100 in this example includes a transistor portion 70 and a diode portion 80. This figure is an enlarged top view of the region A in FIG. 2A.

[0089] The semiconductor device 100 in this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 provided inside the semiconductor substrate 10 on the front surface 21 side. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0090] The dummy trench portion 30 in this example may have a U shape on the front surface 21 of the semiconductor substrate 10, similarly to the gate trench portion 40. That is, the dummy trench portion 30 may have two extending portions 31 extending along the extending direction and a connecting portion 33 connecting the two extending portions 31.

[0091] The semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor portion 70 in this example includes a boundary portion 90 located at the boundary between the transistor portion 70 and the diode portion 80. However, the semiconductor device 100 may not include the boundary portion 90.

[0092] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The boundary portion 90 in this example does not have an emitter region 12. In one example, the trench portion of the boundary portion 90 is the dummy trench portion 30. The boundary portion 90 in this example is arranged such that both ends in the X-axis direction are the dummy trench portions 30.

[0093] The contact hole 54 is provided above the base region 14 in the diode portion 80. The contact hole 54 is provided above the contact region 15 in the boundary portion 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0094] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0095] The mesa portion 81 is provided in the region sandwiched between adjacent dummy trench portions 30 in the diode portion 80. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a well region 17 on the negative side in the Y-axis direction.

[0096] The emitter region 12 is provided in the mesa portion 71, but does not have to be provided in the mesa portion 81 and the mesa portion 91. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but does not have to be provided in the mesa portion 81.

[0097] FIG. 2C shows a cross-section taken along the line b-b' of a modified example of the semiconductor device 100. This figure corresponds to the cross-section taken along the line b-b' of FIG. 2B. The semiconductor device 100 of this example includes a back surface side lifetime control region 151 and a front surface side lifetime control region 152. However, the semiconductor device 100 does not have to include either the back surface side lifetime control region 151 or the front surface side lifetime control region 152. The semiconductor device 100 of this example includes a collector region 22 and a cathode region 82 on the back surface 23 side of the buffer region 20.

[0098] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross-sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0099] The storage region 16 is provided in the transistor portion 70 and the diode portion 80. The storage region 16 of this example is provided over the entire surfaces of the transistor portion 70 and the diode portion 80. However, the storage region 16 does not have to be provided in the diode portion 80.

[0100] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 of this example.

[0101] The back surface side lifetime control region 151 is provided in both the transistor section 70 and the diode section 80. Thereby, the semiconductor device 100 of this example can accelerate the recovery in the diode section 80 and further improve the switching loss. The back surface side lifetime control region 151 may be formed by the same method as the back surface side lifetime control region 151 of other embodiments.

[0102] The front surface side lifetime control region 152 is provided on the front surface 21 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The front surface side lifetime control region 152 of this example is provided in the drift region 18. The front surface side lifetime control region 152 is provided in both the transistor section 70 and the diode section 80. The front surface side lifetime control region 152 is provided at the boundary between the diode section 80 and the boundary section 90, and may not be provided in a part of the transistor section 70. The front surface side lifetime control region 152 can suppress the injection of holes from the diode section 80 and the transistor section 70 and reduce the reverse recovery loss.

[0103] The front surface side lifetime control region 152 may be formed by any method among the methods for forming the back surface side lifetime control region 151. The elements, dose amounts, etc. for forming the back surface side lifetime control region 151 and the front surface side lifetime control region 152 may be the same or different.

[0104] The front - side lifetime control region 152 extends from the diode portion 80 to the transistor portion 70. The front - side lifetime control region 152 may be formed by irradiation from the front surface 21 of the semiconductor substrate 10. The front - side lifetime control region 152 may also be formed by irradiation from the back - surface 23 side of the semiconductor substrate 10. The front - side lifetime control region 152 of this example is provided below the gate trench portion 40. When a particle beam or the like for forming the front - side lifetime control region 152 passes through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0105] The semiconductor device 100 may be a power semiconductor device for controlling power or the like. The semiconductor device 100 of this example may have a vertical semiconductor structure including a back - side metal layer on the back - surface 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may have a lateral semiconductor structure without a metal layer on the back - surface 23 side.

[0106] In this example, the semiconductor device 100 is exemplified and described as an RC - IGBT with a trench - gate structure. However, the semiconductor device 100 may be a semiconductor device with a planar - gate structure, or may be other semiconductor devices such as diodes. The semiconductor device 100 may include an N - channel MOSFET or a P - channel MOSFET.

[0107] FIG. 3A is an enlarged cross - sectional view of the semiconductor device 100. In this example, an enlarged cross - sectional view in the vicinity of the contact hole 54 is shown. The cross - section of this example is an XZ cross - section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The emitter region 12 is an example of the first conductivity - type region 161. The semiconductor device 100 includes a barrier metal layer 60, a first alloy layer 63, a plug layer 64, and an oxide layer 66.

[0108] In this specification, although the contact hole 54 may be used to describe the structure in the vicinity of the contact hole, the same structure may also be applied to other contact holes such as the contact hole 55 and the contact hole 56. That is, the barrier metal layer 60, the first alloy layer 63, the plug layer 64, and the oxide layer 66 may be provided in other contact holes such as the contact hole 55 and the contact hole 56. Similarly, for the contact hole 58 described later, the barrier metal layer 60, the first alloy layer 63, the plug layer 64, and the oxide layer 66 may be provided.

[0109] The barrier metal layer 60 is provided above the oxide layer 66 in the contact hole 54. The barrier metal layer 60 is provided on the bottom surface of the contact hole 54 and the side wall of the interlayer insulating film 38. The barrier metal layer 60 may be provided in contact with the upper surface of the interlayer insulating film 38. In the contact hole 54 of this example, the barrier metal layer 60 is provided on the upper surface of the oxide layer 66 and the side wall of the interlayer insulating film 38. The barrier metal layer 60 contains a predetermined conductive first metal. The first metal may be at least one of titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), magnesium (Mg), vanadium (V), lanthanum (La), palladium (Pd), or zirconium (Zr). The first metal may be a metal having a hydrogen storage effect. The barrier metal layer 60 of this example has a first barrier metal portion 61 and a second barrier metal portion 62.

[0110] The first barrier metal portion 61 is provided on the side wall of the interlayer insulating film 38 in the contact hole 54. The first barrier metal portion 61 contains a predetermined conductive first metal. For example, the first barrier metal portion 61 is TiN. The first barrier metal portion 61 may be a hydrogen storage alloy. The first barrier metal portion 61 is formed by annealing an initial metal film containing the first metal. The first barrier metal portion 61 of this example is TiN formed by annealing Ti formed on the side wall of the interlayer insulating film 38 as an initial metal film in a nitrogen atmosphere.

[0111] The second barrier metal portion 62 is laminated on the first barrier metal portion 61 in the contact hole 54. The second barrier metal portion 62 contains a conductive material. For example, the second barrier metal portion 62 is TiN. The second barrier metal portion 62 is provided by being laminated with a first alloy layer 63 provided on the upper surface of the semiconductor substrate 10. The second barrier metal portion 62 may be formed by sputtering a conductive material. The second barrier metal portion 62 in this example is TiN formed by sputtering. The second barrier metal portion 62 may be provided in contact with the first barrier metal portion 61 and the oxide layer 66.

[0112] The first alloy layer 63 is provided on the upper surface of the semiconductor substrate 10 below the contact hole 54. The first alloy layer 63 in this example is provided on the upper surface of the semiconductor substrate 10. The first alloy layer 63 is formed by annealing an initial metal film containing a first metal. The first alloy layer 63 may be an alloy composed of the first metal and the constituent elements of the layer at the bottom surface of the contact hole 54. As an example, when the semiconductor substrate 10 is a silicon substrate, the first alloy layer 63 may be a silicide layer. As another example, when the semiconductor substrate 10 is a silicon carbide substrate, a gallium nitride substrate, a diamond substrate, or the like, the first alloy layer 63 may be an alloy layer containing these substrate materials and the first metal. The first alloy layer 63 in this example is a titanium silicide layer formed by annealing Ti formed as an initial metal film on the bottom surface of the contact hole 54. The N-type regions including the first conductivity type region 161 are formed such that N-type impurities have a high concentration at the locations in contact with the first alloy layer 63, and the contact resistance may be reduced.

[0113] The first barrier metal portion 61 and the first alloy layer 63 may be formed by the same annealing process. For example, the first barrier metal portion 61 of TiN is formed on the sidewall of the interlayer insulating film 38, and the first alloy layer 63 of titanium silicide is formed on the upper surface of the semiconductor substrate 10. Note that all the formed initial metal films are used for forming the first barrier metal portion 61 or the first alloy layer 63, and the initial metal films do not have to remain. An initial metal film may remain on the first alloy layer 63 and the metal film 67 described later may be formed, or the first barrier metal portion 61 may be formed on the first alloy layer 63 or the metal film 67.

[0114] The plug layer 64 is provided above the barrier metal layer 60 in the contact hole 54. The plug layer 64 may be provided in contact with the second barrier metal portion 62 in the contact hole 54. The plug layer 64 is a conductive material filled inside the contact hole 54. The plug layer 64 may be made of a material different from the front-side metal layer 53. For example, the material of the plug layer 64 is tungsten. Note that the plug layer 64 may also be provided in contact with the second barrier metal portion 62 above the interlayer insulating film 38 outside the contact hole 54. The plug layer 64 may be omitted and the front-side metal layer 53 may be filled inside the contact hole 54. As will be described later, the plug layer 64 may penetrate into the second barrier metal portion 62.

[0115] The oxide layer 66 is provided on the upper surface of the first alloy layer 63 in the contact hole 54. The oxide layer 66 may be in contact with the upper surface of the first alloy layer 63, or may be in contact with the lower surface of the barrier metal layer 60. The oxide layer 66 may be provided in contact with the first alloy layer 63 and the barrier metal layer 60. That is, the oxide layer 66 may be laminated between the first alloy layer 63 and the barrier metal layer 60. Note that when the first barrier metal portion 61 or the metal film 67 is formed on the upper surface of the first alloy layer 63, the oxide layer 66 may be formed on the first barrier metal portion 61 or the metal film 67. Further, the oxide layer 66 may be formed under the second barrier metal portion 62 on the sidewall of the interlayer insulating film 38 in the contact hole 54.

[0116] The oxide layer 66 may contain elements constituting the first alloy layer 63, the first barrier metal portion 61, or the metal film 67. The oxide layer 66 may contain an element constituting the semiconductor substrate 10 or an oxide of silicon. For example, the oxide layer 66 is a silicon oxide film. The composition of the oxide layer 66 may be at least one of SiO, SiO2, or Si2O3. The oxide layer 66 may contain a predetermined conductive first metal. For example, the oxide layer 66 may contain titanium and may include a titanium oxide film. The composition of the oxide layer 66 may be at least one of TiO, TiO2, or Ti2O3. The oxide layer 66 may be a dense film that functions as a metal diffusion prevention layer. For example, the oxide layer 66 can prevent the diffusion of the plug layer 64 during the formation of the plug layer 64 and protect the first alloy layer 63 from damage during the formation of the plug layer 64.

[0117] The film thickness of the oxide layer 66 may be thinner than the film thickness of the first alloy layer 63. The film thickness of the oxide layer 66 may be thinner than the film thickness of the second barrier metal portion 62. The film thickness of the oxide layer 66 may be 0.5 nm or more and 4.0 nm or less. For example, the film thickness of the oxide layer 66 is 2.5 nm. The film thickness of the oxide layer 66 may be the film thickness at the thickest position in the contact hole 54.

[0118] The oxide layer 66 may be formed by exposure to chemical substances such as etching. The oxide layer 66 may be formed by etching the upper surface of the first alloy layer 63, the first barrier metal portion 61, or the metal film 67. The etching of the upper surface of the first alloy layer 63, the first barrier metal portion 61, or the metal film 67 may be wet etching or dry etching. The oxide layer 66 may be formed by dry etching of the upper surface of the first alloy layer 63. Also, the oxide layer 66 may be formed by oxidation of the upper surface of the first alloy layer 63, the first barrier metal portion 61, or the metal film 67. The oxide layer 66 may be formed by annealing the semiconductor substrate 10 in an oxygen atmosphere. The oxide layer 66 may be formed by being deposited on the first alloy layer 63, the first barrier metal portion 61, the metal film 67, or the interlayer insulating film 38.

[0119] The interlayer insulating film 38 has contact holes 54 and is provided above the semiconductor substrate 10. The interlayer insulating film 38 has a single insulating film provided above the front surface 21, but may have a plurality of stacked insulating films. The interlayer insulating film 38 may be a silicon oxide film such as BPSG.

[0120] The first barrier metal portion 61 is denser than the second barrier metal portion 62. The first barrier metal portion 61 and the second barrier metal portion 62 may be formed by different film formation methods. The first barrier metal portion 61 may be a TiN film formed by annealing Ti deposited on the sidewalls of the interlayer insulating film 38. The second barrier metal portion 62 may be a TiN film formed by sputtering TiN. Thereby, the first barrier metal portion 61 may be a denser TiN film than the second barrier metal portion 62. The first barrier metal portion 61 and the second barrier metal portion 62 may contain the same material.

[0121] By forming the first barrier metal portion 61 densely, the interlayer insulating film 38 can be protected from damage during the film formation of the plug layer 64. On the other hand, since it is not necessary to form an initial metal film for the second barrier metal portion 62 formed by sputtering, the influence of the hydrogen storage effect due to the remaining Ti or the like can be avoided. However, since the second barrier metal portion 62 is not a dense film like the first barrier metal portion 61, the plug layer 64 may penetrate into the second barrier metal portion 62 during the formation of the plug layer 64.

[0122] The film thickness of the first barrier metal portion 61 may be thinner than the film thickness of the second barrier metal portion 62. The film thickness of the first barrier metal portion 61 may be thinner than the film thickness of the first alloy layer 63. The first barrier metal portion 61 may be thinned by etching after a dense film is formed. The etching after a dense film is formed may be performed with a chemical solution. The chemical solution for performing the etching may be, for example, hydrofluoric acid (HF), ammonium peroxide, or sulfuric acid. Ammonium peroxide is a mixed solution of ammonia (NH4OH), hydrogen peroxide (H2O2), and water (H2O). The etching after a dense film is formed may be dry etching or reverse sputtering. The film thickness of the first barrier metal portion 61 may be 1 nm or more and 10 nm or less. The film thickness of the first barrier metal portion 61 may be the film thickness at the thickest position in the contact hole 54. The film thickness of the first barrier metal portion 61 may be formed within a predetermined range over the entire sidewall of the interlayer insulating film 38. The film thickness of the second barrier metal portion 62 may be 1 nm or more and 100 nm or less. The film thickness of the first alloy layer 63 may be 1 nm or more and 200 nm or less.

[0123] The first barrier metal portion 61 may cover the sidewall of the interlayer insulating film 38. The lower end of the first barrier metal portion 61 may be in contact with the oxide layer 66. That is, the bottom surface of the contact hole 54 and the sidewall of the interlayer insulating film 38 may be covered with the oxide layer 66 and the first barrier metal portion 61, respectively. Thereby, erosion of the interlayer insulating film 38 and the first alloy layer 63 by the gas during the film formation of the plug layer 64 can be avoided.

[0124] The opening width W54 of the contact hole 54 is the width in the trench arrangement direction of the contact hole 54 on the upper surface of the interlayer insulating film 38. The opening width W54 of the contact hole 54 may be 100 nm or more and 1000 nm or less.

[0125] Here, when an electron beam, a particle beam, etc. for forming a lifetime control region pass through the MOS gate structure, defects may occur in the vicinity of the interface between the oxide film and the semiconductor layer of the MOS gate structure. And when a metal such as Ti having a hydrogen storage effect exists near the MOS gate structure, it absorbs hydrogen diffusing into the gate portion, inhibits the hydrogen termination of the dangling bond of the MOS gate structure, and the threshold voltage may fluctuate.

[0126] On the upper surface of the first alloy layer 63, an unreacted initial metal film having a hydrogen storage effect may remain. The semiconductor device 100 of this example can reduce the remaining amount of the initial metal film having a hydrogen storage effect and form the oxide layer 66 by etching and oxidizing the upper surface of the first alloy layer 63. Further, the semiconductor device 100 of this example can reduce the remaining amount of the first metal having a hydrogen storage effect by thinning the first barrier metal portion 61. Thereby, the influence of the hydrogen storage effect can be suppressed, and the hydrogen termination of the dangling bond of the MOS gate structure can be promoted. Thereby, the fluctuation of the threshold voltage can be suppressed.

[0127] The semiconductor device 100 can secure the barrier property during the film formation of the plug layer 64 by including the oxide layer 66. The semiconductor device 100 of this example can suppress the fluctuation of the threshold voltage while enhancing the reliability on the front surface 21 side. Further, since the semiconductor device 100 can form a lifetime control region while suppressing the fluctuation of the threshold voltage, the reverse recovery loss can be reduced.

[0128] Note that when irradiating with an electron beam or a particle beam to form a lifetime control region, the influence on the MOS gate structure becomes significant when irradiating from the front surface 21 side of the semiconductor substrate 10, but it can also affect the MOS gate structure when irradiating from the back surface 23 side of the semiconductor substrate 10. Therefore, the semiconductor device 100 can recover the damage to the MOS gate structure and suppress the fluctuation of the threshold voltage even when irradiating from the back surface 23 side. Note that when irradiating with a particle beam or the like from the back surface 23 side of the semiconductor substrate 10, as the acceleration voltage increases and the device becomes larger, in the semiconductor device 100 of this example, since the influence of irradiating with a particle beam or the like from the front surface 21 can be suppressed, a lifetime control region can be formed with a smaller device.

[0129] The first conductivity type region 161 is provided on the front surface 21 of the semiconductor substrate 10 and is a first conductivity type region having a higher doping concentration than the drift region 18. The first conductivity type region 161 may be the N-type region of the transistor portion 70. The first conductivity type region 161 of this example is the emitter region 12, but is not limited thereto. The first conductivity type region 161 may be the N-type region of the MOSFET. The first conductivity type region 161 may be an N-type region provided outside the transistor portion 70. The first conductivity type region 161 may be the N-type region of the temperature sense diode. The first conductivity type region 161 may also be the N-type region of the diode portion such as an RC-IGBT.

[0130] FIG. 3B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of this example is different from the cross-section of FIG. 3A at the point where it passes through the contact region 15 on the front surface 21. The contact region 15 is an example of the second conductivity type region 162. In this example, the points different from FIG. 3A will be particularly described.

[0131] The p-type region 162 is a p-type region provided on the front surface 21 of the semiconductor substrate 10. The p-type region 162 may be the p-type region of the transistor portion 70. The p-type region 162 in this example is the contact region 15, but is not limited thereto. The p-type region 162 may be the p-type region of the MOSFET. The p-type region 162 may be a p-type region provided outside the transistor portion 70. The p-type region 162 may be the p-type region of the temperature sense diode. The p-type region 162 may also be the p-type region of the diode portion such as an RC-IGBT.

[0132] The structure of the contact hole 54 above the p-type region 162 may be the same as or different from the structure of the contact hole 54 above the n-type region 161. That is, the film thicknesses of the barrier metal layer 60, the first alloy layer 63, and the oxide layer 66 may be the same above the n-type region 161 and above the p-type region 162, respectively. In this example, the film thickness of the oxide layer 66 provided above the p-type region 162 is the same as the film thickness of the oxide layer 66 provided above the n-type region 161, but may be different. The film thickness of the oxide layer 66 may be thinner above the p-type region 162 than above the n-type region 161. The p-type region including the p-type region 162 is formed such that the p-type impurities have a high concentration at the portion in contact with the first alloy layer 63, and the contact resistance may be reduced.

[0133] FIG. 4A is an enlarged cross-sectional view of the semiconductor device 100. The cross-section in this example is an XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example is different from the embodiment of FIG. 3A in that it does not include the first barrier metal portion 61 and includes a metal film 67 between the second barrier metal portion 62 and the interlayer insulating film 38.

[0134] The metal film 67 may be formed by the remaining of the initial metal film. That is, in the step of forming the first alloy layer 63, the initial metal film may remain, and even after the etching in the step of forming the oxide layer 66, a part of the initial metal film may remain and the metal film 67 may be formed. The metal film 67 may be denser than the second barrier metal portion 62. The metal film 67 is provided on the sidewall of the interlayer insulating film 38 in the contact hole 54. The metal film 67 may be provided in contact with the upper surface of the interlayer insulating film 38. The second barrier metal portion 62 is provided on the bottom surface of the contact hole 54 and the sidewall of the interlayer insulating film 38. The second barrier metal portion 62 may be provided above the interlayer insulating film 38, and the metal film 67 may be provided between the second barrier metal portion 62 and the interlayer insulating film 38. In the second barrier metal portion 62 of this example, in the contact hole 54, it is provided on the upper surface of the oxide layer 66 and the sidewall of the interlayer insulating film 38, and the metal film 67 is provided between the sidewall of the interlayer insulating film 38 and the second barrier metal portion 62.

[0135] The first barrier metal portion 61 may not be formed or may be formed. When the first barrier metal portion 61 is formed, after the first barrier metal portion 61 is formed on the surface of the metal film 67 by the annealing process in the step of forming the first alloy layer 63, all of the first barrier metal portion 61 may be removed by the etching in the step of forming the oxide layer 66.

[0136] FIG. 4B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of this example is the XZ plane passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is different from the embodiment of FIG. 3B in that it does not include the first barrier metal portion 61 and includes the metal film 67 between the second barrier metal portion 62 and the interlayer insulating film 38.

[0137] Also in the embodiments of FIGS. 4A and 4B, since the semiconductor device 100 includes the oxide layer 66, the barrier property during the film formation of the plug layer 64 can be ensured. Further, since the metal film 67 is thinned by etching in the process of forming the oxide layer 66, the influence of the hydrogen storage effect can be suppressed, and the hydrogen termination of the dangling bond of the MOS gate structure can be promoted. Thereby, the variation of the threshold voltage can be suppressed.

[0138] FIG. 5A is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of this example is an XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is different from the embodiments of FIGS. 3A and 4A in that a metal film 67 is provided between the first barrier metal portion 61 and the interlayer insulating film 38.

[0139] The metal film 67 may be formed by the remaining of the initial metal film. In this example, by the annealing process in the process of forming the first alloy layer 63, the first barrier metal portion 61 is formed and the metal film 67 remains. A part of the first barrier metal portion 61 may remain even after passing through the etching in the process of forming the oxide layer 66. The metal film 67 is provided on the side wall of the interlayer insulating film 38 in the contact hole 54. The metal film 67 may be provided in contact with the upper surface of the interlayer insulating film 38. The barrier metal layer 60 is provided on the bottom surface of the contact hole 54 and the side wall of the interlayer insulating film 38. The barrier metal layer 60 may be provided above the interlayer insulating film 38, and the metal film 67 may be provided between the barrier metal layer 60 and the interlayer insulating film 38. The barrier metal layer 60 of this example is provided on the upper surface of the oxide layer 66 and the side wall of the interlayer insulating film 38 in the contact hole 54, and the metal film 67 is provided between the side wall of the interlayer insulating film 38 and the barrier metal layer 60.

[0140] FIG. 5B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of this example is an XZ plane passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is different from the embodiments of FIGS. 3B and 4B in that a metal film 67 is provided between the first barrier metal portion 61 and the interlayer insulating film 38.

[0141] In the embodiments of FIGS. 5A and 5B as well, since the semiconductor device 100 includes the oxide layer 66, it is possible to ensure the barrier property during the film formation of the plug layer 64. Further, by being thinned by the etching in the process of forming the first barrier metal portion 61 into the oxide layer 66, the influence of the hydrogen storage effect can be suppressed, and the hydrogen termination of the dangling bond of the MOS gate structure can be promoted. Thereby, the variation of the threshold voltage can be suppressed.

[0142] FIG. 6A is an enlarged cross-sectional view of the semiconductor device 100. In this example, an enlarged cross-sectional view in the vicinity of the contact hole 54 is shown. The cross-section of this example is an XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is different from the embodiment of FIG. 3A in that it does not include the first barrier metal portion 61.

[0143] The barrier metal layer 60 has a second barrier metal portion 62. The barrier metal layer 60 does not have to have the first barrier metal portion 61. The first barrier metal portion 61 formed at the time of forming the first alloy layer 63 and / or the initial metal film remaining without forming the first barrier metal portion 61 may be removed by etching. The second barrier metal portion 62 of this example may be provided in contact with the side wall of the interlayer insulating film 38. Note that the second barrier metal portion 62 may be provided above the interlayer insulating film 38.

[0144] The film thickness D66a is the thickness of the oxide layer 66 in the depth direction of the semiconductor substrate 10. In particular, the film thickness D66a may be the thickness of the oxide layer 66 in the depth direction of the semiconductor substrate 10 above the first conductivity type region 161. The film thickness D66a may be the film thickness at the thickest position of the oxide layer 66. The film thickness D66a may be thinner than the film thickness of the first alloy layer 63.

[0145] FIG. 6B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of this example is different from the cross-section of FIG. 6A in that it passes through the contact region 15 on the front surface 21. In this example, the points different from FIG. 6A will be particularly described.

[0146] The film thickness D66b is the thickness of the oxide layer 66 in the depth direction of the semiconductor substrate 10. In particular, the film thickness D66b is the thickness of the oxide layer 66 in the depth direction of the semiconductor substrate 10 above the second conductivity type region 162. The film thickness D66b may be thinner than the film thickness of the first alloy layer 63. The film thickness D66b of the oxide layer 66 above the second conductivity type region 162 in this example is thinner than the film thickness D66a of the oxide layer 66 above the first conductivity type region 161.

[0147] After the oxide layer 66 is formed above the first conductivity type region 161 and the second conductivity type region 162, it may be selectively etched above the second conductivity type region 162. By using a mask, the oxide layer 66 may be separately formed above the first conductivity type region 161 and above the second conductivity type region 162 to provide oxide layers 66 with different film thicknesses. In this example, the thickness of the oxide layer 66 above the second conductivity type region 162 is thinner than the thickness of the oxide layer 66 above the first conductivity type region 161, but the thickness of the oxide layer 66 above the first conductivity type region 161 may also be thinner than the thickness of the oxide layer 66 above the second conductivity type region 162. Also, in any of the embodiments of FIGS. 3A, 3B, 4A, 4B, 5A, and 5B, the thickness of the oxide layer 66 may be different above the first conductivity type region 161 and above the second conductivity type region 162.

[0148] FIG. 7A is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of this example is an XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is different from the embodiment of FIG. 3A in that the barrier metal layer 60 and the plug layer 64 are provided above the interlayer insulating film 38 outside the contact hole 54.

[0149] The barrier metal layer 60 may be provided in contact with the upper surface of the interlayer insulating film 38 outside the contact hole 54. The plug layer 64 may be provided in contact with the second barrier metal portion 62 above the interlayer insulating film 38 outside the contact hole 54. However, only the barrier metal layer 60 may be provided outside the contact hole 54, and the plug layer 64 may be formed only inside the contact hole 54. By forming the barrier metal layer 60 and the plug layer 64 on the interlayer insulating film 38 as well, the reliability during mounting such as wire bonding and resin sealing can be improved. Further, the barrier metal layer 60 may not have the first barrier metal portion 61 formed either outside or inside the contact hole 54, and a metal film 67 may be formed between the barrier metal layer 60 and the interlayer insulating film 38. As an example, the barrier metal layer 60 may not have the first barrier metal portion 61 provided, and only the second barrier metal portion 62 may be provided inside and outside the contact hole 54, and the plug layer 64 may be provided only inside the contact hole 54.

[0150] FIG. 7B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of this example is the XZ plane passing through the contact region 15 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is different from the embodiment of FIG. 3B in that the barrier metal layer 60 and the plug layer 64 are provided above the interlayer insulating film 38 outside the contact hole 54. Also in the embodiments of FIGS. 7A and 7B, since the semiconductor device 100 includes the oxide layer 66, the barrier property during the film formation of the plug layer 64 can be ensured. Further, the first barrier metal portion 61 or / and the metal film 67 are removed or thinned by etching in the process of forming the oxide layer 66, so that the influence of the hydrogen storage effect can be suppressed and the hydrogen termination of the dangling bond of the MOS gate structure can be promoted. Thereby, the variation of the threshold voltage can be suppressed.

[0151] FIG. 8A is an enlarged cross-sectional view of the semiconductor device 100. In this example, an enlarged cross-sectional view in the vicinity of the contact hole 54 is shown. The cross-section of this example is an XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is different from the embodiment of FIG. 3A in that it includes a trench contact portion 65.

[0152] The trench contact portion 65 has a contact hole 54 and is provided to extend in the depth direction of the semiconductor substrate 10 from the front surface 21 of the semiconductor substrate 10. The lower end of the trench contact portion 65 of this example is shallower than the lower end of the emitter region 12. The lower end of the trench contact portion 65 may be deeper than the lower end of the emitter region 12. The lower end of the trench contact portion 65 of this example is shallower than the upper end of the gate conductive portion 44. The lower end of the trench contact portion 65 may be deeper than the upper end of the gate conductive portion 44.

[0153] The barrier metal layer 60 may have a first barrier metal portion 61 and a second barrier metal portion 62 in the trench contact portion 65. However, the first barrier metal portion 61 may be removed and only the second barrier metal portion 62 may be provided. The first barrier metal portion 61 is provided in contact with the side wall of the interlayer insulating film 38. The first barrier metal portion 61 may not be provided below the front surface 21. The first alloy layer 63 is provided in contact with the side wall and the upper surface of the semiconductor substrate 10 in the trench contact portion 65.

[0154] The oxide layer 66 is in contact with the first alloy layer 63. The oxide layer 66 is provided laminated with the first alloy layer 63. The oxide layer 66 is provided on the upper surface and the side surface of the first alloy layer 63 in the trench contact portion 65. The oxide layer 66 may be provided on the entire exposed surface of the first alloy layer 63 during the formation of the oxide layer 66.

[0155] The barrier metal layer 60 is provided in contact with an oxide layer 66 provided on the sidewall of the semiconductor substrate 10. The second barrier metal portion 62 of this example is provided in contact with the first barrier metal portion 61 and the oxide layer 66. The second barrier metal portion 62 is provided laminated with the first barrier metal portion 61 provided on the sidewall of the interlayer insulating film 38. The plug layer 64 is provided inside the second barrier metal portion 62 at the contact hole 54.

[0156] Note that the interlayer insulating film 38 of this example has a single insulating film, but may have a laminated structure in which a plurality of insulating films are laminated. The semiconductor device 100 of this example can increase the contact area with the semiconductor substrate 10 by providing the trench contact portion 65 and reduce the contact resistance. By providing the trench contact portion 65 in the transistor portion 70, hole extraction can be facilitated and latch-up can be suppressed.

[0157] FIG. 8B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section of this example is different from the cross-section of FIG. 8A at the point where it passes through the contact region 15 on the front surface 21. In this example, points different from FIG. 8A will be particularly described.

[0158] The oxide layer 66 is provided above the first conductivity type region 161 and is not provided above the second conductivity type region 162. That is, the oxide layer 66 does not have to be provided above the contact region 15. The oxide layer 66 may be selectively removed above the second conductivity type region 162 after being formed above the first conductivity type region 161 and the second conductivity type region 162. The oxide layer 66 may be formed only above the first conductivity type region 161 by using a mask and does not have to be formed above the second conductivity type region 162.

[0159] The semiconductor device 100 of this example can improve hole extraction and make it easier to suppress latch-up by removing the oxide layer 66 above the contact region 15. The semiconductor device 100 can reduce the damage during the formation of the plug layer 64 by providing the oxide layer 66 above the emitter region 12.

[0160] In this example, in the semiconductor device 100 including the trench contact portion 65, the oxide layer 66 is omitted above the p-type region 162. Similarly, in the semiconductor device 100 not including the trench contact portion 65, the oxide layer 66 may be omitted. That is, the oxide layer 66 may be omitted in any of the embodiments of FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, and 7B. Further, in this example, the oxide layer 66 above the p-type region 162 is omitted, but the oxide layer 66 above the n-type region 161 may be omitted. Also, in this example, the thickness of the oxide layer 66 may be the same or different above the n-type region 161 and above the p-type region 162.

[0161] FIG. 9A shows an example of the c-c' cross section in FIG. 1A or FIG. 2B. The c-c' cross section is a YZ plane passing through the active region inter-gate wiring 131. The active region inter-gate wiring 131 in this example includes a gate metal layer 50 and a connection portion 25. The gate metal layer 50 is an example of the front-side metal layer 53. The connection portion 25 is an example of the polycrystalline layer 165. The polycrystalline layer 165 is a polycrystalline layer provided above or inside the semiconductor substrate 10, and may be a semiconductor or a metal. The polycrystalline layer 165 in this example is a polysilicon layer. As another example, when the semiconductor substrate 10 is a silicon carbide substrate, the polycrystalline layer 165 may be a polycrystalline layer containing silicon carbide. When the semiconductor substrate 10 is a gallium nitride substrate, the polycrystalline layer 165 may be a polycrystalline layer containing gallium nitride. When the semiconductor substrate 10 is a diamond substrate, the polycrystalline layer 165 may be a polycrystalline layer containing diamond. A coating layer 68 such as polyimide may be provided above the active region inter-gate wiring 131.

[0162] The polycrystalline layer 165 may be provided above the semiconductor substrate 10 via the insulating film 26. The polycrystalline layer 165 is electrically connected to the gate conductive portion 44. Note that the polycrystalline layer 165 may be omitted, and only the front-side metal layer 53 may function as the inter-active-region gate wiring 131. Further, the front-side metal layer 53 above the polycrystalline layer 165 may be omitted, and only the polycrystalline layer 165 may function as the inter-active-region gate wiring 131. In this example, the cross-section of the inter-active-region gate wiring 131 has been described, but the front-side metal layer 53 and the polycrystalline layer 165 may be similarly provided for the outer peripheral gate wiring 130.

[0163] The front-side metal layer 53 is provided above the semiconductor substrate 10. A part of the front-side metal layer 53 may be provided to overlap with the polycrystalline layer 165 in the depth direction of the semiconductor substrate 10. The front-side metal layer 53 in this example is electrically connected to the polycrystalline layer 165 through the contact hole 55 provided above the polycrystalline layer 165. The front-side metal layer 53 may be formed of the same material as the emitter electrode 52 or may be a different material from the emitter electrode 52.

[0164] The contact hole 55 may be provided with a barrier metal layer 60, a first alloy layer 63, a plug layer 64, and an oxide layer 66. The contact hole 55 may be provided with a barrier metal layer 60, a first alloy layer 63, a plug layer 64, and an oxide layer 66 as disclosed in any of the embodiments of FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, or 8A. The contact hole 55 may be provided with a metal film 67 as disclosed in any of the embodiments of FIGS. 4A, 4B, 5A, or 5B. The contact hole 55 may not be provided with the oxide layer 66 as disclosed in the embodiment of FIG. 8B.

[0165] The film thickness of the oxide layer 66 may be thinner above the polycrystalline layer 165 than above the semiconductor substrate 10 and the first alloy layer 63 on the mesa portions 71, 81, 91. The oxide layer 66 may be omitted in the contact hole 55 provided above the polycrystalline layer 165. The film thickness of the oxide layer 66 may be thicker above the polycrystalline layer 165 than above the semiconductor substrate 10 and the first alloy layer 63 on the mesa portions 71, 81, 91. The oxide layer 66 may be provided in the contact hole 55 provided above the polycrystalline layer 165 and may be omitted above the semiconductor substrate 10 and the first alloy layer 63 on the mesa portions 71, 81, 91. By changing the film thickness of the oxide layer 66 above the polycrystalline layer 165, the magnitude of the gate resistance of the semiconductor device 100 can be adjusted. Also, depending on the magnitude of the gate resistance of the semiconductor device 100, whether or not to provide the oxide layer 66 above the polycrystalline layer 165 may be adjusted. In addition to the film thickness of the oxide layer 66, the magnitude of the gate resistance of the semiconductor device 100 may be adjusted by changing the area of the contact hole 55. Instead of the oxide layer 66, the magnitude of the gate resistance of the semiconductor device 100 may be adjusted by providing a resistance layer.

[0166] Note that the contact hole 55 may be provided in the gate wiring 131 between active regions. That is, the contact hole 55 may function as a contact hole for connecting the front-side metal layer 53 provided in the gate wiring 131 between active regions and the polycrystalline layer 165. Also in the gate wiring 131 between active regions, the magnitude of the gate resistance may be adjusted according to the magnitude of the film thickness of the oxide layer 66, the presence or absence of the oxide layer 66, the presence or absence of the resistance layer, and the area of the contact hole 55.

[0167] FIG. 9B shows an example of the d-d' cross section in FIG. 1A or FIG. 2B. The d-d' cross section is the XZ plane passing through the dummy trench portion 30.

[0168] The polycrystalline layer 165 may be provided in the semiconductor substrate 10. The dummy conductive portion 34 in this example is an example of the polycrystalline layer 165 provided in the semiconductor substrate 10. A contact hole 56 may be provided above the dummy conductive portion 34. The contact hole 56 functions as a contact hole for connecting the emitter electrode 52 and the polycrystalline layer 165. The emitter electrode 52 is an example of the front-side metal layer 53. In this example, the presence or absence of the oxide layer 66, the thickness of the oxide layer 66, and the area of the contact hole 56 may be appropriately adjusted.

[0169] A barrier metal layer 60, a first alloy layer 63, a plug layer 64, and an oxide layer 66 may be provided in the contact hole 56. The contact hole 56 may be provided with a barrier metal layer 60, a first alloy layer 63, a plug layer 64, and an oxide layer 66 as disclosed in any of the embodiments of FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, or 8A. A metal film 67 may be provided in the contact hole 56 as disclosed in any of the embodiments of FIGS. 4A, 4B, 5A, or 5B. The oxide layer 66 may not be provided in the contact hole 56 as disclosed in the embodiment of FIG. 8B. In FIGS. 1A, 2B, 9A, and 9B, the gate conductive portion 44 and the front-side metal layer 53 are connected via the connection portion 25 and the contact hole 55, and the dummy conductive portion 34 and the emitter electrode 52 are connected via the contact hole 56. The gate conductive portion 44 and the front-side metal layer 53 may be connected via the contact hole 55, and the dummy conductive portion 34 and the emitter electrode 52 may be connected via the connection portion 25 and the contact hole 56.

[0170] FIG. 10A shows an example of a top view of a semiconductor device 100 including a temperature sense portion 180. The semiconductor device 100 in this example includes a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118.

[0171] The front-side metal layer 53 may include a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118. The front-side metal layer 53 may be electrically connected to a conductive member such as a lead frame. The front-side metal layer 53 may be electrically connected to an external electrode of the semiconductor device 100 by wire bonding or the like. Note that the number and position of the front-side metal layers 53 are not limited to this example.

[0172] The sense electrode 114 is electrically connected to a current sense portion 115 provided below the sense electrode 114. The sense electrode 114 detects the current flowing through the current sense portion 115. The current sense portion 115 detects the current flowing through the transistor portion 70. The current sense portion 115 has a structure corresponding to the transistor portion 70, simulates the operation of the transistor portion 70, and a current proportional to the current flowing through the transistor portion 70 flows therethrough. By using the current sense portion 115, the current flowing through the transistor portion 70 can be monitored.

[0173] The temperature sense portion 180 is provided on the upper part or inside of the semiconductor substrate 10. In this example, the temperature sense portion 180 is provided on the well region 17 between the transistor portions 70 at the center of the semiconductor device 100. The temperature sense portion 180 detects the temperature of the active portion 120. The temperature sense portion 180 may have a diode formed of single-crystalline or polycrystalline silicon. The temperature sense portion 180 is used to detect the temperature of the semiconductor device 100 and protect the semiconductor chip from overheating. The temperature sense portion 180 is connected to a constant current source. When the temperature of the semiconductor device 100 changes, the forward voltage of the current flowing through the temperature sense portion 180 changes. The semiconductor device 100 can detect the temperature based on the change in the forward voltage of the temperature sense portion 180. The temperature sense portion 180 has a longitudinal direction in the Y-axis direction and a short-side direction in the X-axis direction, but is not limited thereto.

[0174] The anode pad 116 is electrically connected to the anode region of the temperature sensing unit 180. The anode pad 116 is electrically connected to the anode region of the temperature sensing unit 180 by the anode wiring 117.

[0175] The cathode pad 118 is electrically connected to the cathode region of the temperature sensing unit 180. The cathode pad 118 is electrically connected to the cathode region of the temperature sensing unit 180 by the cathode wiring 119.

[0176] FIG. 10B is an example of an enlarged cross-sectional view of the temperature sensing unit 180. The temperature sensing unit 180 in this example has the contact hole 58, but the structure of any contact hole in other embodiments may be applied.

[0177] The temperature sensing unit 180 has a diode provided on the semiconductor substrate 10. The temperature sensing unit 180 detects the temperature of the semiconductor device 100 by utilizing the fact that the current-voltage characteristics of the diode change according to the temperature. The temperature sensing unit 180 is disposed above the semiconductor substrate 10 via the interlayer insulating film 184. The interlayer insulating film 184 may be an HTO film. The temperature sensing unit 180 may be provided above the well region 17. The temperature sensing unit 180 in this example has a cathode region 181, an anode region 182, an interlayer insulating film 184, a cathode electrode 186, and an anode electrode 187.

[0178] The cathode region 181 and the anode region 182 constitute a PN diode. For example, the cathode region 181 is formed of an N-type semiconductor and functions as the cathode of the PN diode. The anode region 182 is formed of a P-type semiconductor and functions as the anode of the PN diode. The cathode region 181 and the anode region 182 are provided on the interlayer insulating film 184. The materials of the cathode region 181 and the anode region 182 may be polysilicon.

[0179] The cathode region 181 and the anode region 182 are an example of the polycrystalline layer 165. That is, in the contact hole 58, an oxide layer 66 may or may not be provided above the cathode region 181 and the anode region 182. The oxide layer 66 may be provided only above either the cathode region 181 or the anode region 182. For example, the oxide layer 66 may be provided above the cathode region 181, and the oxide layer 66 may not be provided above the anode region 182. Conversely, the oxide layer 66 may be provided above the anode region 182, and the oxide layer 66 may not be provided above the cathode region 181. Whether to form the oxide layer 66 may be determined in consideration of the resistance so that the stability of the temperature sense unit 180 is not impaired.

[0180] The cathode electrode 186 is electrically connected to the cathode region 181 via the contact hole 58. The cathode electrode 186 is an example of the front-side metal layer 53. That is, the cathode electrode 186 may be formed of the same material as the emitter electrode 52. The cathode electrode 186 is electrically connected to the cathode pad 118 by the cathode wiring 119.

[0181] The anode electrode 187 is electrically connected to the anode region 182 via the contact hole 58. The anode electrode 187 is an example of the front-side metal layer 53. That is, the anode electrode 187 may be formed of the same material as the emitter electrode 52. The anode electrode 187 is electrically connected to the anode pad 116 by the anode wiring 117.

[0182] The interlayer insulating film 38 is provided on the upper surfaces of the cathode region 181 and the anode region 182. Contact holes 58 may be formed in the interlayer insulating film 38 of the temperature sense unit 180.

[0183] Below the temperature sensing section 180, element regions such as the transistor section 70 and the diode section 80 may be provided. Below the temperature sensing section 180 of this example, a collector region 22 is provided. That is, the temperature sensing section 180 of this example is provided in the transistor section 70. However, the temperature sensing section 180 may be provided in the diode section 80, or may be provided in a region away from the active section 120 or in the vicinity of the edge termination structure section 140. Therefore, a high-concentration region such as the collector region 22 may not be formed below the temperature sensing section 180.

[0184] FIG. 11 is a flowchart showing an example of the manufacturing process of the semiconductor device 100. In step S100, an element structure on the front surface 21 side of the semiconductor device 100 is formed. In step S100, the process of forming the dummy trench portion 30 and the gate trench portion 40 may be included as the element structure on the front surface 21 side. In step S100, the process of forming the base region 14, the emitter region 12, the contact region 15, etc. by ion implantation into the semiconductor substrate 10 may be included as the element structure on the front surface 21 side.

[0185] In step S102, an interlayer insulating film 38 is formed above the semiconductor substrate 10. The interlayer insulating film 38 may be formed by laminating a plurality of insulating films. In step S104, contact holes are formed by etching the interlayer insulating film 38. In step S104, contact holes such as contact hole 54, contact hole 55, contact hole 56, and contact hole 58 may be formed in the interlayer insulating film 38.

[0186] In step S106, an initial metal film for forming the first alloy layer 63 is formed. In this example, in the contact hole 54, a predetermined initial metal film is formed on the sidewalls of the interlayer insulating film 38 and the upper surface of the semiconductor substrate 10. That is, the initial metal film is formed so as to be in contact with the interlayer insulating film 38 and the semiconductor substrate 10. The initial metal film may be composed of a first metal. The first alloy layer 63 may be formed by processing the initial metal film. For example, the initial metal film is a Ti film formed by sputtering. The film thickness of the initial metal film may be 1 nm or more and 100 nm or less. Further, the first barrier metal portion 61 and the oxide layer 66 may be formed by processing the initial metal film.

[0187] In step S108, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. Thereby, the first alloy layer 63 is formed on the upper surface of the semiconductor substrate 10. In this way, the initial metal film in contact with the semiconductor substrate 10 becomes the first alloy layer 63. The first alloy layer 63 in this example is a titanium silicide film formed by annealing the Ti film on the upper surface of the semiconductor substrate 10. The annealing temperature may be 300 degrees or more and 1100 degrees or less. The annealing for forming the first alloy layer 63 may be performed before forming the second barrier metal portion 62. Further, in step S108, the first barrier metal portion 61 may be formed on the sidewalls of the interlayer insulating film 38. The initial metal film in contact with the interlayer insulating film 38 may become the first barrier metal portion 61. The first barrier metal portion 61 in this example is a dense TiN film formed by annealing the Ti film on the sidewalls of the interlayer insulating film 38. In this example, the case of forming a TiN film as the first barrier metal portion 61 is described, but when the material of the first barrier metal portion 61 is not TiN, an initial metal film of a different material may be formed. Note that there may be a metal film 67 of the first metal remaining without reacting between the interlayer insulating film 38 and the first barrier metal portion 61.

[0188] In step S110, after forming the first alloy layer 63 on the upper surface of the semiconductor substrate 10, an oxide layer 66 is formed. The oxide layer 66 may be formed before forming the second barrier metal portion 62. The oxide layer 66 is formed on the upper surface of the first alloy layer 63 at the contact hole 54. The oxide layer 66 may be formed on the entire exposed surface of the first alloy layer 63 at the contact hole 54. The step of forming the oxide layer 66 may include a step of wet etching, a step of dry etching, a step of annealing, and a step of deposition. A specific method for forming the oxide layer 66 will be described later.

[0189] When the oxide layer 66 is formed by etching, in the step of forming the oxide layer 66, the first barrier metal portion 61 and / or the metal film 67 may be etched. Thereby, the first barrier metal portion 61 and / or the metal film 67 may be adjusted to have a predetermined film thickness. The first barrier metal portion 61 may be etched to have a film thickness of 1 nm or more and 10 nm or less. The first barrier metal portion 61 and / or the metal film 67 may be entirely removed by etching.

[0190] In step S112, the second barrier metal portion 62 is formed. The second barrier metal portion 62 may be formed by laminating on the oxide layer 66 below the contact hole 54. When the oxide layer 66 is not formed, the second barrier metal portion 62 may be formed by laminating on the first alloy layer 63. The second barrier metal portion 62 may be formed by laminating on the first barrier metal portion 61 and / or the metal film 67 on the side wall of the contact hole 54. When the first barrier metal portion 61 and / or the metal film 67 are entirely removed, the second barrier metal portion 62 may be formed in contact with the interlayer insulating film 38 on the side wall of the contact hole 54. The second barrier metal portion 62 in this example is a TiN film formed by sputtering.

[0191] In step S114, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. The annealing conditions in step S114 may be the same as or different from the annealing conditions in step S108. The annealing in this example is performed after the second barrier metal portion 62 is formed. The annealing of the second barrier metal portion 62 may be performed before the plug layer 64 is formed.

[0192] In step S116, the plug layer 64 is formed. In this example, tungsten is formed so as to fill the inside of the contact hole 54 by a CVD (Chemical Vapor Deposition) method.

[0193] The oxide layer 66 in this example is provided on the upper surface of the first alloy layer 63 and may function as a metal diffusion prevention layer when the plug layer 64 is formed. By providing the oxide layer 66, when the plug layer 64 is formed by CVD, it is possible to prevent the plug layer 64 from invading the first alloy layer 63.

[0194] In step S118, the plug layer 64 is etched back. Thereby, unnecessary tungsten films outside the contact hole 54 may be removed. The etch back may be performed by dry etching or CMP (Chemical Mechanical Polishing). When the tungsten film is removed, the metal film 67, the first barrier metal portion 61, and the second barrier metal portion 62 on the interlayer insulating film 38 may also be removed. The metal film 67, the first barrier metal portion 61, and the second barrier metal portion 62 on the interlayer insulating film 38 may be removed in a process different from the etch back of the plug layer 64. The metal film 67, the first barrier metal portion 61, and the second barrier metal portion 62 on the interlayer insulating film 38 may not be removed. Note that step S118 may be omitted and the plug layer 64 may be left outside the contact hole 54.

[0195] After step S118, the front-side metal layer 53 may be formed above the semiconductor substrate 10. Also, after step S118, members on the back surface 23 side such as the collector electrode 24 may be formed. After step S118, the back-side lifetime control region 151 and the front-side lifetime control region 152 may be formed.

[0196] FIG. 12A shows an example of the formation process of the oxide layer 66. In this example, a method of forming the oxide layer 66 by etching will be described. Steps S1100 to S1104 are an example of step S110 in FIG. 11.

[0197] In step S1100, a mask is formed above the semiconductor substrate 10. For example, a mask is formed on the region to be protected from etching. A mask may be formed on one of the first conductivity type region 161 or the second conductivity type region 162, and it is not necessary to form a mask on the other. A mask may be formed above the contact region 15, and it is not necessary to form a mask above the emitter region 12. When the oxide layer 66 is not formed above the polycrystalline layer 165, a mask may be formed on the contact hole 58 above the polycrystalline layer 165.

[0198] In step S1102, the upper surface of the first alloy layer 63 is etched. In this example, the upper surface of the first alloy layer 63 is wet-etched, but dry etching may also be used. The step of wet-etching the upper surface of the first alloy layer 63 may include the step of wet-etching using hydrogen peroxide. By wet-etching, the upper surface of the first alloy layer 63 can be etched while being oxidized. By oxidizing the upper surface of the first alloy layer 63, the oxide layer 66 may be formed. The chemical solution for wet-etching may be hydrogen peroxide, may be buffered hydrofluoric acid, or may be other chemical solutions such as hydrofluoric acid or ammonium hydroxide. In step S1102, the first barrier metal portion 61 may be etched.

[0199] In step S1104, the mask provided above the semiconductor substrate 10 is removed. Note that steps S1100 and S1104 may be omitted. Thereafter, the process proceeds to step S112 in FIG. 11, and the second barrier metal portion 62 may be formed.

[0200] FIG. 12B shows a modification of the process for forming the oxide layer 66. In this example, a method of forming the oxide layer 66 by annealing will be described. Steps S1110 to S1114 are an example of step S110 in FIG. 11. In this example, it is different from the embodiment of FIG. 12A in that step S1112 is the annealing step. In this example, the differences from FIG. 12A will be particularly described.

[0201] In step S1112, the semiconductor substrate 10 is annealed in an oxygen atmosphere. As a result, an oxide layer 66 is formed in a region where no mask is formed on the upper surface of the first alloy layer 63. On the other hand, the oxide layer 66 is not formed in a region where the mask is formed on the upper surface of the first alloy layer 63. Note that steps S1110 and S1114 may also be omitted when the oxide layer 66 is formed by annealing.

[0202] FIG. 12C shows a modification of the process for forming the oxide layer 66. In this example, a method of forming the oxide layer 66 by deposition will be described. Steps S1120 to S1124 are an example of step S110 in FIG. 11. In this example, it is different from the embodiment of FIG. 12A in that step S1122 is the deposition step. In this example, the differences from FIG. 12A will be particularly described.

[0203] In step S1122, an oxide layer 66 is deposited on the semiconductor substrate 10 by a CVD method, a sputtering method, or the like. The oxide layer 66 may be, for example, an LTO (Low Temperature Oxide) film or an HTO film. As a result, on the upper surface of the first alloy layer 63, the oxide layer 66 is formed on the region where no mask is formed. On the other hand, on the upper surface of the mask formed on the upper surface of the first alloy layer 63, the oxide layer 66 is formed on the upper surface of the mask. Note that the oxide layer 66 on the upper surface of the mask may be removed together with the mask when removing the mask in step S1124. Even in the case of forming by deposition, steps S1120 and S1124 may be omitted.

[0204] FIG. 13 is a flowchart showing a manufacturing process of a semiconductor device according to a comparative example. Steps S500 to S504 may be the same as steps S100 to S104 in FIG. 11, respectively.

[0205] In step S506, a Ti film and a TiN film are formed inside the contact hole. In step S508, by annealing the semiconductor substrate 10 in a nitrogen atmosphere, a dense TiN film is formed from the Ti film on the sidewall of the interlayer insulating film 38. On the upper surface of the semiconductor substrate 10, a titanium silicide layer is formed.

[0206] In step S510, a plug layer 64 is formed inside the contact hole. In step S512, the plug layer 64 is etched back.

[0207] Thus, in the semiconductor device of the comparative example, the Ti film and the TiN film are formed together, and the oxide layer 66 is not formed on the upper surface of the first alloy layer 63. In addition, a part of the Ti film may not be nitrided and Ti having a hydrogen storage effect may remain.

[0208] On the other hand, the semiconductor device 100 can protect the first alloy layer 63 from damage during the film formation of the plug layer 64 by forming an oxide layer 66 on the upper surface of the first alloy layer 63. Further, unreacted first metal having a hydrogen storage effect can be removed, and defects around the MOS gate structure can be terminated with hydrogen to suppress fluctuations in the threshold voltage.

[0209] As described above, the present invention has been described using embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0210] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly stated as "earlier" or "preceding" etc., and can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if it is described using "first," "next," etc. for convenience, it does not mean that it is essential to implement in this order.

Description of Reference Numerals

[0211] 10 ··· semiconductor substrate, 12 ··· emitter region, 14 ··· base region, 15 ··· contact region, 16 ··· storage region, 17 ··· well region, 18 ··· drift region, 20 ··· buffer region, 21 ··· front surface, 22 ··· collector region, 23 ··· back surface, 24 ··· collector electrode, 25 ··· connection part, 26 ··· insulating film, 30 ··· dummy trench part, 31 ··· extension part, 32 ··· dummy insulating film, 33 ··· connection part, 34 ··· dummy conductive part, 38 ··· interlayer insulating film, 40 ··· gate trench part, 41 ··· extension part, 42 ··· gate insulating film, 43 ··· connection part, 44 ··· gate conductive part, 50 ··· gate metal layer, 52 ··· emitter electrode, 53 ··· front surface side metal layer, 54 ··· contact hole, 55 ··· contact hole, 56 ··· contact hole, 58 ··· contact hole, 60 ··· barrier metal layer, 61 ··· first barrier metal part, 62 ··· second barrier metal part, 63 ··· first alloy layer, 64 ··· plug layer, 65 ··· trench contact part, 66 ··· oxide layer, 67 ··· metal film, 68 ··· coating layer, 70 ··· transistor part, 71 ··· mesa part, 80 ··· diode part, 81 ··· mesa part, 82 ··· cathode region, 85 ··· extension region, 90 ··· boundary part, 91 ··· mesa part, 100 ··· semiconductor device, 102 ··· side edge, 112 ··· gate pad, 114 ··· sense electrode, 115 ··· current sense part, 116 ··· anode pad, 117 ··· anode wiring, 118 ··· cathode pad, 119 ··· cathode wiring, 120 ··· active part, 130 ··· outer peripheral gate wiring, 131 ··· gate wiring between active parts, 140 ··· edge termination structure part, 151 ··· back surface side lifetime control region, 152 ··· front surface side lifetime control region, 161 ··· first conductivity type region, 162 ··· second conductivity type region, 165 ··· polycrystalline layer, 180 ··· temperature sense part, 181 ··· cathode region, 182 ··· anode region, 184 ··· interlayer insulating film, 186 ··· cathode electrode, 187 ··· anode electrode

Claims

1. A semiconductor substrate, An interlayer insulating film having contact holes and provided above the semiconductor substrate, A first alloy layer provided on the upper surface of the semiconductor substrate below the contact holes, An oxide layer provided on the upper surface of the first alloy layer in the contact holes, A conductive barrier metal layer provided above the oxide layer in the contact holes, A plug layer provided above the barrier metal layer in the contact holes A semiconductor device comprising the same.

2. The oxide layer is provided in contact with the first alloy layer and the barrier metal layer The semiconductor device according to claim 1.

3. The first alloy layer and the barrier metal layer contain a predetermined first metal, The oxide layer contains the first metal The semiconductor device according to claim 1.

4. A first conductivity type drift region provided in the semiconductor substrate, A first conductivity type first conductivity type region provided on the front surface of the semiconductor substrate and having a higher doping concentration than the drift region, A second conductivity type second conductivity type region provided on the front surface of the semiconductor substrate, Comprising The film thickness of the oxide layer is thinner above the second conductivity type region than above the first conductivity type region The semiconductor device according to claim 1.

5. The oxide layer is not provided above the second conductivity type region The semiconductor device according to claim 4.

6. A polycrystalline layer provided above the semiconductor substrate or in the semiconductor substrate, A front-side metal layer that is electrically connected to the polycrystalline layer through the contact hole provided above the polycrystalline layer comprising The semiconductor device according to claim 1.

7. The barrier metal layer is provided on the upper surface of the oxide layer and the side wall of the interlayer insulating film in the contact hole. The semiconductor device according to any one of claims 1 to 6.

8. The barrier metal layer A conductive first barrier metal part provided on the side wall of the interlayer insulating film, In the contact hole, a conductive second barrier metal part laminated on the first barrier metal part, comprising The first barrier metal part is denser than the second barrier metal part. The semiconductor device according to claim 7.

9. The second barrier metal part is provided in contact with the first barrier metal part and the oxide layer. The semiconductor device according to claim 8.

10. Having the contact hole and comprising a trench contact part provided to extend in the depth direction of the semiconductor substrate from the front surface of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 6.

11. The first alloy layer is provided in contact with the side wall and the upper surface of the semiconductor substrate in the trench contact part. The oxide layer is provided in contact with the upper surface and the side surface of the first alloy layer in the trench contact part. The semiconductor device according to claim 10.

12. The barrier metal layer is provided in contact with the oxide layer provided on the side wall of the semiconductor substrate. The semiconductor device according to claim 10.

13. Comprising a transistor section and a diode section The semiconductor device according to any one of claims 1 to 6.

14. Comprising a front surface side lifetime control region provided on the front surface side of the semiconductor substrate, closer to the front surface than the center of the semiconductor substrate, in the depth direction of the semiconductor substrate. The semiconductor device according to claim 13.

15. The front surface side lifetime control region is formed by irradiating the semiconductor substrate with a particle beam. The semiconductor device according to claim 14.

16. Comprising a back surface side metal layer provided in contact with the back surface of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 6.

17. Forming an interlayer insulating film having contact holes above the semiconductor substrate; Forming a first alloy layer on the upper surface of the semiconductor substrate below the contact hole; Forming an oxide layer on the upper surface of the first alloy layer in the contact hole; Forming a conductive barrier metal layer above the oxide layer in the contact hole; Forming a plug layer above the barrier metal layer in the contact hole; A method for manufacturing a semiconductor device comprising:

18. The step of forming the oxide layer includes the step of wet etching the upper surface of the first alloy layer after forming the first alloy layer on the upper surface of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 17.

19. The step of wet etching the upper surface of the first alloy layer includes the step of wet etching using hydrogen peroxide or buffered hydrofluoric acid. The method of manufacturing a semiconductor device according to claim 18.

20. The step of forming the oxide layer includes the step of annealing the semiconductor substrate in an oxygen atmosphere. The method of manufacturing a semiconductor device according to claim 17.

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