Wiring Substrate, Semiconductor Device, and Method for Manufacturing Wiring Substrate

Abstract

To provide a wiring board, a semiconductor device, and a method for manufacturing wiring board that can reduce warpage.SOLUTION: A wiring board has a first wiring structure including a plurality of first wiring layers and a plurality of first insulating layers mainly comprising a photosensitive resin, and an encapsulating resin layer mainly comprising a non-sensitive thermosetting resin laminated on the topmost first insulating layer, the first wiring layer on the topmost layer includes pads protruding from the first insulating layer on the topmost layer and the encapsulating resin layer exposes the top surface of the pad and covers at least a portion of the side surface of the pad and at least a portion of the side surface of the plurality of first insulating layers, and a semiconductor chip is mounted on top of the pad.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board.

Background Art

[0002] Conventionally, as a wiring board on which electronic components such as semiconductor chips are mounted, in order to increase the density of wiring patterns, a wiring board in which a plurality of wiring layers and insulating layers are alternately laminated by a build-up method is known. As this type of wiring board, a wiring board has been proposed in which a high-density wiring layer including an insulating layer made of a photosensitive resin is formed on a low-density wiring layer including an insulating layer made of a thermosetting resin (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above wiring board, warpage may occur due to the difference in the coefficient of thermal expansion between the insulating layer made of a thermosetting resin and the insulating layer made of a photosensitive resin.

[0005] An object of the present disclosure is to provide a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can reduce warpage.

Means for Solving the Problems

[0006] According to one embodiment of the present disclosure, there is provided a first wiring structure including a plurality of first wiring layers and a plurality of first insulating layers mainly composed of a photosensitive resin, and a sealing resin layer mainly composed of a non-photosensitive thermosetting resin laminated on the topmost first insulating layer. The topmost first wiring layer includes pads protruding from the topmost first insulating layer. The sealing resin layer exposes the upper surface of the pads and covers at least a part of the side surfaces of the pads and at least a part of the side surfaces of the plurality of first insulating layers. On the upper surface of the uppermost first insulating layer, a slit in which the encapsulation resin layer is embedded is formed. There is provided a wiring board on which a semiconductor chip is mounted on the pads.

Effects of the Invention

[0007] According to the present disclosure, warpage can be reduced.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Embodiments for Carrying Out the Invention

[0009] Hereinafter, the embodiments will be specifically described with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant descriptions may be omitted. In the present disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are taken as directions perpendicular to each other. The plane including the X1-X2 direction and the Y1-Y2 direction is referred to as the XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is referred to as the YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is referred to as the ZX plane. For convenience, the Z1-Z2 direction is taken as the vertical direction, the Z1 side is the upper side, and the Z2 side is the lower side. In addition, a plan view means viewing an object from the Z1 side, and a planar shape means the shape of an object viewed from the Z1 side. However, the wiring board and the semiconductor device can be used in an upside-down state or arranged at an arbitrary angle.

[0010] (Reference Example) First, the reference example will be described. FIG. 1 is a diagram showing the layout of a wiring board according to the reference example. FIG. 2 is a cross-sectional view showing the wiring board according to the reference example.

[0011] As shown in FIGS. 1 and 2, the wiring board 9 according to the reference example includes a second wiring structure 1L, a first wiring structure 1H laminated on the second wiring structure 1L, and a sealing resin layer 24 laminated on the first wiring structure 1H. The planar shape of the wiring board 9 can be, for example, a square shape or a rectangular shape.

[0012] The wiring board 9 has a first semiconductor chip mounting region 51, a second semiconductor chip mounting region 52, a third semiconductor chip mounting region 53, a fourth semiconductor chip mounting region 54, and a fifth semiconductor chip mounting region 55. The first semiconductor chip mounting region 51, the second semiconductor chip mounting region 52, the third semiconductor chip mounting region 53, the fourth semiconductor chip mounting region 54, and the fifth semiconductor chip mounting region 55 have a rectangular planar shape. In a plan view, the first semiconductor chip mounting region 51 is larger than the second semiconductor chip mounting region 52, the third semiconductor chip mounting region 53, the fourth semiconductor chip mounting region 54, and the fifth semiconductor chip mounting region 55. In a plan view, the second semiconductor chip mounting region 52, the third semiconductor chip mounting region 53, the fourth semiconductor chip mounting region 54, and the fifth semiconductor chip mounting region 55 have common dimensions with each other.

[0013] The first semiconductor chip mounting region 51 is disposed at the center of the wiring board 9 in a plan view. The second semiconductor chip mounting region 52 and the third semiconductor chip mounting region 53 are disposed on the X1 side of the first semiconductor chip mounting region 51, and the fourth semiconductor chip mounting region 54 and the fifth semiconductor chip mounting region 55 are disposed on the X2 side of the first semiconductor chip mounting region 51. The third semiconductor chip mounting region 53 is disposed on the Y2 side of the second semiconductor chip mounting region 52, and the fifth semiconductor chip mounting region 55 is disposed on the Y2 side of the fourth semiconductor chip mounting region 54.

[0014] One semiconductor chip is mounted on each of the first semiconductor chip mounting region 51, the second semiconductor chip mounting region 52, the third semiconductor chip mounting region 53, the fourth semiconductor chip mounting region 54, and the fifth semiconductor chip mounting region 55.

[0015] The wiring board 9 has a first capacitor mounting area 61, a second capacitor mounting area 62, a third capacitor mounting area 63, and a fourth capacitor mounting area 64. The first capacitor mounting area 61, the second capacitor mounting area 62, the third capacitor mounting area 63, and the fourth capacitor mounting area 64 have a rectangular planar shape.

[0016] The first capacitor mounting area 61 is disposed on the Y1 side of the first semiconductor chip mounting area 51, the second semiconductor chip mounting area 52, and the fourth semiconductor chip mounting area 54. In the X1-X2 direction, the dimension of the first capacitor mounting area 61 is larger than the sum of the dimensions of the first semiconductor chip mounting area 51, the second semiconductor chip mounting area 52, and the fourth semiconductor chip mounting area 54. A plurality of capacitors are mounted on the first capacitor mounting area 61.

[0017] The second capacitor mounting area 62 is disposed on the Y2 side of the second semiconductor chip mounting area 52. In the X1-X2 direction, the dimension of the second capacitor mounting area 62 is approximately the same as the dimension of the first semiconductor chip mounting area 51. A plurality of capacitors are mounted on the second capacitor mounting area 62.

[0018] The third capacitor mounting area 63 is disposed on the X1 side of the second capacitor mounting area 62 and on the Y2 side of the third semiconductor chip mounting area 53. The fourth capacitor mounting area 64 is disposed on the X2 side of the second capacitor mounting area 62 and on the Y2 side of the fifth semiconductor chip mounting area 55. Two capacitors are mounted on each of the third capacitor mounting area 63 and the fourth capacitor mounting area 64.

[0019] The second wiring structure 1L is a low-density wiring layer in which a wiring layer having a lower wiring density than the first wiring structure 1H is formed, and includes a wiring layer 11, an insulating layer 12, and a wiring layer 13. In contrast, the first wiring structure 1H is a high-density wiring layer in which a wiring layer having a higher wiring density than the second wiring structure 1L is formed, and includes a wiring layer 14, an insulating layer 15, a wiring layer 16, an insulating layer 17, a wiring layer 18, an insulating layer 19, and a wiring layer 21.

[0020] The wiring layer 11 is the lowermost wiring layer exposed on the lower surface side of the insulating layer 12, and its upper surface and side surfaces are covered by the insulating layer 12. The lower surface of the wiring layer 11 may be flush with the lower surface 12b of the insulating layer 12, for example. The lower surface of the wiring layer 11 may be exposed at a position recessed from the lower surface 12b of the insulating layer 12 toward the wiring layer 13 side, and a part of the side surface and the lower surface of the wiring layer 11 may protrude downward from the lower surface 12b of the insulating layer 12.

[0021] The wiring layer 11 is, for example, a pad having a circular planar shape, but may include a wiring pattern. A surface treatment layer 110 may be formed on the lower surface of the wiring layer 11.

[0022] The insulating layer 12 covers the upper surface and side surfaces of the wiring layer 11. The insulating layer 12 is mainly composed of a non-photosensitive thermosetting resin and has a reinforcing member 128. The upper surface 12a of the insulating layer 12 is a smooth surface (low roughness surface) with few irregularities. For example, the upper surface 12a of the insulating layer 12 is a polished surface. The upper surface 12a of the insulating layer 12 has a smaller surface roughness than, for example, the inner surface of the via hole 12x.

[0023] The wiring layer 13 is a via wiring embedded in the insulating layer 12. More specifically, the wiring layer 13 is a via wiring filled in a via hole 12x that penetrates the insulating layer 12 and exposes the upper surface of the wiring layer 11, and is electrically connected to the wiring layer 11.

[0024] The upper surface of the wiring layer 13, which is a via wiring, is exposed from the upper surface 12a of the insulating layer 12. The upper surface of the wiring layer 13 can be flush with the upper surface 12a of the insulating layer 12, for example. The upper surface of the wiring layer 13 is directly joined to the lower surface of the wiring layer 14. The lower surface of the wiring layer 13 is directly joined to the wiring layer 11 within the insulating layer 12. The upper end surface of the wiring layer 13 is a smooth surface (low roughness surface) with few irregularities, similar to the upper surface 12a of the insulating layer 12. For example, the upper end surface of the wiring layer 13 is a polished surface.

[0025] The wiring layer 14 is formed on the upper surface 12a of the insulating layer 12. The wiring layer 14 is formed directly on the upper surface 12a of the insulating layer 12 and includes wirings (wiring patterns and pads) that are electrically connected to the wiring layer 11 via the wiring layer 13. That is, a part of the lower surface of the wiring layer 14 is in contact with the upper surface of the wiring layer 13, and the two are electrically connected.

[0026] The insulating layer 15 is an insulating layer mainly composed of a photosensitive resin. The insulating layer 15 is formed on the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 14.

[0027] The wiring layer 16 is formed on one side (Z1 side) of the insulating layer 15 and is electrically connected to the wiring layer 14. The wiring layer 16 includes via wirings filled in via holes 15x that penetrate the insulating layer 15 and expose the upper surface of the wiring layer 14, and wiring patterns formed on the upper surface of the insulating layer 15.

[0028] The insulating layer 17 is an insulating layer mainly composed of a photosensitive resin. The insulating layer 17 is formed on one surface of the insulating layer 15 so as to cover the wiring layer 16.

[0029] The wiring layer 18 is formed on one side (Z1 side) of the insulating layer 17 and is electrically connected to the wiring layer 16. The wiring layer 18 includes via wirings filled in via holes 17x that penetrate the insulating layer 17 and expose the upper surface of the wiring layer 16, and wiring patterns formed on the upper surface of the insulating layer 17.

[0030] The insulating layer 19 is an insulating layer mainly composed of a photosensitive resin. The insulating layer 19 is formed on one surface of the insulating layer 17 so as to cover the wiring layer 18. In the first wiring structure 1H, the insulating layer 19 is the uppermost insulating layer.

[0031] The wiring layer 21 is formed on one side (Z1 side) of the insulating layer 19. In the first wiring structure 1H, the wiring layer 21 is the topmost wiring layer. The wiring layer 21 includes via wirings 22 filled in via holes 19x that penetrate the insulating layer 19 and expose the upper surface of the wiring layer 18, and conductive pads 23 protruding from the upper surface of the insulating layer 19. A surface treatment layer 210 similar to the surface treatment layer 110 may be formed on the upper surface of the pad 23.

[0032] The pads 23 are provided in the first semiconductor chip mounting region 51, the second semiconductor chip mounting region 52, the third semiconductor chip mounting region 53, the fourth semiconductor chip mounting region 54, the fifth semiconductor chip mounting region 55, the first capacitor mounting region 61, the second capacitor mounting region 62, the third capacitor mounting region 63, and the fourth capacitor mounting region 64.

[0033] The encapsulation resin layer 24 is laminated on the insulating layer 19, which is the topmost insulating layer in the first wiring structure 1H. The encapsulation resin layer 24 exposes the upper surface of the pad 23 and covers at least a part of the side surface of the pad 23.

[0034] As the material of the encapsulation resin layer 24, for example, a mold resin can be used. The mold resin is an insulating resin mainly composed of a non-photosensitive thermosetting resin that can be used in transfer molding methods, compression molding methods, injection molding methods, etc. For example, the thermal expansion coefficient of the encapsulation resin layer 24 is 20 ppm / K or less, and the Young's modulus of the encapsulation resin layer 24 is 1 GPa or more.

[0035] According to the reference example having such a configuration, it is possible to reduce warping compared to the case where the encapsulation resin layer 24 is not provided. Also, the thicker the encapsulation resin layer 24, the higher the effect of suppressing warping.

[0036] However, when the pad 23 is formed by the semi-additive method, if the thickness of the encapsulation resin layer 24 is increased, it becomes difficult to form the pad 23 with high precision without increasing the diameter of the pad 23. This is because the exposure accuracy decreases as the aspect ratio of the pad 23 increases. For example, it is difficult to form a pad 23 with an aspect ratio of 8 or more with high precision by the semi-additive method. Therefore, even according to the reference example, it may be difficult to sufficiently suppress warping.

[0037] Therefore, the inventors of the present application intensively studied a configuration that can further suppress warping without thickening the portion of the encapsulation resin layer 24 where the pad 23 is formed. As a result, it was found that by providing the encapsulation resin layer 24 so as to be in contact with at least a part of the side surface of the laminated structure of the insulating layers 15, 17, and 19, the volume of the encapsulation resin layer 24 included in the wiring substrate can be increased to further suppress warping. Based on such findings, the inventors of the present application conceived the following embodiments.

[0038] (First Embodiment) Next, the first embodiment will be described. The first embodiment relates to a wiring substrate.

[0039] [Structure of Wiring Substrate According to First Embodiment] FIG. 3 is a diagram showing the layout of the wiring substrate according to the first embodiment. FIG. 4 is a cross-sectional view showing the wiring substrate according to the first embodiment. As shown in FIGS. 3 and 4, the wiring substrate 1 according to the first embodiment, similar to the wiring substrate 9, has a second wiring structure 1L, a first wiring structure 1H laminated on the second wiring structure 1L, and an encapsulation resin layer 24 laminated on the first wiring structure 1H. The planar shape of the wiring substrate 1 can be, for example, a square shape or a rectangular shape. However, it is not limited thereto, and the wiring substrate 1 can have an arbitrary planar shape.

[0040] Like the wiring board 9, the wiring board 1 has a first semiconductor chip mounting region 51, a second semiconductor chip mounting region 52, a third semiconductor chip mounting region 53, a fourth semiconductor chip mounting region 54, and a fifth semiconductor chip mounting region 55. Like the wiring board 9, the wiring board 1 also has a first capacitor mounting region 61, a second capacitor mounting region 62, a third capacitor mounting region 63, and a fourth capacitor mounting region 64.

[0041] The second wiring structure 1L is a low-density wiring layer in which a wiring layer with a lower wiring density than the first wiring structure 1H is formed, and has a wiring layer 11, an insulating layer 12, and a wiring layer 13. In contrast, the first wiring structure 1H is a high-density wiring layer in which a wiring layer with a higher wiring density than the second wiring structure 1L is formed, and has a wiring layer 14, an insulating layer 15, a wiring layer 16, an insulating layer 17, a wiring layer 18, an insulating layer 19, and a wiring layer 21.

[0042] The wiring layer 11 is the lowermost wiring layer exposed on the lower surface side of the insulating layer 12, and its upper surface and side surfaces are covered by the insulating layer 12. The lower surface of the wiring layer 11 may be flush with, for example, the lower surface 12b of the insulating layer 12. The lower surface of the wiring layer 11 may be exposed at a position recessed from the lower surface 12b of the insulating layer 12 toward the wiring layer 13 side, and a part of the side surface and the lower surface of the wiring layer 11 may protrude downward from the lower surface 12b of the insulating layer 12.

[0043] The wiring layer 11 is, for example, a circular pad having a planar shape with a diameter of about 150 μm, but may include a wiring pattern. The interval between adjacent wiring layers 11 can be, for example, about 200 μm. As the material of the wiring layer 11, for example, copper (Cu) or the like can be used. The thickness of the wiring layer 11 can be, for example, about 10 μm to 20 μm. Note that the wiring layer 11 can be used as an external connection terminal (pad) for electrically connecting to other wiring boards. The wiring layer 11 may be used as an external connection terminal (pad) for connecting a chip capacitor or the like.

[0044] A surface treatment layer 110 may be formed on the lower surface of the wiring layer 11. Examples of the surface treatment layer 110 include an Au layer, a Ni / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), a Ni / Pd / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order), and the like. Further, an antioxidant treatment such as a water-soluble preflux (organic solderability preservative: OSP) treatment may be performed on the lower surface of the wiring layer 11.

[0045] The insulating layer 12 covers the upper surface and the side surfaces of the wiring layer 11. The insulating layer 12 is mainly composed of a non-photosensitive thermosetting resin and has a reinforcing member 128. The insulating layer 12 can be configured by impregnating the reinforcing member 128 with a non-photosensitive thermosetting resin. Here, "mainly composed of a non-photosensitive thermosetting resin" means that other components such as fillers may be contained in addition to the thermosetting resin.

[0046] Examples of the non-photosensitive thermosetting resin used for the insulating layer 12 include epoxy resins, imide resins, phenolic resins, cyanate resins, and the like. Examples of the reinforcing member 128 include woven fabrics and non-woven fabrics such as glass fibers, carbon fibers, and aramid fibers. Examples of the filler contained in the insulating layer 12 include silica (SiO2), kaolin (Al2Si2O5(OH ) 4), talc (Mg3Si4O 10 (OH ) 2), alumina (Al2O3), and the like. Further, these may be mixed. As the reinforcing member 128, for example, a glass cloth using a glass fiber bundle, a carbon fiber bundle, a polyester fiber bundle, a nylon (polyamide) fiber bundle, an aramid fiber bundle, or the like may be used.

[0047] The thickness T1 of the insulating layer 12 can be, for example, about 60 μm to 70 μm. The thermal expansion coefficient of the insulating layer 12 can be, for example, 5 ppm / K or more and 10 ppm / K or less. The thermal expansion coefficient of the insulating layer 12 can be adjusted to a predetermined value depending on, for example, the filler content, the composition of the insulating resin, and the like. The thermal expansion coefficient of the insulating layer 12 is lower than the thermal expansion coefficients of the insulating layers 15, 17, and 19.

[0048] The reinforcing member 128 is unevenly distributed in the insulating layer 12 on the side of the first wiring structure 1H (here, the upper side) from the center in the thickness direction of the insulating layer 12. Specifically, the reinforcing member 128 is disposed at a position offset toward the first wiring structure 1H side from the center in the thickness direction of the insulating layer 12. More specifically, in the insulating layer 12, the thickness of the resin layer (specifically, the thickness from the upper surface 12a of the insulating layer 12 to the reinforcing member 128) is set to be thinner than the thickness of the resin layer (specifically, the thickness from the reinforcing member 128 to the lower surface 12b of the insulating layer 12).

[0049] The upper surface 12a of the insulating layer 12 is a smooth surface (low roughness surface) with few irregularities. For example, the upper surface 12a of the insulating layer 12 is a polished surface. The upper surface 12a of the insulating layer 12 has a smaller surface roughness than, for example, the inner surface of the via hole 12x. The roughness of the upper surface 12a of the insulating layer 12 is set to be about 15 μm to 40 nm in terms of the surface roughness Ra value. Also, the roughness of the inner surface of the via hole 12x is set to be about 300 nm to 400 nm in terms of the surface roughness Ra value. Here, the surface roughness Ra value is a kind of numerical value representing the surface roughness, which is called the arithmetic mean roughness. Specifically, it is obtained by measuring the absolute value of the height changing within the measurement region from the surface, which is the average line, and then calculating the arithmetic mean.

[0050] The wiring layer 13 is a via wiring embedded in the insulating layer 12. More specifically, the wiring layer 13 is a via wiring filled in a via hole 12x that penetrates the insulating layer 12 and exposes the upper surface of the wiring layer 11, and is electrically connected to the wiring layer 11. The via hole 12x can be a frustum-shaped recess with a diameter of the opening on the insulating layer 15 side larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 11. The diameter of the opening of the via hole 12x can be, for example, about 60 μm to 70 μm.

[0051] The upper surface of the wiring layer 13, which is a via wiring, is exposed from the upper surface 12a of the insulating layer 12. The upper surface of the wiring layer 13 can be flush with, for example, the upper surface 12a of the insulating layer 12. The upper surface of the wiring layer 13 is directly joined to the lower surface of the wiring layer 14. The lower surface of the wiring layer 13 is directly joined to the wiring layer 11 within the insulating layer 12. The material of the wiring layer 13 can be the same as that of the wiring layer 11, for example.

[0052] The upper end surface of the wiring layer 13 is a smooth surface (low roughness surface) with few irregularities, similar to the upper surface 12a of the insulating layer 12. For example, the upper end surface of the wiring layer 13 is a polished surface. The roughness of the upper end surface of the wiring layer 13 is set to be about 15 nm to 40 nm, for example, in terms of the surface roughness Ra value.

[0053] In the first embodiment, the wiring layer 13 consists only of via wirings formed in the via holes 12x of the insulating layer 12. In other words, there is no wiring pattern integrally formed on the upper surface 12a of the insulating layer 12 in the wiring layer 13. The wiring layer 13 and the wiring layer 14 are electrically connected but not integral. Specifically, when the wiring layer 14 is formed by the semi-additive method in the manufacturing method described later, a seed layer is interposed at the boundary between the upper surface of the wiring layer 13 and the lower surface of the wiring layer 14. The reason for such a structure is to form a high-density wiring pattern (for example, a line / space of about 3 μm / 3 μm) as the wiring layer 14 described later. Details will be described in the section on the manufacturing method of the wiring board 1.

[0054] The wiring layer 14 is formed on the upper surface 12a of the insulating layer 12. The wiring layer 14 is directly formed on the upper surface 12a of the insulating layer 12 and includes wirings (wiring patterns and pads) electrically connected to the wiring layer 11 via the wiring layer 13. That is, a part of the lower surface of the wiring layer 14 is in contact with the upper surface of the wiring layer 13, and the two are electrically connected. As the material of the wiring layer 14, for example, copper (Cu) or the like can be used. The wiring layer 14 may be a laminated film in which a plurality of conductor layers are laminated.

[0055] The wiring layer 14 has a higher wiring density (narrower line / space) and is thinner than the wiring layer 11. In this specification, a wiring layer with a line / space of 8 μm / 8 μm or less is defined as a wiring layer with a high wiring density. The line / space of the wiring layer 14 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm. The thickness of the wiring layer 14 can be, for example, about 1 μm to 3 μm.

[0056] Note that the "line" in the line / space represents the wiring width, and the "space" represents the interval between adjacent wirings (wiring interval). For example, when the line / space is described as 2 μm / 2 μm, it means that the wiring width is 2 μm and the interval between adjacent wirings is 2 μm.

[0057] The insulating layer 15 is an insulating layer mainly composed of a photosensitive resin. "Mainly composed of a photosensitive resin" means that other components such as fillers may be contained in addition to the photosensitive resin. For example, the insulating layer 15 may contain a filler such as silica (SiO2).

[0058] The insulating layer 15 is formed on the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 14. Examples of the photosensitive resin used for the insulating layer 15 include insulating resins such as phenolic resins and polyimide resins. The thickness T2 of the insulating layer 15 can be, for example, 5 μm or more and 10 μm or less. The coefficient of thermal expansion of the insulating layer 15 can be, for example, 40 ppm / K or more and 60 ppm / K or less. The coefficient of thermal expansion of the insulating layer 15 can be adjusted to a predetermined value, for example, by the filler content, the composition of the insulating resin, etc.

[0059] In plan view, the insulating layer 15 is formed narrower than the insulating layer 12, and the outer peripheral portion of the upper surface of the insulating layer 12 is not covered by the insulating layer 15. That is, the outer peripheral portion of the upper surface of the insulating layer 12 is exposed from the insulating layer 15.

[0060] The wiring layer 16 is formed on one side (Z1 side) of the insulating layer 15 and is electrically connected to the wiring layer 14. The wiring layer 16 includes via wirings filled in via holes 15x that penetrate the insulating layer 15 and expose the upper surface of the wiring layer 14, and wiring patterns formed on the upper surface of the insulating layer 15. The via holes 15x can be reverse frustum-shaped recesses in which the diameter of the opening on the insulating layer 17 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 14. The diameter of the opening of the via holes 15x can be, for example, about 10 μm to 20 μm. The material of the wiring layer 16 and the thickness of the wiring patterns constituting the wiring layer 16 can be, for example, the same as those of the wiring layer 14.

[0061] Note that the line / space of the wiring layer 16 can be, for example, about 1 μm / 1 μm to 3 μm / 3 μm, but it is possible to make the line / space narrower than that of the wiring layer 14. That is, the upper surface 12a of the insulating layer 12 is a polished surface and is smoother than the lower surface 12b of the insulating layer 12. The upper surface of the insulating layer 15 mainly composed of a photosensitive resin is smoother than the upper surface 12a of the insulating layer 12 mainly composed of a non-photosensitive thermosetting resin. Therefore, the line / space of the wiring layer 16 can be made narrower than the line / space of the wiring layer 14. For example, the line / space of the wiring layer 14 can be 3 μm / 3 μm, and the line / space of the wiring layer 16 can be 1 μm / 1 μm. The same applies to the wiring layer 18 described later.

[0062] The insulating layer 17 is formed on one surface of the insulating layer 15 so as to cover the wiring layer 16. In plan view, the insulating layer 17 is formed narrower than the insulating layer 12, and the outer peripheral portion of the upper surface of the insulating layer 12 is exposed from the insulating layer 17. In plan view, the edge of the insulating layer 17 overlaps with the edge of the insulating layer 15. The material, thickness, and thermal expansion coefficient of the insulating layer 17 can be, for example, the same as those of the insulating layer 15. The insulating layer 17 may contain fillers such as silica (SiO2).

[0063] The wiring layer 18 is formed on one side (Z1 side) of the insulating layer 17 and is electrically connected to the wiring layer 16. The wiring layer 18 includes via wirings filled in via holes 17x that penetrate the insulating layer 17 and expose the upper surface of the wiring layer 16, and wiring patterns formed on the upper surface of the insulating layer 17. The via hole 17x can be a frustum-shaped concave portion with a diameter of the opening on the insulating layer 19 side larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 16. The diameter of the opening of the via hole 17x can be, for example, about 10 μm to 20 μm. The material of the wiring layer 18 and the thickness of the wiring patterns constituting the wiring layer 18 can be, for example, the same as those of the wiring layer 14. The line / space of the wiring patterns constituting the wiring layer 18 can be, for example, the same as those of the wiring layer 16.

[0064] The insulating layer 19 is formed on one surface of the insulating layer 17 so as to cover the wiring layer 18. In plan view, the insulating layer 19 is formed narrower than the insulating layer 12, and the outer peripheral portion of the upper surface of the insulating layer 12 is exposed from the insulating layer 19. In plan view, the edge of the insulating layer 19 overlaps the edges of the insulating layers 15 and 17. In the first wiring structure 1H, the insulating layer 19 is the uppermost insulating layer. The material, thickness, and thermal expansion coefficient of the insulating layer 19 can be, for example, the same as those of the insulating layer 15. The insulating layer 19 may contain fillers such as silica (SiO2).

[0065] The wiring layer 21 is formed on one side (Z1 side) of the insulating layer 19. In the first wiring structure 1H, the wiring layer 21 is the uppermost wiring layer. The wiring layer 21 includes via wirings 22 filled in via holes 19x that penetrate the insulating layer 19 and expose the upper surface of the wiring layer 18, and conductive pads 23 protruding from the upper surface of the insulating layer 19. The via hole 19x can be a frustum-shaped concave portion with a diameter of the opening on the pad 23 side larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 18. The diameter of the opening of the via hole 19x can be, for example, about 10 μm to 20 μm.

[0066] The material of the wiring layer 21 can be the same as that of the wiring layer 14, for example. The thickness of the pad 23 (the thickness from the upper surface of the insulating layer 19 to the upper surface of the pad 23) can be, for example, 80 μm to 150 μm. The planar shape of the pad 23 can be, for example, a circle with a diameter of about 20 μm to 30 μm. The pitch of the pads 23 can be, for example, about 40 μm to 50 μm. Note that the portion of the pad 23 exposed from the encapsulating resin layer 24 is used as an external connection terminal for electrically connecting to the semiconductor chip. That is, a semiconductor chip, a capacitor, or the like is mounted on the pad 23.

[0067] The pads 23 are provided in the first semiconductor chip mounting region 51, the second semiconductor chip mounting region 52, the third semiconductor chip mounting region 53, the fourth semiconductor chip mounting region 54, the fifth semiconductor chip mounting region 55, the first capacitor mounting region 61, the second capacitor mounting region 62, the third capacitor mounting region 63, and the fourth capacitor mounting region 64.

[0068] A surface treatment layer 210 similar to the surface treatment layer 110 may be formed on the upper surface of the pad 23. When a part of the side surface and the upper surface of the pad 23 protrude from the upper surface 24a of the encapsulating resin layer 24, the surface treatment layer 210 is formed only on the upper surface of the pad 23, or on a part of the side surface and the upper surface.

[0069] The first slit 71, the second slit 72, the third slit 73, the fourth slit 74, and the fifth slit 75 are formed in the insulating layer 19. The first slit 71, the second slit 72, the third slit 73, the fourth slit 74, and the fifth slit 75 are provided, for example, so as to penetrate the insulating layer 19 in the thickness direction and expose the upper surface of the insulating layer 17. The structure of the first slit 71, the second slit 72, the third slit 73, the fourth slit 74, and the fifth slit 75 is not limited to this, and may be a recess having a bottom surface at approximately the center in the thickness direction of the insulating layer 19. In FIG. 4, the first slit 71, the second slit 72, the third slit 73, the fourth slit 74, and the fifth slit 75 are illustrated as the slit 70.

[0070] The first slit 71 surrounds, in a plan view, the first semiconductor chip mounting region 51, the second semiconductor chip mounting region 52, the third semiconductor chip mounting region 53, the fourth semiconductor chip mounting region 54, and the fifth semiconductor chip mounting region 55. The first slit 71 is also formed between the first semiconductor chip mounting region 51 and the second semiconductor chip mounting region 52, the third semiconductor chip mounting region 53, the fourth semiconductor chip mounting region 54, and the fifth semiconductor chip mounting region 55. In a plan view, the second slit 72 surrounds the first capacitor mounting region 61. The third slit 73 surrounds the second capacitor mounting region 62. The fourth slit 74 surrounds the third capacitor mounting region 63. The fifth slit 75 surrounds the fourth capacitor mounting region 64.

[0071] The encapsulation resin layer 24 is laminated on the insulating layer 19 which is the uppermost insulating layer in the first wiring structure 1H. The encapsulation resin layer 24 exposes the upper surface of the pad 23 and covers at least a part of the side surface of the pad 23. The encapsulation resin layer 24 may expose the upper surface of the pad 23 and cover the entire side surface of the pad 23. In this case, the upper surface of the pad 23 is flush with, for example, the upper surface 24a of the encapsulation resin layer 24. However, a part of the side surface and the upper surface of the pad 23 may protrude from the upper surface 24a of the encapsulation resin layer 24, or the upper surface of the pad 23 may be exposed at a position recessed from the upper surface 24a of the encapsulation resin layer 24. When a part of the side surface and the upper surface of the pad 23 protrude from the upper surface 24a of the encapsulation resin layer 24, since the distance between the encapsulation resin layer 24 and the semiconductor chip can be ensured, it becomes easier to fill the underfill resin between the encapsulation resin layer 24 and the semiconductor chip. Also, when the upper surface of the pad 23 is exposed at a position recessed from the upper surface 24a of the encapsulation resin layer 24, the outflow of solder is reduced, and it can also have the effect of preventing a short circuit between adjacent pads 23.

[0072] In the wiring board 1, as described above, the outer peripheral portion of the upper surface of the insulating layer 12 is exposed from the insulating layers 15, 17, and 19. That is, as shown in FIG. 4, the side surface 15S of the insulating layer 15, the side surface 17S of the insulating layer 17, and the side surface 19S of the insulating layer 19 are located inside the side surface 12S of the insulating layer 12. Further, as shown in FIG. 3, in a plan view, there is a first region 76 where the upper surface of the insulating layer 12 is exposed around the insulating layers 15, 17, and 19.

[0073] The encapsulating resin layer 24 covers, in the first region 76, the portions of the outer peripheral portion of the upper surface of the insulating layer 12 that are exposed from the insulating layers 15, 17, and 19. The encapsulating resin layer 24 further covers the side surface 15S of the insulating layer 15, the side surface 17S of the insulating layer 17, and the side surface 19S of the insulating layer 19.

[0074] Also, the first slit 71, the second slit 72, the third slit 73, the fourth slit 74, and the fifth slit 75 formed in the insulating layer 19 are filled with the encapsulating resin layer 24.

[0075] As the material of the encapsulating resin layer 24, for example, a molding resin can be used. The molding resin is an insulating resin mainly composed of a non-photosensitive thermosetting resin that can be used in a transfer molding method, a compression molding method, an injection molding method, etc. The molding resin is, for example, an insulating resin such as a non-photosensitive and thermosetting epoxy resin, and may contain the same filler as the insulating layer 12, but does not contain a reinforcing member such as glass fiber.

[0076] From the viewpoint of reducing the warp of the wiring board 1, the thickness T3 of the encapsulating resin layer 24 is preferably greater than the thickness T1 of the insulating layer 12. The thickness T3 of the encapsulating resin layer 24 here is the thickness on the upper surface of the insulating layer 19 of the encapsulating resin layer 24. If the thickness T1 of the insulating layer 12 is 60 μm or more and 70 μm or less, for example, the thickness T3 of the encapsulating resin layer 24 can be 80 μm or more and 150 μm or less. The thermal expansion coefficient of the encapsulating resin layer 24 is lower than the thermal expansion coefficients of the insulating layers 15, 17, and 19. For example, the thermal expansion coefficient of the encapsulating resin layer 24 is 20 ppm / K or less, and the Young's modulus of the encapsulating resin layer 24 is 1 GPa or more.

[0077] Also, from the viewpoint of reducing the warp of the wiring board 1, it is preferable that the coefficient of thermal expansion of the sealing resin layer 24 is substantially equal to the coefficient of thermal expansion of the insulating layer 12. Here, "substantially equal" means that the coefficient of thermal expansion of the sealing resin layer 24 is ±20% or less with respect to the coefficient of thermal expansion of the insulating layer 12.

[0078] For example, if the coefficient of thermal expansion of the insulating layer 12 is 5 ppm / K or more and 10 ppm / K or less, it is preferable that the coefficient of thermal expansion of the sealing resin layer 24 is also 5 ppm / K or more and 10 ppm / K or less. The coefficient of thermal expansion of the sealing resin layer 24 can be adjusted to a predetermined value, for example, by the content of the filler, the composition of the insulating resin, and the like.

[0079] [Manufacturing Method of Wiring Board According to First Embodiment] Next, the manufacturing method of the wiring board according to the first embodiment will be described. FIGS. 5 to 13 are cross-sectional views showing the manufacturing method of the wiring board according to the first embodiment. Here, an example of the process of manufacturing one wiring board is shown, but it may also be a process of manufacturing a plurality of parts that will become the wiring board and then separating them into individual wiring boards.

[0080] First, as shown in FIG. 5(a), a support 100 is prepared. The support 100 has a structure in which a prepreg 103 and a copper foil 104 with a carrier are sequentially laminated on both sides of a core substrate 101 having copper foils 102 formed on both sides. The core substrate 101 is, for example, a glass epoxy substrate with a thickness of about 0.7 mm, and the thickness of the copper foil 102 can be, for example, about 7 μm to 50 μm. The prepreg 103 is, for example, a thermosetting epoxy resin, a polyimide resin, or the like impregnated in advance into a woven fabric or a non-woven fabric such as glass fiber or aramid fiber.

[0081] The copper foil 104 with carrier has a structure in which a thin foil 104a made of, for example, copper with a thickness of about 1.5 μm to 5 μm is adhered in a peelable state via a release layer (not shown) on a thick foil (carrier foil) 104b made of, for example, copper with a thickness of about 10 μm to 50 μm. The thick foil 104b is provided as a support material for facilitating the handling of the thin foil 104a. The thick foil 104b is adhered to the copper foil 102 of the core substrate 101 by the prepreg 103. The thin foil 104a is disposed on the outermost layers on both sides of the support 100.

[0082] Note that the structure of the support 100 described above is an example and is not limited thereto. For example, in the support 100, instead of the core substrate 101, a laminate in which a plurality of prepregs 103 are laminated may be used. Further, the support 100 may have a structure in which the copper foil 104 with carrier is disposed via a release layer on both sides of a glass substrate, a metal substrate, or the like.

[0083] Next, as shown in FIG. 5(b), a photosensitive resist layer 500 is formed over the entire upper surface (the upper surface of the thin foil 104a) of the upper copper foil 104 with carrier, and the resist layer 500 is exposed and developed to form an opening 500x that exposes the portion where the wiring layer 11 is to be formed. Similarly, a photosensitive resist layer 510 is formed over the entire lower surface (the lower surface of the thin foil 104a) of the lower copper foil 104 with carrier, and the resist layer 510 is exposed and developed to form an opening 510x that exposes the portion where the wiring layer 31 is to be formed. As the resist layers 500 and 510, for example, a dry film resist can be used. The opening 500x and the opening 510x are formed at positions facing each other with the support 100 interposed therebetween. Then, by an electrolytic plating method using the upper copper foil 104 with carrier as a power supply layer, a wiring layer 11, which is an electrolytic plating layer, is formed on the upper surface of the copper foil 104 with carrier exposed in the opening 500x. Similarly, by an electrolytic plating method using the lower copper foil 104 with carrier as a power supply layer, a wiring layer 31, which is an electrolytic plating layer, is formed on the lower surface of the copper foil 104 with carrier exposed in the opening 510x. The material and thickness of the wiring layer 11 are as described above. The material and thickness of the wiring layer 31 can be, for example, the same as those of the wiring layer 11.

[0084] Next, as shown in FIG. 5(c), the resist layers 500 and 510 are peeled off. Next, as shown in FIG. 5(d), a photosensitive resist layer 520 that covers the entire upper surface of the copper foil 104 with a carrier is formed, and a photosensitive resist layer 530 that covers the entire lower surface of the copper foil 104 with a carrier is formed. As the resist layers 520 and 530, for example, a dry film resist can be used. Then, the resist layer 520 is exposed and developed to form an opening 520x that exposes the outer peripheral portion of the upper copper foil 104 with a carrier. Also, the resist layer 530 is exposed and developed to form an opening 530x that exposes the outer peripheral portion of the lower copper foil 104 with a carrier. The opening 520x and the opening 530x are formed at positions facing each other via the support 100.

[0085] Next, as shown in FIG. 6(a), the upper copper foil 104 with a carrier exposed in the opening 520x shown in FIG. 5(d) and the lower copper foil 104 with a carrier exposed in the opening 530x shown in FIG. 5(d) are removed by etching. As a result, the upper surface of the upper prepreg 103 is exposed at the outer peripheral portion on one side (Z1 side) of the support 100, and the lower surface of the lower prepreg 103 is exposed at the outer peripheral portion on the other side (Z2 side) of the support 100. Then, the resist layers 520 and 530 are peeled off. Note that exposing the prepregs 103 at the outer peripheral portions on one side (Z1 side) and the other side (Z2 side) of the support 100 is to provide a region where each prepreg 103 and the insulating layers 12 and 32 are in direct contact without passing through the copper foil 104 with a carrier, in order to improve the adhesion between the two.

[0086] Next, as shown in FIG. 6(b), an insulating layer 12 that covers the upper copper foil 104 with a carrier and the wiring layer 11 is formed on the upper surface of the upper prepreg 103. Also, an insulating layer 32 that covers the lower copper foil 104 with a carrier and the wiring layer 31 is formed on the lower surface of the lower prepreg 103.

[0087] Specifically, a semi-cured film-like insulating resin containing a non-photosensitive thermosetting resin as a main component and having a reinforcing member 128 is prepared. Then, this insulating resin is laminated on the upper surface of the copper foil 104 with a carrier, and cured while heating and applying pressure to form the insulating layer 12. The material, thickness, coefficient of thermal expansion, etc. of the insulating layer 12 are as described above.

[0088] Similarly, the insulating resin is laminated on the lower surface of the copper foil 104 with a carrier on the lower side, and cured while heating and applying pressure to form the insulating layer 32. The insulating layer 32 contains a non-photosensitive thermosetting resin as a main component and has a reinforcing member 328. The material, thickness, coefficient of thermal expansion, etc. of the insulating layer 32 and the reinforcing member 328 are as described above.

[0089] Note that the above process is an example. For example, a multilayer film in which a semi-cured insulating resin containing a non-photosensitive thermosetting resin as a main component and having a reinforcing member 128 is laminated on a semi-cured insulating resin containing a non-photosensitive thermosetting resin as a main component and having no reinforcing member may be used.

[0090] Next, as shown in FIG. 6(c), via holes 12x that penetrate the insulating layer 12 and expose the upper surface of the wiring layer 11 are formed in the insulating layer 12. Similarly, via holes 32x that penetrate the insulating layer 32 and expose the lower surface of the wiring layer 31 are formed in the insulating layer 32. The via holes 12x and 32x can be formed, for example, by a laser processing method using a CO2 laser, a YAG laser, an excimer laser, or the like. After forming the via holes 12x and 32x, it is preferable to perform a desmear treatment to remove the resin residues adhering to the surfaces of the wiring layers 11 and 31 exposed at the bottoms of the via holes 12x and 32x, respectively.

[0091] Next, as shown in FIGS. 7(a) to 7(c), wiring layers 13 and 33 are formed. The wiring layers 13 and 33 can be formed, for example, using a semi-additive method. Specifically, first, as shown in FIG. 7(a), a seed layer 131 is formed on the surface of the insulating layer 12 including the inner wall of the via hole 12x and the surface of the wiring layer 11 exposed in the via hole 12x by electroless plating or sputtering. Similarly, a seed layer 331 is formed on the surface of the insulating layer 32 including the inner wall of the via hole 32x and the surface of the wiring layer 31 exposed in the via hole 32x by electroless plating or sputtering. As the seed layers 131 and 331, for example, a copper layer with a thickness of about 100 nm to 350 nm can be used. Also, as the seed layers 131 and 331, a laminated film in which a titanium layer with a thickness of about 20 nm to 50 nm and a copper layer with a thickness of about 100 nm to 300 nm are laminated in this order may be used. By forming a titanium layer under the seed layers 131 and 331, the adhesion between the insulating layer 12 and the wiring layer 13 and the adhesion between the insulating layer 32 and the wiring layer 33 can be improved. Instead of titanium, titanium nitride or the like may be used. Note that titanium and titanium nitride are metals with higher corrosion resistance than copper.

[0092] Next, as shown in FIG. 7(b), a photosensitive resist layer 540 is formed on the entire upper surface of the seed layer 131, and the resist layer 540 is exposed and developed to form an opening 540x that exposes the portion where the wiring layer 13 is to be formed. Similarly, a photosensitive resist layer 550 is formed on the entire lower surface of the seed layer 331, and the resist layer 550 is exposed and developed to form an opening 550x that exposes the portion where the wiring layer 33 is to be formed. As the resist layers 540 and 550, for example, a dry film resist can be used. The opening 540x and the opening 550x are formed at positions facing each other via the support 100. Then, an electrolytic plating layer 132 (for example, a copper layer) is formed on the upper surface of the seed layer 131 exposed in the opening 540x by an electrolytic plating method using the seed layer 131 as the power supply layer. Similarly, an electrolytic plating layer 332 (for example, a copper layer) is formed on the lower surface of the seed layer 331 exposed in the opening 550x by an electrolytic plating method using the seed layer 331 as the power supply layer.

[0093] Next, as shown in FIG. 7(c), after the resist layer 540 is peeled off, using the electrolytic plating layer 132 as a mask, the seed layer 131 in the portion not covered by the electrolytic plating layer 132 is removed by etching. Thereby, the wiring layer 13 with the electrolytic plating layer 132 laminated on the seed layer 131 is formed. Similarly, after the resist layer 550 is peeled off, using the electrolytic plating layer 332 as a mask, the seed layer 331 in the portion not covered by the electrolytic plating layer 332 is removed by etching. Thereby, the wiring layer 33 with the electrolytic plating layer 332 laminated on the seed layer 331 is formed.

[0094] By the steps up to this point, a layer structure in which the insulating layer and the wiring layer are arranged symmetrically above and below with the support 100 as the center is formed. By adopting such an upper and lower symmetric layer structure, the balance of physical property values (elastic modulus and coefficient of thermal expansion) above and below the support 100 can be achieved, so that warping of the structure during the manufacturing process of the wiring board 1 can be suppressed. Note that the lower layer structure is not a part to be commercialized as a wiring board, but the lower layer structure may also be completed and commercialized as the wiring board 1. Further, when warping of the structure during the manufacturing process of the wiring board 1 is not a problem, a layer structure may not be formed on the lower side of the support 100.

[0095] Next, as shown in FIG. 8(a), the upper surface side of the wiring layer 13 is polished to expose the upper surface 12a of the insulating layer 12 and the upper surface of the wiring layer 13 filling the via hole 12x, and the wiring layer 13 which is the via wiring filled in the via hole 12x is formed. For polishing the wiring layer 13, for example, a chemical mechanical polishing (CMP) method or the like can be used. The upper surface of the wiring layer 13 can be flush with the upper surface 12a of the insulating layer 12, for example.

[0096] When polishing the wiring layer 13, a part of the upper surface 12a of the insulating layer 12 may be polished and removed simultaneously. By polishing the upper surface 12a of the insulating layer 12 together with the wiring layer 13 and removing a part of the upper surface 12a of the insulating layer 12, the roughness of the upper surface 12a of the insulating layer 12 can be made smaller than before polishing. That is, the smoothness of the upper surface 12a of the insulating layer 12 can be improved. The roughness of the upper surface 12a of the insulating layer 12 is, for example, about 300 nm to 400 nm in terms of the surface roughness Ra value before polishing, and can be about 15 nm to 40 nm in terms of the surface roughness value Ra by polishing. In this way, by reducing the roughness of the upper surface 12a of the insulating layer 12 and improving the smoothness, it becomes possible to form fine wiring (a wiring layer with a high wiring density) in a subsequent process. Note that the roughness of the lower surface 12b of the insulating layer 12 is, for example, about 180 nm to 280 nm in terms of the surface roughness Ra value.

[0097] Next, as shown in FIG. 8(b), a wiring layer 14 is formed. The wiring layer 14 can be formed, for example, by the semi-additive method in the same manner as the wiring layers 13 and 33. Specifically, first, a seed layer is formed by electroless plating or sputtering so as to continuously cover the upper surface of the wiring layer 13 and the upper surface 12a of the insulating layer 12. Although the electroless plating method may be used for forming the seed layer, the sputtering method is more advantageous for increasing the density of the wiring layer because a thinner film can be formed by the sputtering method.

[0098] Then, a photosensitive resist layer is formed on the entire upper surface of the seed layer, the resist layer is exposed and developed, and an opening is formed to expose the portion where the wiring layer 14 is to be formed. Then, an electrolytic plating layer is formed on the upper surface of the seed layer exposed in the opening by the electrolytic plating method using the seed layer as a power supply layer. Then, after peeling the resist layer, the seed layer in the portion not covered by the electrolytic plating layer is removed by etching using the electrolytic plating layer as a mask. Thereby, a wiring layer 14 in which an electrolytic plating layer is laminated on the seed layer is formed. The material, thickness, line / space, etc. of the wiring layer 14 are as described above. Note that the wiring layer 14 has a structure in which an electrolytic plating layer is laminated on the seed layer, but in FIG. 8 and the like, the distinction between the seed layer and the electrolytic plating layer is omitted (the distinction may be omitted in the same manner for other wiring layers).

[0099] Next, as shown in FIG. 8(c), a liquid or paste-like photosensitive insulating resin is applied to the upper surface 12a of the insulating layer 12 so as to cover the wiring layer 14, and then heated at a temperature below the curing temperature to form a semi-cured insulating layer 15. The material and thickness of the insulating layer 15 are as described above.

[0100] Next, as shown in FIG. 9(a), for example, via holes 15x are formed by a photolithography method, and then the insulating layer 15 is heated to a temperature equal to or higher than the curing temperature to be cured. When forming the via holes 15x, the insulating layer 15 is removed from above the outer peripheral portion of the upper surface of the insulating layer 12, and the side surface 15S of the insulating layer 15 is positioned inside the side surface 12S of the insulating layer 12. The side surface 12S of the insulating layer 12 is the side surface of the insulating layer 12 that is exposed when cut by subsequent dicing. The upper surface of the insulating layer 15 mainly composed of a photosensitive insulating resin becomes smoother than the upper surface 12a of the insulating layer 12. The roughness of the upper surface of the insulating layer 15 can be, for example, about 2 nm to 6 nm in terms of the surface roughness Ra value.

[0101] Next, as shown in FIG. 9(b), a wiring layer 16 is formed. The wiring layer 16 can be formed, for example, by a semi-additive method in the same manner as the wiring layer 14. Next, a liquid or paste-like photosensitive insulating resin is applied to the upper surface of the insulating layer 15 so as to cover the wiring layer 16, and then heated at a temperature below the curing temperature to form a semi-cured insulating layer 17. The material and thickness of the insulating layer 17 are as described above.

[0102] Next, for example, via holes 17x are formed by a photolithography method, and then the insulating layer 17 is heated to a temperature equal to or higher than the curing temperature to be cured. When forming the via holes 17x, the insulating layer 17 is removed from above the outer peripheral portion of the upper surface of the insulating layer 12, and the side surface 17S of the insulating layer 17 is positioned inside the side surface 12S of the insulating layer 12. The upper surface of the insulating layer 17 mainly composed of a photosensitive insulating resin becomes smoother than the upper surface 12a of the insulating layer 12. The surface roughness Ra of the upper surface of the insulating layer 17 can be, for example, about 2 nm to 6 nm.

[0103] Next, as shown in FIG. 9(c), a wiring layer 18 is formed. Similar to the wiring layer 14, the wiring layer 18 can be formed, for example, using a semi-additive method. Next, a liquid or paste-like photosensitive insulating resin is applied onto the upper surface of the insulating layer 17 so as to cover the wiring layer 18, and then heated at a temperature below the curing temperature to form a semi-cured insulating layer 19. The material and thickness of the insulating layer 19 are as described above.

[0104] Next, for example, via holes 19x and slits 70 are formed by a photolithography method, and then the insulating layer 19 is heated to a temperature equal to or higher than the curing temperature to be cured. When forming the via holes 19x and the slits 70, the insulating layer 19 is removed from above the outer peripheral portion on the upper surface of the insulating layer 12, and the side surface 19S of the insulating layer 19 is positioned inside the side surface 12S of the insulating layer 12. The upper surface of the insulating layer 19 mainly composed of a photosensitive insulating resin becomes smoother than the upper surface 12a of the insulating layer 12. The surface roughness Ra of the upper surface of the insulating layer 19 can be, for example, about 2 nm to 6 nm.

[0105] Next, as shown in FIG. 10(a), a wiring layer 21 including via wirings 22 and pads 23 is formed. Similar to the wiring layer 14, the wiring layer 21 can be formed, for example, using a semi-additive method.

[0106] Next, as shown in FIG. 10(b), a sealing resin layer 24 is formed on the insulating layer 12 so as to cover the upper surface and the side surface of the pad 23 of the wiring layer 21 and the upper surface and the side surface of the laminated structure 20 of the insulating layers 15, 17, and 19. The sealing resin layer 24 can be formed, for example, by a molding method using a molding resin. For example, the structure shown in FIG. 10(a) is housed in a mold, and a pressure (for example, 5 MPa to 10 MPa) is applied to the mold to introduce a fluidized molding resin. Then, the molding resin is heated at a temperature of about 180°C to be cured, thereby forming the sealing resin layer 24. After the required sealing process is completed, the structure covered with the sealing resin layer 24 is taken out from the mold. As the molding method, for example, a transfer molding method, a compression molding method, an injection molding method, etc. can be used.

[0107] Next, as shown in FIG. 11(a), the upper surface side of the sealing resin layer 24 shown in FIG. 10(b) is polished to expose at least the upper surface of the pad 23. For polishing the sealing resin layer 24, for example, the CMP method or the like can be used. The upper surface of the pad 23 can be flush with the upper surface 24a of the sealing resin layer 24, for example. However, by adjusting the polishing amount of the sealing resin layer 24 or the like, a part of the side surface and the upper surface of the pad 23 may protrude from the upper surface 24a of the sealing resin layer 24, or the upper surface of the pad 23 may be exposed at a position recessed from the upper surface 24a of the sealing resin layer 24.

[0108] Next, as shown in FIG. 11(b), the outer peripheral portion of the structure shown in FIG. 11(a) is cut using a dicing blade or the like. The cutting is performed so as to remove the region where the insulating layer 12 and the upper prepreg 103 are in direct contact and the region where the insulating layer 32 and the lower prepreg 103 are in direct contact. Thereby, as shown in FIG. 12(a), the portion where the thick foil 104b and the thin foil 104a are in contact can be easily peeled off. That is, the main part of the support 100 can be easily removed.

[0109] Next, as shown in FIG. 12(b), the thin foil 104a is removed from the structure (the portion shown obliquely in FIG. 12(a)) from which the main part of the support 100 shown in FIG. 12(a) has been removed. The thin foil 104a can be removed by, for example, wet etching. Thereby, the lower surface of the wiring layer 11 is exposed on the lower surface 12b of the insulating layer 12. The lower surface 12b of the insulating layer 12 and the lower surface of the wiring layer 11 can be flush, for example.

[0110] Next, as shown in FIG. 13, if necessary, a surface treatment layer 210 is formed on the upper surface of the pad 23 of the structure in FIG. 12(b), and a surface treatment layer 110 is formed on the lower surface of the wiring layer 11. As the surface treatment layers 110 and 210, for example, the above-described metal layer or laminate of metal layers may be formed by electroless plating, or an antioxidant treatment such as OSP treatment may be performed.

[0111] In this way, the wiring board 1 according to the first embodiment can be manufactured.

[0112] Thus, in the wiring board 1, a second wiring structure 1L including an insulating layer 12 mainly composed of a non-photosensitive thermosetting resin and a first wiring structure 1H including insulating layers 15, 17, and 19 mainly composed of a photosensitive resin are arranged with each other sandwiching the first wiring structure 1H. And a sealing resin layer 24 mainly composed of a non-photosensitive thermosetting resin is disposed. Then, the thermal expansion coefficient of the insulating layer 12 and the thermal expansion coefficient of the sealing resin layer 24 are lower than the respective thermal expansion coefficients of the insulating layers 15, 17, and 19. With this structure, since the imbalance in the thermal expansion coefficient in the thickness direction of the wiring board 1 is improved, the warp of the wiring board 1 can be reduced.

[0113] Furthermore, the sealing resin layer 24 covers side surfaces 15S of the insulating layer 15, side surfaces 17S of the insulating layer 17, and side surfaces 19S of the insulating layer 19. Therefore, the portion of the sealing resin layer 24 outside the side surfaces 15S, 17S, and 19S is thicker than the portion where the pads 23 are formed (the portion above the upper surface of the insulating layer 19). For this reason, compared with the wiring board 9, the volume of the sealing resin layer 24 on the upper side (Z1 side) of the insulating layer 12 is large, and the warp of the wiring board 1 is suppressed more than the warp of the wiring board 9.

[0114] Also, the first slit 71, the second slit 72, the third slit 73, the fourth slit 74, and the fifth slit 75 are embedded by the sealing resin layer 24. For this reason, also in this respect, compared with the wiring board 9, the volume of the sealing resin layer 24 on the upper side (Z1 side) of the insulating layer 12 is large, and the warp of the wiring board 1 is suppressed more than the warp of the wiring board 9.

[0115] Furthermore, by reducing the warp of the wiring board 1, it becomes easy to mount a semiconductor chip on the sealing resin layer 24 side of the wiring board 1 or to mount the wiring board 1 on another wiring board.

[0116] Note that the encapsulation resin layer 24 does not necessarily cover all of the side surfaces 15S of the insulating layer 15, 17S of the insulating layer 17, and 19S of the insulating layer 19, and may cover only a part thereof. For example, in a plan view, if the side surface 15S of the insulating layer 15 overlaps with the side surface 12S of the insulating layer 12, the encapsulation resin layer 24 may cover the side surfaces 17S of the insulating layer 15 and 17S of the insulating layer 17 without covering the side surface 15S of the insulating layer 15.

[0117] Also, the state shown in Fig. 11(a) may be used as the shipping form. That is, the wiring board 1 with the support 100 may be used as the shipping form.

[0118] (Second Embodiment) Next, the second embodiment will be described. The second embodiment relates to a wiring board and is mainly different from the first embodiment in that it does not include the second wiring structure 1L.

[0119] [Structure of Wiring Board According to Second Embodiment] Fig. 14 is a cross-sectional view showing a wiring board according to the second embodiment. As shown in Fig. 14, the wiring board 2 according to the second embodiment includes the first wiring structure 1H but does not include the second wiring structure 1L.

[0120] The first wiring structure 1H includes a wiring layer 81 and an insulating layer 82 in addition to the wiring layer 14, the insulating layer 15, the wiring layer 16, the insulating layer 17, the wiring layer 18, the insulating layer 19, and the wiring layer 21.

[0121] The wiring layer 81 is the lowermost wiring layer exposed on the lower surface side of the insulating layer 82, and its upper surface and side surfaces are covered by the insulating layer 82. The lower surface of the wiring layer 81 may be flush with, for example, the lower surface 82b of the insulating layer 82. The lower surface of the wiring layer 81 may be exposed at a position recessed from the lower surface 82b of the insulating layer 82 toward the wiring layer 14 side, and a part of the side surface and the lower surface of the wiring layer 81 may protrude downward from the lower surface 82b of the insulating layer 82.

[0122] The wiring layer 81 is, for example, a circular pad having a planar shape with a diameter of about 150 μm, but may include a wiring pattern. The interval between adjacent wiring layers 81 can be, for example, about 200 μm. As the material of the wiring layer 81, for example, copper (Cu) or the like can be used. The thickness of the wiring layer 81 can be, for example, about 1 μm to 3 μm. Note that the wiring layer 81 can be used as an external connection terminal (pad) for electrically connecting to other wiring boards. The wiring layer 81 may be used as an external connection terminal (pad) for connecting a chip capacitor or the like. A surface treatment layer 110 may be formed on the lower surface of the wiring layer 81.

[0123] The insulating layer 82 covers the upper surface and the side surfaces of the wiring layer 81. In plan view, the edges of the insulating layer 82 overlap with the edges of the insulating layers 15, 17, and 19. The material, thickness, and coefficient of thermal expansion of the insulating layer 82 can be, for example, the same as those of the insulating layer 15. The insulating layer 17 may contain a filler such as silica (SiO2).

[0124] In this embodiment, the wiring layer 14 is formed on one side (Z1 side) of the insulating layer 82 and is electrically connected to the wiring layer 81. The wiring layer 14 includes via wiring filled in a via hole 82x that penetrates the insulating layer 82 and exposes the upper surface of the wiring layer 81, and a wiring pattern formed on the upper surface of the insulating layer 15. The via hole 82x can be a frustum-shaped concave portion with a diameter of the opening on the insulating layer 15 side being larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 81. The diameter of the opening of the via hole 82x can be, for example, about 10 μm to 20 μm.

[0125] The sealing resin layer 24 covers the side surfaces 82S of the insulating layer 82 in addition to the side surfaces 15S of the insulating layer 15, the side surfaces 17S of the insulating layer 17, and the side surfaces 19S of the insulating layer 19. The lower surface of the sealing resin layer 24 may be flush with the lower surface 82b of the insulating layer 82.

[0126] Other configurations are the same as those in the first embodiment.

[0127] [Method for manufacturing a wiring board according to the second embodiment] Next, a method for manufacturing a wiring board according to the second embodiment will be described. FIGS. 15 to 16 are cross-sectional views showing the method for manufacturing a wiring board according to the second embodiment.

[0128] First, similar to the first embodiment, a support 100 is prepared (see FIG. 5(a)). Next, as shown in FIG. 15(a), without forming the wiring layer 11, a part of the upper copper foil 104 with a carrier and a part of the lower copper foil 104 with a carrier are removed by etching.

[0129] Next, as shown in FIG. 15(b), a wiring layer 81 is formed. The wiring layer 81 can be formed, for example, by the semi-additive method in the same manner as the wiring layer 14 in the first embodiment.

[0130] Next, as shown in FIG. 15(c), a liquid or paste-like photosensitive insulating resin is applied to the upper surface of the upper copper foil 104 with a carrier so as to cover the wiring layer 81, and then heated at a temperature below the curing temperature to form a semi-cured insulating layer 82. The material and thickness of the insulating layer 82 are as described above.

[0131] Next, for example, via holes 82x are formed by photolithography, and then the insulating layer 82 is heated to a temperature equal to or higher than the curing temperature to be cured. When forming the via holes 82x, the insulating layer 82 is removed from above the outer peripheral portion of the upper surface of the upper copper foil 104 with a carrier, and the side surface 82S of the insulating layer 82 is positioned inside the side surface of the upper copper foil 104 with a carrier.

[0132] Next, as shown in FIG. 15(d), in the same manner as the first embodiment, a wiring layer 14, an insulating layer 15, a wiring layer 16, an insulating layer 17, a wiring layer 18, and an insulating layer 19 are formed on the insulating layer 82. Also, via holes 15x, 17x, and 19x are formed as appropriate.

[0133] Next, as shown in FIG. 16(a), a sealing resin layer 24 is formed so as to cover the upper surface and side surfaces of the pads 23 of the wiring layer 21 and the upper surface and side surfaces of the laminated structure 20 of the insulating layers 15, 17, 19, and 82 on the support 100. Similar to the first embodiment, the sealing resin layer 24 can be formed, for example, by a molding method using a molding resin.

[0134] Next, as shown in FIG. 16(b), similar to the first embodiment, cutting using a dicing blade or the like and removal of the thin foil 104a are performed, and if necessary, the surface treatment layer 210 and the surface treatment layer 110 are formed.

[0135] In this way, the wiring board 2 according to the second embodiment can be manufactured.

[0136] In the wiring board 2, the sealing resin layer 24 covers not only the upper surface of the insulating layer 19 but also the side surface 15S of the insulating layer 15, the side surface 17S of the insulating layer 17, the side surface 19S of the insulating layer 19, and the side surface 82S of the insulating layer 82. Therefore, the portion of the sealing resin layer 24 outside the side surfaces 15S, 17S, 19S, and 82S is thicker than the portion where the pads 23 are formed (the portion above the upper surface of the insulating layer 19). Further, the first slit 71, the second slit 72, the third slit 73, the fourth slit 74, and the fifth slit 75 are embedded by the sealing resin layer 24. For this reason, similar to the first embodiment, warpage can be reduced.

[0137] (Third Embodiment) Next, the third embodiment will be described. The third embodiment relates to a semiconductor device including the wiring board 1 according to the first embodiment. FIG. 17 is a cross-sectional view showing the semiconductor device according to the third embodiment.

[0138] As shown in FIG. 17, the semiconductor device 3 according to the third embodiment includes the wiring board 1 according to the first embodiment and a base board 200.

[0139] The base substrate 200 is a multilayer wiring substrate in which wiring layers and insulating layers are laminated on both sides of the core layer 250, and can be manufactured, for example, by a well-known build-up method. Each wiring layer of the base substrate 200 has a lower wiring density (wider line / space) compared to the wiring layers 14, 16, 18, 21 of the wiring substrate 1. The line / space of each wiring layer of the base substrate 200 can be, for example, about 20 μm / 20 μm.

[0140] In the base substrate 200, on one surface of the core layer 250, a wiring layer 252, an insulating layer 253, a wiring layer 254, an insulating layer 255, a wiring layer 256, and a solder resist layer 257 are sequentially laminated. Also, on the other surface of the core layer 250, a wiring layer 262, an insulating layer 263, a wiring layer 264, an insulating layer 265, a wiring layer 266, and a solder resist layer 267 are sequentially laminated.

[0141] As the core layer 250, for example, a so-called glass epoxy substrate obtained by impregnating a glass cloth with an insulating resin such as an epoxy resin can be used. As the core layer 250, a substrate obtained by impregnating a woven fabric or non-woven fabric of glass fiber, carbon fiber, aramid fiber, etc. with an epoxy resin or a polyimide resin can also be used. The thickness of the core layer 250 can be, for example, about 60 μm to 400 μm. The core layer 250 is provided with a through hole 250x penetrating in the thickness direction. The planar shape of the through hole 250x is, for example, circular.

[0142] The wiring layer 252 is formed on one surface of the core layer 250. Also, the wiring layer 262 is formed on the other surface of the core layer 250. The wiring layer 252 and the wiring layer 262 are electrically connected by a through wiring 251 formed in the through hole 250x. The wiring layers 252 and 262 are each patterned into a predetermined planar shape. As the material of the wiring layers 252 and 262, and the through wiring 251, for example, copper (Cu) etc. can be used. The thickness of the wiring layers 252 and 262 can be, for example, about 10 μm to 30 μm. Note that the wiring layer 252, the wiring layer 262, and the through wiring 251 may be integrally formed.

[0143] The insulating layer 253 is formed to cover the wiring layer 252 on one surface of the core layer 250. As the material of the insulating layer 253, for example, an insulating resin mainly composed of an epoxy resin or a polyimide resin can be used. The thickness of the insulating layer 253 can be, for example, about 30 μm to 40 μm. The insulating layer 253 can contain a filler such as silica (SiO2).

[0144] The wiring layer 254 is formed on one side (Z1 side) of the insulating layer 253. The wiring layer 254 includes via wirings filled in via holes 253x that penetrate the insulating layer 253 and expose the upper surface of the wiring layer 252, and wiring patterns formed on the upper surface of the insulating layer 253. The wiring patterns constituting the wiring layer 254 are electrically connected to the wiring layer 252 via the via wirings. The via hole 253x can be a frustum-shaped recess with a diameter of the opening on the insulating layer 255 side larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 252. The material of the wiring layer 254 and the thickness of the wiring patterns can be, for example, the same as those of the wiring layer 252.

[0145] The insulating layer 255 is formed to cover the wiring layer 254 on the upper surface of the insulating layer 253. The material and thickness of the insulating layer 255 can be, for example, the same as those of the insulating layer 253. The insulating layer 255 can contain a filler such as silica (SiO2).

[0146] The wiring layer 256 is formed on one side (Z1 side) of the insulating layer 255. The wiring layer 256 includes via wirings filled in via holes 255x that penetrate the insulating layer 255 and expose the upper surface of the wiring layer 254, wiring patterns formed on the upper surface of the insulating layer 255, and pads formed inside the openings 257x of the solder resist layer 257. The wiring patterns constituting the wiring layer 256 are electrically connected to the wiring layer 254 via the via wirings. The via hole 255x can be a frustum-shaped concave portion with a diameter of the opening on the wiring substrate 1 side larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 254. The material of the wiring layer 256 and the thickness of the wiring patterns can be the same as those of the wiring layer 252, for example.

[0147] The solder resist layer 257 is formed on the upper surface of the insulating layer 255 so as to cover the wiring layer 256. The solder resist layer 257 can be formed from a photosensitive resin such as an epoxy resin or an acrylic resin, for example. The thickness of the solder resist layer 257 can be about 15 μm to 35 μm, for example.

[0148] The planar shape of the pads constituting the wiring layer 256 can be circular, for example. If necessary, the aforementioned surface treatment layer may be formed on the surface (only the upper surface, or the upper surface and the side surface) of the pads constituting the wiring layer 256.

[0149] The insulating layer 263 is formed on the other surface of the core layer 250 so as to cover the wiring layer 262. The material and thickness of the insulating layer 263 can be the same as those of the insulating layer 253, for example. The insulating layer 263 can contain a filler such as silica (SiO2).

[0150] The wiring layer 264 is formed on the other side (Z2 side) of the insulating layer 263. The wiring layer 264 includes via wirings filled in via holes 263x that penetrate the insulating layer 263 and expose the lower surface of the wiring layer 262, and wiring patterns formed on the lower surface of the insulating layer 263. The wiring patterns constituting the wiring layer 264 are electrically connected to the wiring layer 262 via the via wirings. The via hole 263x can be a frustum-shaped recess in which the diameter of the opening on the insulating layer 265 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 262. The material and thickness of the wiring layer 264 can be the same as those of the wiring layer 252, for example.

[0151] The insulating layer 265 is formed on the lower surface of the insulating layer 263 so as to cover the wiring layer 264. The material and thickness of the insulating layer 265 can be the same as those of the insulating layer 253, for example. The insulating layer 265 can contain fillers such as silica (SiO2).

[0152] The wiring layer 266 is formed on the other side (Z2 side) of the insulating layer 265. The wiring layer 266 includes via wirings filled in via holes 265x that penetrate the insulating layer 265 and expose the lower surface of the wiring layer 264, and wiring patterns formed on the lower surface of the insulating layer 265. The wiring patterns constituting the wiring layer 266 are electrically connected to the wiring layer 264 via the via wirings. The via hole 265x can be a frustum-shaped recess in which the diameter of the opening on the solder resist layer 267 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 264. The material and thickness of the wiring layer 266 can be the same as those of the wiring layer 252, for example.

[0153] The solder resist layer 267 is formed on the lower surface of the insulating layer 265 so as to cover the wiring layer 266. The material and thickness of the solder resist layer 267 can be the same as those of the solder resist layer 257, for example. The solder resist layer 267 has an opening 267x, and a part of the lower surface of the wiring layer 266 is exposed in the opening 267x. The planar shape of the opening 267x can be circular, for example. If necessary, the aforementioned surface treatment layer may be formed on the lower surface of the wiring layer 266 exposed in the opening 267x.

[0154] The wiring board 1 is mounted on the base board 200. Specifically, the wiring layer 11 which is an external connection terminal of the wiring board 1 and the wiring layer 256 which is an external connection terminal of the base board 200 are joined by a solder layer 221. Also, an adhesive layer 222 is filled between the lower surface (the lower surface of the insulating layer 12) of the wiring board 1 and the upper surface (the upper surface of the insulating layer 255) of the base board 200. The adhesive layer 222 also covers a part of the side surface of the wiring board 1. The wiring board 1 and the base board 200 are adhered by the adhesive layer 222.

[0155] A stiffener 270 is fixed to the outer peripheral portion of the upper surface (the upper surface of the solder resist layer 257) of the base board 200. The stiffener 270 has a frame-like planar shape, for example, and reinforces the overall strength of the semiconductor device 3. As the material of the stiffener 270, for example, SUS304 (stainless steel mainly composed of Cr and Ni: 0.08C - 18Cr - 8Ni) etc. can be used. As the material of the stiffener 270, a metal plate such as copper or a copper alloy, or a resin plate such as a glass epoxy substrate may be used. The stiffener 270 can be provided as necessary.

[0156] The semiconductor device 3 further has a semiconductor chip 280, bumps 290, an underfill resin 295, a chip capacitor 380, and bumps 390. A plurality of semiconductor chips 280 are flip-chip mounted on the wiring board 1.

[0157] The semiconductor chip 280 is formed by forming a semiconductor integrated circuit (not shown) or the like on a thin semiconductor substrate 281 made of, for example, silicon or the like. On the circuit formation surface of the semiconductor substrate 281, electrode pads 282 electrically connected to a semiconductor integrated circuit (not shown) are formed.

[0158] The electrode pads 282 of the semiconductor chip 280 are electrically connected to the wiring layer 21 of the wiring substrate 1 via bumps 290. The underfill resin 295 is filled between the circuit formation surface of the semiconductor chip 280 and the upper surface of the wiring substrate 1 and covers the side surface of the semiconductor chip 280. The bumps 290 are, for example, solder bumps. As the material of the solder bumps, for example, SnBi solder or the like can be used.

[0159] Each semiconductor chip 280 may have the same size or different sizes. Also, each semiconductor chip 280 may have the same function or different functions. Examples of the functions of the semiconductor chip 280 include memory (such as DRAM) and logic (such as CPU). Further, one or two semiconductor chips 280 may be mounted on the wiring substrate 1, or four or more semiconductor chips 280 may be mounted.

[0160] The chip capacitor 380 has, for example, a main body portion 381 and electrode pads 382. The electrode pads 382 of the chip capacitor 380 are electrically connected to the wiring layer 266 of the base substrate 200 via bumps 390. The material of the bumps 390 can be, for example, the same as that of the bumps 290.

[0161] The semiconductor device 3 according to the third embodiment includes the wiring substrate 1. Therefore, the warp of the wiring substrate 1 is suppressed, and excellent reliability can be obtained for the semiconductor device 3.

[0162] Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications and substitutions can be made to the above-described embodiments and the like without departing from the scope described in the claims.

Description of Symbols

[0163] 1, 2 Wiring board 1H First wiring structure 1L Second wiring structure 3 Semiconductor device 11, 13, 14, 16, 18, 21, 81 Wiring layer 12, 15, 17, 19, 82 Insulating layer 12S, 15S, 17S, 19S, 82S Side surface 20 Laminated structure 24 Encapsulating resin layer 70, 71, 72, 73, 74, 75 Slit 76 First region 100 Support 200 Base substrate

Claims

1. A first wiring structure including a plurality of first wiring layers and a plurality of first insulating layers mainly composed of a photosensitive resin, A sealing resin layer mainly composed of a non-photosensitive thermosetting resin laminated on the topmost first insulating layer, having, The topmost first wiring layer includes pads protruding from the topmost first insulating layer, The sealing resin layer, exposes the upper surface of the pad, covers at least a part of the side surface of the pad and at least a part of the side surface of the plurality of first insulating layers, A slit in which the sealing resin layer is embedded is formed on the upper surface of the topmost first insulating layer, A wiring board on which a semiconductor chip is mounted on the pad.

2. The wiring board according to claim 1, wherein the sealing resin layer covers the entire side surface of the plurality of first insulating layers.

3. The wiring board according to claim 1 or 2, wherein the slit is provided so as to surround a region where the semiconductor chip is mounted.

4. Having a second wiring structure including a second wiring layer and a second insulating layer mainly composed of a non-photosensitive thermosetting resin, The first wiring structure is laminated on the second wiring structure, and the sealing resin layer covers the upper surface of the second wiring structure. The wiring board according to any one of claims 1 to 3.

5. A first wiring structure including a plurality of first wiring layers and a plurality of first insulating layers mainly composed of a photosensitive resin, A second wiring structure including a second wiring layer and a second insulating layer mainly composed of a non-photosensitive thermosetting resin, A sealing resin layer mainly composed of a non-photosensitive thermosetting resin laminated on the topmost first insulating layer, having, The topmost first wiring layer includes pads protruding from the topmost first insulating layer, The encapsulation resin layer exposes the upper surface of the pad, covers at least a part of the side surface of the pad and at least a part of the side surface of the plurality of first insulating layers, The first wiring structure is laminated on the second wiring structure, and the encapsulation resin layer covers the upper surface of the second wiring structure, The thickness from the upper surface of the topmost first insulating layer of the encapsulation resin layer to the upper surface of the encapsulation resin layer is thicker than the thickness of the second insulating layer, A wiring board on which a semiconductor chip is mounted on the pad.

6. In the second wiring structure, the second wiring layer is exposed on the lower surface side of the second insulating layer, The second wiring structure includes via wirings that penetrate the second insulating layer and are connected to the second wiring layer, The wiring board according to claim 5, wherein the lowermost first wiring layer of the first wiring structure is directly joined to the upper end surface of the via wiring via a seed layer.

7. The wiring board according to claim 5 or 6, wherein the coefficient of thermal expansion of the encapsulation resin layer is lower than the coefficient of thermal expansion of the first insulating layer, and the coefficient of thermal expansion of the encapsulation resin layer is substantially equal to the coefficient of thermal expansion of the second insulating layer.

8. A base substrate, The wiring board according to any one of claims 1 to 7 mounted on the base substrate, A semiconductor chip mounted on the wiring board, And a semiconductor device having the same.

9. A step of forming a first wiring structure including a plurality of first wiring layers and a plurality of first insulating layers mainly composed of a photosensitive resin on a support, wherein the topmost first wiring layer includes pads protruding from the topmost first insulating layer, and a semiconductor chip is mounted on the pads. A step of forming a sealing resin layer mainly composed of a non-photosensitive thermosetting resin so as to expose the upper surface of the pad and cover at least a part of the side surface of the pad and at least a part of the side surfaces of the plurality of first insulating layers; A step of peeling the support from the first wiring structure; A method of manufacturing a wiring board having the above.

Images