Inverter, Inverter Control Method, Inverter Control Program, Converter, Drive Device

Abstract

This inverter 10 comprises a high-potential input terminal 11, a low-potential input terminal 12, an output terminal 13 that outputs AC power, a transistor pair 14, and a driver that performs complementary switching control of the transistor pair 14. The driver 16 includes a current adjustment element that adjusts the channel current of the transistor pair 14 and a voltage adjustment element that adjusts the channel voltage. In the switching control of the transistor pair 14, the rate of time change of the channel current is adjusted to be greater than the rate of time change of the channel voltage.

Description

Technical Field

[0001] The present invention relates to control technologies for inverters and converters.

Background Art

[0002] An inverter used for AC drive of a motor or the like outputs AC power by complementarily turning on and off a pair of transistors on the high-potential side and the low-potential side of the output terminals. A converter outputs DC power from AC power by an operation opposite to that of the inverter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the on / off control of each transistor, when the transistor is on, the current path (the channel between the source / drain when the transistor is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the path between the emitter / collector when the transistor is a bipolar transistor) is in a conductive state, so current flows and the voltage can be regarded as zero. Also, when the transistor is off, the current path is in an insulating state, so the current can be regarded as zero and a voltage is generated. Since the voltage is zero when on and the current is zero when off, the transistor does not consume power. However, when the on / off of the transistor switches, the voltage and current do not become zero, so wasted power consumption known as switching loss occurs.

[0005] The present invention has been made in view of such circumstances, and its object is to provide an inverter and a converter capable of reducing switching loss.

Means for Solving the Problem

[0006] To solve the above problems, an inverter according to an aspect of the present invention includes a high-potential input terminal at a high potential and a low-potential input terminal at a low potential, an input terminal to which DC power is input between both input terminals, an output terminal that outputs AC power, a high-potential transistor having a current path connecting the high-potential input terminal side and the output terminal side, and a low-potential transistor having a current path connecting the low-potential input terminal side and the output terminal side. A transistor pair, and a driver that inputs a control signal to each of the high-potential transistor and the low-potential transistor and performs switching control to convert DC power into AC power by switching the conduction states of the respective current paths complementarily to each other. The driver includes at least one of a current adjustment element that adjusts the current of each current path and a voltage adjustment element that adjusts the voltage of each current path. At least one of the current adjustment element and the voltage adjustment element adjusts so that the rate of change of the current of each current path with respect to time is larger than the rate of change of the voltage of each current path with respect to time in the switching control.

[0007] In a conventional general inverter, since the on and off of each transistor are simply switched by a control signal input to the control electrode (gate electrode when the transistor is a MOSFET, base electrode when the transistor is a bipolar transistor), there is no difference in the rate of change with respect to time when the current switches and the rate of change with respect to time when the voltage switches. On the other hand, in the inverter of this aspect, at least one of the current adjustment element and the voltage adjustment element provided in the driver adjusts so that the rate of change of the current with respect to time is larger than the rate of change of the voltage with respect to time. Since the current switching time can be shortened by a steep current change, the switching loss associated with the switching of the current can be reduced. On the other hand, if the rate of change of the voltage with respect to time becomes excessive, the risk of insulation breakdown of the motor winding increases, so it is preferably smaller than the rate of change of the current with respect to time. Thus, according to the inverter of this aspect, it is possible to achieve both reduction of switching loss associated with the switching of the current and reduction of the risk of insulation breakdown of the motor winding and the like.

[0008] The time change rates of the current and voltage in the above are defined as follows. When the current switches between a minimum value Imin and a maximum value Imax during a time Ti, the time change rate of the current is represented by (Imax - Imin) / Ti, and hereinafter this is also represented as di / dt using the differential symbol. When the voltage switches between a minimum value Vmin and a maximum value Vmax during a time Tv, the time change rate of the current is represented by (Vmax - Vmin) / Tv, and hereinafter this is also represented as dv / dt using the differential symbol. When the current and voltage change in opposite directions to each other, the signs of the time change rates become positive and negative inversely, but in this specification, when comparing the magnitudes of the time change rates of the current and voltage, the absolute values of each are compared.

[0009] Another aspect of the present invention is a converter. This device includes a high-potential output terminal at a high potential and a low-potential output terminal at a low potential, an output terminal that outputs DC power between both output terminals, an input terminal to which AC power is input, a high-potential transistor having a current path connecting the high-potential output terminal side and the input terminal side, a transistor pair including a low-potential transistor having a current path connecting the low-potential output terminal side and the input terminal side, and a driver that inputs a control signal to each of the high-potential transistor and the low-potential transistor and performs switching control to convert AC power into DC power by switching the conduction states of the respective current paths complementarily to each other. The driver includes at least one of a current adjustment element that adjusts the current in each current path and a voltage adjustment element that adjusts the voltage in each current path, and at least one of the current adjustment element and the voltage adjustment element adjusts so that the time change rate of the current in each current path becomes larger than the time change rate of the voltage in each current path in the switching control.

[0010] Another aspect of the present invention is a drive device. This device includes a motor driven by polyphase alternating current power with different phases from each other, and a plurality of inverters that generate alternating current power for each phase. Each inverter includes a high-potential input terminal at a high potential and a low-potential input terminal at a low potential, an input terminal where direct current power is input between both input terminals, an output terminal that outputs alternating current power, a high-potential transistor having a current path connecting the high-potential input terminal side and the output terminal side, a transistor pair including a low-potential transistor having a current path connecting the low-potential input terminal side and the output terminal side, and a driver that inputs control signals to each of the high-potential transistor and the low-potential transistor and performs switching control to convert direct current power into alternating current power by switching the conduction states of the respective current paths complementarily to each other. The driver includes at least one of a current adjustment element that adjusts the current of each current path and a voltage adjustment element that adjusts the voltage of each current path, and at least one of the current adjustment element and the voltage adjustment element adjusts so that the time change rate of the current of each current path is larger than the time change rate of the voltage of each current path in the switching control.

[0011] Still another aspect of the present invention is a control method for an inverter. This method is a control method for an inverter including a high-potential input terminal at a high potential and a low-potential input terminal at a low potential, an input terminal where direct current power is input between both input terminals, an output terminal that outputs alternating current power, a high-potential transistor having a current path connecting the high-potential input terminal side and the output terminal side, and a transistor pair including a low-potential transistor having a current path connecting the low-potential input terminal side and the output terminal side, and includes a switching control step of inputting control signals to each of the high-potential transistor and the low-potential transistor and converting direct current power into alternating current power by switching the conduction states of the respective current paths complementarily to each other. In the switching control, it is adjusted so that the time change rate of the current of each current path is larger than the time change rate of the voltage of each current path.

[0012] In addition, any combination of the above components, as well as those obtained by converting the expression of the present invention among methods, apparatuses, systems, recording media, computer programs, etc., are also effective as aspects of the present invention.

Advantages of the Invention

[0013] According to the present invention, the switching losses of inverters and converters can be reduced.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

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Figure 10

Embodiments for Carrying Out the Invention

[0015] FIG. 1 schematically shows the configuration of a motor device 1 including an embodiment of the present invention. The motor device 1 includes an inverter 10 that generates AC power based on DC power, and a motor 20 that is driven by the AC power.

[0016] The motor 20 is a three-phase brushless motor having three-phase coils 20U, 20V, and 20W for U-phase, V-phase, and W-phase. The inverter 10 includes a U-phase inverter 10U that generates U-phase AC power, a V-phase inverter 10V that generates V-phase AC power, and a W-phase inverter 10W that generates W-phase AC power, corresponding to each phase of the motor 20. The inverters 10U, 10V, and 10W for each phase apply AC power with different phases to the coils 20U, 20V, and 20W of each phase based on the rotational position of the rotor detected by the hall elements H1, H2, and H3 of the motor 20, thereby generating a rotating magnetic field. Desired rotational power is obtained from the rotor that rotates by this rotating magnetic field. Note that the motor 20 may be another type of motor driven by an AC voltage. Also, the number of phases of the motor 20 is not limited to three and may be any natural number of two or more.

[0017] Since the configurations of the inverters 10U, 10V, and 10W for each phase are common, hereinafter, they will be collectively referred to as the inverter 10 as appropriate, and their configurations, operations, and effects will be described. The inverter 10 that generates AC power includes a high-potential input terminal 11 to which a high DC power supply potential Vdd is input, a low-potential input terminal 12 to which a low DC power supply potential Vss is input, and an output terminal 13 provided between the high-potential input terminal 11 and the low-potential input terminal 12 that outputs an AC voltage that varies between Vdd and Vss. Vss may be any potential lower than Vdd, but hereinafter, for simplicity of explanation, Vss is set to zero. And the DC operating voltage Vdd - Vss = Vdd input between both input terminals 11 and 12 of the inverter 10 is represented as V DC as well.

[0018] FIG. 2 schematically shows the configuration of the inverter 10 (U-phase inverter 10U). The inverter 10 includes a first transistor pair 14, a second transistor pair 15, a first driver 16, a second driver 17, a connection path 18, and a controller 100.

[0019] The first transistor pair 14 includes a first high-potential transistor 14H having a current path connecting the high-potential input terminal 11 side and the output terminal 13 side, and a first low-potential transistor 14L having a current path connecting the low-potential input terminal 12 side and the output terminal 13 side. Each of the transistors 14H and 14L is an N-channel MOSFET, and a channel formed between the source and the drain in response to a control signal input to the gate electrode by the first driver 16 constitutes the current path. Note that these transistors 14H and 14L and other transistors described later are not limited to N-channel MOSFETs, and all or part of them may be constituted by P-channel MOSFETs. Also, these transistors are not limited to MOSFETs, and may be constituted by PNP-type or NPN-type bipolar transistors, or IGBTs (Insulated Gate Bipolar Transistors).

[0020] The second transistor pair 15 includes a second high-potential transistor 15H having a current path connecting the high-potential input terminal 11 side and the first high-potential transistor 14H side, and a second low-potential transistor 15L having a current path connecting the low-potential input terminal 12 side and the first low-potential transistor 14L side. That is, between the output terminal 13 and the high-potential input terminal 11, the first high-potential transistor 14H and the second high-potential transistor 15H are connected in series in the direction from the output terminal 13 toward the high-potential input terminal 11, and between the output terminal 13 and the low-potential input terminal 12, the first low-potential transistor 14L and the second low-potential transistor 15L are connected in series in the direction from the output terminal 13 toward the low-potential input terminal 12. Each of the transistors 15H and 15L is a MOSFET, and a channel formed between the source and the drain in response to a control signal input to the gate electrode by the second driver 17 constitutes the current path.

[0021] The first driver 16 includes a first high-potential driver 16H that inputs a control signal to the gate electrode of the first high-potential transistor 14H under the control of the controller 100, and a first low-potential driver 16L that inputs a control signal to the gate electrode of the first low-potential transistor 14L under the control of the controller 100. The first switching control is performed to convert DC power into AC power by complementarily switching the conduction states of the current paths of the respective transistors 14H and 14L. Here, "complementarily switching" means controlling so that the on / off states of the respective transistors 14H and 14L are opposite to each other. That is, when the transistor 14H is on, the transistor 14L is off; when the transistor 14H is off, the transistor 14L is on; when the transistor 14H switches from on to off, the transistor 14L switches from off to on; and when the transistor 14H switches from off to on, the transistor 14L switches from on to off.

[0022] The second driver 17 includes a second high-potential driver 17H that inputs a control signal to the gate electrode of the second high-potential transistor 15H under the control of the controller 100, and a second low-potential driver 17L that inputs a control signal to the gate electrode of the second low-potential transistor 15L under the control of the controller 100. The second switching control is performed to convert DC power into AC power by complementarily switching the conduction states of the current paths of the respective transistors 15H and 15L. The meaning of "complementarily switching" is the same as that of the first driver 16 described above, which means controlling so that the on / off states of the respective transistors 15H and 15L are opposite to each other. Although details will be described later, the second switching control by the second driver 17 is performed at a timing shifted by a predetermined time from the timing of the first switching control by the first driver 16.

[0023] The connection path 18 connects the connection part 18H between the first high-potential transistor 14H and the second high-potential transistor 15H and the connection part 18L between the first low-potential transistor 14L and the second low-potential transistor 15L to each other. A capacitor 181 with a capacitance value C, which is one aspect of the voltage fluctuation suppression element, is provided in the connection path 18.

[0024] Before explaining the operation of the inverter 10 with the above configuration, the detailed configurations of the drivers 16H, 16L, 17H, and 17L will be explained with reference to FIG. 3. Since the configurations of the drivers 16H, 16L, 17H, and 17L are common, they will be collectively referred to as the driver 30 and explained in FIG. 3. FIGS. 3(A) and 3(B) show two configuration examples of the driver 30.

[0025] The driver 30 according to the first configuration example in FIG. 3(A) has a pair of voltage input terminals 31 to which a voltage v corresponding to the gate / source voltage of the transistor to be driven is input, an operational amplifier 32 connected to the voltage input terminal 31 on the gate side, a gate resistor 33 with a resistance value R provided between the operational amplifier 32 and the gate electrode, and a mirror capacitor 34 with a capacitance value C provided on a branch line that branches from between the gate resistor 33 and the gate electrode and is connected to the drain of the transistor. Note that the input voltage v GS is generated by the controller 100 in FIG. 2. G The gate resistor 33 functions as a current adjustment element that adjusts the channel current when the on / off state of the transistor is switched. Specifically, the resistance value R M can adjust the time change rate di / dt of the current when the on / off state of the transistor is switched. If the resistance value R GS is increased, di / dt becomes smaller, and if the resistance value R

[0026] is decreased, di / dt becomes larger. As will be described later, in this embodiment, it is preferable to increase di / dt and it is preferable to decrease the resistance value R G . According to the simulation conducted by the present inventor, for a realistic resistance value R G , if it is increased, di / dt becomes smaller, and if it is decreased, di / dt becomes larger. As will be described later, in this embodiment, it is preferable to increase di / dt, and it is preferable to decrease the resistance value R G . According to the simulation conducted by the present inventor, for a realistic resistance value R G , it is preferable to increase di / dt and it is preferable to decrease the resistance value R GWithin the range, substantially infinite di / dt can be achieved. In this case, when the transistor turns on and off, the current instantaneously switches between the minimum value and the maximum value. Such a steep current change can substantially reduce the current switching time to zero, thereby reducing the switching loss associated with the current switching. During the operation of the driver 30, the resistance value R G may be made variable to precisely control di / dt when the transistor turns on and off.

[0027] The mirror capacitor 34 functions as a voltage regulating element that regulates the voltage of the channel when the transistor turns on and off. Specifically, with the capacitance value C M , the time change rate dv / dt of the voltage when the transistor turns on and off can be adjusted. To reduce the switching loss associated with the voltage switching, it is preferable to increase dv / dt as well as di / dt as described above. However, if dv / dt is increased too much, the risk of dielectric breakdown of the coils 20U, 20V, and 20W of the motor 20 increases. Therefore, the capacitance value C M is set to an appropriate value to increase dv / dt as much as possible within the range where the risk of dielectric breakdown is acceptable. As a result, such restricted dv / dt is adjusted to be smaller than unrestricted di / dt. During the operation of the driver 30, the capacitance value C M may be made variable to precisely control dv / dt when the transistor turns on and off.

[0028] The operational amplifier 32 can function as both a current regulating element and a voltage regulating element by appropriately adjusting its configuration and parameters. The adjustment targets for di / dt and dv / dt are as described above. Di / dt is made as large as possible (substantially infinite), and dv / dt is made as large as possible within the range where the risk of dielectric breakdown is acceptable.

[0029] The driver 30 according to the second configuration example of FIG. 3(B) has a voltage v corresponding to the gate / source voltage of the transistor to be driven GSA pair of voltage input terminals 31 to which input is applied, an operational amplifier 32 connected to the voltage input terminal 31 on the gate side, and a gate resistor 33 having a resistance value R provided between the operational amplifier 32 and the gate electrode G and a capacitor 35 having a capacitance value C provided on a branch line branched from between the voltage input terminal 31 on the gate side and the operational amplifier 32 and connected to the drain of the transistor. V It includes a capacitor 35. It is different only in the capacitor 35 from the first configuration example in FIG. 3(A).

[0030] Similar to the mirror capacitor 34, the capacitor 35 functions as a voltage adjustment element that adjusts the voltage of the channel when the on / off of the transistor is switched. Specifically, with the capacitance value C V it is possible to adjust the rate of change of voltage with respect to time dv / dt when the on / off of the transistor is switched. Similar to the capacitance value C M of the mirror capacitor 34, the capacitance value C V may also be made variable during the operation of the driver 30 to finely control dv / dt when the on / off of the transistor is switched. Furthermore, according to the capacitor 35, not only the output waveform of the driver 30 but also the output waveform of the entire inverter 10 can be adjusted, so that the radiation of unnecessary electromagnetic noise can be suppressed.

[0031] The operation of the inverter 10 having the above configuration is shown in FIG. 4. FIG. 4(A) shows the configuration of the inverter 10 shown in FIG. 2. FIG. 4(B) shows the case where the current i U flowing through the output terminal 13 is positive. FIG. 4(C) shows the case where the current i U flowing through the output terminal 13 is negative. The current i U is taken as positive when flowing out from the output terminal 13 in FIG. 4(A) and negative when flowing into the output terminal 13. FIGS. 4(B1) and (C1) show the voltage and current appearing at the output terminal 13. FIGS. 4(B2) and (C2) show the voltage and current of the channels between the source / drain of the four transistors 15H, 14H, 14L, and 15L. FIGS. 4(B3) and (C3) show the switching losses of the inverter 10.

[0032] First, the current i UAn explanation will be given for FIG. 4(B) when [the value] is positive. FIG. 4(B1) shows the voltage and current that appear at the output terminal 13 when the inverter 10 performs one switching operation. Although details will be described later, the voltage is a trapezoidal pulse of height V DC (Vdd - Vss), and the magnitude of the current i U is constant. From time 0 s to the rise time t R , the high-potential-side transistors 15H, 14H are sequentially turned on, and complementarily, the low-potential-side transistors 15L, 14L are sequentially turned off, so that the voltage at the output terminal 13 linearly increases from 0 V to V DC . After the rise time t R , until the switch-off time dT SW , the magnitude of the voltage is constant at V DC . That is, the switch-off time dT SW determines the width of the trapezoidal voltage pulse. By changing the width or duty ratio of each voltage pulse according to a general pulse-width modulation (PWM) technique, an AC voltage of a desired frequency is generated. From the switch-off time dT SW to the fall time t F , the high-potential-side transistors 15H, 14H are sequentially turned off, and complementarily, the low-potential-side transistors 15L, 14L are sequentially turned on, so that the voltage at the output terminal 13 linearly decreases from V DC to 0 V.

[0033] When explaining the operation of the four transistors 15H, 14H, 14L, 15L in FIG. 4(B2), it is divided into six sections i-vi shown in FIG. 4(B3). FIG. 5 shows the conduction states and current paths of the respective transistors in each section i-vi. The current i U flowing through the output terminal in FIG. 5 is positive in all sections and has a constant magnitude as shown in FIG. 4(B1).

[0034] In section i before time 0 s, the transistors 15H, 14H are in the off state, and the transistors 14L, 15L are in the on state. Since the low-potential input terminal 12 is conducting with the output terminal 13, the voltage at the output terminal 13 is 0 V. The voltage V DCSince it is evenly divided by transistors 15H and 14H, the voltage of each transistor is V DC / 2. The voltages of transistors 14L and 15L in the on state are 0V, and current i U flows.

[0035] In section ii from time 0s to t R / 2, the on / off states of transistors 15H and 15L are switched complementarily. That is, transistor 15H switches from the off state to the on state, and transistor 15L switches from the on state to the off state. This corresponds to the second switching control of the present invention. At this time, as shown in FIG. 5, as transistor 15H switches to the on state, the current from the high-potential input terminal 11 flows through transistor 15H and then through the capacitor 181 of the connection path 18 and the on-state transistor 14L to the output terminal 13. Looking at the voltages and currents of transistors 15H and 15L in FIG. 4(B2), the time change rate of the voltage dv / dt is (V DC / 2) / (t R / 2)=V DC / t R , and the time change rate of the current di / dt is infinite. That is, the voltage changes linearly over the interval ii from 0s to t R / 2, while the current instantaneously switches at the start time 0s of interval ii. The configuration for adjusting dv / dt and di / dt in this way was described with reference to FIG. 3.

[0036] In section iii from time t R / 2 to t R , the on / off states of transistors 14H and 14L are switched complementarily. That is, transistor 14H switches from the off state to the on state, and transistor 14L switches from the on state to the off state. This corresponds to the first switching control of the present invention. At this time, as shown in FIG. 5, as transistor 14H switches to the on state, the current from the high-potential input terminal 11 flows through the on-state transistor 15H and then through transistor 14H. Looking at the voltages and currents of transistors 14H and 14L in FIG. 4(B2), the time change rate of the voltage dv / dt is (V DC / (2) / (t R / 2)=V DC / t R and the time change rate di / dt of the current is infinite. That is, the voltage is at t R / 2 to t R while linearly changing over the interval iii, the current instantaneously switches at the start time t R / 2 of the interval iii.

[0037] As described above, in interval ii, the second switching control is performed in which the on / off states of transistors 15H and 15L are complementarily switched, and in the subsequent interval iii, the first switching control is performed in which the on / off states of transistors 14H and 14L are complementarily switched. That is, the second switching control is performed before the first switching control. In other words, the timing of the switching control of each transistor pair is earlier for the transistor pair farther from the output terminal 13 (the second transistor pair 15 in this example). Also, the timing of the second switching control and the first switching control is shifted by the transient time t R / 2 of the voltage switching of each channel of transistors 15H and 15L in the second switching control (interval ii). As a result, after the voltages of transistors 15H and 15L are switched in interval ii, the voltages of transistors 14H and 14L are switched immediately in interval iii. Further, as described above, the time change rates dv / dt of the voltages in intervals ii and iii are equal to each other as V DC / t R . As a result, as shown in FIG. 4(B1), a voltage waveform smoothly connected at time t R / 2 is obtained. If the timing of the second switching control and the first switching control is shifted by more than t R / 2, the output voltage remains near the intermediate voltage V R / 2 from the end time t DC / 2 of the second switching control to the start time of the first switching control, so it does not become a single trapezoidal voltage pulse as shown in FIG. 4(B1), but 0V, V DC / 2, V DCIt becomes a three-level stepped voltage pulse. Even with a stepped voltage pulse, there is no problem with the operation of the inverter 10. However, when there is a need to shape the voltage pulse waveform, it is preferable to use a trapezoidal voltage pulse. The trapezoidal voltage pulse takes two levels of 0V and V DC Originally, it should be three levels of 0V, V DC / 2, and V DC Here, it is pseudo-two levels of 0V and V DC by making what should be three levels into two levels. Therefore, this is also referred to as "three-level / pseudo two-level control".

[0038] At time t R to dT SW In section iv, the state at the end of section iii is maintained as it is, and a voltage pulse with a desired width based on pulse width modulation is formed. In section iv, transistors 15H and 14H are in the on state, and transistors 14L and 15L are in the off state. Since the high potential input terminal 11 is conducting with the output terminal 13, the voltage of the output terminal 13 is V DC The voltage V DC between the low potential input terminal 12 and the output terminal 13 is evenly divided by transistors 14L and 15L. Therefore, the voltage of each transistor is V DC / 2. The voltage of the on transistors 15H and 14H is 0V, and a current i U flows.

[0039] At time dT SW to dT SW +t F / 2 in section v, the on-off states of transistors 15H and 15L are switched complementarily. That is, transistor 15H switches from the on state to the off state, and transistor 15L switches from the off state to the on state. Similar to section ii, this also corresponds to the second switching control of the present invention. At this time, as shown in FIG. 5, similar to section iv, transistors 15H and 14H have a current i U flowing. Looking at the voltage and current of transistors 15H and 15L in FIG. 4(B2), the time change rate of the voltage dv / dt is (V DC / 2) / (t F / 2)=V DC / t Fand the time change rate di / dt of the current is infinite. That is, the voltage is dT SW ~dT SW +t F / 2, it changes linearly across the interval v, while the current instantaneously switches at the end time dT SW +t F / 2.

[0040] At time dT SW +t F / 2 to dT SW +t F in the interval vi, the on / off states of the transistors 14H and 14L switch complementarily. That is, the transistor 14H switches from the on state to the off state, and the transistor 14L switches from the off state to the on state. Similar to the interval iii, this also corresponds to the first switching control of the present invention. At this time, as shown in FIG. 5, the current from the low potential input terminal 12 flows through the on-state transistor 15L, and flows through the output terminal 13 via the capacitor 181 of the connection path 18 and the transistor 14H. Looking at the voltage and current of the transistors 14H and 14L in FIG. 4(B2), the time change rate dv / dt of the voltage is (V DC / 2) / (t F / 2)=V DC / t F and the time change rate di / dt of the current is infinite. That is, the voltage is dT SW +t F / 2 to dT SW +t F in the interval vi, it changes linearly, while the current instantaneously switches at the end time dT SW +t F .

[0041] As described above, in section v, second switching control is performed in which the on / off states of transistors 15H and 15L are complementarily switched, and in subsequent section vi, first switching control is performed in which the on / off states of transistors 14H and 14L are complementarily switched. That is, similar to the above-described sections ii and iii, the second switching control is performed before the first switching control. In other words, the timing of the switching control of each transistor pair is earlier for the transistor pair farther from the output terminal 13 (the second transistor pair 15 in this example). Also, the timing of the second switching control and the first switching control is shifted by the transient time t F / 2 of the voltage switching of each channel of transistors 15H and 15L in the second switching control (section v). As a result, after the voltages of transistors 15H and 15L are switched in section v, the voltages of transistors 14H and 14L are switched in section vi without a gap. Further, as described above, the time change rate dv / dt of the voltage in sections v and vi is V DC / t F and is equal to each other. As a result, as shown in FIG. 4(B1), a voltage waveform smoothly connected at time dT SW +t F / 2 is obtained. That is, the above-described "3-level / pseudo 2-level control" is realized not only on the rising side but also on the falling side of the voltage pulse.

[0042] FIG. 4(B3) shows the switching loss of the inverter 10. The switching loss is the sum of the power consumed by each of the transistors 15H, 14H, 14L, and 15L through one switching operation of the inverter 10. Power is consumed when the voltage and current of each of the transistors 15H, 14H, 14L, and 15L shown in FIG. 4(B2) are not both zero. Specifically, transistor 15H consumes power in section ii, transistor 14H consumes power in section iii, transistor 15H consumes power in section v, and transistor 14H consumes power in section vi. As shown in FIG. 4(B3), the power consumed in the four sections ii, iii, v, and vi has heights of V DC ×i UIt is represented by the area of a right triangle of / 2. The length of the base of each right triangle is t in intervals ii and iii R / 2, and t in intervals v and vi F / 2. Therefore, the switching loss, which is the sum of the areas of these four right triangles, is t R ×V DC ×i U / 4 + t F ×V DC ×i U / 4. Here, the reason why the power consumed by each transistor 15H and 14H is represented by the area of a right triangle is that the time change rate di / dt of the current in each of intervals ii, iii, v, and vi is infinite, and the current instantaneously changes in a direction perpendicular to the time axis. As a comparative example, the case where di / dt is not infinite is shown by a dotted line. In this case, additional switching losses occur adjacent to the right-angled portions of each of the above right triangles. Therefore, the switching loss can be reduced by making di / dt infinite.

[0043] Above, the operation of the inverter 10 when the current i U is positive has been described with reference to FIGS. 4(B) and 5. FIGS. 4(C) and 6 show the operation of the inverter 10 when the current i U is negative. Since the basic content is common, the description will be omitted as appropriate.

[0044] FIG. 4(C1) shows the voltage and current that appear at the output terminal 13 when the inverter 10 performs one switching operation. The voltage is a trapezoidal pulse with a height of V DC , and the magnitude of the current i U is constant (since i U is negative, it is shown with a minus sign in the positive region). From time 0 s to the rise time t R , the transistors 15H and 14H on the high-potential side are sequentially turned on, and complementarily, the transistors 15L and 14L on the low-potential side are sequentially turned off, so that the voltage at the output terminal 13 linearly increases from 0 V to V DC . After the rise time t R , until the switch-off time dT SW , the magnitude of the voltage is V DCis constant. The switch-off time dT SW to the fall time t F During this period, the transistors 15H and 14H on the high-potential side are sequentially turned off, and complementarily, the transistors 15L and 14L on the low-potential side are sequentially turned on, so that the voltage at the output terminal 13 decreases linearly from V DC to 0V.

[0045] When explaining the operation of the four transistors 15H, 14H, 14L, and 15L in Fig. 4(C2), it is divided into six sections i-vi shown in Fig. 4(C3). Fig. 6 shows the conduction states and current paths of the respective transistors in each section i-vi. The current i flowing through the output terminal in Fig. 6 U is negative in all sections and has a constant magnitude as shown in Fig. 4(C1).

[0046] In section i before time 0s, the transistors 15H and 14H are in the off state, and the transistors 14L and 15L are in the on state. Since the low-potential input terminal 12 is conducting with the output terminal 13, the voltage at the output terminal 13 is 0V. The voltage V DC between the high-potential input terminal 11 and the output terminal 13 is evenly divided by the transistors 15H and 14H, so the voltage of each transistor is V DC / 2. The voltages of the on-state transistors 14L and 15L are 0V, and the current i U flows.

[0047] In section ii from time 0s to t R / 2, the on / off states of the transistors 15H and 15L are complementarily switched. That is, the transistor 15H switches from the off state to the on state, and the transistor 15L switches from the on state to the off state. This corresponds to the second switching control of the present invention. At this time, as shown in Fig. 6, the transistors 14L and 15L are the same as in section i, and the current i U flows. Looking at the voltages and currents of the transistors 15H and 15L in Fig. 4(C2), the time change rate dv / dt of the voltage is (V DC / 2) / (t R / 2)=V DC / t Rand the time change rate di / dt of the current is infinite. That is, the voltage changes linearly over the interval ii from 0 s to t R / 2, while the current instantaneously switches at the end time t R / 2 of the interval ii.

[0048] At time t R / 2 to t R in the interval iii up to, the on / off states of the transistors 14H and 14L switch complementarily. That is, the transistor 14H switches from the off state to the on state, and the transistor 14L switches from the on state to the off state. This corresponds to the first switching control of the present invention. At this time, as shown in FIG. 6, the current from the output terminal 13 flows through the transistor 14L and flows through the high potential input terminal 11 via the capacitor 181 of the connection path 18 and the on-state transistor 15H. Looking at the voltage and current of the transistors 14H and 14L in FIG. 4(C2), the time change rate dv / dt of the voltage is (V DC / 2) / (t R / 2)=V DC / t R and the time change rate di / dt of the current is infinite. That is, the voltage changes linearly over the interval iii from t R / 2 to t R while the current instantaneously switches at the end time t R of the interval iii.

[0049] As described above, in the interval ii, the second switching control in which the on / off states of the transistors 15H and 15L switch complementarily is performed, and in the subsequent interval iii, the first switching control in which the on / off states of the transistors 14H and 14L switch complementarily is performed. That is, the second switching control is performed before the first switching control. Also, the timings of the second switching control and the first switching control are such that in the second switching control (interval ii), the transient time t RIt is only shifted by / 2. As a result, after the voltages of transistors 15H and 15L are switched in section ii, the voltages of transistors 14H and 14L are switched in section iii without a gap. Furthermore, as described above, the time change rate dv / dt of the voltages in sections ii and iii is V DC / t R and is equal to each other. As a result, as shown in Fig. 4(C1), a voltage waveform smoothly connected at time t R / 2 is obtained (3-level / pseudo 2-level control).

[0050] At time t R to dT SW in section iv up to, the state at the end of section iii is maintained as it is, and a voltage pulse with a desired width based on pulse width modulation is formed. In section iv, transistors 15H and 14H are in the on state, and transistors 14L and 15L are in the off state. Since the high potential input terminal 11 is conducting with the output terminal 13, the voltage of the output terminal 13 is V DC . The voltage V DC between the low potential input terminal 12 and the output terminal 13 is evenly divided by transistors 14L and 15L, so the voltage of each transistor is V DC / 2. The voltages of the on-state transistors 15H and 14H are 0V, and a current i U flows.

[0051] At time dT SW to dT SW +t F / 2 in section v, the on / off states of transistors 15H and 15L are switched complementarily. That is, transistor 15H switches from the on state to the off state, and transistor 15L switches from the off state to the on state. Similar to section ii, this also corresponds to the second switching control of the present invention. At this time, as shown in Fig. 6, as transistor 15L switches to the on state, the current from the output terminal 13 flows through the on-state transistor 14H and flows through the high potential input terminal 11 via the capacitor 181 of the connection path 18 and transistor 15L. Looking at the voltages and currents of transistors 15H and 15L in Fig. 4(C2), the time change rate dv / dt of the voltage is (V DC / 2) / (tF / 2) = V DC / t F and the time change rate di / dt of the current is infinite. That is, the voltage is dT SW ~dT SW +t F varies linearly across the interval v of / 2, while the current instantaneously switches at the start time dT of the interval v SW .

[0052] Time dT SW +t F From / 2 to dT SW +t F In the interval vi up to, the on / off states of transistors 14H and 14L switch complementarily. That is, transistor 14H switches from the on state to the off state, and transistor 14L switches from the off state to the on state. Similar to interval iii, this also corresponds to the first switching control of the present invention. At this time, as shown in FIG. 6, as transistor 14L switches to the on state, the current from output terminal 13 flows through transistor 14L and the on-state transistor 15L to the low-potential input terminal 12. Looking at the voltages and currents of transistors 14H and 14L in FIG. 4(C2), the time change rate dv / dt of the voltage is (V DC / 2) / (t F / 2) = V DC / t F and the time change rate di / dt of the current is infinite. That is, the voltage is dT SW +t F / 2 ~ dT SW +t F varies linearly across the interval vi of, while the current instantaneously switches at the start time dT + t / 2 of the interval vi SW +t F .

[0053] As described above, in the interval v, the second switching control is performed in which the on / off states of the transistors 15H and 15L are complementarily switched, and in the subsequent interval vi, the first switching control is performed in which the on / off states of the transistors 14H and 14L are complementarily switched. That is, similar to the above-described intervals ii and iii, the second switching control is performed before the first switching control. Also, the timings of the second switching control and the first switching control are shifted by the transient time t F / 2 of the voltage switching of each channel of the transistors 15H and 15L in the second switching control (interval v). As a result, after the voltages of the transistors 15H and 15L are switched in the interval v, the voltages of the transistors 14H and 14L are switched in the interval vi without any delay. Further, as described above, the time change rates dv / dt of the voltages in the intervals v and vi are equal to each other at V DC / t F . As a result, as shown in FIG. 4(C1), a voltage waveform smoothly connected at the time dT SW +t F / 2 is obtained. That is, the above-described "3-level / pseudo 2-level control" is realized not only on the rising side but also on the falling side of the voltage pulse.

[0054] FIG. 4(C3) shows the switching loss of the inverter 10. The switching loss is the sum of the power consumed by each of the transistors 15H, 14H, 14L, and 15L through one switching operation of the inverter 10. Power is consumed when both the voltage and current of each of the transistors 15H, 14H, 14L, and 15L shown in FIG. 4(C2) are not zero. Specifically, the transistor 15L consumes power in the interval ii, the transistor 14L consumes power in the interval iii, the transistor 15L consumes power in the interval v, and the transistor 14L consumes power in the interval vi. As shown in FIG. 4(C3), the power consumed in the four intervals ii, iii, v, and vi is represented by the area of a right triangle with a height of V DC ×(-i U ) / 2. The length of the base of each right triangle is t R / 2 in the intervals ii and iii, and t FIt is / 2. Therefore, the switching loss, which is the sum of the areas of these four right triangles, is t R ×V DC ×(-i U ) / 4 + t F ×V DC ×(-i U ) / 4. Here, the reason why the power consumed by each of the transistors 15L and 14L is represented by the area of a right triangle is that the time change rate di / dt of the current in each of the sections ii, iii, v, and vi is infinite, and the current instantaneously changes in a direction perpendicular to the time axis.

[0055] In the inverter 10 described above, the capacitor 181 provided in the connection path 18 stabilizes the operation by maintaining the voltage between the connection portion 18H of the high - potential - side transistor and the connection portion 18L of the low - potential - side transistor near the intermediate voltage V DC / 2. That is, the capacitor 181 functions as a voltage - fluctuation - suppressing element that suppresses fluctuations in the voltage between the high - potential - side connection portion 18H and the low - potential - side connection portion 18L. FIGS. 7(B4) and (C4) show the current and voltage of the capacitor 181. (B2), (B3), (C2), and (C3) in this figure are shown for reference as the same as those in FIG. 4.

[0056] When the current i U is positive, in FIG. 7(B4), current flows through the capacitor 181 in sections ii and vi. As shown in FIG. 5, in section ii, current flows from the high - potential - side connection portion 18H toward the low - potential - side connection portion 18L, and the capacitor 181 accumulates charge. In section vi, current flows from the low - potential - side connection portion 18L toward the high - potential - side connection portion 18H, and the capacitor 181 discharges charge. The voltage between the electrodes of the capacitor 181 oscillates and slightly changes between the charge - accumulation state and the charge - discharge state around the intermediate voltage V DC / 2. In an ideal situation, the magnitude of the current flowing through the capacitor 181 in sections ii and vi and the flowing times t R / 2 and t F / 2 are respectively equal, and through one switching operation of the inverter 10, the charge of the capacitor 181 does not increase or decrease.

[0057] Current i U In FIG. 7(C4) when the current i is negative, current flows through the capacitor 181 in sections iii and v. As shown in FIG. 6, in section iii, current flows from the low-potential connection part 18L to the high-potential connection part 18H, and the capacitor 181 discharges charge. In section v, current flows from the high-potential connection part 18H to the low-potential connection part 18L, and the capacitor 181 accumulates charge. The voltage between the electrodes of the capacitor 181 oscillates and slightly changes between the charge accumulation state and the charge discharge state around the intermediate voltage V DC / 2. In an ideal situation, the magnitude of the current flowing through the capacitor 181 in sections iii and v and the flowing time t R / 2, t F / 2 are equal respectively, and through one switching operation of the inverter 10, the charge of the capacitor 181 does not increase or decrease.

[0058] FIG. 8 shows an example where there is an increase or decrease in the charge of the capacitor 181 through one switching operation of the inverter 10. (B1)-(B4) and (C1)-(C4) in this figure correspond to FIGS. 4 and 7.

[0059] Current i U FIG. 7(B1) representing the output of the inverter 10 when the current i is positive, and FIG. 7(C1) representing the output of the inverter 10 when the current i is negative. In these figures, the voltage pulse waveform is distorted from the trapezoidal shape in FIG. 4. As shown in FIGS. 7(B2) and (C2) showing the voltage and current of each transistor, the transition time t U required for the second switching control = t a = t aR = t aF is different from the transition time t b required for the first switching control = t bR = t bF . This figure shows the case where t a is larger than t b , but when t a is smaller than t b , the voltage pulse waveform is also distorted from the trapezoidal shape.

[0060] Current i U In FIG. 7(B4) where the current i is positive, the time t during which the capacitor 181 accumulates charge aR is longer than the time t during which the capacitor 181 discharges charge bF Therefore, through one switching operation of the inverter 10, the capacitor 181 accumulates excessive charge. The current i U In FIG. 7(C4) where the current i is negative, the time t during which the capacitor 181 accumulates charge aF is longer than the time t during which the capacitor 181 discharges charge bR Therefore, through one switching operation of the inverter 10, the capacitor 181 accumulates excessive charge. In either case, through one switching operation of the inverter 10, the voltage between the electrodes of the capacitor 181 shifts in the positive direction, which may hinder the stable operation of the inverter 10. Although not shown, conversely to this figure, when t a is smaller than t b the capacitor 181 discharges excessive charge through one switching operation of the inverter 10, so the voltage between the electrodes of the capacitor 181 shifts in the negative direction, which may hinder the stable operation of the inverter 10.

[0061] FIG. 9 shows two configuration examples of a correction device 40 that corrects the imbalance in the switching times as described above. These correction devices 40 control the transient time t DC of the first voltage switching and the transient time t b = t bR = t bF and the transient time t a = t aR = t aF so that the center voltage of the capacitor 181 becomes the intermediate voltage V a and t b which is the target voltage. The controller 100 in FIG. 2 controls the input voltage v GS to each driver 30 in FIG. 3 according to these transient times t

[0062] In the correction device 40 according to the first configuration example in FIG. 9(A), the target voltage providing unit 41 is the target voltage V of the capacitor 181DC provides 1 / 2. The voltage error calculation unit 42 calculates the error between the measured voltage v of the capacitor 181 and the target voltage V c / 2. In the first configuration example, the voltage v of the capacitor 181 is constantly measured, and the high-frequency component thereof is removed by the low-pass filter 421 and supplied to the voltage error calculation unit 42. The voltage error calculated by the voltage error calculation unit 42 is supplied to the voltage controller 431 and converted into the charge correction amount of the capacitor 181. The divider 432 divides the charge correction amount by the absolute value of the output current i DC obtained from the absolute value calculation unit 433 and converts it into the time correction amount. The regulation unit 434 performs a cap process based on a predetermined upper limit value so that the absolute value of this time correction amount does not become excessive, and sets it as the final time correction amount δt. c U

[0063] The switching time correction unit 44 corrects at least one of the transient time t of the first voltage switching and the transient time t of the second voltage switching based on the voltage error calculated by the voltage error calculation unit 42. In this configuration example, a first correction unit 441 that calculates a correction value for the first transient time t and a second correction unit 442 that calculates a correction value for the second transient time t are provided. The first correction unit 441 subtracts the time correction amount δt from the rise time / fall time t of the inverter 10 b (=t a ) and multiplies the result by 1 / 2 to obtain the correction value for the first transient time t. That is, t b =(t a -δt) / 2. The second correction unit 442 adds the time correction amount δt to the rise time / fall time t of the inverter 10 RF (=t R =t F ) and multiplies the result by 1 / 2 to obtain the correction value for the second transient time t. That is, t b =(t b +δt) / 2. At this time, the first transient time t RF and the second transient time t RF (=t R =t F ) a a RF b and the second transient time t​​​​​a The sum is equal to the rise time / fall time t of the inverter 10. RF Therefore, the switching time correction unit 44 distributes t RF to the first transient time t b and the second transient time t a When distributing, it can be said that the capacitor 181 specifies an optimal distribution ratio that results in the target voltage V DC / 2 by the time correction amount δt.

[0064] In the correction device 40 according to the second configuration example of FIG. 9(B), the sample / hold circuit 422 supplies the voltage v c of the capacitor 181 acquired based on the trigger signal to the voltage error calculation unit 42. The voltage error calculated by the voltage error calculation unit 42 is multiplied by the capacitance value C of the capacitor 181 and converted into a charge correction amount of the capacitor 181. The rest is the same as the first configuration example of FIG. 9(A).

[0065] As described above, the present invention has been described based on the embodiments. It is understood by those skilled in the art that the embodiments are examples, and various modifications are possible for each combination of their respective components and each processing process, and such modifications are also within the scope of the present invention.

[0066] In the embodiment, the inverter 10 that outputs AC power based on the input DC power has been described. Conversely, the present invention can also be applied to a converter that outputs DC power based on the input AC power. In the configuration of the inverter 10 in FIG. 2, the output terminal 13 is used as an input terminal to which AC power is input, and the high-potential input terminal 11 and the low-potential input terminal 12, which were originally there, are used as a high-potential output terminal and a low-potential output terminal that output DC power, respectively, thereby realizing the basic configuration of the converter.

[0067] In the embodiment, with reference to FIGS. 2 and 4, the "three-level / pseudo two-level control" of the inverter 10 has been described. That is, 0V, V DC / 2, V DCUsing two transistor pairs 14 and 15 capable of outputting three levels of voltage, 0V and V shown in FIGS. 4(B1) and (C1) DC Two-level voltage pulses were pseudo-formed. According to the present invention, with N being any natural number of 2 or more and M being any natural number of 2 or more and N-1 or less, N-level / pseudo-M-level control can be realized. Two-level control with N = 2 can be realized with one transistor pair. Four-level control with N = 4 can be realized with three transistor pairs. Thus, N-level control can be realized with N-1 transistor pairs. In this case, similar to FIG. 4 showing an example of three-level control, an N-level voltage can be output by performing switching control in order from the transistor pair farthest from the output terminal 13. In order to pseudo-form an M-level voltage pulse based on such an N-level voltage, as described with respect to FIG. 4, the switching control of adjacent transistor pairs may be continuously performed and the voltage pulses may be smoothly connected.

[0068] A more specific configuration is as follows. Let n (=N-1) be an integer of 2 or more. The first to n high-potential transistors connected in series from the output terminal 13 toward the high-potential input terminal 11, and the first to n low-potential transistors connected in series from the output terminal 13 toward the low-potential input terminal 12 constitute the first to n transistor pairs. First to n drivers for performing switching control on the first to n transistor pairs are provided. First to n-1 connection paths for connecting the high-potential side connection part and the low-potential side connection part of adjacent transistor pairs to each other are provided. In the first to n-1 connection paths, first to n-1 voltage fluctuation suppression elements for suppressing voltage fluctuations between the high-potential side connection part and the low-potential side connection part are provided. The switching control of adjacent transistor pairs is performed at a timing shifted by a predetermined time. Specifically, the timing of the switching control of each transistor pair is made earlier for the transistor pair farther from the output terminal 13. In particular, it is preferable to shift the timing of the switching control of adjacent transistor pairs by the transient time of the voltage switching of the current paths of the high-potential transistor and the low-potential transistor constituting each transistor pair.

[0069] In an embodiment, by providing a capacitor 181 as a voltage fluctuation suppressing element in a connection path 18, the voltage between its electrodes is maintained near V DC / 2, and the operation of the inverter 10 is stabilized. However, the same effect can be obtained by using a diode as a voltage fluctuation suppressing element instead of the capacitor 181. A configuration example thereof is shown in FIG. 10. In the connection path 18 of this inverter 10, two diodes 182L and 182H that allow current to flow in the direction from the connection portion 18L of the low-potential-side transistor to the connection portion 18H of the high-potential-side transistor are provided in series. The connection portion 19 of these two diodes 182L and 182H is connected to an intermediate potential (Vdd - Vss) / 2 = V DC / 2. Since the intermediate potential is connected to a constant potential, the diodes 182L and 182H function as voltage fluctuation suppressing elements that suppress fluctuations in the voltage between the high-potential-side connection portion 18H and the low-potential-side connection portion 18L.

[0070] In the embodiment, an example in which each transistor pair is composed of one high-potential transistor and one low-potential transistor has been described. However, the high-potential transistor and the low-potential transistor that constitute each transistor pair may each be plural. As an example of a technique in which a pair is constituted by a plurality of high-potential transistors and a plurality of low-potential transistors, a modular multilevel converter (MMC) is known. This is to provide a group of circuit elements called cells having the same configuration in pairs on the high-potential side and the low-potential side. Each cell includes a plurality of transistors connected in series and / or in parallel. By adjusting so that di / dt becomes larger than dv / dt in the switching control of these transistors, effects such as reduction of switching loss equivalent to that described in the embodiment can be obtained.

[0071] Note that the functional configurations of the respective devices described in the embodiments can be realized by hardware resources, software resources, or the cooperation of hardware resources and software resources. As hardware resources, a processor, ROM, RAM, and other LSIs can be used. As software resources, programs such as an operating system and applications can be used.

[0072] Among the embodiments disclosed in this specification, for those in which a plurality of functions are provided in a distributed manner, some or all of the plurality of functions may be provided in an aggregated manner. Conversely, for those in which a plurality of functions are provided in an aggregated manner, some or all of the plurality of functions can be provided in a distributed manner. Regardless of whether the functions are aggregated or distributed, it only needs to be configured so that the object of the invention can be achieved.

Industrial Applicability

[0073] The present invention relates to control technologies for inverters and converters.

Explanation of Reference Numerals

[0074] 1 Motor device, 10 Inverter, 11 High-potential input terminal, 12 Low-potential input terminal, 13 Output terminal, 14 First transistor pair, 15 Second transistor pair, 16 First driver, 17 Second driver, 18 Connection path, 20 Motor, 30 Driver, 32 Operational amplifier, 33 Gate resistor, 34 Miller capacitor, 35 Capacitor, 40 Correction device, 41 Target voltage providing unit, 42 Voltage error calculation unit, 44 Switching time correction unit, 181 Capacitor, 182 Diode.

Claims

1. including a high-potential input terminal at a high potential and a low-potential input terminal at a low potential, an input terminal to which DC power is input between both input terminals, an output terminal for outputting AC power, a transistor pair including a high-potential transistor having a current path connecting the high-potential input terminal side and the output terminal side, and a low-potential transistor having a current path connecting the low-potential input terminal side and the output terminal side, a driver that inputs a control signal to each of the high-potential transistor and the low-potential transistor, and performs switching control to convert the DC power into the AC power by switching the conduction states of the respective current paths complementarily to each other, the driver includes at least one of a current adjustment element for adjusting the current of each current path and a voltage adjustment element for adjusting the voltage of each current path, the current adjustment element adjusts the time change rate of the current of each current path to be substantially infinite in the switching control, the transistor pair includes first to nth transistor pairs each constituted by first to nth high-potential transistors connected in series from the output terminal toward the high-potential input terminal and first to nth low-potential transistors connected in series from the output terminal toward the low-potential input terminal, where n is an integer of 2 or more, the driver includes first to nth drivers that perform the switching control on the first to nth transistor pairs, first to n−1 connection paths that mutually connect the high-potential side connection part and the low-potential side connection part of adjacent transistor pairs, and first to n−1 voltage fluctuation suppression elements provided in each connection path for suppressing the voltage fluctuation between the high-potential side connection part and the low-potential side connection part, the switching control of adjacent transistor pairs is performed at timings shifted by a predetermined time, The predetermined time is the transient time of voltage switching of the current paths of the high-potential transistor and the low-potential transistor that constitute the transistor pair in the switching control. Inverter.

2. The timing of the switching control of each transistor pair is earlier for the transistor pair farther from the output terminal. The inverter according to claim 1.

3. The voltage fluctuation suppression element is a capacitor. The inverter according to claim 1 or 2.

4. A target voltage providing unit that provides a target voltage of the capacitor, A voltage error calculating unit that calculates an error of the measured voltage of the capacitor from the target voltage, Based on the error, a switching time correcting unit that corrects the transient time of voltage switching of the current paths of the high-potential transistor and the low-potential transistor that constitute at least one of the adjacent transistor pairs The inverter according to claim 3, comprising:

5. The voltage fluctuation suppression element is two diodes connected in series that conduct current in a direction from the connection portion on the low-potential side to the connection portion on the high-potential side, The connection portion of the two diodes is connected to an intermediate potential between the high potential and the low potential. The inverter according to claim 1 or 2.

6. An output terminal that includes a high-potential high-potential output terminal and a low-potential low-potential output terminal and outputs DC power between both output terminals, An input terminal to which AC power is input, A transistor pair including a high-potential transistor having a current path connecting the high-potential output terminal side and the input terminal side, and a low-potential transistor having a current path connecting the low-potential output terminal side and the input terminal side, A driver that inputs control signals to each of the high-potential transistor and the low-potential transistor, and performs switching control to convert the AC power into DC power by complementarily switching the conduction states of the respective current paths. The driver includes at least one of a current adjustment element that adjusts the current of each current path and a voltage adjustment element that adjusts the voltage of each current path. In the switching control, the current adjustment element adjusts the time change rate of the current of each current path to be substantially infinite. The transistor pair includes first to n-th transistor pairs each constituted by first to n high-potential transistors connected in series from the input terminal toward the high-potential output terminal and first to n low-potential transistors connected in series from the input terminal toward the low-potential output terminal, where n is an integer of 2 or more. The driver includes first to n drivers that perform the switching control on the first to n transistor pairs. First to n−1 connection paths that connect the high-potential side connection part and the low-potential side connection part of adjacent transistor pairs to each other. First to n−1 voltage fluctuation suppression elements provided in each connection path to suppress voltage fluctuations between the high-potential side connection part and the low-potential side connection part. The switching control of adjacent transistor pairs is performed at timings shifted by a predetermined time. The predetermined time is the transient time of voltage switching of the current paths of the high-potential transistor and the low-potential transistor that constitute the transistor pair in the switching control. Converter.

7. A motor driven by polyphase AC power having different phases from each other. A plurality of inverters that generate the AC power of each phase. Each inverter Includes a high-potential input terminal at a high potential and a low-potential input terminal at a low potential, and an input terminal to which DC power is input between both input terminals. An output terminal for outputting the AC power, A high-potential transistor having a current path connecting the high-potential input terminal side and the output terminal side, and a transistor pair including a low-potential transistor having a current path connecting the low-potential input terminal side and the output terminal side, A driver that inputs a control signal to each of the high-potential transistor and the low-potential transistor, and performs switching control to convert the DC power into the AC power by switching the conduction states of the respective current paths complementarily to each other, The driver includes at least one of a current adjustment element for adjusting the current of each current path and a voltage adjustment element for adjusting the voltage of each current path, The current adjustment element adjusts the time change rate of the current of each current path to be substantially infinite in the switching control, The transistor pair includes first to nth transistor pairs constituted by first to n high-potential transistors connected in series from the output terminal toward the high-potential input terminal and first to n low-potential transistors connected in series from the output terminal toward the low-potential input terminal, where n is an integer of 2 or more, The driver includes first to n drivers that perform the switching control on the first to n transistor pairs, First to n - 1 connection paths that mutually connect the connection portions on the high-potential side and the connection portions on the low-potential side of adjacent transistor pairs, First to n - 1 voltage fluctuation suppression elements provided in each connection path for suppressing the voltage fluctuation between the connection portion on the high-potential side and the connection portion on the low-potential side, The switching control of adjacent transistor pairs is performed at timings shifted by a predetermined time, The predetermined time is the transient time of the voltage switching of the respective current paths of the high-potential transistor and the low-potential transistor constituting the transistor pair in the switching control, A driving device.

8. An input terminal including a high-potential input terminal at a high potential and a low-potential input terminal at a low potential, and into which DC power is input between both input terminals, An output terminal that outputs AC power, A transistor pair including a high-potential transistor having a current path connecting the high-potential input terminal side and the output terminal side, and a low-potential transistor having a current path connecting the low-potential input terminal side and the output terminal side A control method for an inverter including: A switching control step of inputting control signals to the high-potential transistor and the low-potential transistor respectively by a driver, and converting the DC power into the AC power by switching the conduction states of the respective current paths complementarily to each other, In the switching control step, adjusting the time change rate of the current in each current path to be substantially infinite, The transistor pair includes first to nth transistor pairs each including first to nth high-potential transistors connected in series from the output terminal toward the high-potential input terminal, and first to nth low-potential transistors connected in series from the output terminal toward the low-potential input terminal, where n is an integer of 2 or more, The driver includes first to nth drivers that perform the switching control step on the first to nth transistor pairs, First to n−1 connection paths that mutually connect the high-potential side connection portion and the low-potential side connection portion of adjacent transistor pairs, First to n−1 voltage fluctuation suppression elements provided in each connection path for suppressing voltage fluctuations between the high-potential side connection portion and the low-potential side connection portion, The switching control steps of adjacent transistor pairs are performed at timings shifted by a predetermined time, The predetermined time is the transient time of voltage switching of the current paths of the high-potential transistor and the low-potential transistor constituting the transistor pair in the switching control step A control method for an inverter. Claim 9 An input terminal including a high-potential input terminal at a high potential and a low-potential input terminal at a low potential, to which DC power is input between the two input terminals, An output terminal for outputting AC power, A transistor pair including a high-potential transistor having a current path connecting the high-potential input terminal side and the output terminal side, and a low-potential transistor having a current path connecting the low-potential input terminal side and the output terminal side A control program for an inverter including: A switching control step of inputting control signals to each of the high-potential transistor and the low-potential transistor by a driver, and converting the DC power into the AC power by switching the conduction states of the respective current paths complementarily to each other, and causing a computer to execute the step; In the switching control step, adjusting the time change rate of the current in each current path to be substantially infinite; The transistor pair includes first to nth transistor pairs each constituted by first to n high-potential transistors connected in series from the output terminal toward the high-potential input terminal and first to n low-potential transistors connected in series from the output terminal toward the low-potential input terminal, where n is an integer of 2 or more. The driver includes first to n drivers that perform the switching control step on the first to n transistor pairs. First to n - 1 connection paths that mutually connect connection portions on the high-potential side and connection portions on the low-potential side of adjacent transistor pairs; First to n - 1 voltage fluctuation suppression elements provided in the respective connection paths for suppressing voltage fluctuations between the connection portions on the high-potential side and the connection portions on the low-potential side; The switching control steps of adjacent transistor pairs are performed at timings shifted by a predetermined time. The predetermined time is the transient time of voltage switching of the current paths of the high-potential transistor and the low-potential transistor constituting the transistor pair in the switching control step. Inverter control program.

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