Semiconductor device

Abstract

To provide a semiconductor device capable of improving electrical characteristics.SOLUTION: A semiconductor device 401 includes: a semiconductor layer 402 that has a first principal surface 403 at one side and a second principal surface 404 at the other side; an active region 406 that has an active principal surface 461 that is a part of the first principal surface 403; an outside region 407 that has an outside principal surface 462 formed at a height position at the second principal surface 404 side with respect to a height position of the active principal surface 461 and that is a part of the first principal surface 403, the outside region being provided outside the active region 406; a trench gate structure 451 formed on the active principal surface 461 in the active region 406; and a field region 473 that is formed on a surface layer part of the outside principal surface 462 in the outside region 407, having a conductivity type different from that of the semiconductor layer 402.SELECTED DRAWING: Figure 55

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a gate trench and a source trench. The gate trench and the source trench are formed on the surface of an n-type semiconductor layer at substantially the same depth. A p-type body region is formed in a region between the gate trench and the source trench in a surface layer portion of the surface of the semiconductor layer.

[0003] An n-type source region is formed in a surface layer portion of the p-type body region. A p-type breakdown voltage holding region (deep well region) is formed in a region along the source trench in the semiconductor layer. A gate electrode is embedded in the gate trench via a gate insulating layer. A source electrode is embedded in the source trench. A drain electrode is connected to the back surface of the semiconductor layer.

[0004]

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] One embodiment provides a semiconductor device capable of improving electrical characteristics.

Means for Solving the Problems

[0007] ​One embodiment provides a semiconductor device including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; an active region having an active main surface as a part of the first main surface; an outer region having an outer main surface as a part of the first main surface formed at a height position on the second main surface side with respect to the height position of the active main surface, the outer region being provided outside the active region; a trench gate structure formed on the active main surface in the active region; and a field region formed in a surface layer portion of the outer main surface in the outer region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008]

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[0009] Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

[0010] FIG. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.

[0011] The semiconductor device 1 is a switching device including a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). Referring to FIGS. 1 and 2, the semiconductor device 1 has an n-type SiC semiconductor layer 2 including a SiC (silicon carbide) single crystal.

[0012] The SiC semiconductor layer 2 includes a first main surface 3 on one side and a second main surface 4 on the other side. In this embodiment, the SiC semiconductor layer 2 has a stacked structure including a SiC semiconductor substrate 5 including a SiC single crystal and an n- - type SiC epitaxial layer 6 including a SiC single crystal. The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 5. The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 6.

[0013] A drain electrode 7 is connected to the second main surface 4 of the SiC semiconductor layer 2. The SiC semiconductor substrate 5 is formed as an n- + type drain region. The SiC epitaxial layer 6 is formed as an n- - type drain drift region.

[0014] The n-type impurity concentration of the SiC semiconductor substrate 5 is 1.0×10 18cm -3 1.0×10 or more above 21 cm -3 It may be below. The n-type impurity concentration of the SiC epitaxial layer 6 is 1.0×10 15 cm -3 1.0×10 or more above 17 cm -3 It may be below. Hereinafter, in this specification, "impurity concentration" refers to the peak value of the impurity concentration.

[0015] Referring to FIGS. 1 and 2, a plurality of trench gate structures 10 and a plurality of trench source structures 11 are formed on the first main surface 3 of the SiC semiconductor layer 2. The trench gate structures 10 and the trench source structures 11 are alternately formed at intervals along an arbitrary first direction X.

[0016] The trench gate structures 10 and the trench source structures 11 are formed in a strip shape extending along a second direction Y orthogonal to the first direction X. The first direction X is preferably the [11-20] direction, and the second direction Y is preferably the [1-100] direction.

[0017] On the first main surface 3 of the SiC semiconductor layer 2, a stripe structure including a plurality of trench gate structures 10 and a plurality of trench source structures 11 is formed. With respect to the first direction X, the distance between the trench gate structures 10 and the trench source structures 11 may be 0.3 μm or more and 1.0 μm or less.

[0018] Each trench gate structure 10 includes a gate trench 12, a gate insulating layer 13, and a gate electrode layer 14. In FIG. 1, for clarity, the gate electrode layer 14 is shown by hatching.

[0019] The gate trench 12 is formed by digging down the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4 side. The gate trench 12 includes a first side wall 15 and a first bottom wall 16.

[0020] The gate insulating layer 13 is formed in a film shape along the first side wall 15, the first bottom wall 16, and the corner 17 connecting the first side wall 15 and the first bottom wall 16 of the gate trench 12. The gate insulating layer 13 partitions a concave space within the gate trench 12.

[0021] The gate insulating layer 13 may contain silicon oxide. The gate insulating layer 13 may contain at least one of impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride in addition to silicon oxide.

[0022] The gate electrode layer 14 is embedded in the gate trench 12 with the gate insulating layer 13 interposed therebetween. More specifically, the gate electrode layer 14 is embedded in the concave space partitioned by the gate insulating layer 13.

[0023] The gate electrode layer 14 may contain conductive polysilicon. The gate electrode layer 14 may contain at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten in addition to conductive polysilicon.

[0024] Each trench source structure 11 includes a source trench 18, a barrier formation layer 19, a source electrode layer 20, and a p - -type deep well region 21. In FIG. 1, for clarity, the source electrode layer 20 is shown by hatching. The deep well region 21 is also referred to as a breakdown voltage holding region.

[0025] The source trench 18 is formed by digging down the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4 side. The source trench 18 includes a second side wall 22 and a second bottom wall 23.

[0026] The second sidewall 22 of the source trench 18 includes a first wall portion 24 and a second wall portion 25. The first wall portion 24 of the source trench 18 is located on the first main surface 3 side of the SiC semiconductor layer 2 with respect to the first bottom wall 16 of the gate trench 12. That is, the first wall portion 24 is a portion that overlaps the gate trench 12 in the lateral direction parallel to the first main surface 3 of the SiC semiconductor layer 2.

[0027] The second wall portion 25 of the source trench 18 is located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the first bottom wall 16 of the gate trench 12. That is, the second wall portion 25 is a portion that is located in the region on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the first bottom wall 16 of the gate trench 12 in the source trench 18.

[0028] In the thickness direction of the SiC semiconductor layer 2, the length of the second wall portion 25 of the source trench 18 is greater than the length of the first wall portion 24 of the source trench 18. The second bottom wall 23 of the source trench 18 is located in the region between the first bottom wall 16 of the gate trench 12 and the second main surface 4 of the SiC semiconductor layer 2 in the thickness direction of the SiC semiconductor layer 2.

[0029] In this form, the second bottom wall 23 of the source trench 18 is located in the SiC epitaxial layer 6. The second bottom wall 23 of the source trench 18 may be located in the SiC semiconductor substrate 5.

[0030] The barrier formation layer 19 is formed in a film shape along the second sidewall 22, the second bottom wall 23, and the corner portion 26 connecting the second sidewall 22 and the second bottom wall 23 of the source trench 18. The barrier formation layer 19 partitions a concave space in the source trench 18.

[0031] The barrier formation layer 19 is made of a material different from the conductive material of the source electrode layer 20. The barrier formation layer 19 has a potential barrier higher than the potential barrier between the source electrode layer 20 and the deep well region 21.

[0032] The conductive barrier forming layer may be employed as the barrier forming layer 19. The conductive barrier forming layer may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0033] The insulating barrier forming layer may be employed as the barrier forming layer 19. The insulating barrier forming layer may contain at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. In FIG. 2, an example in which the insulating barrier forming layer is formed as the barrier forming layer 19 is shown.

[0034] More specifically, the barrier forming layer 19 is silicon oxide. Preferably, the barrier forming layer 19 and the gate insulating layer 13 are formed of the same material. In this case, preferably, the thickness of the barrier forming layer 19 and the thickness of the gate insulating layer 13 are the same. When the barrier forming layer 19 and the gate insulating layer 13 are formed of silicon oxide, the barrier forming layer 19 and the gate insulating layer 13 can be simultaneously formed by a thermal oxidation treatment method.

[0035] The source electrode layer 20 is embedded in the concave space of the source trench 18 with the barrier forming layer 19 interposed therebetween. The source electrode layer 20 may contain conductive polysilicon. The source electrode layer 20 may be n-type polysilicon doped with an n-type impurity, or p-type polysilicon doped with a p-type impurity.

[0036] In addition to conductive polysilicon, the source electrode layer 20 may contain at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0037] The source electrode layer 20 may be formed of the same conductive material as the gate electrode layer 14. In this case, the gate electrode layer 14 and the source electrode layer 20 can be formed simultaneously. Of course, the source electrode layer 20 may be formed of a conductive material different from that of the gate electrode layer 14.

[0038] The deep well region 21 is formed in a region along the source trench 18 in the SiC semiconductor layer 2. The p-type impurity concentration of the deep well region 21 is 1.0×10 17 cm -3 or more and may be 1.0×10 19 cm -3 or less.

[0039] The deep well region 21 is formed in a region along the second side wall 22 of the source trench 18 in the SiC semiconductor layer 2. The deep well region 21 is formed in a region along the second bottom wall 23 of the source trench 18 in the SiC semiconductor layer 2.

[0040] In this form, the deep well region 21 is continuously formed in a region along the second side wall 22, the corner portion 26, and the second bottom wall 23 of the source trench 18 in the SiC semiconductor layer 2. The deep well region 21 includes a first region 27 and a second region 28 in a portion along the second side wall 22 of the source trench 18.

[0041] The first region 27 of the deep well region 21 is formed along the first wall portion 24 of the second side wall 22 of the source trench 18. The second region 28 of the deep well region 21 is formed along the second wall portion 25 of the second side wall 22 of the source trench 18. In the thickness direction of the SiC semiconductor layer 2, the length of the second region 28 of the deep well region 21 is greater than the length of the first region 27 of the deep well region 21.

[0042] The thickness of the portion along the second bottom wall 23 of the source trench 18 in the deep well region 21 may be equal to or greater than the thickness of the portion along the second side wall 22 of the source trench 18 in the deep well region 21.

[0043] The portion along the second bottom wall 23 of the source trench 18 in the deep well region 21 may be located within the SiC semiconductor substrate 5 across the boundary region between the SiC semiconductor substrate 5 and the SiC epitaxial layer 6.

[0044] In the SiC semiconductor layer 2, in the portion along the second bottom wall 23 of the source trench 18, p-type impurities are implanted along the normal direction of the first main surface 3 of the SiC semiconductor layer 2. On the other hand, in the portion along the second side wall 22 of the source trench 18 in the SiC semiconductor layer 2, p-type impurities are implanted in a state inclined with respect to the first main surface 3 of the SiC semiconductor layer 2.

[0045] Therefore, in the SiC semiconductor layer 2, in the portion along the second bottom wall 23 of the source trench 18, p-type impurities are implanted at a deeper position than in the portion along the second side wall 22 of the source trench 18. As a result, in the deep well region 21, a difference in thickness occurs between the portion along the second bottom wall 23 of the source trench 18 and the portion along the second side wall 22 of the source trench 18.

[0046] On the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2, a p - -type body region 30 is formed. The body region 30 is formed in the region between the gate trench 12 and the source trench 18. The body region 30 is formed in a strip shape extending along the second direction Y in a plan view.

[0047] The body region 30 is exposed from the first side wall 15 of the gate trench 12 and the second side wall 22 of the source trench 18. The body region 30 is continuous with the first region 27 of the deep well region 21.

[0048] The p-type impurity concentration of the body region 30 may be 1.0×10 16 cm -3 or more and 1.0×10 19 cm -3 or less. The p-type impurity concentration of the body region 30 may be approximately equal to the p-type impurity concentration of the deep well region 21. The p-type impurity concentration of the body region 30 may be higher than the p-type impurity concentration of the deep well region 21.

[0049] On the surface layer portion of the body region 30, n +A source region 31 of a type is formed. The source region 31 is formed in a region along the first side wall 15 of the gate trench 12 in the surface layer portion of the body region 30. The source region 31 is exposed from the first side wall 15 of the gate trench 12.

[0050] The source region 31 may be formed in a strip shape extending along the second direction Y in a plan view. Although not shown, the source region 31 may include a portion exposed from the second side wall 22 of the source trench 18.

[0051] The width WS of the source region 31 may be 0.2 μm or more and 0.6 μm or less (for example, about 0.4 μm). In this form, the width WS is the width along the first direction X in the source region 31. The n-type impurity concentration of the source region 31 is 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0052] In the surface layer portion of the body region 30, a p + -type contact region 32 is formed. The contact region 32 is formed in a region along the second side wall 22 of the source trench 18 in the surface layer portion of the body region 30. The contact region 32 is exposed from the second side wall 22 of the source trench 18.

[0053] The contact region 32 may be connected to the source region 31. The contact region 32 may be formed in a strip shape extending along the second direction Y in a plan view. The contact region 32 may include a portion exposed from the first side wall 15 of the adjacent gate trench 12.

[0054] The width WC of the contact region 32 may be 0.1 μm or more and 0.4 μm or less (for example, about 0.2 μm). In this form, the width WC is the width along the first direction X in the contact region 32. The p-type impurity concentration of the contact region 32 is 1.0×10 18 cm -3 or more and 1.0×10 21cm -3 It may be as follows.

[0055] An insulating layer 40 is formed on the first main surface 3 of the SiC semiconductor layer 2. The insulating layer 40 collectively covers a plurality of trench gate structures 10. A contact hole 41 is formed in the insulating layer 40. The contact hole 41 selectively exposes the trench source structure 11, the source region 31, and the contact region 32.

[0056] A main surface source electrode 42 is formed on the insulating layer 40. The main surface source electrode 42 enters the contact hole 41 from above the insulating layer 40. The main surface source electrode 42 is electrically connected to the source electrode layer 20, the source region 31, and the contact region 32 within the contact hole 41.

[0057] The main surface source electrode 42 may be formed of the same conductive material as the source electrode layer 20. The main surface source electrode 42 may be formed of a conductive material different from the source electrode layer 20.

[0058] In this form, the source electrode layer 20 includes n-type polysilicon or p-type polysilicon, and the main surface source electrode 42 includes a metal material containing aluminum or aluminum as a main component. The main surface source electrode 42 may include at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0059] The main surface source electrode 42 may be composed of an electrode layer integrally formed with the source electrode layer 20. In this case, the source electrode layer 20 and the main surface source electrode 42 may be formed through a common process.

[0060] Hereinafter, the dimensions of the trench gate structure 10 and the dimensions of the trench source structure 11 will be specifically described.

[0061] The trench gate structure 10 has an aspect ratio D1 / W1. The aspect ratio D1 / W1 of the trench gate structure 10 is defined by the ratio of the depth D1 of the trench gate structure 10 to the width W1 of the trench gate structure 10.

[0062] The width W1 is, in this form, the width along the first direction X in the trench gate structure 10. The aspect ratio D1 / W1 of the trench gate structure 10 is also the aspect ratio of the gate trench 12.

[0063] The aspect ratio D1 / W1 of the trench gate structure 10 may be 0.25 or more and 15.0 or less. The width W1 of the trench gate structure 10 may be 0.2 μm or more and 2.0 μm or less (for example, about 0.4 μm). The depth D1 of the trench gate structure 10 may be 0.5 μm or more and 3.0 μm or less (for example, about 1.0 μm).

[0064] The trench source structure 11 has an aspect ratio D2 / W2. The aspect ratio D2 / W2 of the trench source structure 11 is the ratio of the depth D2 of the trench source structure 11 to the width W2 of the trench source structure 11.

[0065] The width W2 of the trench source structure 11 is the sum of the width WST of the source trench 18, the first width Wα of the deep well region 21, and the second width Wβ of the deep well region 21 (W2 = WST + Wα + Wβ).

[0066] The width WST is, in this form, the width along the first direction X in the source trench 18. The first width Wα is, in this form, the width along the first direction X of the portion along the second sidewall 22 on one side of the source trench 18 in the deep well region 21. The second width Wβ is, in this form, the width along the first direction X of the portion along the second sidewall 22 on the other side of the source trench 18 in the deep well region 21.

[0067] The aspect ratio D2 / W2 of the trench source structure 11 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 may be 0.5 or more and 18.0 or less.

[0068] The ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 may be 1.5 or more and 4.0 or less. By increasing the depth D2 of the trench source structure 11, the breakdown voltage holding effect by the SJ (Super Junction) structure can also be enhanced.

[0069] The width W2 of the trench source structure 11 may be 0.6 μm or more and 2.4 μm or less (for example, about 0.8 μm). The depth D2 of the trench source structure 11 may be 1.5 μm or more and 11 μm or less (for example, about 2.5 μm). The width W2 of the trench source structure 11 may be equal to the width W1 of the trench gate structure 10. The width W2 of the trench source structure 11 may be different from the width W1 of the trench gate structure 10.

[0070] In the trench source structure 11, the source trench 18 has an aspect ratio DST / WST. The aspect ratio DST / WST of the source trench 18 is the ratio of the depth DST of the source trench 18 to the width WST of the source trench 18.

[0071] The aspect ratio DST / WST of the source trench 18 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio DST / WST of the source trench 18 may be 0.5 or more and 18.0 or less.

[0072] The width WST of the source trench 18 may be 0.2 μm or more and 2.0 μm or less (for example, about 0.4 μm). The width WST of the source trench 18 may be equal to the width W1 of the gate trench 12 (WST = W1).

[0073] When the width WST of the source trench 18 or the width W1 of the gate trench 12 varies along the depth direction, the width WST and the width W1 are defined as the width of the opening portion. The depth DST of the source trench 18 may be 1.0 μm or more and 10 μm or less (for example, about 2.0 μm).

[0074] The ratio of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 (gate trench 12) is preferably 2 or more. The ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 may exceed 4.0. In this case, it is necessary to pay attention to the durability of the resist mask used when forming the source trench 18 by an etching method.

[0075] For example, when the depth D1 of the trench gate structure 10 is about 3.0 μm and the ratio DST / D1 exceeds 4, it is assumed that the resist mask approaches or exceeds the durability limit by etching. When the resist mask exceeds the durability limit, unwanted etching of the SiC semiconductor layer 2 is caused.

[0076] Therefore, the ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 is preferably more than 1.0 and 4.0 or less. If the ratio DST / D1 is within this range, the source trench 18 can be appropriately formed.

[0077] FIG. 3 is a cross-sectional view for explaining the operation of the semiconductor device 1 of FIG. 1. In FIG. 3, the same reference numerals are given to the same structures as in FIG. 2.

[0078] In the semiconductor device 1, a pn junction 45 is formed in the boundary region between the SiC semiconductor layer 2 and the deep well region 21. When the semiconductor device 1 switches from the on state to the off state, a depletion layer 46 spreads from the pn junction 45 toward the SiC semiconductor layer 2. In FIG. 3, the depletion layer 46 is indicated by a two-dot chain line.

[0079] The deep well region 21 includes a first region 27 and a second region 28. The first region 27 is formed along a first wall portion 24 of a second side wall 22 of the source trench 18. The second region 28 is formed along a second wall portion 25 of the second side wall 22 of the source trench 18.

[0080] The depletion layer 46 from the pn junction 45 extends in the SiC semiconductor layer 2 in a region closer to the first main surface 3 than the first bottom wall 16 of the gate trench 12. The depletion layer 46 from the pn junction 45 extends in the SiC semiconductor layer 2 in a region closer to the second main surface 4 than the first bottom wall 16 of the gate trench 12.

[0081] When the semiconductor device 1 switches from the on state to the off state, the current path of the short-circuit current flowing from the drain electrode 7 toward the source electrode layer 20 is constricted by the depletion layer 46. Thereby, the time until the semiconductor device 1 reaches breakdown can be delayed.

[0082] In particular, according to the semiconductor device 1, the aspect ratio D2 / W2 of the trench source structure 11 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 is 0.5 or more and 18.0 or less.

[0083] Moreover, the ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 is 1.5 or more and 4.0 or less. In the thickness direction of the SiC semiconductor layer 2, the length of the second region 28 of the deep well region 21 is larger than the length of the first region 27 of the deep well region 21.

[0084] Therefore, in the SiC semiconductor layer 2, the ratio of the area occupied by the depletion layer 46 extending in the region on the second main surface 4 side can be surely increased more than the ratio of the area occupied by the depletion layer 46 extending in the region on the first main surface 3 side. Thereby, the current path of the short-circuit current can be surely constricted in the region on the drain electrode 7 side.

[0085] The depletion layer 46 from the pn junction 45 may overlap the first bottom wall 16 of the gate trench 12. The depletion layer 46 on the second region 28 side of the deep well region 21 may overlap the first bottom wall 16 of the gate trench 12.

[0086] In this structure, the current path of the short-circuit current can be reliably narrowed in the region on the drain electrode 7 side. Of course, the depletion layer 46 on the first region 27 side of the deep well region 21 may overlap the first bottom wall 16 of the gate trench 12.

[0087] Furthermore, according to the semiconductor device 1, since the region occupied by the depletion layer 46 in the SiC semiconductor layer 2 can be increased, the feedback capacitance Crss can be reduced inversely proportionally. The feedback capacitance Crss is the electrostatic capacitance between the gate electrode layer 14 and the drain electrode 7.

[0088] As described above, according to the semiconductor device 1, the short-circuit resistance can be improved and the feedback capacitance Crss can be reduced.

[0089] Moreover, according to the semiconductor device 1, a barrier-forming layer 19 is formed in the source trench 18. The barrier-forming layer 19 has a potential barrier higher than the potential barrier between the deep well region 21 and the source electrode layer 20.

[0090] Therefore, even if the depletion layer 46 expanding from the pn junction 45 between the SiC semiconductor layer 2 and the deep well region 21 comes into contact with the inner wall surface of the source trench 18, the occurrence of punch-through can be suppressed. This makes it possible to suppress the leakage current caused by punch-through.

[0091] In the absence of the barrier-forming layer 19, punch-through tends to be more pronounced at the corners 26 of the source trench 18 because the depletion layer 46 extends from the second sidewall 22 of the source trench 18 further along the second bottom wall 23 of the source trench 18.

[0092] Therefore, in the semiconductor device 1, the inner wall surface of the source trench 18 including the corner portion 26 is covered with the barrier formation layer 19. Thereby, the occurrence of punch-through in the source trench 18 can be effectively suppressed.

[0093] According to the semiconductor device 1, from the viewpoint of the design related to the short-circuit withstand and the feedback capacitance Crss, the depletion layer 46 is formed in a relatively wide region in the SiC semiconductor layer 2, but the barrier formation layer 19 can appropriately suppress the leakage current caused by the depletion layer 46.

[0094] FIG. 4 is a graph showing the drain current-drain voltage characteristics of the semiconductor device 1 of FIG. 1. In FIG. 4, the vertical axis represents the drain current ID [A / cm 2 , and the horizontal axis represents the drain voltage VD [V]. The drain current ID is the current (short-circuit current) flowing between the drain electrode 7 and the source electrode layer 20.

[0095] In FIG. 4, a curve L1 and a curve L2 are shown. Both the curve L1 and the curve L2 are obtained by simulation. The curve L1 and the curve L2 show the change in the drain current ID when a drain voltage VD in a predetermined range is applied to the drain electrode 7. The drain voltage VD is changed in the range between 0 V and 1000 V.

[0096] The curve L1 shows the drain current-drain voltage characteristics of the semiconductor device according to the reference example. The curve L2 shows the drain current-drain voltage characteristics of the semiconductor device 1. The semiconductor device according to the reference example has the same structure as the semiconductor device 1 except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0097] Referring to the curve L1, in the semiconductor device according to the reference example, when the drain voltage VD exceeds 200 V, the drain current ID exceeds 15000 A / cm 2 . On the other hand, referring to the curve L2, in the semiconductor device 1, in the range where the drain voltage VD is between 0 V and 1000 V, the drain current ID is 15000 A / cm 2is less than.

[0098] In the semiconductor device 1, when the drain voltage VD is in the range of 400 V or more and 1000 V or less, the drain current ID is 10000 A / cm 2 or more and less than 15000 A / cm 2 and is within the range.

[0099] Looking at the case where the drain voltage VD is 600 V, the drain current ID of the semiconductor device 1 is reduced by about 45% compared to the drain current ID of the semiconductor device according to the reference example.

[0100] From this simulation result, it was confirmed that by forming the deep well region 21 along the source trench 18 deeper than the gate trench 12, the short-circuit withstand capacity can be significantly improved.

[0101] FIG. 5 is a graph showing the feedback capacitance-drain voltage characteristics of the semiconductor device 1 of FIG. 1. In FIG. 5, the vertical axis represents the feedback capacitance Crss [F / cm 2 , and the horizontal axis represents the drain voltage VD [V].

[0102] In FIG. 5, curve L3 and curve L4 are shown. Both curve L3 and curve L4 are obtained by simulation. Curve L3 and curve L4 show the change in the feedback capacitance Crss when a drain voltage VD in a predetermined range is applied to the drain electrode 7. The drain voltage VD is changed in the range between 0 V and 1000 V.

[0103] Curve L3 shows the feedback capacitance-drain voltage characteristics of the semiconductor device according to the reference example. Curve L4 shows the feedback capacitance-drain voltage characteristics of the semiconductor device 1. The semiconductor device according to the reference example has the same structure as the semiconductor device 1 except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0104] Referring to the curve L3, in the semiconductor device according to the reference example, the feedback capacitance Crss gradually decreases in the range where the drain voltage VD is from 1V to 10V. In the semiconductor device according to the reference example, in the range of the drain voltage VD from 1V to 10V, the reduction rate of the feedback capacitance Crss is about 25%.

[0105] On the other hand, in the semiconductor device 1, the feedback capacitance Crss rapidly decreases in the range where the drain voltage VD is from 1V to 10V. Looking at the case when the drain voltage VD is 10V, the feedback capacitance Crss of the semiconductor device 1 is reduced by about 95% compared to the feedback capacitance Crss of the semiconductor device according to the reference example. In the semiconductor device 1, in the range of the drain voltage VD from 1V to 10V, the reduction rate of the feedback capacitance Crss is from 95% to 99%.

[0106] From this simulation result, it was confirmed that by forming the deep well region 21 along the source trench 18 deeper than the gate trench 12, the feedback capacitance Crss can be significantly reduced. That is, it was confirmed that by reducing the feedback capacitance Crss, the switching speed can be significantly improved.

[0107] FIG. 6 is a cross-sectional view showing a semiconductor device 51 according to the second embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals are given and the description is omitted.

[0108] Referring to FIG. 6, the source region 31 is exposed from the first side wall 15 of the gate trench 12 and the second side wall 22 of the source trench 18. The contact region 32 is formed in the deep well region 21 in a region along the second bottom wall 23 of the source trench 18. The contact region 32 is exposed from the second bottom wall 23 of the source trench 18.

[0109] The contact region 32 may cover the entire second bottom wall 23 of the source trench. The p-type impurity concentration of the contact region 32 is higher than the p-type impurity concentration of the deep well region 21.

[0110] In FIG. 6, an example is shown in which the barrier forming layer 19 is a conductive barrier forming layer. The barrier forming layer 19 is formed along the inner wall surface of the source trench 18, and selectively exposes the contact region 32 from the second bottom wall 23 of the source trench 18.

[0111] More specifically, the barrier forming layer 19 includes a first portion 52 and a second portion 53. The first portion 52 of the barrier forming layer 19 covers the second side wall 22 of the source trench 18. The second portion 53 of the barrier forming layer 19 partially covers the second bottom wall 23 of the source trench 18.

[0112] The second portion 53 of the barrier forming layer 19 is continuous with the first portion 52 of the barrier forming layer 19. The second portion 53 of the barrier forming layer 19 extends along the second bottom wall 23 from the corner portion 26 of the source trench 18.

[0113] The second portion 53 of the barrier forming layer 19 exposes the central portion of the second bottom wall 23 of the source trench 18. The second portion 53 of the barrier forming layer 19 may be formed in an endless (annular) shape in plan view.

[0114] As described above, according to the semiconductor device 51, the same effects as those described for the semiconductor device 1 can be achieved. Further, according to the semiconductor device 51, even if the depletion layer 46 spreads along the second bottom wall 23 from the corner portion 26 of the source trench 18, the distance until the depletion layer 46 reaches the source electrode layer 20 can be extended by the barrier forming layer 19. Thereby, the occurrence of punch-through can be suppressed in the vicinity of the corner portion 26 of the source trench 18.

[0115] FIG. 7 is a cross-sectional view showing a semiconductor device 61 according to the third embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 51, the same reference numerals are given and the description thereof is omitted.

[0116] In the deep well region 21, an exposed portion 62 is formed to selectively expose the second bottom wall 23 of the source trench 18. More specifically, the second region 28 of the deep well region 21 is formed along the corner portion 26 of the source trench 18 so as to expose the central portion of the second bottom wall 23 of the source trench 18. The second region 28 of the deep well region 21 may be formed in an endless (annular) shape in plan view.

[0117] In this form, the contact region 32 is not formed. The contact region 32 may be formed in a region along the second side wall 22 of the source trench 18 in the surface layer portion of the body region 30.

[0118] The source electrode layer 20 forms a heterojunction with the SiC semiconductor layer 2 at the exposed portion 62 of the deep well region 21. Thereby, a heterojunction diode 63 is formed with the source electrode layer 20 as the anode and the SiC semiconductor layer 2 as the cathode.

[0119] The source electrode layer 20 may contain conductive polysilicon. Of course, as long as the heterojunction diode 63 is formed, the source electrode layer 20 may contain a conductive material other than conductive polysilicon.

[0120] A body diode 64 is formed at the pn junction between the SiC semiconductor layer 2 and the body region 30. The junction barrier of the heterojunction diode 63 is smaller than the diffusion potential of the body diode 64. The junction barrier of the heterojunction diode 63 may be 1.0 eV or more and 1.5 eV or less. The diffusion potential of the body diode 64 may be 2.8 eV or more and 3.2 eV or less.

[0121] As described above, the semiconductor device 61 can achieve the same effects as those described for the semiconductor device 51. Further, in the semiconductor device 61, when a reverse bias voltage is applied, current can preferentially flow through the heterojunction diode 63. As a result, the expansion of crystal defects in SiC in the SiC semiconductor layer 2 can be suppressed. Consequently, while improving the short-circuit withstand voltage and reducing the reverse transfer capacitance Crss, an increase in the on-resistance can be suppressed.

[0122] FIG. 8 is a cross-sectional view showing a semiconductor device 71 according to a fourth embodiment of the present invention. Hereinafter, the structures corresponding to those described for the semiconductor device 51 will be denoted by the same reference numerals, and the description thereof will be omitted.

[0123] The barrier formation layer 19 has a laminated structure including a plurality of barrier formation layers formed along the inner wall of the source trench 18. In this embodiment, the barrier formation layer 19 has a laminated structure including an insulating barrier formation layer 72 and a conductive barrier formation layer 73 laminated in this order from the inner wall of the source trench 18.

[0124] The insulating barrier formation layer 72 is formed in a film shape along the inner wall surface of the source trench 18. The insulating barrier formation layer 72 selectively exposes the contact region 32 from the second bottom wall 23 of the source trench 18.

[0125] More specifically, the insulating barrier formation layer 72 includes a first portion 74 and a second portion 75. The first portion 74 covers the second side wall 22 of the source trench 18. The second portion 75 selectively covers the second bottom wall 23 of the source trench 18.

[0126] The second portion 75 is continuous with the first portion 74. The second portion 75 extends along the second bottom wall 23 from the corner 26 of the source trench 18 so as to expose the central portion of the second bottom wall 23 of the source trench 18.

[0127] The insulating barrier formation layer 72 may contain at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0128] The conductive barrier formation layer 73 is formed in a film shape along the insulating barrier formation layer 72 so as to selectively expose the contact region 32 from the second bottom wall 23 of the source trench 18. The conductive barrier formation layer 73 contains a conductive material different from that of the source electrode layer 20.

[0129] The conductive barrier formation layer 73 may be formed of the same conductive material as that of the gate electrode layer 14. The conductive barrier formation layer 73 may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0130] As described above, according to the semiconductor device 71, the same effects as those described for the semiconductor device 51 can be achieved. Further, in the semiconductor device 71, the barrier formation layer 19 has a laminated structure including the insulating barrier formation layer 72 and the conductive barrier formation layer 73. Thereby, the occurrence of punch-through can be suppressed by the two layers of the insulating barrier formation layer 72 and the conductive barrier formation layer 73.

[0131] If the conductive material of the conductive barrier formation layer 73 is the same as that of the gate electrode layer 14, the gate electrode layer 14 and the conductive barrier formation layer 73 can be formed by the same process. Therefore, an increase in the number of man-hours can be suppressed.

[0132] FIG. 9 is a cross-sectional view showing a semiconductor device 81 according to the fifth embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 1, the same reference numerals are given and the description is omitted.

[0133] The barrier formation layer 19 includes a first portion 82 and a second portion 83. The first portion 82 of the barrier formation layer 19 covers the second side wall 22 of the source trench 18. The second portion 83 of the barrier formation layer 19 covers the second bottom wall 23 of the source trench 18.

[0134] The first portion 82 of the barrier forming layer 19 selectively has a sidewall contact hole 84 that exposes the SiC semiconductor layer 2 from the second sidewall 22 of the source trench 18. The first portion 82 covers the first wall portion 24 of the source trench 18 and exposes the second wall portion 25.

[0135] The first portion 82 may be formed so as to cross the boundary region between the SiC semiconductor layer 2 and the body region 30. The end portion on the second main surface 4 side in the first portion 82 may be formed in a region deeper than the bottom of the body region 30.

[0136] In the first portion 82, the end portion on the second main surface 4 side may be formed in a region shallower than the bottom of the body region 30. In the first portion 82, the end portion on the second main surface 4 side may be formed in a region between the bottom of the body region 30 and the bottom of the contact region 32. In these cases, the source electrode layer 20 is connected to at least the body region 30 within the source trench 18.

[0137] In the first portion 82, the end portion on the second main surface 4 side may be formed in a region between the first main surface 3 of the SiC semiconductor layer 2 and the bottom of the contact region 32. The barrier forming layer 19 may have only the second portion 83 without having the first portion 82. In these cases, the source electrode layer 20 is connected to the body region 30 and the contact region 32 within the source trench 18.

[0138] The second portion 83 of the barrier forming layer 19 is formed at a distance from the first portion 82 of the barrier forming layer 19. The second portion 83 is separated from the first portion 82. The second portion 83 may cover the corner portion 26 of the source trench 18.

[0139] The second portion 83 may expose the corner portion 26 of the source trench 18. The second portion 83 may cover the corner portion 26 of the source trench 18 and may also cover a part of the second sidewall 22 of the source trench 18.

[0140] The source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 within the source trench 18. As a result, a Schottky barrier diode 85 is formed with the source electrode layer 20 as the anode and the SiC semiconductor layer 2 as the cathode.

[0141] The source electrode layer 20 may be formed of the same conductive material as the main surface source electrode 42. The source electrode layer 20 and the main surface source electrode 42 may be formed of a metal material containing aluminum or aluminum as a main component.

[0142] The source electrode layer 20 and the main surface source electrode 42 may contain at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten. In this case, the gate electrode layer 14 is preferably formed of polysilicon (n-type polysilicon or p-type polysilicon).

[0143] The p-type deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the second bottom wall 23 of the source trench 18. The deep well region 21 may be continuously formed in the SiC semiconductor layer 2 in a region along the second side wall 22 and the corner 26 of the source trench 18 so as to expose the source electrode layer 20 from the second side wall 22 of the source trench 18.

[0144] That is, the deep well region 21 covers the second bottom wall 23 of the source trench 18. Also, the deep well region 21 covers the corner 26 connecting the second side wall 22 and the second bottom wall 23 of the source trench 18. The deep well region 21 may expose substantially the entire area of the second side wall 22 of the source trench 18 in the SiC semiconductor layer 2.

[0145] The deep well region 21 extends horizontally from the second bottom wall 23 of the source trench 18 in a direction parallel to the first main surface 3 of the SiC semiconductor layer 2. As a result, the deep well region 21 faces the body region 30 across a partial region of the SiC semiconductor layer 2 with respect to the normal direction of the first main surface 3 of the SiC semiconductor layer 2.

[0146] More specifically, the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 at a depth position between the body region 30 and the deep well region 21 with respect to the normal direction of the first main surface 3 of the SiC semiconductor layer 2.

[0147] Even more specifically, the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 in a region of the SiC semiconductor layer 2 sandwiched between the body region 30 and the deep well region 21 with respect to the normal direction of the first main surface 3 of the SiC semiconductor layer 2.

[0148] The width W2 of the trench source structure 11 may be the same as the width WST of the source trench 18. That is, both the first width Wα and the second width Wβ of the deep well region 21 may be zero.

[0149] As described above, according to the semiconductor device 81, the same effects as those described for the semiconductor device 1 can be achieved. Further, in the semiconductor device 81, when a reverse bias voltage is applied, current can be preferentially passed through the Schottky barrier diode 85. Thereby, the expansion of crystal defects of SiC in the SiC semiconductor layer 2 can be suppressed. As a result, while improving the short - circuit withstand capacity and reducing the reverse transfer capacitance Crss, an increase in the on - resistance can be suppressed.

[0150] In this embodiment, an example in which the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 within the sidewall contact hole 84 of the barrier formation layer 19 has been described. However, a form in which the barrier formation layer 19 (the first portion 82 and the second portion 83) is not formed may also be adopted.

[0151] FIG. 10 is a plan view of a semiconductor device 91 according to the sixth embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0152] Referring to FIG. 10, in this embodiment, the trench gate structure 10 is formed in a lattice pattern in a plan view. The trench source structure 11 may be formed in a region surrounded by the trench gate structure 10.

[0153] The source region 31 may be formed along the periphery of the trench gate structure 10. The contact region 32 may be formed along the periphery of the trench source structure 11.

[0154] As described above, the semiconductor device 91 can also achieve the same effects as those described for the semiconductor device 1. Further, according to the semiconductor device 91, the density of the current flowing through the SiC semiconductor layer 2 can also be increased.

[0155] The structure of the semiconductor device 91 can also be applied to each of the above-described embodiments. That is, the structure in which the trench gate structure 10 is formed in a lattice pattern in a plan view and the trench source structure 11 is formed in a region surrounded by the trench gate structure 10 can also be applied to each of the above-described embodiments.

[0156] Although the first to sixth embodiments of the present invention have been described, the first to sixth embodiments of the present invention can also be implemented in other forms.

[0157] In the above-described first to sixth embodiments, the barrier formation layer 19 may selectively expose the SiC semiconductor layer 2 from the second side wall 22 of the source trench 18. For example, the barrier formation layer 19 may expose at least one of the contact region 32, the source region 31, and the body region 30 in the source trench 18.

[0158] In the above-described first to sixth embodiments, a structure in which the barrier formation layer 19 is omitted may be adopted.

[0159] In the first to sixth embodiments described above, the gate trench 12 may be formed in a tapered shape in which the area of ​​the first bottom wall 16 is smaller than the area of ​​the opening in a cross-sectional view.

[0160] In the above-described first to sixth embodiments, the first bottom wall 16 of the gate trench 12 may be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The first bottom wall 16 of the gate trench 12 may be formed in a convex curved shape extending from the first side wall 15 toward the second main surface 4 of the SiC semiconductor layer 2.

[0161] In the first to sixth embodiments described above, the source trench 18 may be formed in a tapered shape in which the area of ​​the second bottom wall 23 is smaller than the area of ​​the opening in a cross-sectional view.

[0162] In the above-described first to sixth embodiments, the second bottom wall 23 of the source trench 18 may be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The second bottom wall 23 of the source trench 18 may be formed in a convex curved shape extending from the second side wall 22 outward.

[0163] In the above-described first to sixth embodiments, a Si semiconductor layer (2) made of Si (silicon) may be used instead of the SiC semiconductor layer 2 made of SiC single crystal. That is, the Si semiconductor layer (2) may have a layered structure including a Si semiconductor substrate (5) made of Si and a Si epitaxial layer (6) made of Si.

[0164] In the first to sixth embodiments described above, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted, that is, a p-type portion may be formed as an n-type, and an n-type portion may be formed as a p-type.

[0165] In the first to sixth embodiments described above, n + Instead of the SiC semiconductor substrate 5 of the p +A SiC semiconductor substrate (5) of a certain type may be adopted. According to this structure, instead of a MISFET, an IGBT (Insulated Gate Bipolar Transistor) can be provided.

[0166] In this case, the "source" of the MISFET is read as the "emitter" of the IGBT. Also, the "drain" of the MISFET is read as the "collector" of the IGBT. Even when an IGBT is adopted instead of a MISFET, the same effects as those described in the above-described embodiments can be achieved.

[0167] FIG. 11 is a plan view showing a semiconductor device 101 according to a seventh embodiment of the present invention.

[0168] Referring to FIG. 11, the semiconductor device 101 has a SiC semiconductor layer 102 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may contain a 4H-SiC single crystal.

[0169] The 4H-SiC single crystal has an off-angle inclined at an angle within 10° with respect to the [11-20] direction from the (0001) plane. The off-angle may be 0° or more and 4° or less. The off-angle may be more than 0° and less than 4°. The off-angle is typically set in the range of 2° or 4°, more specifically, in the range of 2° ± 0.2° or 4° ± 0.4°.

[0170] In this form, the SiC semiconductor layer 102 is formed in a rectangular parallelepiped chip shape. The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, 105D connecting the first main surface 103 and the second main surface 104.

[0171] The first main surface 103 and the second main surface 104 are formed in a square shape in a plan view (hereinafter simply referred to as "plan view") as viewed from their normal directions. The side surface 105A faces the side surface 105C. The side surface 105B faces the side surface 105D.

[0172] The side surfaces 105A to 105D each extend planar along the normal direction of the first main surface 103 and the second main surface 104. The length of the side surfaces 105A to 105D may each be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0173] An active region 106 and an outer region 107 are set in the SiC semiconductor layer 102. The active region 106 is a region where a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is a region outside the active region 106.

[0174] In plan view, the active region 106 is set in the central portion of the SiC semiconductor layer 102 at a distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 toward the inner region of the SiC semiconductor layer 102. The active region 106 is set in a rectangular shape having four sides parallel to the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view.

[0175] The outer region 107 is set in the region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 106. The outer region 107 is set in an endless shape (square annular shape) surrounding the active region 106 in plan view.

[0176] On the first main surface 103 of the SiC semiconductor layer 102, a gate pad 108, a gate finger 109, and a source pad 110 as the first main surface electrodes are formed. In FIG. 11, the gate pad 108, the gate finger 109, and the source pad 110 are shown by hatching for clarity. The gate pad 108, the gate finger 109, and the source pad 110 may contain aluminum or copper.

[0177] The gate pad 108 is formed along the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 is formed along the central region of the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 may be formed along a corner connecting any two of the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0178] The gate pad 108 is formed in a rectangular shape in a plan view. The gate pad 108 is drawn out from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in a plan view.

[0179] The gate finger 109 is formed in the outer region 107. The gate finger 109 is drawn out from the gate pad 108 and extends in a strip shape in the outer region 107. In this form, the gate finger 109 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0180] The source pad 110 is formed in the active region 106 at a distance from the gate pad 108 and the gate finger 109. The source pad 110 is formed in a concave shape in a plan view so as to cover the concave region partitioned by the gate pad 108 and the gate finger 109.

[0181] A gate voltage is applied to the gate pad 108 and the gate finger 109. The gate voltage may be 10V or more and 50V or less (for example, about 30V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, GND voltage).

[0182] FIG. 12 is an enlarged view of region XII shown in FIG. 11, and is an enlarged view for explaining the structure of the first main surface 103 of the SiC semiconductor layer 102. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 12. FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. 12.

[0183] Referring to FIGS. 12 to 14, in this embodiment, the SiC semiconductor layer 102 has a stacked structure including an n + -type SiC semiconductor substrate 111 and an n-type SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 111.

[0184] The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 may be a ground surface. The second main surface 104 of the SiC semiconductor layer 102 may have grinding marks.

[0185] The thickness of the SiC semiconductor substrate 111 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 111 may be 5 μm or more. The thickness of the SiC semiconductor substrate 111 may be 25 μm or more. The thickness of the SiC semiconductor substrate 111 may be 50 μm or more. The thickness of the SiC semiconductor substrate 111 may be 100 μm or more.

[0186] The thickness of the SiC semiconductor substrate 111 may be 700 μm or less. The thickness of the SiC semiconductor substrate 111 may be 500 μm or less. The thickness of the SiC semiconductor substrate 111 may be 400 μm or less. The thickness of the SiC semiconductor substrate 111 may be 300 μm or less.

[0187] The thickness of the SiC semiconductor substrate 111 may be 250 μm or less. The thickness of the SiC semiconductor substrate 111 may be 200 μm or less. The thickness of the SiC semiconductor substrate 111 may be 150 μm or less. The thickness of the SiC semiconductor substrate 111 may be 100 μm or less.

[0188] The thickness of the SiC semiconductor substrate 111 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 111, the resistance value can be reduced by shortening the current path.

[0189] The thickness of the SiC epitaxial layer 112 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 112 may be 5 μm or more. The thickness of the SiC epitaxial layer 112 may be 10 μm or more.

[0190] The thickness of the SiC epitaxial layer 112 may be 50 μm or less. The thickness of the SiC epitaxial layer 112 may be 40 μm or less. The thickness of the SiC epitaxial layer 112 may be 30 μm or less.

[0191] The thickness of the SiC epitaxial layer 112 may be 20 μm or less. The thickness of the SiC epitaxial layer 112 is preferably 15 μm or less. The thickness of the SiC epitaxial layer 112 is preferably 10 μm or less.

[0192] The n-type impurity concentration of the SiC epitaxial layer 112 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 111. More specifically, the n-type impurity concentration of the SiC epitaxial layer 112 is less than the n-type impurity concentration of the SiC semiconductor substrate 111.

[0193] The n-type impurity concentration of the SiC semiconductor substrate 111 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the SiC epitaxial layer 112 may be 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less. In this form, the SiC epitaxial layer 112 has a plurality of regions having different n-type impurity concentrations along the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0194] The SiC epitaxial layer 112 more specifically includes a high-concentration region 112a with a relatively high n-type impurity concentration and a low-concentration region 112b with a lower n-type impurity concentration than the high-concentration region 112a. The high-concentration region 112a is formed in the region on the side of the first main surface 103. The low-concentration region 112b is formed in the region on the side of the SiC semiconductor substrate 111 with respect to the high-concentration region 112a.

[0195] The n-type impurity concentration of the high-concentration region 112a may be 1×10 16 cm -3 or more and 1×10 18 cm -3 or less. The n-type impurity concentration of the low-concentration region 112b may be 1×10 15 cm -3 or more and 1×10 16 cm -3 or less. The thickness of the high-concentration region 112a is equal to or less than the thickness of the low-concentration region 112b. More specifically, the thickness of the high-concentration region 112a is less than the thickness of the low-concentration region 112b.

[0196] A drain pad 113 as a second main surface electrode is connected to the second main surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between the source pad 110 and the drain pad 113 at off state may be 1000V or more and 10000V or less.

[0197] The SiC semiconductor substrate 111 is formed as a drain region 114 of the MISFET. The SiC epitaxial layer 112 is formed as a drift region 115 of the MISFET.

[0198] In the active region 106, a p-type body region 116 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the body region 116 may be 1×10 17 cm -3 or more and 1×10 20 cm -3 or less. The active region 106 is defined by this body region 116.

[0199] In the active region 106, a plurality of gate trenches 121 are formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 121 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 121 are formed in a strip shape extending along a second direction Y intersecting the first direction X.

[0200] More specifically, the first direction X is a direction along the side surfaces 105B and 105D of the SiC semiconductor layer 102. The second direction Y is a direction orthogonal to the first direction X. The second direction Y is also a direction along the side surfaces 105A and 105C of the SiC semiconductor layer 102.

[0201] The plurality of gate trenches 121 are formed in a stripe shape in plan view. In this form, each gate trench 121 extends in a strip shape from the peripheral portion on one side (side surface 105B side) to the peripheral portion on the other side (side surface 105D side) on the first main surface 103 of the SiC semiconductor layer 102 in plan view.

[0202] Each gate trench 121 crosses the intermediate portion between the peripheral portion on one side of the first main surface 103 and the peripheral portion on the other side of the first main surface 103. One end portion of each gate trench 121 is located at the peripheral portion on one side of the first main surface 103 of the SiC semiconductor layer 102. The other end portion of each gate trench 121 is located at the peripheral portion on the other side of the first main surface 103 of the SiC semiconductor layer 102.

[0203] The first direction X may be set to the [11 - 20] direction ([ - 1 - 120] direction). In this case, each gate trench 121 may extend along the [11 - 20] direction. The first direction X may be set to the [ - 1100] direction ([1 - 100] direction) orthogonal to the [11 - 20] direction. In this case, each gate trench 121 may extend along the [ - 1100] direction ([1 - 100] direction).

[0204] Each gate trench 121 has a length on the order of millimeters (a length of 1 mm or more). The length of the gate trench 121 is the length from the end on the connection portion side of the gate trench 121 and the gate finger 109 to the opposite end in the cross section shown in FIG. 14.

[0205] The length of each gate trench 121 may be 0.5 mm or more. In this form, the length of each gate trench 121 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total extension of one or more gate trenches 121 per unit area is 0.5 μm / μm 2 or more and 0.75 μm / μm 2 or less.

[0206] Each gate trench 121 integrally includes an active trench portion 121a and a contact trench portion 121b. The active trench portion 121a is the portion formed in the active region 106 in the gate trench 121. The contact trench portion 121b is the portion drawn from the active trench portion 121a to the outer region 107 in the gate trench 121.

[0207] Each gate trench 121 penetrates the body region 116 and reaches the SiC epitaxial layer 112. The bottom wall of each gate trench 121 is located within the SiC epitaxial layer 112. More specifically, the bottom wall of each gate trench 121 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0208] Regarding the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the depth of the gate trench 121 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). The depth of the gate trench 121 is preferably 0.5 μm or more and 1.0 μm or less.

[0209] The width of the gate trench 121 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). The width of the gate trench 121 in the first direction is preferably 0.1 μm or more and 0.5 μm or less.

[0210] Referring to FIGS. 13 and 14, the opening edge portion 124 of each gate trench 121 includes a curved portion 125 that curves inwardly of the gate trench 121. The opening edge portion 124 of the gate trench 121 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the side wall of the gate trench 121.

[0211] The electric field with respect to the opening edge portion 124 of the gate trench 121 is dispersed along the curved portion 125. Thereby, the electric field concentration with respect to the opening edge portion 124 of the gate trench 121 can be alleviated.

[0212] In the surface layer portion of the body region 116, an n + -type source region 126 is formed in a region along the side wall of the gate trench 121. The n-type impurity concentration of the source region 126 is 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0213] The source regions 126 are formed in plural along one side wall and the other side wall of the gate trench 121 with respect to the first direction X. The plurality of source regions 126 are each formed in a strip shape extending along the second direction Y. The plurality of source regions 126 are formed in a stripe shape in plan view.

[0214] A gate insulating layer 131 and a gate electrode layer 132 are formed in each gate trench 121. In FIG. 12, the gate insulating layer 131 and the gate electrode layer 132 are shown by hatching for clarity.

[0215] The gate insulating layer 131 may contain silicon oxide. The gate insulating layer 131 may contain other insulating films such as silicon nitride. The gate insulating layer 131 is formed in a film shape along the inner wall surface of the gate trench 121 so that a concave space is defined within the gate trench 121.

[0216] The gate insulating layer 131 includes a first region 131a, a second region 131b, and a third region 131c. The first region 131a is formed along the side wall of the gate trench 121. The second region 131b is formed along the bottom wall of the gate trench 121. The third region 131c is formed along the first main surface 103 of the SiC semiconductor layer 102.

[0217] The thickness T1 of the first region 131a is smaller than the thickness T2 of the second region 131b and the thickness T3 of the third region 131c. The ratio T2 / T1 of the thickness T2 of the second region 131b to the thickness T1 of the first region 131a may be 2 or more and 5 or less. The ratio T3 / T1 of the thickness T3 of the third region 131c to the thickness T1 of the first region 131a may be 2 or more and 5 or less.

[0218] The thickness T1 of the first region 131a may be 0.01 μm or more and 0.2 μm or less. The thickness T2 of the second region 131b may be 0.05 μm or more and 0.5 μm or less. The thickness T3 of the third region 131c may be 0.05 μm or more and 0.5 μm or less.

[0219] By forming the first region 131a of the gate insulating layer 131 thinly, an increase in carriers induced in the region near the side wall of the gate trench 121 in the body region 116 can be suppressed. Thereby, an increase in channel resistance can be suppressed. By forming the second region 131b of the gate insulating layer 131 thickly, the electric field concentration on the bottom wall of the gate trench 121 can be alleviated.

[0220] By thickening the third region 131c of the gate insulating layer 131, the breakdown voltage of the gate insulating layer 131 near the opening edge portion 124 of the gate trench 121 can be improved. Also, by thickening the third region 131c, it is possible to suppress the third region 131c from disappearing by the etching method.

[0221] Thereby, it is possible to suppress the first region 131a from being removed by the etching method due to the disappearance of the third region 131c. As a result, the gate electrode layer 132 can be appropriately opposed to the SiC semiconductor layer 102 with the gate insulating layer 131 interposed therebetween.

[0222] The gate electrode layer 132 is embedded in the gate trench 121 with the gate insulating layer 131 interposed therebetween. More specifically, the gate electrode layer 132 is embedded in the gate trench 121 so as to fill a concave space partitioned by the gate insulating layer 131. The gate electrode layer 132 is controlled by a gate voltage.

[0223] Referring to FIGS. 13 and 14, the gate electrode layer 132 is formed in a wall shape extending along the normal direction of the first main surface 103 of the SiC semiconductor layer 102 in a cross-sectional view perpendicular to the direction in which the gate trench 121 extends.

[0224] The gate electrode layer 132 has an upper end portion located on the opening side of the gate trench 121. The upper end portion of the gate electrode layer 132 is formed in a curved shape recessed toward the bottom wall of the gate trench 121.

[0225] The cross-sectional area of the gate electrode layer 132 (the cross-sectional area perpendicular to the direction in which the gate trench 121 extends) may be 0.05 μm 2 or more and 0.5 μm 2 or less. The cross-sectional area of the gate electrode layer 132 is defined by the product of the depth of the gate electrode layer 132 and the width of the gate electrode layer 132.

[0226] The depth of the gate electrode layer 132 is the distance from the upper end to the lower end of the gate electrode layer 132. The width of the gate electrode layer 132 is the width of the trench at the intermediate position between the upper end and the lower end of the gate electrode layer 132. When the upper end is a curved surface (a curved shape that is recessed downward in this form), the position of the upper end of the gate electrode layer 132 is the intermediate position in the depth direction on the upper surface of the gate electrode layer 132.

[0227] The gate electrode layer 132 contains p-type polysilicon doped with p-type impurities. The p-type impurities may contain at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0228] The p-type impurity concentration of the gate electrode layer 132 is equal to or higher than the p-type impurity concentration of the body region 116. More specifically, the p-type impurity concentration of the gate electrode layer 132 is greater than the p-type impurity concentration of the body region 116.

[0229] The p-type impurity concentration of the gate electrode layer 132 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the gate electrode layer 132 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form).

[0230] Referring to FIG. 14, a gate wiring layer 133 is formed in the outer region 107. The gate wiring layer 133 is electrically connected to the gate pad 108 and the gate finger 109.

[0231] The gate wiring layer 133 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 133 is formed on the third region 131c of the gate insulating layer 131.

[0232] In this embodiment, the gate wiring layer 133 is formed along the gate fingers 109. The gate wiring layer 133 is formed along the three side surfaces 105A, 105B, 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0233] The gate wiring layer 133 is connected to the gate electrode layer 132 exposed from the contact trench portion 121b of each gate trench 121. In this embodiment, the gate wiring layer 133 is formed by a lead-out portion drawn from the gate electrode layer 132 onto the first main surface 103 of the SiC semiconductor layer 102. The upper end portion of the gate wiring layer 133 is connected to the upper end portion of the gate electrode layer 132.

[0234] Referring to FIG. 13, a low-resistance electrode layer 134 is formed on the gate electrode layer 132. The low-resistance electrode layer 134 covers the upper end portion of the gate electrode layer 132 within the gate trench 121.

[0235] The low-resistance electrode layer 134 contains a conductive material having a sheet resistance lower than that of the gate electrode layer 132. The sheet resistance of the low-resistance electrode layer 134 may be 0.01 Ω / sq or more and 10 Ω / sq or less.

[0236] The current supplied into the gate trench 121 flows through the low-resistance electrode layer 134 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 132. As a result, the entire gate electrode layer 132 (the entire active region 106) can be quickly shifted from the off state to the on state, so that the delay of the switching response can be suppressed.

[0237] In particular, in the case of the gate trench 121 having a length on the order of millimeters, it takes time for the current to be transmitted, but according to the low-resistance electrode layer 134, the delay of the switching response can be appropriately suppressed. That is, the low-resistance electrode layer 134 is formed as a current diffusion electrode layer for diffusing the current within the gate trench 121.

[0238] In addition, as the cell structure is miniaturized, the width, depth, cross-sectional area, etc. of the gate electrode layer 132 decrease, so there is concern about a delay in the switching response due to an increase in the electrical resistance in the gate trench 121.

[0239] However, according to the low-resistance electrode layer 134, the entire gate electrode layer 132 can be quickly shifted from the off state to the on state, so that the delay in the switching response due to miniaturization can be appropriately suppressed.

[0240] The low-resistance electrode layer 134 is formed in a film shape. The low-resistance electrode layer 134 has a connection portion 134a in contact with the upper end portion of the gate electrode layer 132 and a non-connection portion 134b opposite thereto. The connection portion 134a and the non-connection portion 134b of the low-resistance electrode layer 134 may be formed in a curved shape following the upper end portion of the gate electrode layer 132. The connection portion 134a and the non-connection portion 134b of the low-resistance electrode layer 134 can take various forms.

[0241] The entire connection portion 134a of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connection portion 134a of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0242] The connection portion 134a of the low-resistance electrode layer 134 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 134a of the low-resistance electrode layer 134 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0243] For example, the central portion of the connection portion 134a of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the connection portion 134a of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0244] The entire non-connected portion 134b of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire non-connected portion 134b of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0245] The non-connected portion 134b of the low-resistance electrode layer 134 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connected portion 134b of the low-resistance electrode layer 134 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0246] For example, the central portion of the non-connected portion 134b of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the non-connected portion 134b of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0247] The low-resistance electrode layer 134 has an edge portion 134c in contact with the gate insulating layer 131. The edge portion 134c of the low-resistance electrode layer 134 is in contact with the corner portion connecting the first region 131a and the third region 131c in the gate insulating layer 131.

[0248] The edge portion 134c of the low-resistance electrode layer 134 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom of the source region 126. That is, the edge portion 134c of the low-resistance electrode layer 134 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 rather than the boundary region between the body region 116 and the source region 126.

[0249] Therefore, the edge portion 134c of the low-resistance electrode layer 134 faces the source region 126 with the gate insulating layer 131 interposed therebetween. The edge portion 134c of the low-resistance electrode layer 134 does not face the body region 116 with the gate insulating layer 131 interposed therebetween.

[0250] This can suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the body region 116 in the gate insulating layer 131. The current path can be formed by the undesired diffusion of the electrode material of the low-resistance electrode layer 134 with respect to the gate insulating layer 131.

[0251] In particular, the design of connecting the edge 134c of the low-resistance electrode layer 134 to the third region 131c (the corner of the gate insulating layer 131) of the relatively thick gate insulating layer 131 is effective in reducing the risk of forming a current path.

[0252] With respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the thickness TR of the low-resistance electrode layer 134 is equal to or less than the thickness TG of the gate electrode layer 132 (TR ≦ TG). Preferably, the thickness TR of the low-resistance electrode layer 134 is less than the thickness TG of the gate electrode layer 132 (TR < TG). More specifically, the thickness TR of the low-resistance electrode layer 134 is preferably equal to or less than half of the thickness TG of the gate electrode layer 132 (TR ≦ TG / 2).

[0253] The ratio TR / TG of the thickness TR of the low-resistance electrode layer 134 to the thickness TG of the gate electrode layer 132 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 132 may be 0.5 μm or more and 3 μm or less. The thickness TR of the low-resistance electrode layer 134 may be 0.01 μm or more and 3 μm or less.

[0254] Referring to FIG. 14, in this form, the low-resistance electrode layer 134 also covers the upper end portion of the gate wiring layer 133. The portion of the low-resistance electrode layer 134 that covers the upper end portion of the gate wiring layer 133 is integrally formed with the portion of the low-resistance electrode layer 134 that covers the upper end portion of the gate electrode layer 132. Thereby, the low-resistance electrode layer 134 covers the entire area of the gate electrode layer 132 and the entire area of the gate wiring layer 133.

[0255] Therefore, the current supplied from the gate pad 108 and the gate finger 109 to the gate wiring layer 133 flows through the low-resistance electrode layer 134 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 132 and the gate wiring layer 133.

[0256] As a result, the entire gate electrode layer 132 (the entire active region 106) can be quickly shifted from the off state to the on state through the gate wiring layer 133, so that the delay of the switching response can be suppressed.

[0257] In particular, in the case of the gate trench 121 having a length on the order of millimeters, the delay of the switching response can be appropriately suppressed by the low-resistance electrode layer 134 covering the upper end portion of the gate wiring layer 133.

[0258] The low-resistance electrode layer 134 includes a polyside layer. The polyside layer is formed by siliciding a portion forming the surface layer portion of the gate electrode layer 132 with a metal material. More specifically, the polyside layer is composed of a p-type polyside layer containing p-type impurities added to the gate electrode layer 132 (p-type polysilicon).

[0259] In this form, the polyside layer has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less. More specifically, the polyside layer contains at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2.

[0260] The sheet resistance in the gate trench 121 when the low-resistance electrode layer 134 is formed on the p-type polysilicon is equal to or less than the sheet resistance of the gate electrode layer 132 (p-type polysilicon) alone. Preferably, the sheet resistance in the gate trench 121 is equal to or less than the sheet resistance of the n-type polysilicon doped with n-type impurities.

[0261] The sheet resistance within the gate trench 121 is approximated to the sheet resistance of the low-resistance electrode layer 134. That is, the sheet resistance within the gate trench 121 may be 0.01 Ω / sq or more and 10 Ω / sq or less. Preferably, the sheet resistance within the gate trench 121 is less than 10 Ω / sq.

[0262] The results of examining the resistivity of the polyside layer are shown in FIG. 15. FIG. 15 is a graph showing the relationship between the resistivity of the polyside and the formation temperature. In FIG. 15, the vertical axis represents the resistivity [μΩ·cm], and the horizontal axis represents the formation temperature [°C] of the polyside.

[0263] Referring to FIG. 15, the resistivity decreases in the order of MoSi2, WSi2, NiSi, CoSi2, and TiSi2. Therefore, the priority of the materials used as the polyside layer increases in the order of MoSi2, WSi2, NiSi, CoSi2, and TiSi2.

[0264] Among these types, in particular, NiSi, CoSi2, and TiSi2 are suitable as the polyside layer for forming the low-resistance electrode layer 134 because their resistivity values and temperature dependencies are relatively small.

[0265] Furthermore, as a result of the inventors' verification, when TiSi2 was adopted as the material of the low-resistance electrode layer 134, an increase in the leakage current between the gate and the source was observed under low electric field application. On the other hand, when CoSi2 was adopted, no increase in the leakage current between the gate and the source was observed under low electric field application. Considering that NiSi has problems with heat resistance compared to CoSi2, CoSi2 is most preferable as the polyside layer for forming the low-resistance electrode layer 134.

[0266] Referring to FIGS. 12 and 13, a plurality of source trenches 141 are formed on the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. Each source trench 141 is formed in a region between two adjacent gate trenches 121.

[0267] The plurality of source trenches 141 are each formed in a strip shape extending along the second direction Y. The plurality of source trenches 141 are formed in a stripe shape in a plan view. With respect to the first direction X, the pitch between the central portions of adjacent source trenches 141 may be 1.5 μm or more and 3 μm or less.

[0268] Each source trench 141 penetrates the body region 116 and reaches the SiC epitaxial layer 112. The bottom wall of each source trench 141 is located within the SiC epitaxial layer 112. More specifically, the bottom wall of each source trench 141 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0269] The depth of the source trench 141 may be approximately equal to the depth of the gate trench 121. The depth of the source trench 141 may be equal to or greater than the depth of the gate trench 121. With respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the depth of the source trench 141 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0270] The width of the source trench 141 in the first direction may be approximately equal to the width of the gate trench 121 in the first direction. The width of the source trench 141 in the first direction may be equal to or greater than the width of the gate trench 121 in the first direction. The width of the source trench 141 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm).

[0271] The opening edge portion 142 of each source trench 141 includes a curved portion 143 that curves inwardly of the source trench 141. The opening edge portion 142 of the source trench 141 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the side wall of the source trench 141.

[0272] The electric field with respect to the opening edge portion 142 of the source trench 141 is dispersed along the curved portion 143. Thereby, the electric field concentration with respect to the opening edge portion 142 of the source trench 141 can be alleviated.

[0273] In the SiC semiconductor layer 102, p + -type contact regions 144 are formed in a region along the side wall of the source trench 141. The p-type impurity concentration of the contact region 144 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. A plurality of contact regions 144 are formed on one side surface and the other side surface of one source trench 141.

[0274] The plurality of contact regions 144 are formed at intervals along the second direction Y. The plurality of contact regions 144 are formed at intervals along the first direction X from the gate trench 121.

[0275] In the SiC semiconductor layer 102, a p-type deep well region 145 is formed in a region along the inner wall of the source trench 141. The deep well region 145 is also referred to as a breakdown voltage holding region. The deep well region 145 is formed in a strip shape extending along the source trench 141. The deep well region 145 extends along the inner wall of the source trench 141.

[0276] Referring to FIGS. 12 and 14, more specifically, the deep well region 145 extends along the side wall of the source trench 141 and covers the bottom wall of the source trench 141 through the edge portion. The deep well region 145 is continuous with the body region 116 on the side wall of the source trench 141.

[0277] The deep well region 145 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 121. The deep well region 145 is formed in the high concentration region 112a of the SiC epitaxial layer 112.

[0278] The p-type impurity concentration in the deep well region 145 may be approximately equal to the p-type impurity concentration in the body region 116. The p-type impurity concentration in the deep well region 145 may exceed the p-type impurity concentration in the body region 116. The p-type impurity concentration in the deep well region 145 may be less than the p-type impurity concentration in the body region 116.

[0279] The p-type impurity concentration in the deep well region 145 may be less than or equal to the p-type impurity concentration in the contact region 144. The p-type impurity concentration in the deep well region 145 may be less than the p-type impurity concentration in the contact region 144. The p-type impurity concentration in the deep well region 145 may be from 1.0×10 17 cm -3 or more to 1.0×10 19 cm -3 or less.

[0280] Referring to FIGS. 12 and 14, a p-type peripheral deep well region 148 is formed in the outer region 107. The peripheral deep well region 148 is electrically connected to the deep well region 145.

[0281] The peripheral deep well region 148 has the same potential as the deep well region 145. In this form, the peripheral deep well region 148 is integrally formed with the deep well region 145.

[0282] More specifically, the peripheral deep well region 148 extends in a strip shape along the periphery of the active region 106 in the outer region 107. More specifically, the peripheral deep well region 148 is formed in an endless shape (a square ring shape in this form) surrounding the active region 106.

[0283] The peripheral deep well region 148 is formed in the outer region 107 in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 and in the region along the inner wall of the contact trench portion 121b of the gate trench 121. The peripheral deep well region 148 extends along the side wall of the contact trench portion 121b and covers the bottom wall of the contact trench portion 121b through the edge portion.

[0284] The peripheral deep well region 148 overlaps the gate wiring layer 133 in plan view. That is, the peripheral deep well region 148 faces the gate wiring layer 133 with the gate insulating layer 131 (third region 131c) interposed therebetween.

[0285] The peripheral deep well region 148 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the contact trench portion 121b of the gate trench 121. The peripheral deep well region 148 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0286] The peripheral deep well region 148 includes a lead-out portion 148a drawn from the outer region 107 to the peripheral portion of the active region 106 in plan view. The lead-out portion 148a of the peripheral deep well region 148 covers the end portion located on the outer region 107 side of the source trench 141 in plan view.

[0287] The lead-out portion 148a of the peripheral deep well region 148 covers the inner wall of the active trench portion 121a at the peripheral portion of the active region 106. The lead-out portion 148a of the peripheral deep well region 148 extends along the side wall of the active trench portion 121a and covers the bottom wall of the active trench portion 121a through the edge portion. The lead-out portion 148a of this peripheral deep well region 148 is continuous with the deep well region 145 in the active region 106.

[0288] The extraction portion 148a of the peripheral deep well region 148 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the active trench portion 121a of the gate trench 121. The extraction portion 148a of the peripheral deep well region 148 is formed in the high concentration region 112a of the SiC epitaxial layer 112.

[0289] The p-type impurity concentration of the peripheral deep well region 148 may be approximately equal to the p-type impurity concentration of the body region 116. The p-type impurity concentration of the peripheral deep well region 148 may exceed the p-type impurity concentration of the body region 116. The p-type impurity concentration of the peripheral deep well region 148 may be less than the p-type impurity concentration of the body region 116.

[0290] The p-type impurity concentration of the peripheral deep well region 148 may be approximately equal to the p-type impurity concentration of the deep well region 145. The p-type impurity concentration of the peripheral deep well region 148 may exceed the p-type impurity concentration of the deep well region 145. The p-type impurity concentration of the peripheral deep well region 148 may be less than the p-type impurity concentration of the deep well region 145.

[0291] The p-type impurity concentration of the peripheral deep well region 148 may be equal to or less than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the peripheral deep well region 148 may be less than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the peripheral deep well region 148 may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0292] A source insulating layer 146 and a source electrode layer 147 are formed in each source trench 141. In FIG. 12, the source insulating layer 146 and the source electrode layer 147 are shown by hatching for clarity.

[0293] The source insulating layer 146 may contain silicon oxide. The source insulating layer 146 is formed in a film shape along the inner wall surface of the source trench 141 so that a concave space is defined within the source trench 141.

[0294] The source insulating layer 146 includes a first region 146a and a second region 146b. The first region 146a is formed along the side wall of the source trench 141. The second region 146b is formed along the bottom wall of the source trench 141. The thickness T11 of the first region 146a is smaller than the thickness T12 of the second region 146b.

[0295] The ratio T12 / T11 of the thickness T12 of the second region 146b to the thickness T11 of the first region 146a may be 2 or more and 5 or less. The thickness T11 of the first region 146a may be 0.01 μm or more and 0.2 μm or less. The thickness T12 of the second region 146b may be 0.05 μm or more and 0.5 μm or less.

[0296] The thickness T11 of the first region 146a may be approximately equal to the thickness T1 of the first region 131a of the gate insulating layer 131. The thickness T12 of the second region 146b may be approximately equal to the thickness T2 of the second region 131b of the gate insulating layer 131.

[0297] The source insulating layer 146 exposes the opening edge portion 142 of the source trench 141. More specifically, the source insulating layer 146 exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141.

[0298] More specifically, the first region 146a of the source insulating layer 146 has an upper end portion located on the opening side of the source trench 141. The upper end portion of the first region 146a is formed below the first main surface 103 of the SiC semiconductor layer 102.

[0299] The upper end portion of the first region 146a exposes the side wall of the source trench 141 on the opening side of the source trench 141. In this way, the first region 146a exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141.

[0300] The source electrode layer 147 is embedded in the source trench 141 with the source insulating layer 146 interposed therebetween. More specifically, the source electrode layer 147 is embedded in the source trench 141 so as to fill the concave space partitioned by the source insulating layer 146. The source electrode layer 147 is controlled by a source voltage.

[0301] The source electrode layer 147 has an upper end portion located on the opening side of the source trench 141. The upper end portion of the source electrode layer 147 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end portion of the source electrode layer 147 may be flush with the upper end portion of the source insulating layer 146.

[0302] The upper end portion of the source electrode layer 147 may protrude above the upper end portion of the source insulating layer 146. The upper end portion of the source electrode layer 147 may be located below the upper end portion of the source insulating layer 146. The thickness of the source electrode layer 147 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0303] The source electrode layer 147 preferably contains polysilicon having properties similar to SiC in terms of material. Thereby, the stress generated in the SiC semiconductor layer 102 can be reduced. The source electrode layer 147 preferably contains p-type polysilicon doped with p-type impurities. In this case, the source electrode layer 147 can be formed simultaneously with the gate electrode layer 132.

[0304] The p-type impurity concentration of the source electrode layer 147 is equal to or higher than the p-type impurity concentration of the body region 116. More specifically, the p-type impurity concentration of the source electrode layer 147 is greater than the p-type impurity concentration of the body region 116. The p-type impurity of the source electrode layer 147 may contain at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0305] The p-type impurity concentration of the source electrode layer 147 is 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the source electrode layer 147 may be 10 Ω / sq or more and 500 Ω / sq or less (about 200 Ω / sq in this form).

[0306] The p-type impurity concentration of the source electrode layer 147 may be approximately equal to the p-type impurity concentration of the gate electrode layer 132. The sheet resistance of the source electrode layer 147 may be approximately equal to the sheet resistance of the gate electrode layer 132.

[0307] Instead of p-type polysilicon, the source electrode layer 147 may contain n-type polysilicon. Instead of p-type polysilicon, the source electrode layer 147 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy.

[0308] Thus, the semiconductor device 101 has a trench gate structure 151 and a trench source structure 152. The trench gate structure 151 includes a gate trench 121, a gate insulating layer 131, a gate electrode layer 132, and a low-resistance electrode layer 134. The trench source structure 152 includes a source trench 141, a source insulating layer 146, and a source electrode layer 147.

[0309] Referring to FIGS. 13 and 14, an interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 153 covers the trench gate structure 151 in the active region 106 and the gate wiring layer 133 in the outer region 107.

[0310] The interlayer insulating layer 153 may contain silicon oxide or silicon nitride. Gate contact holes 154 and source contact holes 155 are formed in the interlayer insulating layer 153.

[0311] The gate contact hole 154 exposes the gate wiring layer 133 (low-resistance electrode layer 134) in the outer region 107. The source contact hole 155 exposes the source region 126, the contact region 144, and the trench source structure 152 in the active region 106. A gate pad 108, a gate finger 109, and a source pad 110 are formed on the interlayer insulating layer 153.

[0312] The gate finger 109 enters the gate contact hole 154 from above the interlayer insulating layer 153. The gate finger 109 is electrically connected to the low-resistance electrode layer 134 within the gate contact hole 154. Thereby, an electrical signal from the gate pad 108 is transmitted to the gate electrode layer 132 via the low-resistance electrode layer 134 having a relatively low resistance value.

[0313] The source pad 110 enters the source contact hole 155 from above the interlayer insulating layer 153. The source pad 110 is electrically connected to the source region 126, the contact region 144, and the source electrode layer 147 within the source contact hole 155. The source electrode layer 147 may be formed using a partial region of the source pad 110.

[0314] FIG. 16 is a graph for explaining sheet resistance. In FIG. 16, the vertical axis represents the sheet resistance [Ω / sq], and the horizontal axis represents items. In FIG. 16, a first bar graph L1, a second bar graph L2, and a third bar graph L3 are shown.

[0315] The first bar graph L1 represents the sheet resistance of n-type polysilicon. The second bar graph L2 represents the sheet resistance of p-type polysilicon. The third bar graph L3 represents the sheet resistance when a low-resistance electrode layer 134 is formed on the p-type polysilicon. The low-resistance electrode layer 134 includes TiSi2 (p-type titanium silicide) here.

[0316] Referring to the first bar graph L1, the sheet resistance of the n-type polysilicon was 10 Ω / sq. Referring to the second bar graph L2, the sheet resistance of the p-type polysilicon was 200 Ω / sq. Referring to the third bar graph L3, the sheet resistance when the low-resistance electrode layer 134 was formed on the p-type polysilicon was 2 Ω / sq.

[0317] The p-type polysilicon has a work function different from that of the n-type polysilicon, and just by embedding the p-type polysilicon in the gate trench 121, the gate threshold voltage Vth can be increased by about 1 V.

[0318] However, the p-type polysilicon has a sheet resistance that is several tens of times (20 times here) higher than that of the n-type polysilicon. Therefore, when p-type polysilicon is adopted as the material of the gate electrode layer 132, the energy loss increases significantly with the increase in the parasitic resistance (hereinafter simply referred to as "gate resistance") in the gate trench 121.

[0319] In contrast, in the structure with the low-resistance electrode layer 134 on the p-type polysilicon, the sheet resistance can be reduced to 1 / 100 or less compared to the case where the low-resistance electrode layer 134 is not formed. In the structure with the low-resistance electrode layer 134, the sheet resistance can be reduced to 1 / 5 or less compared to the gate electrode layer 132 including n-type polysilicon.

[0320] According to the semiconductor device 101 described above, a trench gate structure 151 is formed in which a gate electrode layer 132 is embedded in a gate trench 121 with a gate insulating layer 131 interposed therebetween. In this trench gate structure 151, the gate electrode layer 132 is covered by a low-resistance electrode layer 134 in the limited space of the gate trench 121.

[0321] The gate electrode layer 132 contains p-type polysilicon. Thereby, the gate threshold voltage Vth can be increased. The low-resistance electrode layer 134 contains a conductive material having a sheet resistance less than that of the p-type polysilicon.

[0322] Thereby, the gate resistance can be reduced. As a result, since current can be efficiently diffused along the trench gate structure 151, the switching delay can be shortened.

[0323] In particular, according to the structure in which the gate electrode layer 132 is covered by the low-resistance electrode layer 134, it is not necessary to increase the p-type impurity concentration in the body region 116. Therefore, the gate threshold voltage Vth can be increased while preventing an increase in the channel resistance.

[0324] Moreover, according to the semiconductor device 101, in the outer region 107, the gate wiring layer 133 is covered by the low-resistance electrode layer 134. Thereby, the gate resistance in the gate wiring layer 133 can also be reduced.

[0325] In particular, in the structure in which the gate electrode layer 132 and the gate wiring layer 133 are covered by the low-resistance electrode layer 134, current can be efficiently diffused along the trench gate structure 151. Therefore, the switching delay can be appropriately shortened.

[0326] FIGS. 17A to 17L are cross-sectional views showing an example of a method for manufacturing the semiconductor device 101 shown in FIG. 11. FIGS. 17A to 17L are cross-sectional views of the corresponding portions in FIG. 13.

[0327] Referring to FIG. 17A, first, an n + -type SiC semiconductor substrate 111 is prepared. Next, an SiC epitaxial layer 112 is formed on the main surface of the SiC semiconductor substrate 111. The SiC epitaxial layer 112 is formed by growing SiC from above the main surface of the SiC semiconductor substrate 111 by an epitaxial growth method.

[0328] In this form, an SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b is formed. Thereby, an SiC semiconductor layer 102 including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112 is formed.

[0329] Next, a p-type body region 116 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The body region 116 is formed by introducing p-type impurities into the first main surface 103 of the SiC semiconductor layer 102.

[0330] The body region 116 may be formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 by an ion implantation method through an ion implantation mask (not shown). The active region 106 is defined by this body region 116.

[0331] Next, referring to FIG. 17B, an n + -type source region 126 is formed in the surface layer portion of the body region 116. The source region 126 is formed by introducing n-type impurities into the surface layer portion of the body region 116. The source region 126 may be formed in the surface layer portion of the body region 116 by an ion implantation method through an ion implantation mask 161.

[0332] Next, referring to FIG. 17C, a p + -type contact region 144 is formed in the surface layer portion of the body region 116. The contact region 144 is formed by introducing p-type impurities into the surface layer portion of the body region 116. The contact region 144 may be formed in the surface layer portion of the body region 116 by an ion implantation method through an ion implantation mask 162.

[0333] Next, referring to FIG. 17D, a mask 163 having a predetermined pattern is formed on the first main surface 103 of the SiC semiconductor layer 102. The mask 163 has a plurality of openings 164 that expose regions where the gate trench 121 and the source trench 141 are to be formed.

[0334] Next, unnecessary portions of the SiC semiconductor layer 102 are removed. The unnecessary portions of the SiC semiconductor layer 102 may be removed by an etching method (e.g., a wet etching method) through the mask 163. Thereby, the gate trench 121 and the source trench 141 are formed. Thereafter, the mask 163 is removed.

[0335] Next, a deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the inner wall of the source trench 141. The deep well region 145 may be formed in the SiC semiconductor layer 102 by an ion implantation method through an ion implantation mask (not shown).

[0336] Also, in the outer region 107, a peripheral deep well region 148 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 and in a region along the inner wall of the contact trench portion 121b of the gate trench 121. In this step, a peripheral deep well region 148 including a lead-out portion 148a led out from the outer region 107 to the peripheral portion of the active region 106 is formed.

[0337] The peripheral deep well region 148 may be formed in the SiC semiconductor layer 102 by an ion implantation method through an ion implantation mask (not shown). Part or all of the peripheral deep well region 148 may be formed simultaneously with the deep well region 145 using the formation process of the deep well region 145. Part of the peripheral deep well region 148 may be formed simultaneously with the body region 116 using the formation process of the body region 116.

[0338] Next, referring to FIG. 17E, an annealing process is performed on the SiC semiconductor layer 102. The annealing process may be a high-temperature hydrogen annealing process. The annealing temperature may be 1400° C. or higher.

[0339] As a result, a curved portion 125 is formed at the opening edge portion 124 of the gate trench 121. Also, a curved portion 143 is formed at the opening edge portion 142 of the source trench 141.

[0340] Next, referring to FIG. 17F, a base insulating layer 165 that serves as a base for the gate insulating layer 131 and the source insulating layer 146 is formed to cover the first main surface 103 of the SiC semiconductor layer 102. The base insulating layer 165 may be formed by a CVD (chemical vapor deposition) method. The base insulating layer 165 may contain silicon oxide.

[0341] In this step, portions of the base insulating layer 165 that cover the sidewalls of the gate trench 121 and the source trench 141 are formed to be thinner than other portions.

[0342] The base insulating layer 165 in such a form is formed by adjusting predetermined conditions such as gas flow rate, gas species, gas ratio, and gas supply time in the CVD method. The base insulating layer 165 may be formed by an oxidation treatment method instead of the CVD method. The oxidation treatment method may be a thermal oxidation treatment method or a wet oxidation treatment method.

[0343] Next, referring to FIG. 17G, a base conductor layer 166 that serves as a base for the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147 is formed on the first main surface 103 of the SiC semiconductor layer 102.

[0344] The base conductor layer 166 contains p-type polysilicon doped with p-type impurities. The base conductor layer 166 may be formed by a CVD method. The CVD method may be an LP-CVD (Low Pressure-CVD) method.

[0345] Next, referring to FIG. 17H, unnecessary portions of the base conductor layer 166 are removed. The unnecessary portions of the base conductor layer 166 are removed by an etching method (e.g., a wet etching method) through a mask (not shown) having a predetermined pattern.

[0346] This mask (not shown) covers the region where the gate wiring layer 133 is to be formed. The unnecessary portions of the base conductor layer 166 are removed until at least the portion covering the first main surface 103 of the SiC semiconductor layer 102 in the base insulating layer 165 is exposed. Thereby, the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147 are formed.

[0347] When the source electrode layer 147 is made of an electrode material different from that of the gate electrode layer 132, the same processes as those in the processes of FIGS. 17G to 17H may be separately performed for the electrode material of the source electrode layer 147 to form the source electrode layer 147. When the source electrode layer 147 is formed by a part of the source pad 110, the source electrode layer 147 is formed when the source pad 110 is formed.

[0348] Next, referring to FIG. 17I, a metal material layer 167 is formed on the gate electrode layer 132. In this form, the metal material layer 167 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover the gate electrode layer 132 and the source electrode layer 147 together.

[0349] The metal material layer 167 contains a metal material that can be polysidized with p-type polysilicon. The metal material layer 167 may contain at least one of Mo, W, Ni, Co, or Ti.

[0350] Next, a p-type polyside layer is formed on the surface layer portion of the gate electrode layer 132 and the surface layer portion of the gate wiring layer 133. In this form, a p-type polyside layer is also formed on the surface layer portion of the source electrode layer 147.

[0351] The p-type polysilicide layer is formed by performing heat treatment on the metal material layer 167 to polysilicide the surface layer portions of the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147. The heat treatment on the metal material layer 167 may be the RTA (Rapid Thermal Annealing) method.

[0352] Thereby, depending on the metal material of the metal material layer 167, a p-type polysilicide containing at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2 is formed. The low-resistance electrode layer 134 is formed by this p-type polysilicide layer.

[0353] Next, referring to FIG. 17J, the unreacted portions of the metal material layer 167 that did not bond with the p-type polysilicon are removed. The unreacted portions of the metal material layer 167 may be removed by an etching method (for example, a wet etching method).

[0354] When the low-resistance electrode layer 134 (p-type polysilicide) contains at least one of TiSi or CoSi, after the unreacted portions of the metal material layer 167 are removed, heat treatment may be performed on the low-resistance electrode layer 134 as necessary.

[0355] The heat treatment on the low-resistance electrode layer 134 may be the RTA method. Thereby, TiSi is modified to TiSi2 and CoSi is modified to CoSi2, so that the resistance can be reduced.

[0356] Next, referring to FIG. 17K, an interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover the trench gate structure 151 and the gate wiring layer 133. The interlayer insulating layer 153 contains silicon oxide or silicon nitride. The interlayer insulating layer 153 may be formed by the CVD method.

[0357] Next, a mask 168 having a predetermined pattern is formed over the interlayer insulating layer 153. The mask 168 has a plurality of openings 169 that expose regions where the gate contact holes 154 and the source contact holes 155 are to be formed.

[0358] Next, unnecessary portions of the interlayer insulating layer 153 are removed. The unnecessary portions of the interlayer insulating layer 153 may be removed by an etching method (e.g., a dry etching method) through the mask 168. Thereby, the gate contact holes 154 and the source contact holes 155 are formed.

[0359] Next, referring to FIG. 17L, a gate pad 108, a gate finger 109, and a source pad 110 are formed over the interlayer insulating layer 153. The gate pad 108, the gate finger 109, and the source pad 110 are formed using a mask (not shown) having a predetermined pattern. Also, a drain pad 113 is formed over the second main surface 104 of the SiC semiconductor layer 102. Through the steps including the above, the semiconductor device 101 is manufactured.

[0360] FIG. 18 is a cross-sectional view of a region corresponding to FIG. 13 and shows a cross-sectional view of a semiconductor device 171 according to the eighth embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0361] Referring to FIG. 18, in the semiconductor device 171, the gate insulating layer 131 includes a bulging portion 172 that bulges into the gate trench 121 at the opening edge portion 124 of the gate trench 121. The bulging portion 172 is formed at a corner connecting the first region 131a and the third region 131c of the gate insulating layer 131.

[0362] The bulging portion 172 bulges in a curved shape toward the inside of the gate trench 121. The bulging portion 172 narrows the opening of the gate trench 121 at the opening edge portion 124 of the gate trench 121.

[0363] The upper end portion of the gate electrode layer 132 has a constricted portion that is recessed along the bulging portion 172 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end portion) of the gate electrode layer 132. In this form, the edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 172 of the gate insulating layer 131.

[0364] The bulging portion 172 of the gate insulating layer 131 is formed by setting predetermined conditions (such as gas flow rate, gas species, gas ratio, gas supply time, etc.) of the CVD method in consideration of the shape of the bulging portion 172 of the gate insulating layer 131 in the process of FIG. 17F described above.

[0365] As described above, according to the semiconductor device 171, the edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 172 of the gate insulating layer 131. Thereby, it is possible to appropriately suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the SiC semiconductor layer 102.

[0366] Further, according to the semiconductor device 171, in addition to the opening edge portion 124 of the gate trench 121 having the curved portion 125, the bulging portion 172 is formed in the opening edge portion 124 of the gate trench 121. Thereby, it is possible to further improve the breakdown voltage of the gate insulating layer 131 at the opening edge portion 124 of the gate trench 121.

[0367] FIG. 19 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view showing a semiconductor device 181 according to the ninth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101, the same reference numerals are given and the description is omitted.

[0368] Referring to FIG. 19, in the semiconductor device 181, the opening edge portion 124 of the gate trench 121 has an inclined portion 182 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the side wall of the gate trench 121.

[0369] According to the inclined portion 182 of the gate trench 121, the electric field can be dispersed along the inclined portion 182, so that the electric field concentration on the opening edge portion 124 of the gate trench 121 can be alleviated.

[0370] The gate insulating layer 131 includes a bulging portion 183 that bulges into the gate trench 121 at the inclined portion 182 of the gate trench 121. The bulging portion 183 is formed at a corner connecting the first region 131a and the third region 131c of the gate insulating layer 131.

[0371] The bulging portion 183 protrudes in a curved shape toward the inside of the gate trench 121. The bulging portion 183 narrows the opening of the gate trench 121 at the opening edge portion 124 of the gate trench 121.

[0372] The upper end portion of the gate electrode layer 132 has a constricted portion that is recessed along the bulging portion 183 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end portion) of the gate electrode layer 132. The edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 183 of the gate insulating layer 131 in this form.

[0373] The opening edge portion 142 of the source trench 141 has an inclined portion 184 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the side wall of the source trench 141. According to the inclined portion 184 of the source trench 141, the electric field can be dispersed along the inclined portion 184, so that the electric field concentration on the opening edge portion 142 of the source trench 141 can be alleviated.

[0374] Figs. 20A to 20C are cross-sectional views showing an example of a method for manufacturing the semiconductor device 181 shown in Fig. 19.

[0375] First, referring to Fig. 20A, a SiC semiconductor layer 102 in which the gate trench 121 and the source trench 141 are formed on the first main surface 103 through the steps of Figs. 17A to 17D is prepared.

[0376] Next, referring to FIG. 20B, a thermal oxidation treatment is performed on the first main surface 103 of the SiC semiconductor layer 102 to form a sacrificial oxide film 185. In this step, oxidation uniformly starts from both the first main surface 103 of the SiC semiconductor layer 102 and the sidewalls of the gate trench 121.

[0377] The oxide film advancing from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film advancing from the sidewalls of the gate trench 121 are integrated at the opening edge portion 124 of the gate trench 121.

[0378] Due to the integration of these oxide films, the oxidation at the opening edge portion 124 of the gate trench 121 is accelerated. Then, an inclined portion 182 is formed below the oxide film integrated at the opening edge portion 124 of the gate trench 121.

[0379] The oxide film advancing from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film advancing from the sidewalls of the source trench 141 are integrated at the opening edge portion 142 of the source trench 141.

[0380] Due to the integration of these oxide films, the oxidation at the opening edge portion 142 of the source trench 141 is accelerated. Then, an inclined portion 184 is formed below the oxide film integrated at the opening edge portion 142 of the source trench 141.

[0381] Next, referring to FIG. 20C, the sacrificial oxide film 185 is removed. The sacrificial oxide film 185 may be removed by an etching method (for example, a wet etching method). Then, the steps of FIGS. 17F to 17L are sequentially executed.

[0382] In the step of FIG. 17F, the bulging portion 183 of the gate insulating layer 131 is formed by setting predetermined conditions (gas flow rate, gas species, gas ratio, gas supply time, etc.) of the CVD method in consideration of the shape of the bulging portion 183 of the gate insulating layer 131. Through the steps including the above, the semiconductor device 181 is manufactured.

[0383] As described above, according to the semiconductor device 181, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 183 of the gate insulating layer 131. Thereby, it is possible to appropriately suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the SiC semiconductor layer 102.

[0384] Further, according to the semiconductor device 181, in addition to the opening edge portion 124 of the gate trench 121 having the inclined portion 182, the bulging portion 183 is formed in the opening edge portion 124 of the gate trench 121. Thereby, it is possible to further improve the breakdown voltage of the gate insulating layer 131 at the opening edge portion 124 of the gate trench 121.

[0385] In the present embodiment, a morphological example in which the gate insulating layer 131 having the bulging portion 183 is formed in the semiconductor device 181 has been described. However, the gate insulating layer 131 having no bulging portion 183 may be formed in the semiconductor device 181.

[0386] FIG. 21 is an enlarged view of a region corresponding to FIG. 12, and is an enlarged view showing a semiconductor device 191 according to the tenth embodiment of the present invention. FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 21. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0387] Referring to FIGS. 21 and 22, in the semiconductor device 191, an outer gate trench 192 is formed in the outer region 107 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 192 extends in a strip shape in the outer region 107.

[0388] The outer gate trench 192 is formed in a region directly below the gate finger 109 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 192 extends along the gate finger 109.

[0389] The outer gate trench 192 is formed, more specifically, along three side surfaces 105A, 105B, 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions. The outer gate trench 192 may be formed in an endless shape (for example, a square ring shape) surrounding the active region 106.

[0390] The outer gate trench 192 communicates with the contact trench portion 121b of each gate trench 121. Thereby, the outer gate trench 192 and the gate trench 121 are formed by one trench.

[0391] The gate wiring layer 133 is embedded in the outer gate trench 192. The gate wiring layer 133 is connected to the gate electrode layer 132 at the communication portion of the outer gate trench 192 and the contact trench portion 121b.

[0392] In this form, the low-resistance electrode layer 134 covers the upper end portion of the gate wiring layer 133 in the outer gate trench 192. Therefore, both the low-resistance electrode layer 134 covering the gate electrode layer 132 and the low-resistance electrode layer 134 covering the gate wiring layer 133 are located in one trench.

[0393] In this form, the peripheral deep well region 148 covers the inner wall of the outer gate trench 192 in the outer region 107. The peripheral deep well region 148 extends along the side wall of the outer gate trench 192 and covers the bottom wall of the outer gate trench 192 through the edge portion.

[0394] That is, in the portion along the inner wall of the outer gate trench 192, the peripheral deep well region 148 faces the gate wiring layer 133 with the gate insulating layer 131 interposed therebetween. Also, in the portion along the inner wall of the gate trench 121, the peripheral deep well region 148 faces the gate electrode layer 132 with the gate insulating layer 131 interposed therebetween.

[0395] As described above, the semiconductor device 191 can also achieve the same effects as those described for the semiconductor device 101. Further, according to the semiconductor device 191, it is not necessary to draw out the gate wiring layer 133 onto the first main surface 103 of the SiC semiconductor layer 102.

[0396] Thereby, it is possible to suppress the gate wiring layer 133 from facing the SiC semiconductor layer 102 with the gate insulating layer 131 interposed therebetween at the opening edge portions of the gate trench 121 and the outer gate trench 192. As a result, it is possible to suppress the concentration of the electric field at the opening edge portion of the gate trench 121.

[0397] FIG. 23 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of a semiconductor device 201 according to the eleventh embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0398] Referring to FIG. 23, in the semiconductor device 201, each source trench 141 is formed deeper than the gate trench 121. Therefore, the bottom wall of each source trench 141 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of the gate trench 121. More specifically, the bottom wall of each source trench 141 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0399] The ratio of the depth of the source trench 141 to the depth of the gate trench 121 may be 1.5 or more. The ratio of the depth of the source trench 141 to the depth of the gate trench 121 is preferably 2 or more.

[0400] The depth of the gate trench 121 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). The depth of the source trench 141 may be 0.75 μm or more and 10 μm or less (for example, about 2 μm).

[0401] Similar to the semiconductor device 101, the deep well region 145 extends along the inner wall of the source trench 141 and has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 121. The deep well region 145 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0402] As described above, the semiconductor device 201 can also achieve the same effects as those described for the semiconductor device 101.

[0403] FIG. 24 is an enlarged view of a region corresponding to FIG. 12, and is an enlarged view for explaining the structure of the semiconductor device 211 according to the twelfth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101, the same reference numerals are given and the description is omitted.

[0404] Referring to FIG. 24, in this embodiment, the gate trench 121 is formed in a lattice shape integrally including a plurality of gate trenches 121 extending along the first direction X and a plurality of gate trenches 121 extending along the second direction Y in a plan view.

[0405] On the first main surface 103 of the SiC semiconductor layer 102, a plurality of cell regions 212 are partitioned in a matrix by the gate trench 121. Each cell region 212 is formed in a square shape in a plan view. The source trench 141 is formed in each of the plurality of cell regions 212. The source trench 141 may be formed in a square shape in a plan view.

[0406] The cross-sectional view taken along the XIII-XIII line in FIG. 24 is substantially the same as the cross-sectional view shown in FIG. 13. The cross-sectional view taken along the XIV-XIV line in FIG. 24 is substantially the same as the cross-sectional view shown in FIG. 14.

[0407] As described above, the semiconductor device 211 can also achieve the same effects as those described for the semiconductor device 101. The gate trench 121 having a structure formed in a lattice shape instead of a stripe shape is applicable to other embodiments.

[0408] FIG. 25 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of the semiconductor device 221 according to the 13th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0409] Referring to FIG. 25, in the semiconductor device 221, the SiC semiconductor layer 102 includes a p + -type SiC semiconductor substrate 222 instead of the n + -type SiC semiconductor substrate 111. The p + -type SiC semiconductor substrate 222 is formed as a collector region of an IGBT (Insulated Gate Bipolar Transistor).

[0410] The description of the semiconductor device 101 is applied mutatis mutandis to the description of the semiconductor device 221 by reading the “source” of the MISFET as the “emitter” of the IGBT and the “drain” of the MISFET as the “collector” of the IGBT.

[0411] That is, the source pad 110 and the source region 126 are respectively read as the emitter pad (110) and the emitter region (126). Also, the drain pad 113 and the drain region 114 are respectively read as the collector electrode layer (113) and the collector region (114).

[0412] As described above, the semiconductor device 221 can also achieve the same effects as those described for the semiconductor device 101.

[0413] FIG. 26 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of the semiconductor device 231 according to the 14th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0414] Referring to FIG. 26, the contact region 144 is formed in the deep well region 145 along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0415] The source insulating layer 146 is formed along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0416] More specifically, the source insulating layer 146 includes a first portion 232 and a second portion 233. The first portion 232 covers the side wall of the source trench 141. The second portion 233 partially covers the bottom wall of the source trench 141.

[0417] The second portion 233 is continuous with the first portion 232. The second portion 233 extends from the corner of the source trench 141 along the bottom wall so as to expose the central portion of the bottom wall of the source trench 141. The second portion 233 may be formed in an endless (annular) shape in plan view.

[0418] As described above, according to the semiconductor device 231, the same effects as those described for the semiconductor device 101 can be achieved. Further, according to the semiconductor device 231, a pn junction is formed in the boundary region between the SiC semiconductor layer 102 and the deep well region 145.

[0419] Even if a depletion layer extends from this pn junction along the bottom wall from the corner of the source trench 141, the distance until the depletion layer reaches the source electrode layer 147 can be provided by the source insulating layer 146. Thereby, the occurrence of punch-through can be suppressed in the vicinity of the corner of the source trench 141.

[0420] FIG. 27 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of a semiconductor device 241 according to the 15th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101, the same reference numerals will be given and the description will be omitted.

[0421] Referring to FIG. 27, an exposed portion 242 is formed in the deep well region 145 to selectively expose the bottom wall of the source trench 141. The exposed portion 242 exposes the central portion of the bottom wall of the source trench 141.

[0422] In this form, the source insulating layer 146 includes a first portion 243 and a second portion 244. The first portion 243 covers the side wall of the source trench 141. The second portion 244 partially covers the bottom wall of the source trench 141.

[0423] The second portion 244 is continuous with the first portion 243. The second portion 244 extends from the corner of the source trench 141 along the bottom wall so as to expose the central portion of the bottom wall of the source trench 141. The second portion 244 may be formed in an endless (annular) shape in plan view.

[0424] The source electrode layer 147 forms a heterojunction with the SiC semiconductor layer 102 at the exposed portion 242 of the deep well region 145. Thereby, a heterojunction diode 245 with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode is formed. The source electrode layer 147 may contain a conductive material other than polysilicon as long as the heterojunction diode 245 is formed.

[0425] A body diode 246 is formed at the pn junction between the SiC semiconductor layer 102 and the body region 116. The junction barrier of the heterojunction diode 245 is smaller than the diffusion potential of the body diode 246.

[0426] The junction barrier of the heterojunction diode 245 may be 1.0 eV or more and 1.5 eV or less. The diffusion potential of the body diode 246 may be 2.8 eV or more and 3.2 eV or less.

[0427] As described above, according to the semiconductor device 241, the same effects as those described for the semiconductor device 101 can be achieved. Further, in the semiconductor device 241, when a reverse bias voltage is applied, current can be preferentially passed through the heterojunction diode 245.

[0428] Thereby, the expansion of crystal defects of SiC in the SiC semiconductor layer 102 can be suppressed. As a result, while improving the short-circuit withstand voltage and reducing the feedback capacitance Crss, an increase in the on-resistance can be suppressed.

[0429] FIG. 28 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of a semiconductor device 251 according to the 16th embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 101, the same reference numerals are given and the description thereof is omitted.

[0430] Referring to FIG. 28, the contact region 144 is formed in a region along the bottom wall of the source trench 141 within the deep well region 145. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0431] The source insulating layer 146 has a laminated structure including a plurality of barrier forming layers formed along the inner wall of the source trench 141. In this form, the source insulating layer 146 has a laminated structure including an insulating barrier forming layer 252 and a conductive barrier forming layer 253 laminated in this order from the inner wall of the source trench 141.

[0432] The insulating barrier forming layer 252 may contain at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0433] The insulating barrier forming layer 252 is formed in a film shape along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0434] The insulating barrier forming layer 252 more specifically includes a first portion 254 and a second portion 255. The first portion 254 covers the sidewalls of the source trench 141. The second portion 255 selectively covers the bottom wall of the source trench 141.

[0435] The second portion 255 is continuous with the first portion 254. The second portion 255 extends along the bottom wall from the corner of the source trench 141 so as to expose the central portion of the bottom wall of the source trench 141.

[0436] The conductive barrier forming layer 253 may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier forming layer 253 includes a conductive material different from the conductive material of the source electrode layer 147.

[0437] The conductive barrier forming layer 253 is formed in a film shape along the insulating barrier forming layer 252 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0438] The source insulating layer 146 may include an insulating barrier forming layer made of an insulating material different from the insulating barrier forming layer 252 instead of the conductive barrier forming layer 253. The source insulating layer 146 may include an insulating barrier forming layer made of the same insulating material as the insulating barrier forming layer 252 instead of the conductive barrier forming layer 253.

[0439] As described above, according to the semiconductor device 251, the same effects as those described for the semiconductor device 101 can be achieved. Further, in the semiconductor device 251, the source insulating layer 146 has a laminated structure including the insulating barrier forming layer 252 and the conductive barrier forming layer 253. Thereby, the occurrence of punch-through can be suppressed by the two layers of the insulating barrier forming layer 252 and the conductive barrier forming layer 253.

[0440] FIG. 29 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of the semiconductor device 261 according to the seventeenth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101, the same reference numerals will be given and the description will be omitted.

[0441] Referring to FIG. 29, the contact region 144 is formed in a region along the sidewall of the source trench 141 within the body region 116. The contact region 144 is exposed from the sidewall of the source trench 141.

[0442] The source insulating layer 146 includes a first portion 262 and a second portion 263. The first portion 262 covers the sidewall of the source trench 141. The second portion 263 covers the bottom wall of the source trench 141.

[0443] The first portion 262 selectively has a sidewall contact hole 264 that exposes the SiC semiconductor layer 102 from the sidewall of the source trench 141. The first portion 262 may be formed so as to cross the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0444] The lower end portion (the end portion on the bottom wall side of the source trench 141) of the first portion 262 may be located on the bottom wall side of the source trench 141 with respect to the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 within the source trench 141.

[0445] The lower end portion of the first portion 262 may be located on the first main surface 103 side with respect to the bottom of the body region 116. The lower end portion of the first portion 262 may be formed in a region between the bottom of the body region 116 and the bottom of the source region 126. In these cases, the source electrode layer 147 is connected to at least the body region 116 within the source trench 141.

[0446] The lower end of the first portion 262 may be formed in a region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the source region 126. The source insulating layer 146 may have only the second portion 263 and not have the first portion 262. In these cases, the source electrode layer 147 is connected to the body region 116 and the contact region 144 within the source trench 141.

[0447] The second portion 263 of the source insulating layer 146 is formed at a distance from the first portion 262 of the source insulating layer 146. That is, the second portion 263 is separated from the first portion 262. The second portion 263 may cover a corner portion of the source trench 141.

[0448] The second portion 263 may expose a corner portion of the source trench 141. The second portion 263 may cover a corner portion of the source trench 141 and also cover a part of the side wall of the source trench 141.

[0449] The source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) within the source trench 141. Thereby, a Schottky barrier diode 265 is formed with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode.

[0450] The p-type deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the bottom wall of the source trench 141. In this form, the deep well region 145 is formed in the high concentration region 112a of the SiC epitaxial layer 112. The entire area of the deep well region 145 is formed in the high concentration region 112a.

[0451] The deep well region 145 may be continuously formed in the SiC semiconductor layer 102 in a region along the side wall and the corner portion of the source trench 141 so as to expose the source electrode layer 147 from the side wall of the source trench 141.

[0452] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the corner connecting the side wall and the bottom wall of the source trench 141. The deep well region 145 may expose substantially the entire area of the side wall of the source trench 141 in the SiC semiconductor layer 102.

[0453] The deep well region 145 is drawn out in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102 from the bottom wall of the source trench 141. Thereby, the deep well region 145 faces the body region 116 with a part of the SiC semiconductor layer 102 (drift region 115) interposed therebetween with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0454] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) at a depth position between the body region 116 and the deep well region 145 with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0455] Even more specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) in a region of the SiC semiconductor layer 102 sandwiched by the body region 116 and the deep well region 145 with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0456] The source electrode layer 147 may have a stacked structure including a plurality of electrode layers. The source electrode layer 147 may include a first electrode layer and a second electrode layer stacked in this order from the SiC semiconductor layer 102 side.

[0457] The first electrode layer may be a barrier electrode layer including a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may have a laminated structure in which a Ti (titanium) film and a TiN (titanium nitride) film are laminated in this order from the SiC semiconductor layer 102 side. The first electrode layer may have a single-layer structure composed of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may contain aluminum or tungsten.

[0458] As described above, according to the semiconductor device 261, the same effects as those described for the semiconductor device 101 can be achieved. Also, in the semiconductor device 261, when a reverse bias voltage is applied, current can preferentially flow through the Schottky barrier diode 265.

[0459] Thereby, the expansion of crystal defects of SiC in the SiC semiconductor layer 102 can be suppressed. As a result, while improving the short-circuit withstand capacity and reducing the feedback capacitance Crss, an increase in the on-resistance can be suppressed.

[0460] In this embodiment, an example in which the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 within the sidewall contact hole 264 of the source insulating layer 146 has been described. However, a form in which the source insulating layer 146 (the first portion 262 and the second portion 263) is not formed may also be adopted.

[0461] FIG. 30 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of a semiconductor device 271 according to the 18th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 201, the same reference numerals will be given and the description will be omitted.

[0462] Referring to FIG. 30, the contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141. The source insulating layer 146 is formed along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0463] More specifically, the source insulating layer 146 includes a first portion 272 and a second portion 273. The first portion 272 covers the side wall of the source trench 141. The second portion 273 partially covers the bottom wall of the source trench 141.

[0464] The second portion 273 is continuous with the first portion 272. The second portion 273 extends along the bottom wall from the corner of the source trench 141 so as to expose the central portion of the bottom wall of the source trench 141. The second portion 273 may be formed in an endless (annular) shape in plan view.

[0465] As described above, according to the semiconductor device 271, the same effects as those described for the semiconductor device 201 can be achieved. Further, according to the semiconductor device 271, a pn junction is formed in the boundary region between the SiC semiconductor layer 102 and the deep well region 145.

[0466] Even if the depletion layer spreads from this pn junction along the bottom wall from the corner of the source trench 141, the source insulating layer 146 can cover the distance until the depletion layer reaches the source electrode layer 147. Thereby, the occurrence of punch-through can be suppressed in the vicinity of the corner of the source trench 141.

[0467] FIG. 31 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of the semiconductor device 281 according to the 19th embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 201, the same reference numerals are given and the description is omitted.

[0468] Referring to FIG. 31, in the deep well region 145, an exposed portion 282 is formed to selectively expose the bottom wall of the source trench 141. The exposed portion 282 exposes the central portion of the bottom wall of the source trench 141.

[0469] In this form, the source insulating layer 146 includes a first portion 283 and a second portion 284. The first portion 283 covers the side wall of the source trench 141. The second portion 284 partially covers the bottom wall of the source trench 141.

[0470] The second portion 284 is continuous with the first portion 283. The second portion 284 extends from the corner of the source trench 141 along the bottom wall so as to expose the central portion of the bottom wall of the source trench 141. The second portion 284 may be formed in an endless (annular) shape in plan view.

[0471] The source electrode layer 147 forms a heterojunction with the SiC semiconductor layer 102 at the exposed portion 282 of the deep well region 145. Thereby, a heterojunction diode 285 is formed with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode. The source electrode layer 147 may contain a conductive material other than polysilicon as long as the heterojunction diode 285 is formed.

[0472] A body diode 286 is formed at the pn junction between the SiC semiconductor layer 102 and the body region 116. The junction barrier of the heterojunction diode 285 is smaller than the diffusion potential of the body diode 286.

[0473] The junction barrier of the heterojunction diode 285 may be 1.0 eV or more and 1.5 eV or less. The diffusion potential of the body diode 286 may be 2.8 eV or more and 3.2 eV or less.

[0474] As described above, according to the semiconductor device 281, the same effects as those described for the semiconductor device 201 can be achieved. Further, in the semiconductor device 281, when a reverse bias voltage is applied, current can be preferentially passed through the heterojunction diode 285.

[0475] Thereby, the expansion of crystal defects of SiC in the SiC semiconductor layer 102 can be suppressed. As a result, while improving the short-circuit withstand voltage and reducing the reverse transfer capacitance Crss, an increase in the on-resistance can be suppressed.

[0476] FIG. 32 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of the semiconductor device 291 according to the 20th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 201, the same reference numerals are given and the description thereof is omitted.

[0477] Referring to FIG. 32, the contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0478] The source insulating layer 146 has a laminated structure including a plurality of barrier forming layers formed along the inner wall of the source trench 141. In this embodiment, the source insulating layer 146 has a laminated structure including an insulating barrier forming layer 292 and a conductive barrier forming layer 293 laminated in this order from the inner wall of the source trench 141.

[0479] The insulating barrier forming layer 292 may contain at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0480] The insulating barrier forming layer 292 is formed in a film shape along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0481] The insulating barrier formation layer 292 more specifically includes a first portion 294 and a second portion 295. The first portion 294 covers the sidewalls of the source trench 141. The second portion 295 selectively covers the bottom wall of the source trench 141.

[0482] The second portion 295 is continuous with the first portion 294. The second portion 295 extends along the bottom wall from the corner of the source trench 141 so as to expose the central portion of the bottom wall of the source trench 141.

[0483] The conductive barrier formation layer 293 may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier formation layer 293 contains a conductive material different from the conductive material of the source electrode layer 147.

[0484] The conductive barrier formation layer 293 is formed in a film shape along the insulating barrier formation layer 292 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0485] As described above, according to the semiconductor device 291, the same effects as those described for the semiconductor device 201 can be achieved. Further, in the semiconductor device 291, the source insulating layer 146 has a laminated structure including the insulating barrier formation layer 292 and the conductive barrier formation layer 293. Thereby, the occurrence of punch-through can be suppressed by the two layers of the insulating barrier formation layer 292 and the conductive barrier formation layer 293.

[0486] FIG. 33 is a cross-sectional view of a region corresponding to FIG. 13, and is a cross-sectional view for explaining the structure of a semiconductor device 301 according to the 21st embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 201, the same reference numerals will be given and the description will be omitted.

[0487] Referring to FIG. 33, the contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0488] The source insulating layer 146 includes a first portion 302 and a second portion 303. The first portion 302 covers the side wall of the source trench 141. The second portion 303 covers the bottom wall of the source trench 141.

[0489] The first portion 302 selectively has a side wall contact hole 304 that exposes the SiC semiconductor layer 102 from the side wall of the source trench 141. The first portion 302 may be formed so as to cross the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0490] The lower end portion (the end portion on the source trench 141 side) of the first portion 302 may be located on the bottom wall side of the source trench 141 with respect to the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 in the source trench 141.

[0491] The lower end portion of the first portion 302 may be located on the first main surface 103 side with respect to the bottom of the body region 116. The lower end portion of the first portion 302 may be formed in a region between the bottom of the body region 116 and the bottom of the source region 126. In these cases, the source electrode layer 147 is connected to at least the body region 116 in the source trench 141.

[0492] The lower end portion of the first portion 302 may be formed in a region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the source region 126. The source insulating layer 146 may have only the second portion 303 without the first portion 302. In these cases, the source electrode layer 147 is connected to the body region 116 and the contact region 144 in the source trench 141.

[0493] The second portion 303 of the source insulating layer 146 is formed at a distance from the first portion 302 of the source insulating layer 146. That is, the second portion 303 is separated from the first portion 302. The second portion 303 may cover the corner of the source trench 141.

[0494] The second portion 303 may expose the corner of the source trench 141. The second portion 303 may cover the corner of the source trench 141 and also cover a part of the sidewall of the source trench 141.

[0495] The source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) within the source trench 141. Thereby, a Schottky barrier diode 305 is formed with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode.

[0496] The p-type deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the bottom wall of the source trench 141. In this form, the deep well region 145 is formed in the high-concentration region 112a of the SiC epitaxial layer 112. The entire area of the deep well region 145 is formed in the high-concentration region 112a.

[0497] The deep well region 145 may be continuously formed in the SiC semiconductor layer 102 in a region along the sidewall and corner of the source trench 141 so as to expose the source electrode layer 147 from the sidewall of the source trench 141.

[0498] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the corner connecting the sidewall and the bottom wall of the source trench 141. The deep well region 145 may expose substantially the entire area of the sidewall of the source trench 141 in the SiC semiconductor layer 102.

[0499] The deep well region 145 is drawn out in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102 from the bottom wall of the source trench 141. As a result, the deep well region 145 faces the body region 116 with a part of the SiC semiconductor layer 102 (drift region 115) interposed therebetween with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0500] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) at a depth position between the body region 116 and the deep well region 145 with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0501] Even more specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) in a region of the SiC semiconductor layer 102 sandwiched by the body region 116 and the deep well region 145 with respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0502] The source electrode layer 147 may have a stacked structure including a plurality of electrode layers. The source electrode layer 147 may include a first electrode layer and a second electrode layer stacked in this order from the SiC semiconductor layer 102 side.

[0503] The first electrode layer may be a barrier electrode layer including a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may have a stacked structure in which a Ti (titanium) film and a TiN (titanium nitride) film are stacked in this order from the SiC semiconductor layer 102 side. The first electrode layer may have a single-layer structure composed of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may contain aluminum or tungsten.

[0504] As described above, the semiconductor device 301 can achieve the same effects as those described for the semiconductor device 201. Further, in the semiconductor device 301, when a reverse bias voltage is applied, current can be preferentially passed through the Schottky barrier diode 305.

[0505] This can suppress the expansion of crystal defects of SiC in the SiC semiconductor layer 102. As a result, while improving the short-circuit withstand capacity and reducing the reverse transfer capacitance Crss, an increase in the on-resistance can be suppressed.

[0506] In this embodiment, an example in which the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 within the sidewall contact hole 264 of the source insulating layer 146 has been described. However, a form in which the source insulating layer 146 (the first portion 302 and the second portion 303) is not formed may be adopted.

[0507] Although the seventh to twenty-first embodiments of the present invention have been described, the seventh to twenty-first embodiments of the present invention can also be implemented in other forms.

[0508] In the above-described seventh to twenty-first embodiments, an example in which the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b is formed by the epitaxial growth method has been described. However, the SiC epitaxial layer 112 can also be formed by the following steps.

[0509] First, a SiC epitaxial layer 112 having a relatively low n-type impurity concentration is formed by the epitaxial growth method. Next, n-type impurities are introduced into the surface layer portion of the SiC epitaxial layer 112 by the ion implantation method. Thereby, the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b is formed.

[0510] In the foregoing 7th to 21st embodiments, an example in which the SiC semiconductor layer 102 has a stacked structure including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112 has been described. However, the SiC semiconductor layer 102 may have a single-layer structure composed of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may have a single-layer structure composed of the SiC epitaxial layer 112.

[0511] In the foregoing 7th to 21st embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0512] In the foregoing 7th to 21st embodiments, an example in which the gate electrode layer 132 and the gate wiring layer 133 including p-type polysilicon to which a p-type impurity is added are formed has been described. However, when the increase in the gate threshold voltage Vth is not emphasized, the gate electrode layer 132 and the gate wiring layer 133 may include n-type polysilicon to which an n-type impurity is added instead of p-type polysilicon.

[0513] The low-resistance electrode layer 134 may be formed by siliciding a portion forming the surface layer portion in the gate electrode layer 132 (n-type polysilicon) with a metal material. That is, the low-resistance electrode layer 134 may include an n-type polyside. In the case of such a structure, reduction of the gate resistance can be achieved.

[0514] In the foregoing 7th to 21st embodiments, the structure of the semiconductor device 221 may be adopted. That is, in the foregoing 7th to 21st embodiments, instead of the n + -type SiC semiconductor substrate 111, a p + -type SiC semiconductor substrate 222 may be adopted. In this case, the descriptions of the foregoing 7th to 13th embodiments shall be read with "source" replaced by "emitter" and "drain" replaced by "collector".

[0515] FIG. 34 is a top view showing a semiconductor device 311 according to the 22nd embodiment of the present invention. FIG. 35 is a bottom view of the semiconductor device 311 shown in FIG. 34. Hereinafter, the structures corresponding to those described for the semiconductor device 101 will be described with the same reference numerals.

[0516] Referring to FIG. 34, the semiconductor device 311 has a SiC semiconductor layer 102 including a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may include a 4H-SiC single crystal.

[0517] The 4H-SiC single crystal has an off-angle inclined at an angle within 10° with respect to the [11-20] direction from the (0001) plane. The off-angle may be 0° or more and 4° or less. The off-angle may be more than 0° and less than 4°. The off-angle is typically set in the range of 2° or 4°, more specifically, in the range of 2° ± 0.2° or 4° ± 0.4°.

[0518] In this form, the SiC semiconductor layer 102 is formed in a rectangular parallelepiped chip shape. The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular shape in this form) in plan view (hereinafter simply referred to as "plan view") as viewed from their normal directions.

[0519] The side surface 105A faces the side surface 105C. The side surface 105B faces the side surface 105D. The four side surfaces 105A to 105D each extend planar along the normal directions of the first main surface 103 and the second main surface 104. The lengths of the side surfaces 105A to 105D may each be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0520] An active region 106 and an outer region 107 are set in the SiC semiconductor layer 102. The active region 106 is a region where vertical MISFETs are formed. The outer region 107 is a region outside the active region 106.

[0521] In plan view, the active region 106 is set in the central portion of the SiC semiconductor layer 102 at an interval from the side surfaces 105A to 105D of the SiC semiconductor layer 102 toward the inner region. The active region 106 is set in a rectangular shape (a rectangular shape in this form) having four sides parallel to the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view.

[0522] The outer region 107 is set in a region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 106. The outer region 107 is set in an endless shape (square annular shape) surrounding the active region 106 in plan view.

[0523] A gate pad 108, a gate finger 109, and a source pad 110 are formed on the first main surface 103 of the SiC semiconductor layer 102. The gate pad 108, the gate finger 109, and the source pad 110 may contain aluminum and / or copper.

[0524] The gate pad 108 is formed along the side surface 105A of the SiC semiconductor layer 102 in plan view. The gate pad 108 is formed along the central region of the side surface 105A of the SiC semiconductor layer 102 in plan view. The gate pad 108 may be formed along a corner connecting any two of the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view.

[0525] The gate pad 108 is formed in a rectangular shape in plan view. The gate pad 108 is drawn from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in plan view.

[0526] The gate finger 109 includes an outer gate finger 109A and an inner gate finger 109B. The outer gate finger 109A is drawn out from the gate pad 108 to the outer region 107. The outer gate finger 109A extends in a strip shape in the outer region 107.

[0527] In this form, the outer gate finger 109A is formed along three side surfaces 105A, 105B, 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0528] The inner gate finger 109B is drawn out from the gate pad 108 to the active region 106. The inner gate finger 109B extends in a strip shape in the active region 106. The inner gate finger 109B extends from the side surface 105A side toward the side surface 105C side.

[0529] The source pad 110 is formed in the active region 106 at a distance from the gate pad 108 and the gate finger 109. The source pad 110 is formed in a C shape (an inverted C shape in FIG. 34) in plan view so as to cover a C-shaped (an inverted C-shaped in FIG. 34) region partitioned by the gate pad 108 and the gate finger 109.

[0530] A gate voltage is applied to the gate pad 108 and the gate finger 109. The gate voltage may be 10V or more and 50V or less (for example, about 30V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, GND voltage).

[0531] A resin layer 312 is formed on the first main surface 103 of the SiC semiconductor layer 102 (more specifically, on the interlayer insulating layer 153). In FIG. 34, for clarity, the resin layer 312 is shown by hatching. The resin layer 312 covers the gate pad 108, the gate finger 109, and the source pad 110.

[0532] The resin layer 312 may contain a negative-type or positive-type photosensitive resin. In this form, the resin layer 312 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 312 may contain polyimide as an example of a negative-type photosensitive resin.

[0533] The peripheral portion of the resin layer 312 is formed at a distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 in the inner region. Thereby, the peripheral portion of the resin layer 312 exposes the first main surface 103 of the SiC semiconductor layer 102. More specifically, the peripheral portion of the resin layer 312 exposes the interlayer insulating layer 153.

[0534] A gate pad opening 313 and a source pad opening 314 are formed in the resin layer 312. The gate pad opening 313 exposes the gate pad 108. The source pad opening 314 exposes the source pad 110.

[0535] Referring to FIG. 35 and the enlarged view of FIG. 35, a group of protrusions 316 including a plurality of protrusions 315 is formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of protrusions 315 are portions that protrude along the normal direction of the second main surface 104 of the SiC semiconductor layer 102 on the second main surface 104 of the SiC semiconductor layer 102.

[0536] The plurality of protrusions 315 are formed at intervals along an arbitrary first direction X and a second direction Y intersecting the first direction X. The first direction X is one of the plane directions of the first main surface 103 of the SiC semiconductor layer 102.

[0537] In this form, the first direction X is set in a direction parallel to the side surfaces 105B and 105D of the SiC semiconductor layer 102. More specifically, the second direction Y is a direction orthogonal to the first direction X. That is, in this form, the second direction Y is set in a direction parallel to the side surfaces 105A and 105C of the SiC semiconductor layer 102.

[0538] The group of protrusions 316 has a first portion 317 in which some of the plurality of protrusions 315 overlap the first direction X in a first-direction view as seen from the first direction X.

[0539] Further, the group of protrusions 316 has a second portion 318 that is formed by separating some of the plurality of protrusions 315 from the first portion 317 and that overlaps the first direction X in the first-direction view.

[0540] The plurality of protrusions 315 are continuously formed along the first direction X. More specifically, the plurality of protrusions 315 have a dot pattern that is spaced apart along the first direction X and the second direction Y.

[0541] The plurality of protrusions 315 are continuously formed along the first direction X while maintaining this dot pattern. In this form, the plurality of protrusions 315 are formed across from the periphery on one side surface 105A side to the periphery on the other side surface 105C side of the SiC semiconductor layer 102 in a plan view.

[0542] The distances between the plurality of protrusions 315 formed at intervals in the first direction X in the group of protrusions 316 may be different from each other. The distances between the plurality of protrusions 315 formed at intervals in the second direction Y in the group of protrusions 316 may be different from each other.

[0543] The plurality of protrusions 315 may each be formed with a non-uniform shape, size, and thickness. The thickness of the protrusion 315 is the distance from the base to the top (tip portion) of the protrusion 315 with respect to the normal direction of the second main surface 104 of the SiC semiconductor layer 102.

[0544] The plurality of protrusions 315 may each have a size exceeding 0 μm and 10 μm or less. Each protrusion 315 may have a thickness of 500 nm or less (for example, 1 nm or more and 250 nm).

[0545] The group of protrusions 316 is formed in a range narrower than the widths of the side surfaces 105A to 105D (in this form, the side surfaces 105A and 105C) of the SiC semiconductor layer 102 on the second main surface 104 of the SiC semiconductor layer 102.

[0546] The group of protrusions 316 is formed, for example, in a range of 1 / 1000 or more and 1 / 5 or less with respect to the widths of the side surfaces 105A to 105D (in this form, the side surfaces 105A and 105C) of the SiC semiconductor layer 102.

[0547] The group of protrusions 316 may be formed in a range of 1 / 200 or more and 1 / 10 or less with respect to the widths of the side surfaces 105A to 105D (in this form, the side surfaces 105A and 105C) of the SiC semiconductor layer 102.

[0548] The group of protrusions 316 may be formed in a range of 10 μm or more and 200 μm or less in the second direction Y. The group of protrusions 316 may be formed in a range of 50 μm or more and 150 μm or less in the second direction Y. The group of protrusions 316 may be formed in a range of 80 μm or more and 120 μm or less in the second direction Y.

[0549] The group of protrusions 316 has a layout in which a plurality of protrusions 315 overlap in the first direction X in a first-direction view seen from the first direction X. Thereby, the group of protrusions 316 forms a strip-shaped protrusion group region 319 along the first direction X by an aggregate pattern of a plurality of protrusions 315 that are continuously scattered along the first direction X.

[0550] In other words, the protrusion group region 319 includes a plurality of protrusions 315 (protrusion group 316) formed in a strip-shaped region extending along the first direction X on the second main surface 104 of the SiC semiconductor layer 102.

[0551] On the second main surface 104 of the SiC semiconductor layer 102, a plurality of protrusion groups 316 (protrusion group regions 319) having such a form are formed at intervals along the second direction Y.

[0552] That is, the scattered pattern of the plurality of protrusions 315 is discontinuously formed in the second direction view as viewed from the second direction Y. The distance between the plurality of protrusion groups 316 may have a value of 1% or more and 25% or less of the range in which the protrusion groups 316 are formed.

[0553] Regarding the second direction Y, the distance between the plurality of adjacent protrusion groups 316 may be 100 μm or less. The distance between the plurality of protrusion groups 316 may be 5 μm or more and 50 μm or less. The distance between the plurality of protrusion groups 316 may be 20 μm or less.

[0554] The first direction X may be set in the [11 - 20] direction, and the second direction Y may be set in the [1 - 100] direction. That is, the protrusion group 316 may form a strip-shaped protrusion group region 319 extending substantially parallel or parallel to the [11 - 20] direction, and a plurality of them may be formed at intervals along the [1 - 100] direction.

[0555] The first direction X may be set in the [1 - 100] direction, and the second direction Y may be set in the [11 - 20] direction. That is, the protrusion group 316 may form a strip-shaped protrusion group region 319 extending substantially parallel or parallel to the [1 - 100] direction, and a plurality of them may be formed at intervals along the [11 - 20] direction.

[0556] In the region between the adjacent protrusion groups 316 in the second direction Y on the second main surface 104 of the SiC semiconductor layer 102, a space 320 having no scattered pattern composed of the plurality of protrusions 315 is defined.

[0557] The space 320 is defined in a strip shape extending parallel to the first direction X by the adjacent protrusion groups 316 (protrusion group regions 319). As a result, on the second main surface 104 of the SiC semiconductor layer 102, a stripe pattern in which the protrusion groups 316 and the spaces 320 are alternately formed along the second direction Y is formed.

[0558] On the second main surface 104 of the SiC semiconductor layer 102, a plurality of grooves 321 are formed. In FIG. 35 and the enlarged view of FIG. 35, the grooves 321 are indicated by lines. The grooves 321 are formed in the raised portion groups 316 and the spaces 320.

[0559] The plurality of grooves 321 include grinding marks caused by grinding the second wafer main surface 333 of the SiC semiconductor wafer 331, which will be described later. Therefore, the direction in which the grooves 321 extend varies depending on the position where the SiC semiconductor layer 102 is cut out from the SiC semiconductor wafer 331.

[0560] The grooves 321 may extend substantially parallel or parallel to each raised portion group 316. The grooves 321 may include portions that intersect the raised portion groups 316. The grooves 321 may extend along a direction that intersects or is orthogonal to each raised portion group 316. The grooves 321 may extend linearly or in an arc shape.

[0561] Some of the plurality of raised portions 315 included in each raised portion group 316 are formed at intervals along the grooves 321. That is, each raised portion group 316 includes a third portion 322 in which some of the plurality of raised portions 315 are formed at intervals along the grooves 321 in a plan view.

[0562] Each raised portion group 316 is formed, for example, by an annealing treatment method. The plurality of raised portions 315 may be laser processing marks formed by a laser annealing treatment method.

[0563] The plurality of raised portions 315 (the third portion 322 of the raised portion group 316) along the grooves 321 may be formed by an annealing treatment method for the unevenness partitioned by the grooves 321 on the second main surface 104 of the SiC semiconductor layer 102 (the second wafer main surface 333 of the SiC semiconductor wafer 331).

[0564] As shown in FIGS. 36A to 36D, each raised portion group 316 can take various forms by adjusting the annealing treatment conditions (here, the laser annealing treatment conditions).

[0565] FIG. 36A is a diagram showing a second exemplary form of each group of protrusions 316.

[0566] As shown in FIG. 36A, the group of protrusions 316 may include convexly curved protrusions 315 that extend along the first direction X in a plan view and protrude along the second direction Y (side surface 105B side in FIG. 36A). The protrusions 315 may be formed by a plurality of protrusions 315 that overlap each other.

[0567] The distance between the two farthest points in the protrusion 315 may be 1 μm or more and 200 μm or less (about 50 μm in this exemplary form). With respect to the first direction X, the distance between a plurality of adjacent protrusions 315 is set to a value of 10% or more of the size of the protrusion 315. The plurality of protrusions 315 are formed by shifting adjacent laser irradiation positions in the first direction X.

[0568] FIG. 36B is a diagram showing a third exemplary form of the group of protrusions 316.

[0569] As shown in FIG. 36B, the group of protrusions 316 may include concavely curved protrusions 315 that extend along the second direction Y in a plan view and are recessed along the first direction X. The protrusions 315 may be formed by a plurality of protrusions 315 that overlap each other.

[0570] The distance between the two farthest points in each protrusion 315 may be 1 μm or more and 200 μm or less (about 50 μm in this exemplary form). The plurality of protrusions 315 are formed by overlapping adjacent laser irradiation positions in a range of 50% or more and 70% or less.

[0571] FIG. 36C is a diagram showing a fourth exemplary form of the group of protrusions 316.

[0572] As shown in FIG. 36C, the group of protrusions 316 may include a linear protrusion 315 that extends along the second direction Y in a plan view and is recessed along the first direction X. The protrusion 315 may have a protruding portion that protrudes along the first direction X. The protrusion 315 may be formed by a plurality of protrusions 315 that overlap each other.

[0573] The distance between the two farthest points in the protrusion 315 may be 1 μm or more and 200 μm or less (about 50 μm in this exemplary form). The plurality of protrusions 315 are formed by overlapping laser irradiation positions adjacent to each other in a range of 70% or more and 90% or less.

[0574] FIG. 36D is a diagram showing a fifth exemplary form of the group of protrusions 316.

[0575] As shown in FIG. 36D, the group of protrusions 316 may have a layout in which a row of protrusions 315 including a plurality of protrusions 315 arranged at intervals along the second direction Y is formed at intervals along the first direction X.

[0576] The distance between the two farthest points in the protrusion 315 may be 1 μm or more and 200 μm or less (about 5 μm in this exemplary form). The plurality of protrusions 315 are formed by overlapping laser irradiation positions adjacent to each other in a range of 90% or more and less than 100%.

[0577] FIG. 37 is an enlarged view of the region XXXVII shown in FIG. 34, and is a view in which the structure above the first main surface 103 of the SiC semiconductor layer 102 is removed. FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII of FIG. 37. FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX of FIG. 37. FIG. 40 is an enlarged view of the region XL shown in FIG. 39.

[0578] Referring to FIGS. 37 to 39, the semiconductor device 311 has the same planar structure and cross-sectional structure as the semiconductor device 101, except that a group of protrusions 316 is formed on the second main surface 104 of the SiC semiconductor layer 102.

[0579] Referring to FIG. 40, the group of protrusions 316 (a plurality of protrusions 315) and the grooves 321 are formed in the SiC semiconductor substrate 111. A modified layer 323 in which a part of the SiC of the SiC semiconductor layer 102 (SiC semiconductor substrate 111) is modified to other properties is formed in the surface layer portion of the second main surface 104 of the SiC semiconductor layer 102. The modified layer 323 is formed by an annealing treatment method for the second main surface 104 of the SiC semiconductor layer 102.

[0580] The modified layer 323 contains Si atoms and C atoms. More specifically, the modified layer 323 has a carbon density lower than that of the region outside the modified layer 323 in the SiC semiconductor layer 102 (SiC semiconductor substrate 111).

[0581] In addition, the modified layer 323 has a silicon density higher than the carbon density. That is, the modified layer 323 includes an Si modified layer in which the SiC of the SiC semiconductor layer 102 (SiC semiconductor substrate 111) is modified to Si. The Si modified layer may be an Si amorphous layer.

[0582] The modified layer 323 may contain lattice defects caused by the modification of SiC. That is, the modified layer 323 may include a lattice defect region having defect levels introduced due to the modification of SiC.

[0583] In this form, the modified layer 323 is formed in a region along the group of protrusions 316 in the surface layer portion of the second main surface 104 of the SiC semiconductor layer 102. Thereby, in each group of protrusions 316, the plurality of protrusions 315 are formed by the modified layer 323.

[0584] In this form, the modified layer 323 further extends from the group of protrusions 316 toward the space 320. That is, the annealing treatment method for the second main surface 104 of the SiC semiconductor layer 102 also reaches the space 320.

[0585] In the modified layer 323, the thickness of the portion along the group of raised portions 316 is greater than or equal to the thickness of the portion along the space 320 in the modified layer 323 due to the presence of the raised portion 315. More specifically, the thickness of the portion along the group of raised portions 316 in the modified layer 323 is greater than the thickness of the portion along the space 320 in the modified layer 323.

[0586] The thickness of the modified layer 323 may be 1 nm or more and 1000 nm or less. The thickness Ta of the region in the modified layer 323 where the raised portion 315 is formed may be 50 nm or more and 1000 nm or less. The thickness Tb of the region outside the raised portion 315 in the modified layer 323 may be 1 nm or more and 300 nm or less.

[0587] The thickness Ta may be 50 nm or more and 100 nm or less. The thickness Ta may be 100 nm or more and 150 nm or less. The thickness Ta may be 150 nm or more and 200 nm or less. The thickness Ta may be 200 nm or more and 250 nm or less.

[0588] The thickness Ta may be 250 nm or more and 300 nm or less. The thickness Ta may be 300 nm or more and 350 nm or less. The thickness Ta may be 350 nm or more and 400 nm or less. The thickness Ta may be 400 nm or more and 450 nm or less. The thickness Ta may be 450 nm or more and 500 nm or less.

[0589] The thickness Ta may be 500 nm or more and 600 nm or less. The thickness Ta may be 600 nm or more and 700 nm or less. The thickness Ta may be 700 nm or more and 800 nm or less. The thickness Ta may be 800 nm or more and 900 nm or less. The thickness Ta may be 900 nm or more and 1000 nm or less.

[0590] The thickness Tb may be 1 nm or more and 10 nm or less. The thickness Tb may be 10 nm or more and 50 nm or less. The thickness Tb may be 50 nm or more and 100 nm or less.

[0591] The thickness Tb may be 100 nm or more and 150 nm or less. The thickness Tb may be 150 nm or more and 200 nm or less. The thickness Tb may be 200 nm or more and 250 nm or less. The thickness Tb may be 250 nm or more and 300 nm or less.

[0592] The thickness Tb may be 1 / 2 or less, 1 / 3 or less, 1 / 4 or less, 1 / 5 or less, 1 / 6 or less, 1 / 7 or less, 1 / 8 or less, 1 / 9 or less, 1 / 10 or less, 1 / 11 or less, 1 / 12 or less, 1 / 13 or less, 1 / 14 or less, 1 / 15 or less, 1 / 16 or less, 1 / 17 or less, 1 / 18 or less, 1 / 19 or less, or 1 / 20 or less of the thickness Ta.

[0593] The resistance value of the second main surface 104 when the group of protrusions 316 does not exist on the second main surface 104 of the SiC semiconductor layer 102 is greater than the resistance value of the second main surface 104 when the group of protrusions 316 exists on the second main surface 104 of the SiC semiconductor layer 102.

[0594] That is, the plurality of groups of protrusions 316 have a resistance value equal to or less than the resistance value of a single crystal of SiC as an electrical characteristic. More specifically, the plurality of groups of protrusions 316 have a resistance value less than the resistance value of a single crystal of SiC.

[0595] Also, the plurality of groups of protrusions 316 have a resistance value equal to or less than the resistance value of the space 320. More specifically, the plurality of groups of protrusions 316 have a resistance value less than the resistance value of the space 320.

[0596] The resistance value of the group of protrusions 316 is reduced by the modified layer 323. That is, the resistance value of the group of protrusions 316 is equal to or less than the resistance value of a single crystal of SiC due to the modified layer 323 in which the properties of SiC are modified. Also, the resistance value of the space 320 is reduced by the modified layer 323.

[0597] In this form, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers the group of protrusions 316 on the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers the plurality of groups of protrusions 316 collectively.

[0598] The drain pad 113 is formed in a film shape following the outer surface of the group of protrusions 316 (the outer surfaces of the plurality of protrusions 315) and the inner surface of the groove 321. As a result, on the outer surface of the drain pad 113, a protrusion 113a that bulges in a direction away from the second main surface 104 is formed at the portion covering the group of protrusions 316 (the plurality of protrusions 315). Also, at the portion of the outer surface of the drain pad 113 that covers the groove 321, a recess 113b that is recessed toward the second main surface 104 is formed.

[0599] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms an ohmic contact with the group of protrusions 316.

[0600] More specifically, the drain pad 113 forms an ohmic contact with the plurality of groups of protrusions 316. Also, in this form, the drain pad 113 forms an ohmic contact with the space 320 as well.

[0601] The drain pad 113 has a laminated structure including a plurality of electrode layers laminated on the second main surface 104 of the SiC semiconductor layer 102. In this form, the drain pad 113 has a four-layer structure including a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327 laminated in this order from the second main surface 104 of the SiC semiconductor layer 102.

[0602] The Ti layer 324, Ni layer 325, Au layer 326, and Ag layer 327 are each formed in a film shape following the outer surface of the group of protrusions 316 (the outer surfaces of the plurality of protrusions 315) and the inner surface of the groove 321. The protrusions 113a and recesses 113b of the drain pad 113 are formed on the outer surface of the Ag layer 327.

[0603] The Ti layer 324 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ti layer 324 collectively covers the plurality of groups of protrusions 316 and forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. In this form, the Ti layer 324 also forms an ohmic contact with the space 320.

[0604] The Ni layer 325 covers almost all or all of the Ti layer 324. The Au layer 326 covers almost all or all of the Ni layer 325. The Ag layer 327 covers almost all or all of the Au layer 326.

[0605] The thickness of the Ti layer 324 may be 0.01 μm or more and 5 μm or less (for example, about 0.07 μm). The thickness of the Ni layer 325 may be 0.1 μm or more and 40 μm or less (for example, about 1.2 μm).

[0606] The thickness of the Au layer 326 may be 0.1 μm or more and 40 μm or less (for example, about 0.07 μm). The thickness of the Ag layer 327 may be 0.1 μm or more and 40 μm or less (for example, about 0.3 μm). Of course, the drain pad 113 may have a single-layer structure composed of the Ti layer 324, Ni layer 325, Au layer 326, or Ag layer 327.

[0607] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without passing through a silicide layer mainly composed of silicide. The drain pad 113 forms an ohmic contact with each group of protrusions 316 without passing through a silicide layer mainly composed of silicide.

[0608] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without passing through a carbon layer mainly composed of carbon. The drain pad 113 forms an ohmic contact with each group of protrusions 316 without passing through a carbon layer mainly composed of carbon.

[0609] The drain pad 113 does not include a region in which a material mainly composed of silicide is formed in a layered manner. Further, the drain pad 113 does not include a region in which a material mainly composed of carbon is formed in a layered manner.

[0610] FIG. 41A is a top view showing a SiC semiconductor wafer 331 used in the manufacture of the semiconductor device 311 shown in FIG. 34. FIG. 41B is a bottom view of the SiC semiconductor wafer 331 shown in FIG. 41A, showing a state after a grinding process and an annealing process on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0611] Referring to FIGS. 41A and 41B, the SiC semiconductor wafer 331 is made of a plate-shaped SiC single crystal formed in a disk shape. The SiC semiconductor wafer 331 serves as a base for the SiC semiconductor substrate 111.

[0612] The SiC semiconductor wafer 331 has a first wafer main surface 332 on one side, a second wafer main surface 333 on the other side, and a wafer side surface 334 connecting the first wafer main surface 332 and the second wafer main surface 333.

[0613] The SiC semiconductor wafer 331 may contain a 4H-SiC single crystal. The first wafer main surface 332 of the SiC semiconductor wafer 331 has an off-angle inclined at an angle within 10° with respect to the [11-20] direction from the (0001) plane.

[0614] The off-angle may be 0° or more and 4° or less. The off-angle may be more than 0° and less than 4°. The off-angle is typically set in the range of 2° or 4°, more specifically, in the range of 2°±0.2° or 4°±0.4°.

[0615] On the wafer side surface 334 of the SiC semiconductor wafer 331, one or more (in this form, one) orientation flats 335 indicating the crystal orientation are formed. The orientation flat 335 is a notch formed at the periphery of the SiC semiconductor wafer 331. In this form, the orientation flat 335 extends linearly along the [11-20] direction.

[0616] The first wafer main surface 332 is an element formation surface on which MISFETs are formed. A plurality of device formation regions 336 corresponding to the semiconductor device 311 are set on the first wafer main surface 332.

[0617] In this form, the plurality of device formation regions 336 are arranged in a matrix along the [11-20] direction ([-1-120] direction) and the [-1100] direction ([1-100] direction).

[0618] The grid-like region partitioning the plurality of device formation regions 336 is the dicing line 337. The semiconductor device 311 is diced out by cutting the SiC semiconductor wafer 331 along the periphery (dicing line 337) of the plurality of device formation regions 336.

[0619] Referring to FIG. 41B, in a state where the grinding process and the annealing process are performed on the second wafer main surface 333 of the SiC semiconductor wafer 331, a plurality of raised portion groups 316 and a plurality of grinding marks 338 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0620] The plurality of raised portion groups 316 are formed in a stripe shape substantially parallel or parallel to the orientation flat 335. The plurality of raised portion groups 316 may be formed in a stripe shape intersecting or orthogonal to the orientation flat 335.

[0621] The plurality of grinding marks 338 each extend in an arc shape from the central portion to the peripheral portion of the SiC semiconductor wafer 331. The plurality of grinding marks 338 generally include grinding marks 338 that intersect in the [11-20] direction and the [1-100] direction.

[0622] Further, the plurality of grinding marks 338 include grinding marks 338 that extend substantially parallel or parallel to the [11-20] direction or the [1-100] direction at portions where the tangent of the arc is along the [11-20] direction or the [1-100] direction. The groove 321 formed on the second main surface 104 of the SiC semiconductor layer 102 may be formed by a part of the grinding marks 338.

[0623] FIG. 42 is a flowchart for explaining an example of the manufacturing method of the semiconductor device 311 shown in FIG. 34. FIGS. 43A to 43I are cross-sectional views for explaining the manufacturing method of the semiconductor device 311 shown in FIG. 34.

[0624] In the manufacturing method of the semiconductor device 311, prior to the formation step of the drain pad 113 (see FIG. 17L) according to the manufacturing method of the semiconductor device 101, a processing step of the second wafer main surface 333 is performed. The processing step of the second wafer main surface 333 may be performed after the formation steps of the gate pad 108, the gate finger 109, and the source pad 110.

[0625] Referring to FIG. 43A, first, the steps of FIGS. 17A to 17L are performed, and a SiC semiconductor wafer 331 in which a MISFET is fabricated on the first wafer main surface 332 is prepared. The second wafer main surface 333 of the SiC semiconductor wafer 331 is in an untreated state.

[0626] Next, referring to FIG. 43B, the second wafer main surface 333 of the SiC semiconductor wafer 331 is ground (step S1 in FIG. 42). In this step, the second wafer main surface 333 of the SiC semiconductor wafer 331 is ground using abrasive grains having a particle size of 500 or more.

[0627] The grit size is preferably 1000 or more and 5000 or less. As a result, a plurality of grinding marks 338 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (see also FIG. 41B). Further, as a result, the second wafer main surface 333 of the SiC semiconductor wafer 331 is planarized, and at the same time, the SiC semiconductor wafer 331 is thinned.

[0628] Next, referring to FIG. 43C, a metal layer 341 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S2 in FIG. 42). In this form, the metal layer 341 is composed of a Ni layer. The Ni layer may be formed by a sputtering method. The thickness of the Ni layer may be 100 Å or more and 1000 Å or less.

[0629] Next, referring to FIG. 43D, an annealing treatment method is performed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S3 in FIG. 42). In this step, a laser annealing treatment method, which is an example of the annealing treatment method, is performed.

[0630] In the laser annealing treatment method, a pulsed laser beam having a laser diameter φ of 50 μm or more and 200 μm or less (for example, about 100 μm) is used. The pulsed laser beam is a UV laser beam having a wavelength in the ultraviolet region. The energy of the pulsed laser beam is 1.0 J / cm 2 or more and 4.0 J / cm 2 or less (for example, about 3.0 J / cm 2 ).

[0631] The pulsed laser beam is driven into the second wafer main surface 333 of the SiC semiconductor wafer 331 through the metal layer 341. In this form, the pulsed laser beam is driven into the second wafer main surface 333 of the SiC semiconductor wafer 331 while moving the irradiation position along the orientation flat 335.

[0632] In the region where the pulsed laser beam is driven into the second wafer main surface 333 of the SiC semiconductor wafer 331, one or more raised portions 315 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0633] Also, in the region where the pulsed laser light is implanted in the second wafer main surface 333 of the SiC semiconductor wafer 331, a modified layer 323 is formed in which the SiC of the SiC semiconductor wafer 331 is modified to other properties. More specifically, the SiC of the SiC semiconductor wafer 331 is modified to Si by the desorption and / or sublimation of C atoms from the SiC by heating.

[0634] Thereby, a modified layer 323 including an Si modified layer is formed. The modified layer 323 may include a silicon amorphous layer. The modified layer 323 may contain C atoms. One or a plurality of raised portions 315 formed on the second wafer main surface 333 may be formed by this modified layer 323.

[0635] Then, the pulsed laser light is continuously implanted in the direction along the orientation flat 335, and a plurality of raised portions 315 are formed along the orientation flat 335. Thereby, one raised portion group 316 including a plurality of raised portions 315 and extending along the [11-20] direction is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0636] When one raised portion group 316 is formed, the irradiation position of the pulsed laser light is moved in the [1-100] direction. Then, the pulsed laser light is implanted into the second wafer main surface 333 of the SiC semiconductor wafer 331 while moving the irradiation position along the orientation flat 335 again.

[0637] Thereby, another raised portion group 316 extending substantially parallel or parallel to one raised portion group 316 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0638] In the laser annealing treatment method, such steps are repeated until a plurality of raised portion groups 316 are formed over substantially the entire area or the entire area of the second wafer main surface 333 of the SiC semiconductor wafer 331 (see also Fig. 41B).

[0639] In this form, the metal layer 341 that has undergone the laser annealing treatment method has a laminated structure including a carbon layer 342, a NiSi (nickel silicide) layer 343, and a Ni layer 344 laminated in this order from the second wafer main surface 333 side of the SiC semiconductor wafer 331.

[0640] That is, the laser annealing treatment method includes a step of reacting the metal layer 341 with the SiC semiconductor wafer 331 to form a silicide. More specifically, the laser annealing treatment method includes a step of forming the NiSi layer 343.

[0641] In the laser annealing treatment method, in addition to the NiSi layer 343, a carbon layer 342 containing C atoms is formed as a by-product in the metal layer 341. The carbon layer 342 is formed by the precipitation of C atoms that had constituted SiC.

[0642] In the metal layer 341, the carbon layer 342 and the NiSi layer 343 can be peeling starting points. That is, the metal layer 341 can be used as the drain pad 113 as it is, but the metal layer 341 has problems of poor connection and an increase in resistance value due to the poor connection. Therefore, it is preferable that a metal layer different from the metal layer 341 is formed as the drain pad 113.

[0643] The temperature applied to the metal layer 341 with the formation of the NiSi layer 343 is equal to or higher than the melting points of the gate pad 108, the gate finger 109, and the source pad 110 (for example, 1000 °C or higher).

[0644] According to the laser annealing treatment method, since the temperature of the second wafer main surface 333 of the SiC semiconductor wafer 331 can be locally increased, it is not necessary to warm the gate pad 108, the gate finger 109, and the source pad 110. Therefore, melting of the gate pad 108, the gate finger 109, and the source pad 110 can be appropriately suppressed.

[0645] Next, referring to FIG. 43E, the removal process of the metal layer 341 is performed. The removal process of the metal layer 341 is performed until the second wafer main surface 333 of the SiC semiconductor wafer 331 is exposed.

[0646] In this process, first, the NiSi layer 343 and the Ni layer 344 in the metal layer 341 are removed (step S4 in FIG. 42). The NiSi layer 343 and the Ni layer 344 may be removed by a wet etching method.

[0647] Next, referring to FIG. 43F, the carbon layer 342 in the metal layer 341 is removed (step S5 in FIG. 42). The carbon layer 342 may be removed by a dry etching method.

[0648] Next, referring to FIG. 43G, the residue of the NiSi layer 343 and the residue of the Ni layer 344 attached to the second wafer main surface 333 of the SiC semiconductor wafer 331 are removed (step S6 in FIG. 42). The NiSi layer 343 and the Ni layer 344 may be removed by a wet etching method.

[0649] Next, referring to FIG. 43H, the residue of the carbon layer 342 attached to the second wafer main surface 333 of the SiC semiconductor wafer 331 is removed (step S7 in FIG. 42). The carbon layer 342 may be removed by a dry etching method.

[0650] Next, the natural oxide film is removed from the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S8 in FIG. 42). The natural oxide film may be removed by a wet etching method.

[0651] Thus, in this embodiment, the removal process of the layer containing Ni (NiSi layer 343 and Ni layer 344) and the removal process of the layer containing carbon (carbon layer 342) are repeated twice.

[0652] As a result, the metal layer 341 can be appropriately removed. Further, after the removal process of the metal layer 341, the second wafer main surface 333 of the SiC semiconductor wafer 331 whose resistance value has been reduced by laser annealing treatment is appropriately exposed.

[0653] Next, referring to FIG. 43I, a drain pad 113 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S9 in FIG. 42).

[0654] This process includes a process of forming a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327 in this order from above the second wafer main surface 333 of the SiC semiconductor wafer 331. The Ti layer 324, the Ni layer 325, the Au layer 326, and the Ag layer 327 may all be formed by a sputtering method.

[0655] Among the drain pads 113, the Ti layer 324 is directly connected to the second wafer main surface 333 of the SiC semiconductor wafer 331. The Ti layer 324 collectively covers the plurality of raised portion groups 316 and forms an ohmic contact between the plurality of raised portion groups 316 and between the plurality of spaces 320.

[0656] Next, the SiC semiconductor wafer 331 is cut along the periphery (dicing line 337) of the plurality of device formation regions 336. As a result, a plurality of semiconductor devices 311 are cut out from the SiC semiconductor wafer 331. Through the steps including the above, the semiconductor device 311 is manufactured.

[0657] As described above, according to the semiconductor device 311, the same effects as those described for the semiconductor device 101 can be achieved. Further, the semiconductor device 311 can increase the connection area of the drain pad 113 with respect to the second main surface 104 of the SiC semiconductor layer 102 by the raised portion group 316. Thereby, the electrical characteristics can be improved.

[0658] The drain pad 113 more specifically forms an ohmic contact with the group of protrusions 316. As a result, good ohmic characteristics can be obtained between the SiC semiconductor layer 102 and the drain pad 113, so that the electrical characteristics can be improved.

[0659] Further, according to the semiconductor device 311, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms an ohmic contact with the group of protrusions 316 without passing through a carbon layer. Further, the drain pad 113 forms an ohmic contact with the group of protrusions 316 without passing through a silicide layer.

[0660] The carbon layer and the silicide layer are likely to be the starting points of peeling. Therefore, the structure in which the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102 can appropriately suppress connection failures and an increase in the resistance value due to connection failures.

[0661] FIG. 44 is a bottom view corresponding to FIG. 35, and is a bottom view showing a semiconductor device 351 according to the 23rd embodiment of the present invention. Hereinafter, the structures corresponding to the structures described for the semiconductor device 311 will be denoted by the same reference numerals and the description thereof will be omitted.

[0662] Referring to FIG. 44, the semiconductor device 351 has a plurality of groups of protrusions 316 including a first group of protrusions 316A and a second group of protrusions 316B.

[0663] The first group of protrusions 316A includes a plurality of first protrusions 315A formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of first protrusions 315A are portions that protrude along the normal direction of the second main surface 104 of the SiC semiconductor layer 102 on the second main surface 104 of the SiC semiconductor layer 102.

[0664] The plurality of first raised portions 315A are formed at intervals along the first direction X and the second direction Y intersecting the first direction X. The first raised portion 315A has a first portion 317A where some of the plurality of first raised portions 315A overlap the first direction X in a first direction view as seen from the first direction X.

[0665] Further, the first raised portion 315A has a second portion 318A that is formed at a distance from the first portion 317A among some of the plurality of first raised portions 315A and overlaps the first direction X in the first direction view.

[0666] The plurality of first raised portions 315A are continuously formed along the first direction X. More specifically, the plurality of first raised portions 315A have a scattered pattern that is scattered at intervals along the first direction X and the second direction Y.

[0667] The plurality of first raised portions 315A are continuously formed along the first direction X while maintaining this scattered pattern. The scattered pattern of the plurality of first raised portions 315A is formed in this form across the periphery on one side surface 105A side to the periphery on the other side surface 105C side of the SiC semiconductor layer 102 in a plan view.

[0668] The first raised portion group 316A has a layout in which a plurality of first raised portions 315A overlap the first direction X as seen from the first direction X. Thereby, the first raised portion group 316A forms a first raised portion group region 319A that extends in a strip shape along the first direction X by an aggregated pattern of a plurality of first raised portions 315A that are continuously scattered along the first direction X.

[0669] In other words, the first raised portion group region 319A includes a plurality of first raised portions 315A (first raised portion group 316A) formed in a strip-shaped region extending along the first direction X on the second main surface 104 of the SiC semiconductor layer 102.

[0670] The second raised portion group 316B includes a plurality of second raised portions 315B formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of second raised portions 315B are portions that bulge along the normal direction of the second main surface 104 of the SiC semiconductor layer 102 on the second main surface 104 of the SiC semiconductor layer 102.

[0671] The plurality of second raised portions 315B are formed at intervals along the first direction X and the second direction Y intersecting the first direction X. The second raised portion group 316B has a first portion 317B in which some of the plurality of second raised portions 315B overlap the second direction Y in a second direction view seen from the second direction Y.

[0672] Also, the second raised portion group 316B has a second portion 318B in which some of the plurality of second raised portions 315B are formed separated from the first portion 317B and overlap the second direction Y in the second direction view.

[0673] The plurality of second raised portions 315B are continuously formed along the second direction Y. More specifically, the plurality of second raised portions 315B have a dotted pattern that is spaced along the first direction X and the second direction Y.

[0674] The plurality of second raised portions 315B are continuously formed along the second direction Y while maintaining this dotted pattern. The dotted pattern of the plurality of second raised portions 315B is formed in this form across the periphery on one side surface 105B side of the SiC semiconductor layer 102 to the periphery on the other side surface 105D side in a plan view.

[0675] The second raised portion group 316B has a layout in which the plurality of second raised portions 315B overlap the second direction Y when viewed from the second direction Y. Thereby, the second raised portion group 316B forms a second raised portion group region 319B that extends in a band shape along the second direction Y by an aggregate pattern of the plurality of second raised portions 315B that are continuously dotted along the second direction Y.

[0676] In other words, the second raised portion group region 319B includes a plurality of second raised portions 315B (second raised portion group 316B) formed in a strip-shaped region extending along the second direction Y on the second main surface 104 of the SiC semiconductor layer 102.

[0677] The second raised portion group 316B (second raised portion group region 319B) crosses the first raised portion group 316A (first raised portion group region 319A). As a result, an intersection region 352 where the first raised portion group 316A (first raised portion group region 319A) and the second raised portion group 316B (second raised portion group region 319B) intersect each other is formed on the second main surface 104 of the SiC semiconductor layer 102.

[0678] In this configuration, a plurality of first raised portions 316A are formed at intervals along the second direction Y on the second main surface 104 of the SiC semiconductor layer 102. That is, the scattered pattern of the plurality of first raised portions 315A is formed intermittently with respect to the second direction Y.

[0679] Also, in this configuration, a plurality of second raised portions 316B are formed at intervals along the first direction X on the second main surface 104 of the SiC semiconductor layer 102. That is, the scattered pattern of the plurality of second raised portions 315B is formed intermittently with respect to the first direction X.

[0680] Therefore, in this configuration, the intersection region 352 is formed in a matrix array spaced apart from each other along the first direction X and the second direction Y. Also, a space 320 is partitioned by the first raised portion group 316A and the second raised portion group 316B. The space 320 is formed in a matrix array spaced apart from each other along the first direction X and the second direction Y.

[0681] In the intersection region 352, the plurality of first raised portions 315A and the plurality of second raised portions 315B may overlap each other. The thicknesses of the plurality of first raised portions 315A and the plurality of second raised portions 315B formed in the intersection region 352 may be larger than the thicknesses of the first raised portions 315A and the second raised portions 315B formed in the regions outside the intersection region 352.

[0682] Also, the number of the plurality of first protrusions 315A and the plurality of second protrusions 315B formed in the intersection region 352 may be larger than the number of the first protrusions 315A and the second protrusions 315B formed in the region outside the intersection region 352.

[0683] The first direction X may be set in the [11 - 20] direction, and the second direction Y may be set in the [1 - 100] direction. That is, the first protrusion group 316A (first protrusion group region 319A) may be formed substantially parallel or parallel to the [11 - 20] direction, and the second protrusion group 316B (second protrusion group region 319B) may be formed substantially parallel or parallel to the [1 - 100] direction.

[0684] The first direction X may be set in the [1 - 100] direction, and the second direction Y may be set in the [11 - 20] direction. That is, the first protrusion group 316A (first protrusion group region 319A) may be formed substantially parallel or parallel to the [1 - 100] direction, and the second protrusion group 316B (second protrusion group region 319B) may be formed substantially parallel or parallel to the [11 - 20] direction.

[0685] The first protrusion 315A and the first protrusion group 316A correspond to the protrusion 315 and the protrusion group 316 according to the 22nd embodiment. The description of the protrusion 315 and the protrusion group 316 according to the 22nd embodiment shall be applied mutatis mutandis to the description of the first protrusion 315A and the first protrusion group 316A, and other specific descriptions of the first protrusion 315A and the first protrusion group 316A are omitted.

[0686] The second protrusion 315B and the second protrusion group 316B correspond to the protrusion 315 and the protrusion group 316 according to the 22nd embodiment. The description of the protrusion 315 and the protrusion group 316 according to the 22nd embodiment shall be applied mutatis mutandis to the other description of the second protrusion 315B and the second protrusion group 316B, and other specific descriptions of the second protrusion 315B and the second protrusion group 316B are omitted.

[0687] In this form, the drain pad 113 covers the first raised portion group 316A and the second raised portion group 316B on the second main surface 104 of the SiC semiconductor layer 102. In this form, the drain pad 113 covers the plurality of first raised portion groups 316A and the plurality of second raised portion groups 316B collectively.

[0688] The drain pad 113 is formed in a film shape following the outer surface of the first raised portion group 316A (the outer surface of the first raised portion 315A), the outer surface of the second raised portion group 316B (the outer surface of the second raised portion 315B), and the inner surface of the groove 321.

[0689] As a result, although not shown in the figure, raised portions 113a are formed in the portions of the outer surface of the drain pad 113 that cover the first raised portion group 316A (the first raised portion 315A) and the second raised portion group 316B (the second raised portion 315B). Also, recesses 113b are formed in the portions of the outer surface of the drain pad 113 that cover the groove 321.

[0690] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms an ohmic contact with the first raised portion group 316A and the second raised portion group 316B.

[0691] More specifically, the drain pad 113 forms an ohmic contact with the plurality of first raised portion groups 316A and the plurality of second raised portion groups 316B. Also, in this form, the drain pad 113 forms an ohmic contact with the space 320 as well.

[0692] The portion of the drain pad 113 that covers the first raised portion group 316A and the second raised portion group 316B meshes with the uneven portion partitioned by the plurality of first raised portion groups 316A, the plurality of second raised portion groups 316B, and the plurality of grooves 321.

[0693] That is, the contact area of the drain pad 113 with respect to the second main surface 104 of the SiC semiconductor layer 102 is increased by the plurality of first protrusion groups 316A, the plurality of second protrusion groups 316B, and the plurality of grooves 321. As a result, the adhesion of the drain pad 113 to the second main surface 104 of the SiC semiconductor layer 102 is enhanced.

[0694] The semiconductor device 351 having such a structure is manufactured by performing the following steps in the above-described laser annealing process (step S3 in FIG. 42).

[0695] First, a plurality of first protrusion groups 316A are formed along a direction substantially parallel to or parallel to the orientation flat 335 by a laser annealing treatment method. Next, a plurality of second protrusion groups 316B are formed along a direction intersecting (orthogonal to) the orientation flat 335 by a laser annealing treatment method.

[0696] In this step, a plurality of first protrusion groups 316A may be formed in a direction intersecting (orthogonal to) the orientation flat 335, and a plurality of second protrusion groups 316B may be formed along a direction substantially parallel to or parallel to the orientation flat 335. Thereafter, the semiconductor device 351 is manufactured through the steps of steps S4 to S9 in FIG. 42.

[0697] The first protrusion group 316A and the second protrusion group 316B may be formed in any order. Therefore, the plurality of first protrusion groups 316A may be formed after the plurality of second protrusion groups 316B are formed. Also, the plurality of first protrusion groups 316A and the plurality of second protrusion groups 316B may be formed alternately.

[0698] As described above, the semiconductor device 351 can also achieve the same effects as those described for the semiconductor device 311.

[0699] FIG. 45 is a cross-sectional view corresponding to FIG. 39, showing a semiconductor device 361 according to the 24th embodiment of the present invention. FIG. 46 is an enlarged view of the region XLVI shown in FIG. 45. Hereinafter, for structures corresponding to the structures described for the semiconductor device 311, the same reference numerals are given and the description is omitted.

[0700] In the semiconductor device 361, the drain pad 113 has a three-layer structure including a Ni layer 325, an Au layer 326, and an Ag layer 327 laminated in this order from the second main surface 104 of the SiC semiconductor layer 102. That is, the drain pad 113 is formed by omitting the step of forming the Ti layer 324 in step S9 of FIG. 42.

[0701] The Ni layer 325 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ni layer 325 collectively covers a plurality of raised portion groups 316.

[0702] The Ni layer 325 forms an ohmic contact between the raised portion groups 316 and between the spaces 320. The Au layer 326 covers substantially the entire area or the entire area of the Ni layer 325. The Ag layer 327 covers substantially the entire area or the entire area of the Au layer 326.

[0703] As described above, the semiconductor device 361 can also achieve the same effects as those described for the semiconductor device 311. In the semiconductor device 361, the drain pad 113 may have a single-layer structure composed of the Ni layer 325.

[0704] FIG. 47 is a cross-sectional view corresponding to FIG. 39, showing a semiconductor device 371 according to the 25th embodiment of the present invention. FIG. 48 is an enlarged view of the region XLVIII shown in FIG. 47. Hereinafter, for structures corresponding to the structures described for the semiconductor device 311, the same reference numerals are given and the description is omitted.

[0705] In the semiconductor device 371, the drain pad 113 includes a metal layer 341, an Au layer 326, and an Ag layer 327. In this form, the metal layer 341 has a laminated structure including a carbon layer 342, a NiSi layer 343, and a Ni layer 344 laminated in this order from the second main surface 104 side of the SiC semiconductor layer 102.

[0706] The metal layer 341 is connected to the second main surface 104 of the SiC semiconductor layer 102. The metal layer 341 collectively covers a plurality of raised portion groups 316.

[0707] The metal layer 341 forms ohmic contacts between the raised portion groups 316 and between the spaces 320. The Au layer 326 covers substantially the entire area or the entire area of the metal layer 341. The Ag layer 327 covers substantially the entire area or the entire area of the Au layer 326.

[0708] The semiconductor device 371 is formed by omitting the removal process of the metal layer 341 (see steps S4 to S8 shown in FIG. 42) in FIG. 42. In the semiconductor device 371, in step S9 of FIG. 42 described above, the Au layer 326 and the Ag layer 327 are formed on the metal layer 341.

[0709] As described above, according to the semiconductor device 371, the drain pad 113 includes the carbon layer 342 and the NiSi layer 343. According to the semiconductor device 371, the connection strength of the drain pad 113 cannot be increased as much as that of the semiconductor device 311, but an effect almost the same as the effect described for the semiconductor device 311 can be achieved. In the semiconductor device 371, the drain pad 113 may be composed only of the metal layer 341.

[0710] As described above, the 22nd to 25th embodiments of the present invention have been described, but the 22nd to 25th embodiments of the present invention can be implemented in other forms as well.

[0711] In the above-described 22nd to 25th embodiments, an example in which the SiC semiconductor layer 102 has a laminated structure including a SiC semiconductor substrate 111 and a SiC epitaxial layer 112 has been described.

[0712] However, the SiC semiconductor layer 102 may have a single-layer structure composed of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may have a single-layer structure composed of the SiC epitaxial layer 112.

[0713] In the foregoing 22nd to 25th embodiments, an example in which the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b is formed by the epitaxial growth method has been described. However, the SiC epitaxial layer 112 can also be formed by the following steps.

[0714] First, a SiC epitaxial layer 112 having a relatively low n-type impurity concentration is formed by the epitaxial growth method. Next, n-type impurities are introduced into the surface layer portion of the SiC epitaxial layer 112 by the ion implantation method. Thereby, the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b is formed.

[0715] In the foregoing 22nd to 25th embodiments, an example in which the gate electrode layer 132 and the gate wiring layer 133 including p-type polysilicon to which p-type impurities are added are formed has been described. However, when the increase in the gate threshold voltage Vth is not emphasized, the gate electrode layer 132 and the gate wiring layer 133 may include n-type polysilicon to which n-type impurities are added instead of p-type polysilicon.

[0716] That is, the low-resistance electrode layer 134 may include an n-type poly side. The low-resistance electrode layer 134 may be formed by siliciding a portion forming the surface layer portion in the gate electrode layer 132 (n-type polysilicon) with a metal material. In this case, the gate resistance can be reduced.

[0717] In the foregoing 22nd to 25th embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0718] In the foregoing 22nd to 25th embodiments, n + type SiC semiconductor substrate 111 may be replaced with a p + type SiC semiconductor substrate (111). In this case, in the description of the foregoing 22nd to 25th embodiments, “source” is read as “emitter” and “drain” is read as “collector”.

[0719] FIG. 49 is a top view showing a semiconductor device 401 according to a 26th embodiment of the present invention. FIG. 50 is a top view showing the semiconductor device 401 shown in FIG. 49, and is a top view with the resin layer 416 removed.

[0720] Referring to FIGS. 49 and 50, the semiconductor device 401 has a SiC semiconductor layer 402 including a SiC (silicon carbide) single crystal. The SiC semiconductor layer 402 may include a 4H-SiC single crystal.

[0721] The 4H-SiC single crystal has an off-angle inclined at an angle within 10° with respect to the [11-20] direction from the (0001) plane. The off-angle may be 0° or more and 4° or less. The off-angle may be more than 0° and less than 4°. The off-angle is typically set in the range of 2° or 4°, more specifically, in the range of 2°±0.2° or 4°±0.4°.

[0722] In this form, the SiC semiconductor layer 402 is formed in a rectangular parallelepiped chip shape. The SiC semiconductor layer 402 has a first main surface 403 on one side, a second main surface 404 on the other side, and side surfaces 405A, 405B, 405C, 405D connecting the first main surface 403 and the second main surface 404. The first main surface 403 and the second main surface 404 are formed in a quadrangular shape (rectangular shape in this form) in a plan view (hereinafter simply referred to as “plan view”) as viewed from their normal directions.

[0723] Side surface 405A faces side surface 405C. Side surface 405B faces side surface 405D. Side surfaces 405A to 405D each extend planar along the normal direction of the first main surface 403 and the second main surface 404. The length of side surfaces 405A to 405D may each be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0724] In the SiC semiconductor layer 402, an active region 406 and an outer region 407 are set. The active region 406 is a region where a vertical MISFET is formed. The outer region 407 is a region outside the active region 406.

[0725] The active region 406 is set at the center of the SiC semiconductor layer 402 with a space from the side surfaces 405A to 405D of the SiC semiconductor layer 402 in the inward region in a plan view. The active region 406 is set in a rectangular shape (a rectangular shape in this form) having four sides parallel to the side surfaces 405A to 405D of the SiC semiconductor layer 402 in a plan view.

[0726] The outer region 407 is set in a region between the side surfaces 405A to 405D of the SiC semiconductor layer 402 and the periphery of the active region 406. The outer region 407 is set in an endless shape (a square ring shape) surrounding the active region 406 in a plan view.

[0727] On the first main surface 403 of the SiC semiconductor layer 402, a main surface gate electrode 408 and a main surface source electrode 409 are formed.

[0728] The main surface gate electrode 408 includes a gate pad 410 and a gate finger 411. The gate pad 410 and the gate finger 411 are arranged in the active region 406 in this form.

[0729] The gate pad 410 is formed along the side surface 405A of the SiC semiconductor layer 402 in a plan view. The gate pad 410 is formed along the central region of the side surface 405A of the SiC semiconductor layer 402 in a plan view.

[0730] The gate pad 410 may be formed along a corner connecting any two of the side surfaces 405A to 405D of the SiC semiconductor layer 402 in a plan view. The gate pad 410 is formed in a square shape in a plan view.

[0731] The gate finger 411 includes an outer gate finger 411A and an inner gate finger 411B.

[0732] The outer gate finger 411A is drawn out from the gate pad 410 and extends in a strip shape along the periphery of the active region 406. In this form, the outer gate finger 411A is formed along three side surfaces 405A, 405B, and 405D of the SiC semiconductor layer 402 so as to partition the inner region of the active region 406 from three directions.

[0733] The outer gate finger 411A has a pair of open ends 412A and 412B. The pair of open ends 412A and 412B of the outer gate finger 411A are formed in a region facing the gate pad 410 with the inner region of the active region 406 interposed therebetween. In this form, the pair of open ends 412A and 412B of the outer gate finger 411A are formed along the side surface 405C of the SiC semiconductor layer 402.

[0734] The inner gate finger 411B is drawn out from the gate pad 410 to the inner region of the active region 406. The inner gate finger 411B extends in a strip shape in the inner region of the active region 406. The inner gate finger 411B extends from the side surface 405A side toward the side surface 405C side.

[0735] In this form, the main surface source electrode 409 includes a source pad 413, a source routing wire 414, and a source connection portion 415.

[0736] The source pad 413 is formed in the active region 406 at a distance from the gate pad 410 and the gate fingers 411. The source pad 413 is formed in a C shape (an inverted C shape in FIGS. 49 and 50) in plan view so as to cover a C-shaped (an inverted C-shaped in FIGS. 49 and 50) region partitioned by the gate pad 410 and the gate fingers 411.

[0737] The source routing wire 414 is formed in the outer region 407. The source routing wire 414 extends in a strip shape along the active region 406. In this form, the source routing wire 414 is formed in an endless (square annular) shape surrounding the active region 406 in plan view. The source routing wire 414 is electrically connected to the SiC semiconductor layer 402 in the outer region 407.

[0738] The source connection portion 415 connects the source pad 413 and the source routing wire 414. The source connection portion 415 is provided in a region between a pair of open end portions 412A and 412B of the outer gate finger 411A. The source connection portion 415 crosses the boundary region between the active region 406 and the outer region 407 from the source pad 413 and is connected to the source routing wire 414.

[0739] The MISFET formed in the active region 406 includes an npn-type parasitic bipolar transistor due to its structure. When an avalanche current generated in the outer region 407 flows into the active region 406, the parasitic bipolar transistor is turned on. In this case, for example, due to latch-up, the control of the MISFET may become unstable.

[0740] Therefore, in the semiconductor device 401, an avalanche current absorption structure for absorbing an avalanche current generated in a region outside the active region 406 is formed by utilizing the structure of the main surface source electrode 409.

[0741] More specifically, the avalanche current generated in the outer region 407 is absorbed by the source routing wiring 414. As a result, the avalanche current reaches the source pad 413 via the source connection portion 415. When an external connection wire (for example, a bonding wire) is connected to the source pad 413, the avalanche current is taken out by this wire.

[0742] This can suppress the parasitic bipolar transistor from being turned on by the unwanted current generated in the outer region 407. Therefore, since latch-up can be suppressed, the control stability of the MISFET can be enhanced.

[0743] A gate voltage is applied to the gate pad 410 and the gate fingers 411. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source pad 413. The source voltage may be a reference voltage (for example, GND voltage).

[0744] A resin layer 416 is formed on the first main surface 403 of the SiC semiconductor layer 402 (more specifically, on the interlayer insulating layer 491 described later). In FIG. 49, the resin layer 416 is shown by hatching for clarity. The resin layer 416 covers the gate pad 410, the gate fingers 411, and the source pad 413.

[0745] The resin layer 416 may contain a negative-type or positive-type photosensitive resin. In this form, the resin layer 416 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 416 may contain polyimide as an example of a negative-type photosensitive resin.

[0746] A gate pad opening 417 and a source pad opening 418 are formed in the resin layer 416. The gate pad opening 417 exposes the gate pad 410. The source pad opening 418 exposes the source pad 413.

[0747] The peripheral portion 419 of the resin layer 416 is formed at an interval from the side surfaces 405A to 405D of the SiC semiconductor layer 402 in the inner region. Thereby, the resin layer 416 exposes the peripheral portion of the SiC semiconductor layer 402 (more specifically, the interlayer insulating layer 491 described later).

[0748] The peripheral portion 419 of the resin layer 416 is a portion where a dicing street was formed when the semiconductor device 401 was cut out from a single SiC semiconductor wafer. By exposing the peripheral portion of the SiC semiconductor layer 402 from the resin layer 416, it becomes unnecessary to physically cut the resin layer 416.

[0749] Therefore, the semiconductor device 401 can be smoothly cut out from a single SiC semiconductor wafer. The side surfaces 405A to 405D of the SiC semiconductor layer 402 may be a cut surface (ground surface). The side surfaces 405A to 405D of the SiC semiconductor layer 402 may have grinding marks.

[0750] FIG. 51 is an enlarged view of the region LI shown in FIG. 50, and is a diagram for explaining the structure of the first main surface 403 of the SiC semiconductor layer 402. FIG. 52 is a cross-sectional view taken along the line LII-LII shown in FIG. 51, and is a cross-sectional view showing a first exemplary form of the gate trench 431 and a first exemplary form of the source trench 441. FIG. 53 is a cross-sectional view taken along the line LIII-LIII shown in FIG. 51, and is a cross-sectional view showing a first exemplary form of the gate wiring layer 436. FIG. 54 is an enlarged view of the region LIV shown in FIG. 52.

[0751] FIG. 55 is a cross-sectional view taken along the line LV-LV shown in FIG. 50, and is a cross-sectional view showing a first exemplary form of the active sidewall 464, a first exemplary form of the outer main surface 462, a first exemplary form of the sidewall 482, a first exemplary form of the diode region 471, a first exemplary form of the outer deep well region 472, a first exemplary form of the field limit structure 473, and a first exemplary form of the anchor hole 495. FIG. 56 is an enlarged view of the region LVI shown in FIG. 55, and is an enlarged view showing a first exemplary form of the active sidewall 464 and a first exemplary form of the outer main surface 462.

[0752] Referring to FIGS. 51 to 55, in this form, the SiC semiconductor layer 402 is n + type and has a stacked structure including an SiC semiconductor substrate 421 and an n-type SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 is formed by the SiC semiconductor substrate 421.

[0753] The first main surface 403 of the SiC semiconductor layer 402 is formed by the SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 may be a ground surface. The second main surface 404 of the SiC semiconductor layer 402 may have grinding marks.

[0754] The thickness of the SiC semiconductor substrate 421 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 421 may be 5 μm or more. The thickness of the SiC semiconductor substrate 421 may be 25 μm or more. The thickness of the SiC semiconductor substrate 421 may be 50 μm or more. The thickness of the SiC semiconductor substrate 421 may be 100 μm or more.

[0755] The thickness of the SiC semiconductor substrate 421 may be 700 μm or less. The thickness of the SiC semiconductor substrate 421 may be 500 μm or less. The thickness of the SiC semiconductor substrate 421 may be 400 μm or less. The thickness of the SiC semiconductor substrate 421 may be 300 μm or less.

[0756] The thickness of the SiC semiconductor substrate 421 may be 250 μm or less. The thickness of the SiC semiconductor substrate 421 may be 200 μm or less. The thickness of the SiC semiconductor substrate 421 may be 150 μm or less. The thickness of the SiC semiconductor substrate 421 may be 100 μm or less.

[0757] The thickness of the SiC semiconductor substrate 421 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 421, the resistance value can be reduced by shortening the current path.

[0758] The thickness of the SiC epitaxial layer 422 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 422 may be 5 μm or more. The thickness of the SiC epitaxial layer 422 may be 10 μm or more.

[0759] The thickness of the SiC epitaxial layer 422 may be 50 μm or less. The thickness of the SiC epitaxial layer 422 may be 40 μm or less. The thickness of the SiC epitaxial layer 422 may be 30 μm or less.

[0760] The thickness of the SiC epitaxial layer 422 may be 20 μm or less. The thickness of the SiC epitaxial layer 422 is preferably 15 μm or less. The thickness of the SiC epitaxial layer 422 is preferably 10 μm or less.

[0761] The n-type impurity concentration of the SiC epitaxial layer 422 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 421. The n-type impurity concentration of the SiC epitaxial layer 422 is 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less.

[0762] In this form, the SiC epitaxial layer 422 has a plurality of regions having different n-type impurity concentrations along the normal direction of the first main surface 403 of the SiC semiconductor layer 402. More specifically, the SiC epitaxial layer 422 includes a high-concentration region 422a having a relatively high n-type impurity concentration and a low-concentration region 422b having a lower n-type impurity concentration than the high-concentration region 422a.

[0763] The high-concentration region 422a is formed in a region on the side of the first main surface 403. The low-concentration region 422b is formed in a region on the side of the second main surface 404 of the SiC semiconductor layer 402 with respect to the high-concentration region 422a.

[0764] The n-type impurity concentration of the high-concentration region 422a is 1×10 16 cm -3 or more and 1×1018 cm -3 It may be as follows. The n-type impurity concentration in the low-concentration region 422b is 1×10 15 cm -3 or more and 1×10 16 cm -3 or less.

[0765] The thickness of the high-concentration region 422a is equal to or less than the thickness of the low-concentration region 422b. More specifically, the thickness of the high-concentration region 422a is less than the thickness of the low-concentration region 422b. That is, the thickness of the high-concentration region 422a is less than half of the total thickness of the SiC epitaxial layer 422.

[0766] A drain pad 423 as a second main surface electrode is connected to the second main surface 404 of the SiC semiconductor layer 402. The maximum voltage that can be applied between the source pad 413 and the drain pad 423 when off may be 1000V or more and 10000V or less.

[0767] The drain pad 423 may include at least one of a Ti layer, a Ni layer, an Au layer, or an Ag layer. The drain pad 423 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in this order from the second main surface 404 of the SiC semiconductor layer 402.

[0768] The SiC semiconductor substrate 421 is formed as a drain region 424 of the MISFET. The SiC epitaxial layer 422 is formed as a drift region 425 of the MISFET.

[0769] In the active region 406, a p-type body region 426 is formed in the surface layer portion of the first main surface 403 of the SiC semiconductor layer 402. The body region 426 defines the active region 406.

[0770] That is, in this form, the body region 426 is formed over the entire region of the first main surface 403 of the SiC semiconductor layer 402 that forms the active region 406. The p-type impurity concentration of the body region 426 is 1×10 17cm -3 1×10 or more 20 cm -3 It may be less than or equal to this value.

[0771] In the active region 406, a plurality of gate trenches 431 are formed in the surface layer portion of the first main surface 403 of the SiC semiconductor layer 402. The plurality of gate trenches 431 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 431 are formed in a strip shape extending along a second direction Y intersecting the first direction X.

[0772] More specifically, the first direction X is a direction along the side surfaces 405B and 405D of the SiC semiconductor layer 402. The second direction Y is a direction orthogonal to the first direction X. The second direction Y is also a direction along the side surfaces 405A and 405C of the SiC semiconductor layer 402.

[0773] The plurality of gate trenches 431 are formed in a stripe shape in plan view. In this form, each gate trench 431 extends in a strip shape from the peripheral edge on one side (side surface 405B side) to the peripheral edge on the other side (side surface 405D side) in the active region 406.

[0774] Each gate trench 431 crosses the middle portion between the peripheral edge on one side and the peripheral edge on the other side in the active region 406. One end portion of each gate trench 431 is located at the peripheral edge on one side in the active region 406. The other end portion of each gate trench 431 is located at the peripheral edge on the other side in the active region 406.

[0775] The first direction X may be set to the [11 - 20] direction ([ - 1 - 120] direction). In this case, each gate trench 431 may extend along the [11 - 20] direction. The first direction X may be set to the [ - 1100] direction ([1 - 100] direction) orthogonal to the [11 - 20] direction. In this case, each gate trench 431 may extend along the [ - 1100] direction ([1 - 100] direction).

[0776] Each gate trench 431 has a length on the order of millimeters. That is, the length of the gate trench 431 is the length from the end on the connection portion side of the gate trench 431 and the gate finger 411 to the end on the opposite side in the cross section shown in FIG. 53.

[0777] The length of each gate trench 431 may be 0.5 mm or more. In this form, the length of each gate trench 431 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total extension of one or more gate trenches 431 per unit area is 0.5 μm / μm 2 or more and 0.75 μm / μm 2 or less.

[0778] Each gate trench 431 integrally includes an active trench portion 431a and a contact trench portion 431b. The active trench portion 431a is a portion along the channel region of the MISFET in the active region 406.

[0779] The contact trench portion 431b is mainly a portion for the purpose of contacting the gate finger 411 in the gate trench 431. The contact trench portion 431b is drawn out from the active trench portion 431a to the peripheral portion of the active region 406. The contact trench portion 431b is formed in the region directly below the gate finger 411. The amount of drawing out of the contact trench portion 431b is arbitrary.

[0780] Each gate trench 431 penetrates the body region 426 and reaches the SiC epitaxial layer 422. The bottom wall of each gate trench 431 is located within the SiC epitaxial layer 422.

[0781] More specifically, the bottom wall of each gate trench 431 is located in the high-concentration region 422a of the SiC epitaxial layer 422. The bottom wall of the gate trench 431 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402.

[0782] The side wall of the gate trench 431 may extend along the normal direction of the first main surface 403 of the SiC semiconductor layer 402. That is, the side wall of the gate trench 431 may be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402.

[0783] Regarding the normal direction of the first main surface 403 of the SiC semiconductor layer 402, the depth of the gate trench 431 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). The depth of the gate trench 431 is preferably 0.5 μm or more and 1.0 μm or less.

[0784] The width of the gate trench 431 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). The width of the gate trench 431 in the first direction is preferably 0.1 μm or more and 0.5 μm or less.

[0785] Referring to FIG. 54, the opening edge portion 432 of each gate trench 431 includes an inclined portion 433 that slopes downward from the first main surface 403 of the SiC semiconductor layer 402 toward the inside of the gate trench 431. The opening edge portion 432 of the gate trench 431 is a corner portion that connects the first main surface 403 of the SiC semiconductor layer 402 and the side wall of the gate trench 431.

[0786] In this form, the inclined portion 433 is formed in a concave curved shape toward the inside of the SiC semiconductor layer 402. The inclined portion 433 may be formed in a convex curved shape toward the inside of the gate trench 431.

[0787] The electric field with respect to the opening edge portion 432 of the gate trench 431 is dispersed along the inclined portion 433. Thereby, the electric field concentration with respect to the opening edge portion 432 of the gate trench 431 can be alleviated.

[0788] A gate insulating layer 434 and a gate electrode layer 435 are formed in each gate trench 431. In FIG. 51, the gate insulating layer 434 and the gate electrode layer 435 are shown by hatching for clarity.

[0789] The gate insulating layer 434 contains silicon oxide. The gate insulating layer 434 may contain other insulating films such as silicon nitride. The gate insulating layer 434 is formed in a film shape along the inner wall surface of the gate trench 431 so that a concave space is defined within the gate trench 431.

[0790] The gate insulating layer 434 includes a first region 434a, a second region 434b, and a third region 434c. The first region 434a is formed along the side wall of the gate trench 431. The second region 434b is formed along the bottom wall of the gate trench 431. The third region 434c is formed along the first main surface 403 of the SiC semiconductor layer 402.

[0791] The thickness T1 of the first region 434a is smaller than the thickness T2 of the second region 434b and the thickness T3 of the third region 434c. The ratio T2 / T1 of the thickness T2 of the second region 434b to the thickness T1 of the first region 434a may be 2 or more and 5 or less. The ratio T3 / T1 of the thickness T3 of the third region 434c to the thickness T1 of the first region 434a may be 2 or more and 5 or less.

[0792] The thickness T1 of the first region 434a may be 0.01 μm or more and 0.2 μm or less. The thickness T2 of the second region 434b may be 0.05 μm or more and 0.5 μm or less. The thickness T3 of the third region 434c may be 0.05 μm or more and 0.5 μm or less.

[0793] By forming the first region 434a of the gate insulating layer 434 thinly, an increase in carriers induced in the region near the side wall of the gate trench 431 in the body region 426 can be suppressed. Thereby, an increase in channel resistance can be suppressed. By forming the second region 434b of the gate insulating layer 434 thickly, the electric field concentration on the bottom wall of the gate trench 431 can be alleviated.

[0794] By thickening the third region 434c of the gate insulating layer 434, the breakdown voltage of the gate insulating layer 434 in the vicinity of the opening edge portion 432 of the gate trench 431 can be improved. Further, by thickening the third region 434c, it is possible to suppress the third region 434c from disappearing by the etching method.

[0795] Thereby, it is possible to suppress the first region 434a from being removed by the etching method due to the disappearance of the third region 434c. As a result, the gate electrode layer 435 can be appropriately opposed to the SiC semiconductor layer 402 (body region 426) with the gate insulating layer 434 interposed therebetween.

[0796] The gate insulating layer 434 further includes a bulging portion 434d that bulges toward the inside of the gate trench 431 at the opening edge portion 432 of the gate trench 431. The bulging portion 434d is formed at a corner portion connecting the first region 434a and the third region 434c of the gate insulating layer 434.

[0797] The bulging portion 434d protrudes in a curved shape toward the inside of the gate trench 431. The bulging portion 434d narrows the opening of the gate trench 431 at the opening edge portion 432 of the gate trench 431.

[0798] The breakdown voltage of the gate insulating layer 434 at the opening edge portion 432 is improved by the bulging portion 434d. Of course, a gate insulating layer 434 having no bulging portion 434d may be formed. A gate insulating layer 434 having a uniform thickness may be formed.

[0799] The gate electrode layer 435 is embedded in the gate trench 431 with the gate insulating layer 434 interposed therebetween. More specifically, the gate electrode layer 435 is embedded in the gate trench 431 so as to fill a concave space partitioned by the gate insulating layer 434. The gate electrode layer 435 is controlled by a gate voltage.

[0800] The gate electrode layer 435 is formed in a wall shape extending along the normal direction of the first main surface 403 of the SiC semiconductor layer 402 in a cross-sectional view perpendicular to the direction in which the gate trench 431 extends. The gate electrode layer 435 has an upper end portion located on the opening side of the gate trench 431.

[0801] The upper end portion of the gate electrode layer 435 is formed in a curved shape that is recessed toward the bottom wall of the gate trench 431. The upper end portion of the gate electrode layer 435 has a constricted portion along the bulging portion 434d of the gate insulating layer 434.

[0802] The cross-sectional area of the gate electrode layer 435 (the cross-sectional area perpendicular to the direction in which the gate trench 431 extends) may be 0.05 μm 2 or more and 0.5 μm 2 or less. The cross-sectional area of the gate electrode layer 435 is defined by the product of the depth of the gate electrode layer 435 and the width of the gate electrode layer 435.

[0803] The depth of the gate electrode layer 435 is the distance from the upper end portion to the lower end portion of the gate electrode layer 435. The width of the gate electrode layer 435 is the width of the trench at an intermediate position between the upper end portion and the lower end portion of the gate electrode layer 435. When the upper end portion is a curved surface (in this form, a curved shape recessed downward), the position of the upper end portion of the gate electrode layer 435 is taken as the intermediate position in the depth direction on the upper surface of the gate electrode layer 435.

[0804] The gate electrode layer 435 may contain conductive polysilicon. The gate electrode layer 435 may contain n-type polysilicon or p-type polysilicon as an example of conductive polysilicon. Instead of conductive polysilicon, the gate electrode layer 435 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy.

[0805] Referring to FIGS. 51 and 53, a gate wiring layer 436 is formed in the active region 406. The gate wiring layer 436 is electrically connected to the gate pad 410 and the gate fingers 411. In FIG. 53, for clarity, the gate wiring layer 436 is shown by hatching.

[0806] The gate wiring layer 436 is formed on the first main surface 403 of the SiC semiconductor layer 402. More specifically, the gate wiring layer 436 is formed on the third region 434c of the gate insulating layer 434.

[0807] In this form, the gate wiring layer 436 is formed along the gate fingers 411. More specifically, the gate wiring layer 436 is formed along the three side surfaces 405A, 405B, and 405D of the SiC semiconductor layer 402 so as to partition the inner region of the active region 406 from three directions.

[0808] The gate wiring layer 436 is connected to the gate electrode layer 435 exposed from the contact trench portion 431b of each gate trench 431. In this form, the gate wiring layer 436 is formed by a lead-out portion drawn from the gate electrode layer 435 onto the first main surface 403 of the SiC semiconductor layer 402. The upper end portion of the gate wiring layer 436 is connected to the upper end portion of the gate electrode layer 435.

[0809] Referring to FIGS. 51, 52, and 54, a plurality of source trenches 441 are formed in the first main surface 403 of the SiC semiconductor layer 402 in the active region 406. Each source trench 441 is formed in a region between two adjacent gate trenches 431.

[0810] The plurality of source trenches 441 are each formed in a strip shape extending along the second direction Y. The plurality of source trenches 441 are formed in a stripe shape in plan view. With respect to the first direction X, the pitch between the central portions of adjacent source trenches 441 may be 1.5 μm or more and 3 μm or less.

[0811] Each source trench 441 penetrates the body region 426 and reaches the SiC epitaxial layer 422. The bottom wall of each source trench 441 is located within the SiC epitaxial layer 422. More specifically, the bottom wall of each source trench 441 is located in the high-concentration region 422a.

[0812] In this form, the depth of the source trench 441 is equal to or greater than the depth of the gate trench 431. More specifically, the depth of the source trench 441 is greater than the depth of the gate trench 431. The bottom wall of the source trench 441 is located on the second main surface 404 side of the SiC semiconductor layer 402 with respect to the bottom wall of the gate trench 431.

[0813] The bottom wall of the source trench 441 is located in the region between the bottom wall of the gate trench 431 and the low-concentration region 422b. The bottom wall of the source trench 441 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402.

[0814] The side wall of the source trench 441 may extend along the normal direction of the first main surface 403 of the SiC semiconductor layer 402. That is, the side wall of the source trench 441 may be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402.

[0815] Regarding the normal direction of the first main surface 403 of the SiC semiconductor layer 402, the depth of the source trench 441 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of the source trench 441 to the depth of the gate trench 431 may be 1.5 or more. The ratio of the depth of the source trench 441 to the depth of the gate trench 431 is preferably 2 or more.

[0816] The width of the source trench 441 in the first direction may be substantially equal to the width of the gate trench 431 in the first direction. The width of the source trench 441 in the first direction may be equal to or greater than the width of the gate trench 431 in the first direction. The width of the source trench 441 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm).

[0817] Inside each source trench 441, a source insulating layer 442 and a source electrode layer 443 are formed. In FIG. 51, the source insulating layer 442 and the source electrode layer 443 are shown by hatching for clarity.

[0818] The source insulating layer 442 may contain silicon oxide. The source insulating layer 442 is formed in a film shape along the inner wall surface of the source trench 441 so that a concave space is defined within the source trench 441.

[0819] The source insulating layer 442 includes a first region 442a and a second region 442b. The first region 442a is formed along the side wall of the source trench 441. The second region 442b is formed along the bottom wall of the source trench 441. The thickness T11 of the first region 442a is smaller than the thickness T12 of the second region 442b.

[0820] The ratio T12 / T11 of the thickness T12 of the second region 442b to the thickness T11 of the first region 442a may be 2 or more and 5 or less. The thickness T11 of the first region 442a may be 0.01 μm or more and 0.2 μm or less. The thickness T12 of the second region 442b may be 0.05 μm or more and 0.5 μm or less.

[0821] The thickness T11 of the first region 442a may be approximately equal to the thickness T1 of the first region 434a of the gate insulating layer 434. The thickness T12 of the second region 442b may be approximately equal to the thickness T2 of the second region 434b of the gate insulating layer 434. Of course, a source insulating layer 442 having a uniform thickness may be formed.

[0822] The source electrode layer 443 is embedded in the source trench 441 with the source insulating layer 442 interposed therebetween. More specifically, the source electrode layer 443 is embedded in the source trench 441 so as to fill the concave space defined by the source insulating layer 442. The source electrode layer 443 ...

Claims

1. A first-conductivity-type semiconductor layer having a first main surface on one side and a second main surface on the other side, An active region having an active main surface as a part of the first main surface, An outer main surface as a part of the first main surface formed at a height position on the second main surface side with respect to the height position of the active main surface, and an outer region provided outside the active region, A trench gate structure formed on the active main surface in the active region, A second-conductivity-type field region formed in a surface layer portion of the outer main surface in the outer region, A second-conductivity-type outer well region formed in a surface layer portion of the outer main surface, An active sidewall connecting the active main surface and the outer main surface and having an inclined surface inclined obliquely downward from the active main surface toward the outer main surface, The semiconductor layer includes an epitaxial layer forming the first main surface, The epitaxial layer includes a high-concentration region and a low-concentration region having a lower first-conductivity-type impurity concentration than the high-concentration region, and the low-concentration region is formed in a region on the second main surface side with respect to the high-concentration region, The field region is formed in a region between the outer well region and a periphery of the outer main surface, The outer well region has a bottom portion located on the second main surface side with respect to a depth position of a bottom wall of the trench gate structure, The semiconductor device in which the field region and the outer well region are formed in the high-concentration region in a surface layer portion of the outer main surface.

2. The semiconductor device according to claim 1, wherein the field region has a bottom portion located on the second main surface side with respect to a depth position of a bottom wall of the trench gate structure.

3. The semiconductor device according to claim 1 or 2, wherein a plurality of the field regions are formed in a surface layer portion of the outer main surface at intervals from the active region to a peripheral side of the outer region.

4. The semiconductor device according to claim 3, wherein intervals between a plurality of the field regions are different.

5. The semiconductor device according to claim 4, wherein an interval between a plurality of the field regions increases from the active region toward a peripheral side of the outer region.

6. The semiconductor device according to any one of claims 3 to 5, wherein a plurality of the field regions have equal depths to each other.

7. The active main surface is formed at an interval inward from a periphery of the first main surface, The semiconductor device according to any one of claims 1 to 6, wherein the outer main surface surrounds the active main surface.

8. The semiconductor device according to any one of claims 1 to 7, wherein the field region extends in a strip shape along the active main surface.

9. The semiconductor device according to any one of claims 1 to 8, wherein the field region surrounds the active main surface.

10. The semiconductor device according to any one of claims 1 to 9, wherein an angle formed by the active sidewall and the active main surface in the semiconductor layer is 135° or less.

11. The semiconductor device further includes a body region formed in a surface layer portion of the active main surface, The semiconductor device according to any one of claims 1 to 10, wherein the trench gate structure penetrates the body region.

12. The semiconductor device according to claim 11, wherein the outer main surface is located closer to the second main surface side than a bottom portion of the body region.

13. The semiconductor device according to claim 11 or 12, wherein the body region is exposed from the active sidewall.

14. The semiconductor device according to claim 13, wherein the body region is exposed from the inclined surface.

15. The semiconductor device according to any one of claims 1 to 14, wherein the bottom of the field region and the bottom of the outer well region are located within the high-concentration region.

16. The semiconductor device according to any one of claims 1 to 15, wherein the bottom of the field region and the bottom of the outer well region face the low-concentration region with a part of the high-concentration region therebetween.

17. The semiconductor layer has a stacked structure including a semiconductor substrate forming the second main surface and the epitaxial layer, the active main surface is formed on the epitaxial layer, and the outer main surface is formed on the epitaxial layer. The semiconductor device according to any one of claims 1 to 16.

18. The semiconductor device according to any one of claims 1 to 17, wherein the semiconductor layer contains SiC.

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