Wiring Substrate, Semiconductor Device, and Electronic Apparatus

Abstract

To provide an electronic apparatus which achieves reduction of EMI and improvement of EMS more easily than the prior arts, and a semiconductor device.SOLUTION: A first face of a wiring board includes a plurality of pads connected to a semiconductor chip by wires and a plurality of wires connected to any of the plurality of pads. A second face includes a plurality of ball electrodes 9 disposed in contact with any of a plurality of opposite pads provided on a mount substrate. In the plurality of wires, a first wire is a ground wire supplying a ground potential to a first circuit block. A second wire is a ground wire supplying a ground potential to a second circuit block. The second face further includes a first extended pad connected to a ball electrode 9d connected with the first wire and a second extended pad connected to a ball electrode 9f connected with the second wire. The first extended pad and the second extended pad are disposed at such positions that they can be interconnected by the ball electrode.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a wiring board, a semiconductor device, and an electronic device.

Background Art

[0002] Reducing the EMI (electromagnetic interference) of a semiconductor device and improving its EMS (electromagnetic susceptibility) are important. The reduction of EMI is achieved by reducing the radiation of unnecessary electromagnetic noise. The improvement of EMS is realized by increasing the resistance to electromagnetic noise. According to Patent Document 1, it has been proposed to provide a plurality of terminals for individually supplying the ground potential of each of a plurality of circuit blocks mounted on a semiconductor device. Thereby, while realizing a common ground potential among the plurality of circuit blocks, the plurality of circuit blocks do not have a common impedance. As a result, electromagnetic noise generated from a specific circuit block is less likely to leak into other circuit blocks. That is, the EMI is reduced.

[0003] According to Patent Document 2, it has been proposed to provide individual ground wirings for each of a plurality of circuit blocks, connect bonding pads to the respective ground wirings, and connect extension pads to the bonding pads via bonding wires. Further, by connecting the plurality of extension pads with wires, the impedance of the ground wiring is adjusted. Thereby, reduction of EMI and improvement of EMS are achieved.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, since semiconductor devices are mounted on various mounting substrates with different designs, it is necessary to reduce EMI and improve EMS for each mounting substrate on which the semiconductor device is mounted. According to Patent Document 2, the impedance is adjusted depending on whether or not wire bonding is used to connect between a plurality of extended pads, and reduction of EMI and improvement of EMS are realized. However, adjustment of the impedance by wire bonding is not easy. Since wire bonding for impedance adjustment may interfere with other wirings, the degree of freedom in arranging the wire bonding may be limited. Therefore, an object of the present invention is to achieve reduction of EMI and improvement of EMS more easily than in the prior art.

Means for Solving the Problems

[0006] According to the present invention, for example, a semiconductor chip including a plurality of circuit blocks and a plurality of first electrode pads connected to any one of the plurality of circuit blocks, a wiring substrate on which the semiconductor chip is mounted, and a sealing body that seals the semiconductor chip on the wiring substrate, a semiconductor device having, an electronic device having a mounting substrate on which the semiconductor device is mounted, the wiring substrate has a first surface on which the semiconductor chip is mounted and a second surface facing the mounting substrate, the first surface has a plurality of second electrode pads connected by wires to the plurality of first electrode pads provided on the semiconductor chip, and a plurality of wirings connected to any one of the plurality of second electrode pads, the second surface has a plurality of ball electrodes connected to any one of the plurality of wirings and arranged to contact any one of the plurality of opposing pads provided on the mounting substrate, a first wiring among the plurality of wirings is a ground wiring that supplies a ground potential to a first circuit block among the plurality of circuit blocks, a second wiring among the plurality of wirings is a ground wiring that supplies a ground potential to a second circuit block among the plurality of circuit blocks, The second surface further has a first extended pad connected to a first ball electrode connected to the first wiring, and a second extended pad connected to a second ball electrode connected to the second wiring. An electronic device is provided, wherein the first extended pad and the second extended pad are arranged at positions where they can be mutually connected by a single ball electrode on the second surface side.

Effect of the Invention

[0007] According to the present invention, reduction of EMI and improvement of EMS can be achieved more easily than before.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] <Example 1> [Structure of Semiconductor Device] As shown in FIG. 1, in the electronic device 100, the semiconductor device 1 is mounted on the mounting substrate 10. The semiconductor device 1 has a semiconductor chip 2, a wiring substrate 4, bonding wires 6, a sealing body 7, and ball electrodes 9. The semiconductor chip 2 is mounted on the first surface 31 of the wiring substrate 4. The bonding wires 6 are conductive and electrically connect the semiconductor chip 2 and the wiring substrate 4. The sealing body 7 is a resin that seals the semiconductor chip 2 and the plurality of bonding wires 6 on the wiring substrate 4. A plurality of ball electrodes 9 are arranged on the second surface 32 of the wiring substrate 4. Since the second surface 32 is the surface on the opposite side of the first surface 31, the first surface 31 may be referred to as the front surface or the top surface, and the second surface 32 may be referred to as the back surface or the bottom surface. The ball electrode 9 is a kind of external terminal. Thus, the semiconductor device 1 is a BGA (Ball Grid Array) type semiconductor package.

[0011] [Wiring Substrate and Semiconductor Chip] As shown in FIG. 2, the semiconductor chip 2 is mounted at the center of the wiring substrate 4. The semiconductor chip 2 has a plurality of circuit blocks formed on a semiconductor wafer such as silicon, for example. A plurality of electrode pads 3 are arranged near the four sides of the semiconductor chip 2, respectively. The electrode pads 3 include a power supply terminal that supplies a power supply voltage and a ground potential to the circuit blocks provided in the semiconductor chip 2, a signal terminal for inputting a signal to the circuit blocks, and a signal terminal for outputting a signal from the circuit blocks.

[0012] The wiring board 4 is, for example, an electronic circuit board in which a wiring pattern is formed of copper foil on a resin board. The wiring board 4 has bonding pad regions 51, 52, 53, and 54. The bonding pad regions 51, 52, 53, and 54 are provided opposite to a plurality of electrode pads 3 provided near each side of the semiconductor chip 2. A plurality of bonding pads 5 are provided in the bonding pad regions 51, 52, 53, and 54. Each of the plurality of bonding pads 5 is electrically connected to the electrode pad 3 via a bonding wire 6. Each of the plurality of bonding pads 5 is electrically connected to a ball electrode 9 provided on the second surface 32 of the wiring board 4 via a via or the like. A via is generally a non-through hole that electrically connects a plurality of layers. The semiconductor chip 2 performs signal input / output to the outside and receives and supplies a power supply voltage and a ground potential via the ball electrode 9.

[0013] [Configuration of Semiconductor Chip] As shown in FIG. 3, the semiconductor chip 2 has a plurality of circuit blocks. The plurality of circuit blocks include, for example, OSC21, PLL22, REG23, ROM24, CPU25, RAM26, Logic27, and ADC28. The lowercase alphabet at the end of the reference numerals assigned to the plurality of components may be omitted when matters common to the plurality of components are described.

[0014] OSC21 is an oscillation circuit that generates a reference clock signal based on an input signal from a crystal oscillator outside the semiconductor chip 2. OSC21 is connected to the electrode pad 3g and the electrode pad 3h. The electrode pad 3g is a pad for receiving and supplying the power supply voltage VCC_OSC. The electrode pad 3h is a pad for receiving and supplying the ground potential (hereinafter also referred to as GND potential) GND_OSC.

[0015] PLL22 is a phase-locked loop circuit that multiplies the frequency of the reference clock signal generated by OSC21. PLL22 is connected to electrode pads 3e and electrode pads 3f. Electrode pad 3e is a pad for receiving and supplying the power supply voltage VDD_PLL. Electrode pad 3f is a pad for receiving and supplying the GND potential GND_PLL. OSC21 and PLL22 are circuits that generate various clock signals from the reference clock signal. The voltage level of the clock signal varies repeatedly. Therefore, oscillation noise may occur due to the clock signal. The oscillation noise may penetrate from one circuit block to another via the common impedance between multiple circuit blocks. Therefore, the oscillation noise may increase the level of radiated noise, which is the main cause of EMI. In Example 1, in order to reduce EMI within semiconductor chip 2, a plurality of power supply wirings for supplying the power supply voltage and a plurality of ground wirings (hereinafter referred to as GND wirings) for supplying the GND potential are separated between a plurality of circuit blocks. As a result, the plurality of circuit blocks do not have a common impedance.

[0016] REG23 is a linear regulator circuit that generates the power supply voltage used inside semiconductor chip 2 from the power supply voltage supplied from a power supply device outside semiconductor device 1. REG23 is connected to electrode pads 3a, electrode pads 3b, and electrode pads 3c. Electrode pad 3a is a pad for receiving the power supply voltage VDD supplied from an external power supply device. Electrode pad 3b is a pad for receiving the GND potential GND_REG. Electrode pad 3c is a pad for outputting the power supply voltage VCC_REG generated by REG23.

[0017] ROM24 is a non-volatile memory that stores the control program executed by CPU25. ROM24 is connected to electrode pads 3i and electrode pads 3j. Electrode pad 3i is a pad for receiving the power supply voltage VCC_ROM. Electrode pad 3j is a pad for receiving the GND potential GND_ROM. CPU25 reads out the control program stored in ROM24 and executes various arithmetic processes according to the control program.

[0018] RAM 26 is a volatile memory. RAM 26 temporarily stores data processed by, for example, CPU 25.

[0019] Logic 27 includes, for example, a hardware circuit such as a communication circuit or a timer circuit. Logic 27 executes an operation according to an instruction output from CPU 25.

[0020] ADC 28 is an analog / digital conversion circuit that converts an analog signal input from an external terminal into a digital signal. ADC 28 is connected to electrode pads 3n and 3m. Electrode pad 3n is a pad for receiving and supplying the power supply voltage VCC_ADC. Electrode pad 3m is a pad for receiving and supplying the GND potential GND_ADC.

[0021] As shown in FIG. 3, CPU 25, RAM 26, and Logic 27 are each connected to electrode pads 3c and 3d, 3k, 3l, 3o. Electrode pad 3c supplies the common power supply voltage VDD to CPU 25, RAM 26, and Logic 27. Electrode pads 3d, 3k, 3l, 3o supply the common GND potential CGND to CPU 25, RAM 26, and Logic 27. In Example 1, the required power supply voltage differs for each circuit block. Therefore, there are the power supply voltage VDD and the power supply voltage VCC.

[0022] [Wiring Pattern of Wiring Substrate] FIG. 4 shows an example of a wiring pattern 11 provided on the first surface 31 of a wiring board 4. A semiconductor chip 2 is mounted in a region surrounded by a dashed line on the first surface 31. In each of the bonding pad regions 51, 52, 53, 54, 17 bonding pads 5 arranged in two rows are provided. In FIG. 4, among the wiring patterns 11 connected to the bonding pads 5 provided in the bonding pad regions 51, 52, 53, 54, hatching is applied to the GND wirings (e.g., GND_PLL, CGND, etc.) that supply a ground potential. The remaining bonding pads 5 excluding the bonding pads 5 of the GND wirings are not hatched. That is, the remaining bonding pads 5 are shown in white. The white bonding pads 5 are connected to electrode pads 3 that function as any of a signal input terminal, a signal output terminal, and a power supply terminal of the semiconductor chip 2. One end of the wiring pattern 11 connected to the white bonding pad 5 is connected to a via 8. The via 8 is electrically connected to a ball electrode 9 disposed on the second surface 32 of the wiring board 4. As shown in FIG. 4, the other ends of all the wiring patterns 11 extend to the side (end portion) of the wiring board 4. Thus, a via 8 is provided at one end of the wiring pattern 11, the other end of the wiring pattern 11 extends to the side of the wiring board 4, and bonding pads 5 are provided in the middle of the wiring pattern 11.

[0023] The circles marked at one end of each wiring pattern 11 connected to the bonding pads 5 for the power supply voltages VDD_PLL, VDD, VCC_REG, VCC_ADC, VCC_OSC, and VCC_ROM indicate vias 8. The circles marked on the wiring pattern 11 connected to the bonding pads 5 for the GND potentials GND_PLL, CGND, GND_REG, GND_ADC, GND_OSC, and GND_ROM also indicate vias 8. As shown in FIG. 4, wiring patterns 11 for the GND potential CGND are provided on each of the four sides of the wiring substrate 4. The four wiring patterns 11 for the GND potential CGND are interconnected via a GND wiring 41 provided in the central portion of the wiring substrate 4. The wiring pattern 11 for the GND potential GND_PLL is connected to the GND wiring 42. The wiring pattern 11 for the GND potential GND_REG is connected to the GND wiring 43.

[0024] In FIG. 4, the bonding pad 5d is connected to the GND wiring 41 for the GND potential CGND via the wiring pattern 11. The bonding pad 5f is connected to the GND wiring 42 for the GND potential GND_PLL via the wiring pattern 11. The bonding pad 5b is connected to the GND wiring 43 for the GND potential GND_REG via the wiring pattern 11.

[0025] The bonding pad 5o is connected to the GND wiring 41 for the GND potential CGND via the wiring pattern 11. The bonding pad 5m is connected to the GND wiring 44 for the GND potential GND_ADC via the wiring pattern 11. The bonding pad 5k is connected to the GND wiring 41 for the GND potential CGND via the wiring pattern 11. The bonding pad 5j is connected to the GND wiring 45 for the GND potential GND_ROM via the wiring pattern 11. The bonding pad 5h is connected to the GND wiring 46 for the GND potential GND_OSC via the wiring pattern 11.

[0026] The wiring patterns 11 for the power supply voltages VDD_PLL, VDD, VCC_REG, VCC_ADC, VCC_OSC, and VCC_ROM are separated from each other. The bonding pads 5 of these wiring patterns 11 for the power supply voltages are connected to the corresponding electrode pads 3. The wiring patterns 11 for the GND potentials GND_PLL, CGND, GND_REG, GND_ADC, GND_OSC, and GND_ROM are also separated from each other. The bonding pads 5 of these wiring patterns 11 for the GND potentials are also connected to the corresponding electrode pads 3.

[0027] As the number of power supply wirings and the number of GND wirings increase, the wiring efficiency on the mounting substrate 10 decreases. When the number of substrate layers constituting the mounting substrate 10 is small (e.g., two layers), the wiring efficiency may further decrease. As a result, the individual impedance of a certain power supply wiring or a certain GND wiring may become so high that it cannot be ignored.

[0028] FIG. 5 shows an example of a wiring pattern provided on the second surface 32 of the wiring substrate 4. Note that since the perspective of FIG. 5 is on the second surface 32 side of the wiring substrate 4, the left and right are reversed compared to the first surface 31 shown in FIG. 4. In FIG. 5, the vicinity of the back surface of the bonding pad region 51 is shown. The GND wiring 61 is connected to the GND wiring 41 provided on the first surface 31 via a plurality of vias 8a. Further, the GND wiring 61 is connected to the bonding pad 5d via the GND wiring 41. The GND wiring 62 is connected to the GND wiring 42 on the first surface 31 via a via 8b. Further, the GND wiring 62 is connected to the bonding pad 5f via the GND wiring 42. The GND wiring 63 is connected to the GND wiring 43 on the first surface 31 via a via 8c. Further, the GND wiring 63 is connected to the bonding pad 5b via the GND wiring 43. The white wiring patterns other than the GND wirings are each connected to the corresponding bonding pad 5 via a via 8.

[0029] A plurality of bonding pads provided in the bonding pad region 51 may each be provided with a ball electrode 9. For example, a ball electrode 9d is provided on the bonding pad 5d via a GND wiring 41, a via 8, and a GND wiring 61. That is, these are electrically connected. Similarly, a ball electrode 9f is connected to the bonding pad 5f via a GND wiring 42, a via 8, and a GND wiring 62. A ball electrode 9b is connected to the bonding pad 5b via a GND wiring 43, a via 8, and a GND wiring 63. Thereby, the plurality of bonding pads 5 provided in the bonding pad region 51 can be electrically connected to the mounting substrate 10 via the ball electrodes 9. When the ball electrode 9 is installed on the extension pad 101, the GND wiring 61 and the GND wiring 62 are connected via the ball electrode 9. When the ball electrode 9 is provided on the extension pad 102, the GND wiring 61 and the GND wiring 63 are connected via the ball electrode 9.

[0030] FIG. 6(A) is a side view of the wiring substrate 4 in a state where the ball electrodes 9 are not provided on the extension pads 101 and 102. Various wirings (power supply wirings, signal wirings, GND wirings, etc.) are formed of copper foil on the front layer side and the back layer side of the base material 71. The surface of the copper foil is covered with a resist 73. In this example, the GND wiring 61 and the GND wiring 62 are provided on the back layer side of the base material 71. A wiring 72 is provided on the front layer side of the base material 71. The wiring 72 is various wirings including the GND wiring 61, the GND wiring 62, and the GND wiring 63. The GND wiring 61, the GND wiring 62, and the GND wiring 63 may each be provided over two layers.

[0031] An extension pad 101 for connecting the GND wiring 61 and the GND wiring 62 is provided. Similarly, an extension pad 102 for connecting the GND wiring 61 and the GND wiring 63 is also provided. The extension pad 101 is composed of the exposed copper foil 103a of the GND wiring 61 and the exposed copper foil 103b of the GND wiring 62. The extension pad 102 is composed of the exposed copper foil 103c of the GND wiring 61 and the exposed copper foil 103d of the GND wiring 63. These exposed copper foils 103a to 103d are formed by either not providing the resist 73 in advance or removing the resist 73 afterwards. Since the exposed copper foils 103a to 103d function as electrodes, each of the exposed copper foils 103a to 103d may be called an extension pad.

[0032] In Fig. 6(B), ball electrodes 9r and 9s are provided on the extension pads 101 and 102, respectively. Thereby, the GND wiring 61 and the GND wiring 62 are connected, and the GND wiring 61 and the GND wiring 63 are connected.

[0033] [Connection between the semiconductor device and the mounting substrate] Fig. 7 is a diagram showing an example of the wiring pattern of the mounting substrate 10. The ball electrodes 9 of the semiconductor device 1 are placed on the circular lands 90 arranged in the regions 60a and 60b on the surface side of the mounting substrate 10. Thereby, the land 90 and the ball electrode 9 are electrically connected. The GND wiring 91 provided on the surface side of the mounting substrate 10 is the GND wiring pattern on the mounting substrate 10. The GND wiring 91 is connected to the GND wiring 61 on the second surface 32 of the wiring substrate 4 via the land 90d and the ball electrode 9d, and is also connected to the GND wiring 41 on the first surface 31 of the wiring substrate 4. The GND wiring 92 is also the GND wiring pattern of the mounting substrate 10. The GND wiring 93 is connected to the GND wiring 63 on the second surface 32 of the wiring substrate 4 via the land 90b and the ball electrode 9b, and is connected to the GND wiring 43 on the first surface 31 of the wiring substrate 4. The GND wiring 92 is also the GND wiring pattern on the mounting substrate 10. The GND wiring 92 is connected to the GND wiring 62 on the second surface 32 of the wiring substrate 4 via the land 90f and the ball electrode 9f, and is connected to the GND wiring 42 on the first surface 31 of the wiring substrate 4.

[0034] The white wiring pattern 96 is a signal wiring or a power supply wiring. A circular land 90 is provided at one end of these wiring patterns 96, and a through hole 94 is provided at the other end. Generally, the through hole 94 refers to a through-type hole into which the lead of an electronic device is inserted, but in this embodiment, it may be an interstitial via into which no lead is inserted. The GND wirings 91, 92, and 93 are electrically connected at position 95. Position 95 is away from the land 90 of the wiring pattern 96 with which the ball electrode 9 of the semiconductor device 1 contacts. Since the land 90 is not provided around the through hole in the first embodiment, it may be called a pad.

[0035] For example, when the individual impedance of the GND wiring 42 becomes high with respect to the GND wiring 41 of the wiring board 4, the semiconductor chip 2 is likely to malfunction due to EMS. EMS causes fluctuations in the ground potential of each GND wiring. Therefore, the high individual impedance of the GND wiring 42 causes distortion in the clock generated by the PLL 22. The CPU 25 operates based on the clock signal supplied from the PLL 22. Therefore, an inconsistency occurs in the operation timing of the CPU 25, and for example, the CPU 25 may enter an error state such as a bus fault.

[0036] The individual impedance of the GND wiring 43 may also become high with respect to the GND wiring 41 of the wiring board 4. In this case, the semiconductor chip 2 is likely to malfunction due to EMS. That is, EMS varies the ground potential of each GND wiring. Therefore, the high individual impedance of the GND wiring 43 causes distortion in the reference voltage generated by the REG 23. The CPU 25 operates based on the voltage supplied from the REG 23. Therefore, the CPU 25 may malfunction.

[0037] In Example 1, in order to avoid such an error state, an extended pad 101 for connecting the GND wiring 61 and the GND wiring 62 is provided on the second surface 32 of the wiring board 4. The extended pad 101 is disposed between the ball electrode 9 provided on the second surface 32 side and the GND wiring 61. The GND wiring 61 is connected to the GND wiring 41. The GND wiring 62 is connected to the GND wiring 42. When the individual impedance of the GND wiring 42 with respect to the GND wiring 41 is high, by installing the ball electrode 9 on the extended pad 101, the GND wiring 61 and the GND wiring 62 are electrically connected. As a result, the individual impedance of the GND wiring 42 of the PLL 22 is reduced, and the malfunction of the PLL 22 is less likely to occur. That is, the EMS (electromagnetic tolerance) is improved.

[0038] According to FIG. 5, an extended pad 102 for connecting the GND wiring 61 and the GND wiring 63 is disposed between the ball electrode 9 and the GND wiring 63. The GND wiring 61 is connected to the GND wiring 41. The GND wiring 63 is connected to the GND wiring 43. When the individual impedance of the GND wiring 43 with respect to the GND wiring 41 is high, by installing the ball electrode 9 on the extended pad 102, the GND wiring 61 and the GND wiring 63 are electrically connected. As a result, the individual impedance of the GND wiring 43 of the REG 23 is reduced, and the malfunction of the REG 23 is less likely to occur. That is, the EMS is improved.

[0039] In FIG. 5, the extended pad 101 and the extended pad 102 are provided, but this is only an example. An extended pad for connecting a GND wiring for any one of the GND potentials GND_ADC, GND_OSC, GND_ROM and the GND wiring 61 may be added.

[0040] FIG. 8(A) shows an extended pad 104 that connects a GND wiring 61 provided on the second surface 32 side and a GND wiring 111 for GND_ADC. The GND wiring 111 has a ball electrode 9 and a via 8. The ball electrode 9 is arranged to be in electrical contact with a pad on the mounting substrate 10. The via 8 electrically connects the GND wiring 111 and a GND wiring 44 for the GND potential GND_ADC provided on the first surface 31 side. Therefore, by providing the ball electrode 9 for the extended pad 104, the GND wiring 61, the GND wiring 111, and the GND wiring 41 can be electrically connected. Thereby, the individual impedance can be adjusted.

[0041] FIG. 8(B) shows an extended pad 105 that connects a GND wiring 61 provided on the second surface 32 side and a GND wiring 121 for GND_OSC. Further, FIG. 8(B) shows an extended pad 106 that connects a GND wiring 61 provided on the second surface 32 side and a GND wiring 122 for GND_ROM. The GND wiring 121 has a ball electrode 9 and a via 8. The ball electrode 9 is arranged to be in electrical contact with a pad on the mounting substrate 10. The via 8 electrically connects the GND wiring 121 and a GND wiring 46 for the GND potential GND_OSC provided on the first surface 31 side. Therefore, by providing the ball electrode 9 for the extended pad 105, the GND wiring 61, the GND wiring 121, and the GND wiring 41 can be electrically connected. Thereby, the individual impedance can be adjusted. The GND wiring 122 has a ball electrode 9 and a via 8. The ball electrode 9 is arranged to be in electrical contact with a pad on the mounting substrate 10. The via 8 electrically connects the GND wiring 122 and a GND wiring 45 for the GND potential GND_ROM provided on the first surface 31 side. Therefore, by providing the ball electrode 9 for the extended pad 106, the GND wiring 61, the GND wiring 122, and the GND wiring 41 can be electrically connected. Thereby, the individual impedance can be adjusted.

[0042] According to Example 1, the extended pads 101 to 106 are arranged on the second surface 32 of the wiring board 4. Depending on whether the ball electrodes 9 are provided on the extended pads 101 to 106 or not, it is possible to switch between connection and separation of the wiring pattern on the first surface 31 side and the wiring pattern on the second surface 32 side. Thereby, adjustment of the individual impedance and the common impedance becomes possible. Further, by adopting the extended pads 101 to 106, the designer can select whether to prioritize EMI reduction or EMS improvement. That is, the degree of freedom in wiring on the mounting board 10 increases.

[0043] According to Example 1, impedance adjustment is realized by the presence or absence of connection of the ball electrodes 9 to the extended pads 101 to 106. When the mounting board 10 is changed to reduce the manufacturing cost, the impedance conditions change, so that a revision of the wiring board 4 may be required. However, in Example 1, since the impedance can be adjusted by the presence or absence of the ball electrodes 9, a revision of the wiring board 4 is not required, and the manufacturing cost is reduced. After the package of the semiconductor device 1 is completed, the combination of the presence or absence of the ball electrodes 9 can be changed, so that the degree of freedom in designing the electronic device 100 including the semiconductor device 1 and the mounting board 10 increases.

[0044] <Example 2> The extended pads 101 to 106 and the ball electrodes 9 of Example 1 were for connecting two wirings. Therefore, in Example 2, it is proposed to connect three GND wirings with one extended pad and one ball electrode 9. In Example 2, descriptions of the same or similar matters as in Example 1 are omitted, and the description of Example 1 is incorporated by reference.

[0045] [Wiring Pattern of Wiring Board] FIG. 9 shows an example of a wiring pattern on the second surface 32 side of the wiring board 4. In FIG. 9, compared with FIG. 5, the GND wirings 61, 62, and 63 extend in the y direction. Further, an extended pad 107 is provided at the position where the GND wirings 61, 62, and 63 are closest to each other. The extended pad 107 includes exposed copper foils 103a, 103b, and 103d. The exposed copper foil 103a is a part of the GND wiring 61. The exposed copper foil 103b is an example of the GND wiring 62. The exposed copper foil 103d is an example of the GND wiring 63. By providing one ball electrode 9 for the extended pad 107, the GND wirings 61, 62, and 63 are collectively electrically connected.

[0046] [Connection between semiconductor device and mounting substrate] FIG. 10 is a drawing corresponding to FIG. 7 of Example 1 and shows the surface side of the mounting substrate 10. Compared with FIG. 7, in FIG. 10, a part of the GND wiring 91 further extends in the y direction and is connected to a circular land 90t provided in the region 60c on the surface side of the mounting substrate 10. The position of this land 90t in the xy coordinates coincides with the position of the extended pad 107 in the xy coordinates. When the ball electrode 9 is placed on the land 90t, the land 90t and the ball electrode 9 are electrically connected. Further, the ball electrode 9 electrically connects the GND wirings 61, 62, and 63 at the extended pad 107. Further, the GND wiring 91 is connected to the GND wiring 61 and the GND wiring 41 of the wiring board 4. The GND wiring 93 is also connected to the GND wiring 63 and the GND wiring 43 via the land 90 and the ball electrode 9. The GND wiring 92 is also connected to the GND wiring 62 and the GND wiring 42 via the land 90 and the ball electrode 9.

[0047] As described in Example 1, when the individual impedances of the GND wiring 42 and the GND wiring 43 become high with respect to the GND wiring 41, malfunction of the semiconductor chip 2 is likely to occur. That is, when the ground potential of each GND wiring fluctuates, the clock generated by the PLL 22 is distorted by the GND wiring 42 and the GND wiring 43 with high individual impedance. Alternatively, the reference voltage generated by the REG 23 may be distorted. These lead to malfunctions of the CPU 25 and the like.

[0048] In Example 3, on the second surface 32 side of the wiring board 4, an extension pad 107 to which the GND wiring 61, the GND wiring 62, and the GND wiring 63 can be connected is provided. When the individual impedances of the GND wiring 42 and the GND wiring 43 are high with respect to the GND wiring 41, by installing one ball electrode 9 on the extension pad 107, the GND wiring 61, the GND wiring 62, and the GND wiring 63 are electrically connected. Thereby, the individual impedance of the GND wiring 42 of the PLL 22 is reduced, the EMS is improved, and malfunction of the PLL 22 is less likely to occur. Further, since the individual impedance of the GND wiring 43 of the REG 23 is also reduced, the EMS is improved and malfunction of the REG 23 is less likely to occur.

[0049] In Example 2, three GND wirings are connected by one ball electrode and one extension pad, but this is just an example. Four or more GND wirings may be connected by one ball electrode and one extension pad. Since the other advantages in Example 2 are common to the advantages of Example 1, the description thereof is omitted.

[0050] <Example 3> In Examples 1 and 2, the number of layers of the wiring board 4 was 2. In Example 3, a wiring board 4 having three or more layers will be described. In Example 3, the description of matters the same as or similar to those in Examples 1 and 2 is omitted, and the descriptions of Examples 1 and 2 are incorporated herein by reference.

[0051] [Wiring Pattern of Wiring Board] The number of wiring layers of the wiring board 4 shown in FIG. 11 is 4. That is, the wiring board 4 has layers L1 to L4. A base material 71 is disposed between adjacent layers. The GND wiring 61 is disposed on the layer L4. The GND wiring 62 is disposed on the layer L3. The GND wiring 63 is provided on the layer L2. The GND wiring 62 provided on the layer L3 extends to the layer L4 through the through hole 151. The extended pad 108 is composed of the exposed copper foil 103e of the GND wiring 62 exposed on the layer L4 and the exposed copper foil 103f of the GND wiring 61. By providing the ball electrode 9 on the extended pad 108, the GND wiring 61 and the GND wiring 62 are electrically connected. The GND wiring 63 provided on the layer L2 extends to the layer L4 through the through hole 152. The extended pad 109 is composed of the exposed copper foil 103h of the GND wiring 63 exposed on the layer L4 and the exposed copper foil 103g of the GND wiring 61. By providing the ball electrode 9 on the extended pad 109, the GND wiring 61 and the GND wiring 63 are electrically connected.

[0052] Also in the third embodiment, as in the first embodiment, when the individual impedance of the GND wiring 42 with respect to the GND wiring 41 is high, one ball electrode 9 is installed on the extended pad 108. Thereby, the GND wiring 61 and the GND wiring 62 are electrically connected. As a result, the individual impedance of the GND wiring 42 of the PLL 22 is reduced, the EMS is improved, and the malfunction of the PLL 22 is less likely to occur. When the individual impedance of the GND wiring 43 with respect to the GND wiring 41 is high, the ball electrode 9 is provided on the extended pad 109. Thereby, the GND wiring 61 and the GND wiring 63 are electrically connected, and the individual impedance of the GND wiring 43 of the REG 23 is reduced. Therefore, the EMS of the REG 23 is improved, and the malfunction of the REG 23 is less likely to occur.

[0053] By multi - layerizing the wiring board 4, it becomes possible to disperse and arrange the GND wiring on a plurality of layers. As a result, it becomes easier to thicken the GND wiring connected to the extension pads 108 and 109 in the wiring board 4, and it becomes possible to further reduce the individual impedance. Since other advantages in Example 3 are common to the advantages of Example 1, the description thereof is omitted.

[0054] <Technical idea derived from the embodiment> [Viewpoints 1, 13, 14] As shown in FIG. 1, the semiconductor device 1 may include a semiconductor chip 2, a wiring board 4 on which the semiconductor chip 2 is mounted, and a sealing body 7 that seals the semiconductor chip 2 on the wiring board. The semiconductor chip 2 has a plurality of circuit blocks and a plurality of first electrode pads (e.g., electrode pad 3) connected to any one of the plurality of circuit blocks. The electronic device 100 includes the semiconductor device 1 and a mounting board 10 on which the semiconductor device 1 is mounted. The wiring board 4 may have a first surface 31 on which the semiconductor chip 2 is mounted and a second surface 32 facing the mounting board 10. The first surface 31 has a plurality of second electrode pads (e.g., a plurality of bonding pads 5) connected by wires to the plurality of first electrode pads provided on the semiconductor chip 2. The first surface 31 may have a plurality of wirings (e.g., GND wirings 41 to 46) connected to any one of the plurality of bonding pads. The second surface 32 may have a plurality of ball electrodes 9 arranged so as to contact any one of the plurality of opposing pads (e.g., lands 90) provided on the mounting board 10. Among the plurality of wirings, the first wiring (e.g., GND wiring 41) is a ground wiring that supplies a ground potential to a first circuit block (e.g., CPU 25, RAM 26) among the plurality of circuit blocks. Among the plurality of wirings, the second wiring (e.g., GND wiring 42) is a ground wiring that supplies a ground potential to a second circuit block (e.g., PLL 22) among the plurality of circuit blocks. The second surface 32 may further have a first extended pad (e.g., exposed copper foil 103a) and a second extended pad (e.g., exposed copper foil 103b). The first extended pad is a pad connected to a first ball electrode (e.g., ball electrode 9d) connected to the first wiring. The second extended pad is a pad connected to a second ball electrode (e.g., ball electrode 9f) connected to the second wiring. As shown in FIGS. 6(A) and 6(B), the first extended pad and the second extended pad are arranged at positions where they can be mutually connected by a single ball electrode 9r on the second surface 32 side. Conventionally, since a plurality of GND wirings were connected by bonding wires, various difficulties existed. However, according to Embodiments 1 to 3, a plurality of GND wirings can be connected by extended pads and ball electrodes. Therefore, EMI reduction and EMS improvement can be achieved more easily than in the prior art.

[0055] [Viewpoint 2] Before the first extension pad and the second extension pad are connected by a single ball electrode 9r, the individual impedance of the second wiring may be higher than that of the first wiring. In this case, after the first extension pad and the second extension pad are connected by a single ball electrode 9r, the individual impedance of the second wiring becomes lower. By performing such impedance adjustment, EMI reduction and EMS improvement can be achieved more easily than before.

[0056] [Viewpoint 3] As described with reference to FIG. 5, via 8a is an example of a first via that connects the first wiring and the first extension pad. Via 8b is an example of a second via that connects the second wiring and the second extension pad. By using via 8 in this way, it becomes possible to more easily electrically connect the wiring on the first surface 31 side of the wiring board 4 and the extension pad on the second surface 32 side.

[0057] [Viewpoint 4] The GND wiring 61 is provided inside the second surface 32 or the wiring board 4 and is an example of a first ground pattern that connects the first ball electrode (e.g., ball electrode 9d) and the first extension pad. The GND wiring 62 is provided inside the second surface 32 or the wiring board 4 and is an example of a second ground pattern that connects the second ball electrode (e.g., ball electrode 9f) and the second extension pad. By providing the GND wiring also inside the second surface 32 or the wiring board 4 in this way, EMI reduction and EMS improvement can be achieved more easily than before.

[0058] [Viewpoint 5] As shown in FIGS. 6(A) and 6(B), the first ground pattern and the second ground pattern may be arranged on the same layer inside the wiring board 4. In this case, the first extension pad is a portion (e.g., exposed copper foil 103a) of the first ground pattern that is exposed on the second surface side. The second extension pad is a portion (e.g., exposed copper foil 103b) of the second ground pattern that is exposed on the second surface side.

[0059] [Aspect 6] As shown in FIG. 11, the first ground pattern may be disposed on a first layer (e.g., layer L4) inside the wiring substrate. The second ground pattern may be disposed on a second layer (e.g., layer L3) inside the wiring substrate. In this case, the first extended pad is a portion (e.g., exposed copper foil 103f) of the first ground pattern that is exposed on the second surface side. The second extended pad is a portion (e.g., exposed copper foil 103e) of the second ground pattern provided on the second layer that extends to the first layer and is exposed on the second surface side. By adopting such a multilayer structure, it becomes possible to thicken the ground pattern and further reduce the individual impedance. Therefore, EMI reduction and EMS improvement can be achieved more easily than before.

[0060] [Aspect 7] As shown in FIG. 7, the mounting substrate 10 may have a wiring group (e.g., GND wirings 91, 92) that connects a first opposing pad (e.g., land 90d) in contact with the first ball electrode and a second opposing pad (e.g., land 90f) in contact with the second ball electrode.

[0061] [Aspect 8] Among the plurality of wirings provided on the wiring substrate 4, the third wiring (e.g., GND wiring 43) is a ground wiring that supplies a ground potential to a third circuit block (e.g., REG23) among the plurality of circuit blocks. The ball electrode 9b is an example of a third ball electrode connected to the third wiring. The exposed copper foil 103d is an example of a third extended pad connected to the ball electrode 9b. The exposed copper foil 103c is an example of a fourth extended pad connected to a first ball electrode connected to the first wiring among the plurality of ball electrodes provided on the second surface. As shown in FIGS. 6(A) and 6(B), the third extended pad and the fourth extended pad are disposed at positions where they can be mutually connected by a single ball electrode (e.g., ball electrode 9s) on the second surface side.

[0062] [Aspect 9] Before the third extension pad and the fourth extension pad are connected by a single ball electrode, the individual impedance of the third wiring may be higher than that of the first wiring. In this case, after the third extension pad and the fourth extension pad are connected by a single ball electrode, the individual impedance of the third wiring becomes lower. Therefore, EMI reduction and EMS improvement can be achieved more easily than before.

[0063] [Aspect 10] As shown in FIG. 9, the first extension pad, the second extension pad, and the third extension pad may be arranged at positions where they can be mutually connected by a single ball electrode on the second surface side. In this way, by connecting the three extension pads with a single ball electrode, EMI reduction and EMS improvement can be achieved more easily than before.

[0064] [Aspect 11] Before the first extension pad, the second extension pad, and the third extension pad are connected by a single ball electrode, the individual impedance of the second wiring may be higher than that of the first wiring. The individual impedance of the third wiring may be higher than that of the first wiring. In this case, after the first extension pad, the second extension pad, and the third extension pad are connected by a single ball electrode, the individual impedances of the second wiring and the third wiring become lower. In this way, since the impedances of a plurality of wirings can be adjusted by a single ball electrode, EMI reduction and EMS improvement can be achieved more easily than before.

[0065] [Aspect 12] Via 8c is an example of a third via that connects the third wiring and the third extension pad. By using via 8 in this way, it becomes possible to more easily electrically connect the GND wiring 43 on the first surface 31 side of the wiring board 4 and the extension pad (e.g., exposed copper foil 103d) on the second surface 32 side.

[0066] The invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the claims are appended to disclose the scope of the invention.

Explanation of Signs

[0067] 100: Electronic device, 1: Semiconductor device, 2: Semiconductor chip, 4: Wiring board, 7: Sealing body

Claims

1. A semiconductor device including a plurality of circuit blocks, a plurality of first electrode pads connected to any of the plurality of circuit blocks, a wiring board on which the semiconductor chip is mounted, and a sealing body that seals the semiconductor chip on the wiring board. An electronic device having a mounting board on which the semiconductor device is mounted. The wiring board has a first surface on which the semiconductor chip is mounted and a second surface facing the mounting board. The first surface A plurality of second electrode pads connected by wires to the plurality of first electrode pads provided on the semiconductor chip. And a plurality of wirings connected to any of the plurality of second electrode pads. The second surface has a plurality of ball electrodes connected to any of the plurality of wirings and arranged to contact any of the plurality of opposing pads provided on the mounting board. Among the plurality of wirings, the first wiring is a ground wiring that supplies a ground potential to a first circuit block among the plurality of circuit blocks. Among the plurality of wirings, the second wiring is a ground wiring that supplies a ground potential to a second circuit block among the plurality of circuit blocks. The second surface further has a first extension pad connected to a first ball electrode connected to the first wiring and a second extension pad connected to a second ball electrode connected to the second wiring. The electronic device is characterized in that the first extension pad and the second extension pad are arranged at positions where they can be mutually connected by a single ball electrode on the second surface side.

2. Before the first extension pad and the second extension pad are connected by the single ball electrode, the individual impedance of the second wiring is larger than the individual impedance of the first wiring. The electronic device according to claim 1, wherein after the first extension pad and the second extension pad are connected by the single ball electrode, the individual impedance of the second wiring becomes low.

3. a first via connecting the first wiring and the first extension pad, a second via connecting the second wiring and the second extension pad, the electronic device according to claim 1 or 2, further comprising:

4. The wiring board further includes: a first ground pattern provided on the second surface or inside the wiring board and connecting the first ball electrode and the first extension pad; a second ground pattern provided on the second surface or inside the wiring board and connecting the second ball electrode and the second extension pad, the electronic device according to any one of claims 1 to 3, characterized by having:

5. The first ground pattern and the second ground pattern are arranged on the same layer inside the wiring board, the first extension pad is a portion of the first ground pattern exposed on the second surface side, the second extension pad is a portion of the second ground pattern exposed on the second surface side, the electronic device according to claim 4, characterized by:

6. The first ground pattern is arranged on a first layer inside the wiring board, the second ground pattern is arranged on a second layer inside the wiring board, the first extension pad is a portion of the first ground pattern exposed on the second surface side, the second extension pad is a portion of the second ground pattern provided on the second layer and extending to the first layer and exposed on the second surface side, the electronic device according to claim 4, characterized by:

7. The implementation substrate has a wiring group that connects a first opposing pad that contacts the first ball electrode and a second opposing pad that contacts the second ball electrode among the plurality of opposing pads. The electronic device according to any one of claims 1 to 6, characterized in that.

8. Among the plurality of wirings provided on the wiring substrate, the third wiring is a ground wiring that supplies a ground potential to a third circuit block among the plurality of circuit blocks. The second surface further has a third extension pad connected to a third ball electrode connected to the third wiring, and a fourth extension pad connected to the first ball electrode connected to the first wiring among the plurality of ball electrodes provided on the second surface. The electronic device according to any one of claims 1 to 7, characterized in that the third extension pad and the fourth extension pad are arranged at positions where they can be mutually connected by a single ball electrode on the second surface side.

9. Before the third extension pad and the fourth extension pad are connected by a single ball electrode, the individual impedance of the third wiring is larger than the individual impedance of the first wiring. The electronic device according to claim 8, characterized in that after the third extension pad and the fourth extension pad are connected by a single ball electrode, the individual impedance of the third wiring becomes low.

10. Among the plurality of wirings provided on the wiring substrate, the third wiring is a ground wiring that supplies a ground potential to a third circuit block among the plurality of circuit blocks. The second surface further has a third extension pad connected to a third ball electrode connected to the third wiring among the plurality of ball electrodes provided on the second surface. The electronic device according to any one of claims 1 to 7, characterized in that the first extension pad, the second extension pad, and the third extension pad are arranged at positions where they can be mutually connected by a single ball electrode on the second surface side.

11. Before the first extension pad, the second extension pad, and the third extension pad are connected by a single ball electrode, the individual impedances of the second wiring and the third wiring are greater than the individual impedance of the first wiring. The electronic device according to claim 10, wherein after the first extension pad, the second extension pad, and the third extension pad are connected by a single ball electrode, the individual impedances of the second wiring and the third wiring become low.

12. The electronic device according to any one of claims 8 to 11, further comprising a third via connecting the third wiring and the third extension pad.

13. A wiring board on which a semiconductor chip having a plurality of circuit blocks and a plurality of first electrode pads connected to any of the plurality of circuit blocks is mounted. A first surface on which the semiconductor chip is mounted. A second surface facing a mounting board on which the wiring board is mounted. The first surface A plurality of second electrode pads connected by wires to the plurality of first electrode pads provided on the semiconductor chip. A plurality of wirings connected to any of the plurality of second electrode pads. The second surface has a plurality of ball electrodes connected to any of the plurality of wirings and arranged to contact any of the plurality of opposing pads provided on the mounting board. Among the plurality of wirings, the first wiring is a ground wiring that supplies a ground potential to a first circuit block among the plurality of circuit blocks. Among the plurality of wirings, the second wiring is a ground wiring that supplies a ground potential to a second circuit block among the plurality of circuit blocks. The second surface further has a first extension pad connected to a first ball electrode connected to the first wiring and a second extension pad connected to a second ball electrode connected to the second wiring. The wiring board is characterized in that the first extension pad and the second extension pad are arranged at positions where they can be mutually connected by a single ball electrode on the second surface side.

14. A semiconductor device having a plurality of circuit blocks, a plurality of first electrode pads connected to any of the plurality of circuit blocks, a semiconductor chip including the plurality of first electrode pads, a wiring board on which the semiconductor chip is mounted, and a sealing body that seals the semiconductor chip on the wiring board, The wiring board is a first surface on which the semiconductor chip is mounted, a second surface facing a mounting board on which the semiconductor device is mounted, The first surface has a plurality of second electrode pads connected by wires to the plurality of first electrode pads provided on the semiconductor chip, and a plurality of wirings connected to any of the plurality of second electrode pads. The second surface has a plurality of ball electrodes connected to any of the plurality of wirings and arranged so as to contact any of the plurality of opposing pads provided on the mounting board. Among the plurality of wirings, the first wiring is a ground wiring that supplies a ground potential to a first circuit block among the plurality of circuit blocks. Among the plurality of wirings, the second wiring is a ground wiring that supplies a ground potential to a second circuit block among the plurality of circuit blocks. The second surface further has a first extension pad connected to a first ball electrode connected to the first wiring and a second extension pad connected to a second ball electrode connected to the second wiring. The semiconductor device is characterized in that the first extension pad and the second extension pad are arranged at positions where they can be mutually connected by a single ball electrode on the second surface side.

Images