Improvement in Handling of High-Resistance Substrate

Abstract

A method is disclosed for modifying a high resistivity substrate so that it can be clamped to a chuck by electrostatic forces. The bottom surface is implanted with a resistivity reducing species. This can significantly reduce the resistivity of the bottom surface of the substrate. In some embodiments, a coating is applied to the top surface in order to implant the bottom surface. After the coating is applied, the substrate is flipped so that the front side is in contact with the top surface of the chuck. The exposed bottom surface is then implanted with ions to form a low resistivity layer. The post-implant resistivity of the low resistivity layer adjacent the bottom surface can be less than 1000 Ω cm. Once the bottom surface is implanted, the substrate can be processed conventionally. The low resistivity layer can be subsequently removed by a wafer backside thinning process.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 17 / 226,277, filed on April 9, 2021, the entire content of which is incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to a method for improving the handling of substrates, particularly high-resistance substrates.

Background Art

[0003] Substrates are processed using multiple processes to fabricate semiconductor devices. In many of these processes, the substrate is clamped to the surface and remains stationary during the process.

[0004] This clamping can be achieved using a mechanical clamp that physically attaches the substrate to the chuck. Mechanical clamps are effective, but can lead to contamination, reduced process uniformity, reduction of useful wafer area, or damage to the substrate due to backside gas pressure. Alternatively, electrostatic force can be used to clamp the substrate to the chuck. An electric field is generated within the chuck. This electric field causes the electrons in the substrate to be pulled to the bottom surface of the substrate and attracted to the positive charges of the chuck. This attractive force serves to clamp the substrate to the chuck.

[0005] Electrostatic chucks are very effective and can reduce the possibility of substrate contamination or damage. However, this technique relies on the fact that the substrate has a fairly low resistivity. This allows electrons to move freely within the substrate and generate the electrostatic clamping force.

[0006] Substrates with high resistivity such as high-res silicon, silicon carbide, and gallium arsenide do not generate the same clamping force as silicon substrates. In fact, in one test, when a silicon substrate was placed on the chuck, the current generated in the electrostatic chuck tripled compared to when nothing was placed on the chuck. Conversely, when a high-resistance substrate was placed on the chuck, the current generated in the chuck was almost the same as when nothing was placed on the chuck.

[0007] Therefore, these high-resistance substrates are difficult to process. For example, when backside gas is applied at low pressure, the substrate may not be clamped. On the other hand, due to the low chuck force, in some cases, the use of high-pressure backside gas used for wafer cooling is restricted. Furthermore, these substrates are prone to damage caused by the inability to dissipate the accumulated charge to the chuck.

[0008] Therefore, a method of processing high-resistance substrates so that they can be clamped to the chuck by electrostatic force is beneficial. Furthermore, it is advantageous if this method does not have an adverse effect on throughput or does not introduce many additional manufacturing processes.

Summary of the Invention

[0009] A method of modifying a high-resistance substrate is disclosed so that the substrate can be clamped to the chuck by electrostatic force. A resistivity-reducing species is implanted into the bottom surface. This can significantly reduce the resistivity of the bottom surface of the substrate. In some embodiments, a coating is applied to the top surface for implantation into the bottom surface. After applying the coating, the substrate is inverted so that the front side contacts the top surface of the chuck. Then, ions are implanted into the exposed bottom surface to form a low-resistance layer. The resistivity of the low-resistance layer after implantation close to the bottom surface can be less than 1000 Ωcm. Once implanted into the bottom surface, the substrate can be processed as usual. The low-resistance layer can be removed later by a wafer backside thinning process, but in some embodiments, the layer is plated or metallized to form an electrode for a vertical transistor.

[0010] According to one embodiment, a method of processing a high-resistance substrate to enable an electrostatic clamp is disclosed. The method includes applying a coating to the upper surface of the high-resistance substrate, implanting ions into the bottom surface of the high-resistance substrate to form a low-resistance layer, and removing the coating such that the high-resistance substrate includes a low-resistance layer adjacent to its bottom surface that can be clamped to an electrostatic chuck. In some embodiments, due to the coating being a low-resistance material, before implanting the ions, the high-resistance substrate is inverted such that the coating contacts the upper surface of the electrostatic chuck, and the high-resistance substrate can be clamped to the electrostatic chuck by the coating. In certain embodiments, the coating includes amorphous carbon or titanium oxide. In certain embodiments, the ions reduce the resistivity of the low-resistance layer by at least five orders of magnitude relative to the resistivity of the high-resistance substrate. In some embodiments, the ions reduce the resistivity of the low-resistance layer to less than 1000 Ωcm. In certain embodiments, the ions reduce the resistivity of the low-resistance layer to less than 100 Ωcm. In some embodiments, the high-resistance substrate includes a GaAs substrate and the ions include silicon. In certain embodiments, the high-resistance substrate includes a SiC substrate and the ions include phosphorus, aluminum, or boron. In some embodiments, the high-resistance substrate includes a high-resistivity silicon substrate and the ions include phosphorus or boron. In certain embodiments, the implantation is performed using a non-zero tilt angle. In some embodiments, the ions are implanted such that the peak concentration of the ions occurs at a depth of less than 500 nanometers. In certain embodiments, the low-resistance layer is later removed. In certain embodiments, the low-resistance layer is later plated or metallized to form an electrode.

[0011] According to another embodiment, a method for processing a high-resistance substrate to enable an electrostatic clamp is disclosed, where the high-resistance substrate includes a sacrificial layer having a low resistivity disposed on an upper surface. The method includes implanting ions into a bottom surface of the high-resistance substrate, inverting the high-resistance substrate such that the sacrificial layer contacts an upper surface of an electrostatic chuck, and clamping the high-resistance substrate to the electrostatic chuck by the sacrificial layer. After implantation, the high-resistance substrate includes, adjacent to its bottom surface, a low-resistance layer that can be clamped to the electrostatic chuck. In certain embodiments, the ions reduce the resistivity of the low-resistance layer by at least five orders of magnitude relative to the resistivity of the high-resistance substrate. In some embodiments, the ions reduce the resistivity of the low-resistance layer to less than 1000 Ωcm. In certain embodiments, the ions reduce the resistivity of the low-resistance layer to less than 100 Ωcm. In certain embodiments, the implantation is performed using a non-zero tilt angle. In some embodiments, the ions are implanted such that a peak concentration of the ions occurs at a depth of less than 500 nanometers. In certain embodiments, the high-resistance substrate includes a GaAs substrate, a SiC substrate, or a high-resistivity silicon substrate, and the ions include silicon, phosphorus, aluminum, or boron.

[0012] According to another embodiment, a high-resistance substrate suitable for an electrostatic clamp is disclosed. The high-resistance substrate includes a low-resistance layer disposed within the substrate, the low-resistance layer includes resistivity-reducing species, and the resistivity of the low-resistance layer is 1000 Ωcm or less. In certain embodiments, a peak concentration of the resistivity-reducing species is disposed at a depth from 2 nanometers to 2 micrometers.

[0013] To better understand the present disclosure, reference is made to the accompanying drawings, which are incorporated herein by reference.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Modes for Carrying Out the Invention

[0015] As described above, the use of a high-resistance substrate using an electrostatic chuck may have problems because the generated clamping force is weak. To address this, a method for improving the ability to handle these high-resistance substrates, and more particularly, a method for using these high-resistance substrates using an electrostatic chuck, is disclosed.

[0016] Figures 1A to 1F are diagrams showing high-resistance substrates to which this method is applied. Figure 2 is a flowchart showing the processes included in this method.

[0017] This method begins with a high-resistance substrate 100, as shown in box 200 of Figures 1A and 2. The high-resistance substrate 100 may be gallium arsenide (GaAs), silicon carbide (SiC), high-resistance silicon (Hi-Res Si), or other high-resistance substrates. A high-resistance substrate is defined as a substrate having a resistivity of 1E4 Ωcm or more. In some embodiments, the high-resistance substrate may have a resistivity of 1E8 or more. In certain embodiments, the methods described herein are performed prior to other manufacturing processes. In some embodiments, it may be inserted into the manufacturing process flow prior to a first process that utilizes an electrostatic clamp. The thickness of the high-resistance substrate 100 is not limited by this embodiment and may be a thickness of up to several microns.

[0018] Next, as shown in box 210 and Figure 1B, a coating 110 is applied to the upper surface 101 of the high-resistance substrate 100. This coating 110 may have a low resistivity, such as less than 1000 Ωcm. In certain embodiments, the coating 110 may have a resistivity of less than 300 Ωcm. The coating 110 is amorphous carbon (a-C), titanium oxide (TiO x) or other suitable materials. In certain embodiments, the coating 110 is selected for ease of application. In certain embodiments, the coating 110 can be applied through spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable methods. The thickness of this coating 110 is not limited by the present disclosure as the coating may be removed at a later time. Thus, the coating 110 may have a thickness from 2 nm to 5 μm.

[0019] Next, as shown in box 220 and FIG. 1C, the high-resistance substrate 100 is inverted such that the top surface 101 having the coating 110 contacts the top surface of the chuck. Note that since the coating 110 is made of a low-resistance material, an electrostatic chuck can be used. The electrostatic force of the electrostatic chuck can clamp the high-resistance substrate by the coating 110.

[0020] Next, as shown in box 230 and FIG. 1D, an ion implantation process is performed to implant ions 120 into the exposed bottom surface of the high-resistance substrate 100. The ion implantation process is performed using ions 120 of a species also referred to as resistivity-reducing species that reduce the resistivity of the high-resistance substrate 100. For example, in the case of a SiC substrate, the resistivity-reducing species may be aluminum, boron, phosphorus, or other suitable species. In the case of a high-resistance Si substrate, the resistivity-reducing species may be boron, phosphorus, or other suitable species. In the case of a GaAs substrate, the resistivity-reducing species may be silicon or other suitable species.

[0021] The energy of the ion implantation process can be selected, for example, such that the thickness of the implantation region is from 2 nm to 5 μm. In certain embodiments, the thickness may be from 2 nm to 500 nm or less. In the case of a GaAs substrate, this energy may be from 5 Kev to 10 MeV. Of course, other thicknesses can also be used depending on the overall thickness of the high-resistance substrate.

[0022] The dosage of the ion implantation process may be sufficient for the implanted region to become a low-resistance layer having a resistivity of less than 1000 Ωcm. In certain embodiments, the dosage may be such that the resistivity of the low-resistance layer 130 is 100 Ωcm or less. In the case of a GaAs substrate, the dosage may be from 1E13 atoms / cm 2 to 1E18 atoms / cm 2 or, in certain embodiments, from 1E14 atoms / cm 2 to 1E16 atoms / cm 2 . A GaAs substrate may have a resistivity of from 1E8 Ωcm to 1E10 Ωcm. Thus, the ion implantation process can reduce the resistivity of the implanted portion of the high-resistance substrate by more than five orders of magnitude and by six orders of magnitude or more. Similar implantation processes using appropriate species can also be carried out for SiC, high-resistivity, and other high-resistance substrates.

[0023] In certain embodiments, the ion implantation process may be performed using a non-zero tilt angle to minimize channeling. FIG. 1D is a diagram showing the non-zero tilt angle (θ) used to implant ions 120. This non-zero tilt angle may be from 1° to 60°. In other embodiments, a non-zero tilt angle may not be used.

[0024] For example, in one test, silicon ions were implanted into a GaAs substrate at a tilt angle of 45° (relative to vertical implantation defined as 0°). The energy of the ions was 30 keV and the dosage was from 1E14 atoms / cm 2 to 1E15 atoms / cm 2 . The thickness of the resulting low-resistance layer 130 was less than 100 nanometers and, in certain embodiments, the peak concentration (Rp) was at a depth of approximately 50 nanometers.

[0025] Accordingly, the low-resistance layer 130 can be formed using a shallow implantation such that ions are concentrated near the bottom surface of the substrate. The peak concentration can be disposed at a depth between 2 nanometers and 2 micrometers depending on the thickness of the substrate. In certain embodiments, the peak concentration can be at a depth of less than 500 nanometers. In some embodiments, the peak concentration can be at a depth of less than 250 nanometers. In some embodiments, the peak concentration can be at a depth of less than 1000 nanometers.

[0026] As shown in box 240 and FIG. 1E, after the ion implantation process, the high-resistance substrate 100 can be inverted again so that the bottom surface 102 having the low-resistance layer 130 can contact the upper surface of the chuck. The coating 110 is exposed.

[0027] Next, as shown in box 250 and FIG. 1F, the coating 110 can be removed. In certain embodiments, the coating 110 can be removed using a reactive ion etching (RIE) process, a wet cleaning process, mechanical polishing, chemical mechanical polishing, or other film removal processes. In other embodiments, when the coating 110 contains amorphous carbon, an oxygen ashing process can be used.

[0028] Thus, after removing the coating 110, the high-resistance substrate 100 having the low-resistance layer 130 disposed adjacent to its bottom surface is ready for further processing. Note that the high-resistance substrate has not changed except for including the low-resistance layer 130 adjacent to the bottom surface. The low-resistance layer 130 can have a thickness of from 2 nanometers to 3 micrometers. In certain embodiments, the thickness of the low-resistance layer 130 can be less than 1 micrometer. In some embodiments, the thickness can be less than 500 nanometers. In some embodiments, the thickness can be less than 250 nanometers. In some embodiments, the thickness can be less than 100 nanometers.

[0029] In certain embodiments, as shown in box 260, an annealing process is performed after the ion implantation process to repair any damage to the low resistance layer 130. However, in certain embodiments, during normal processing, the high resistance substrate can be subjected to an annealing process later. In these embodiments, it may be possible to omit the dedicated annealing process shown in box 260. For this purpose, various annealing processes can be used, such as a furnace (from 300°C to 100°C, from 10 minutes to 60 minutes), rapid thermal annealing (from 1050°C to 1200°C, from 5 seconds to 20 seconds), or a laser annealing process (>1000°C, several tens of nanoseconds).

[0030] Next, as shown in box 270, the high resistance substrate 100 can be processed according to an existing manufacturing process. For example, the high resistance substrate 100 can be processed to form transistors, power devices, optical devices, solar cells, sensors, or other components. By including the low resistance layer 130 in proximity to the bottom surface 102 of the high resistance substrate 100, it becomes possible to clamp the high resistance substrate 100 using a conventional electrostatic chuck.

[0031] After the processing of the high resistance substrate 100 is completed, as shown in box 280, the low resistance layer 130 is processed. In one embodiment, the low resistance layer 130 is removed using conventional wafer thinning techniques. In other embodiments, such as embodiments where vertical transistors are formed, the low resistance layer 130 can be plated or metallized to form one or more electrodes.

[0032] Figures 1A - 1F and 2 show one way to modify a high resistance substrate to be usable with an electrostatic chuck, but other methods are possible.

[0033] For example, in certain embodiments, the high-resistance substrate may initially have an upper sacrificial layer. This sacrificial layer, which has a low resistivity, is used as a hard mask or transfer layer during the patterning process. This upper sacrificial layer can function as the coating described above and may be used as a clamp during the backside ion implantation process to form the low-resistance layer 130.

[0034] In this case, the box 210 in FIG. 2 is optional. Further, the removal of the coating shown in box 250 may also be optional. In other words, the sacrificial layer can serve the role of the coating described above.

[0035] Thus, in the present disclosure, several methods for processing a high-resistance substrate to enable an electrostatic clamp have been described. Further, a high-resistance substrate capable of an electrostatic clamp is also disclosed. The high-resistance substrate includes a low-resistance layer disposed within the substrate. This low-resistance layer can be formed using ion implantation of resistivity-reducing species and may have a resistivity of 1000 Ωcm or less. In some embodiments, the low-resistance layer may have a resistivity of 100 Ωcm or less. Further, the peak concentration (Rp) of the resistivity-reducing species can be disposed at a depth from 2 nanometers to 2 micrometers.

[0036] The embodiments described above in the present application may have many advantages. As described above, high-resistance substrates cannot be properly clamped using electrostatic force. By adding a low-resistance layer in proximity to the bottom surface of the high-resistance substrate, these substrates can be clamped in the same manner as conventional silicon substrates without modifying the electrostatic chuck.

[0037] Furthermore, by incorporating the low-resistance layer, the charge accumulated in the high-resistance substrate during processing can be dissipated to the chuck. Thereby, the possibility of damage can be reduced.

[0038] Finally, the RC time constant of the substrate clamp time and declamp time can be modeled as follows. TIFF0007697039000001.tif17170In the above formula, ρchuck is the resistivity of the dielectric layer of the chuck, d chuck is the thickness of the dielectric layer, ρ wafer is the resistivity of the substrate, d wafer is the thickness of the substrate, and gap is the thickness of the gap between the chuck and the substrate. ρ wafer In a high-resistance substrate with a resistivity of 1E8 Ωcm or more, the second term of the molecule dominates the RC constant and may exceed 100 seconds. By adding a low-resistance layer having a resistivity at least five orders of magnitude lower than that of the substrate, the RC constant can be reduced to less than 0.5 seconds.

[0039] The present disclosure is not limited in scope by the specific embodiments described herein. Indeed, in addition to those described herein, various other embodiments and modifications of the present disclosure will be apparent to those skilled in the art from the foregoing description and the accompanying drawings. Accordingly, such other embodiments and modifications are intended to be included within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation for a particular purpose in a particular environment, those skilled in the art will recognize that its usefulness is not limited thereto, and that the present disclosure can be beneficially implemented in any number of environments for any number of purposes. Accordingly, the following claims are to be construed in view of the full scope and spirit of the present disclosure described herein.

Claims

1. A method for processing a high-resistance substrate, comprising: applying a coating of a low-resistance material to the upper surface of the high-resistance substrate; inverting the high-resistance substrate such that the coating contacts the upper surface of an electrostatic chuck and the high-resistance substrate can be clamped to the electrostatic chuck by the coating; injecting ions into the bottom surface of the high-resistance substrate while clamped to the electrostatic chuck to form a low-resistance layer, wherein the low-resistance layer has a thickness of from 2 nanometers to 3 micrometers; removing the coating such that the high-resistance substrate includes the low-resistance layer proximate to the bottom surface that can be clamped to the electrostatic chuck; clamping the bottom surface to the electrostatic chuck; processing the upper surface of the high-resistance substrate while clamped to the electrostatic chuck; removing the low-resistance layer after the high-resistance substrate has been processed. A method comprising the above steps.

2. The method according to claim 1, wherein the coating comprises amorphous carbon or titanium oxide.

3. The method according to claim 1, wherein the ions reduce the resistivity of the low-resistance layer by at least five orders of magnitude relative to the resistivity of the high-resistance substrate.

4. The method according to claim 1, wherein the ions reduce the resistivity of the low-resistance layer to less than 1000 Ωcm.

5. The method according to claim 4, wherein the ions reduce the resistivity of the low-resistance layer to less than 100 Ωcm.

6. The high-resistance substrate includes a GaAs substrate, a SiC substrate, or a high-resistance silicon substrate. When the high-resistance substrate is a GaAs substrate, the ions include silicon. When the high-resistance substrate is a SiC substrate, the ions include phosphorus, aluminum, or boron. When the high-resistance substrate is a high-resistance silicon substrate, the ions include phosphorus or boron. The method according to claim 1.

7. The implantation is performed using a non-zero tilt angle. The method according to claim 1.

8. The ions are implanted such that the peak concentration of the ions occurs at a depth of less than 500 nanometers. The method according to claim 1.

9. A method for processing a high-resistance substrate, the high-resistance substrate including a sacrificial layer having a low resistivity disposed on an upper surface, implanting ions into a bottom surface of the high-resistance substrate, including inverting the high-resistance substrate such that the sacrificial layer contacts an upper surface of an electrostatic chuck, and clamping the high-resistance substrate to the electrostatic chuck by the sacrificial layer, after the implantation, the high-resistance substrate includes a low-resistance layer adjacent to the bottom surface that can be clamped to the electrostatic chuck, the low-resistance layer having a thickness of from 2 nanometers to 3 micrometers, The processing method further includes clamping the bottom surface to the electrostatic chuck, processing an upper surface of the high-resistance substrate while clamped to the electrostatic chuck, and removing the low-resistance layer after the high-resistance substrate has been processed. A method including.

10. The ions reduce the resistivity of the low-resistance layer by at least five orders of magnitude relative to the resistivity of the high-resistance substrate. The method according to claim 9.

11. The ions reduce the resistivity of the low-resistance layer to less than 1000 Ωcm. The method according to claim 9.

12. The method according to claim 11, wherein the ions reduce the resistivity of the low-resistance layer to less than 100 Ωcm.

13. The method according to claim 9, wherein the implantation is performed using a non-zero tilt angle.

14. The method according to claim 9, wherein the ions are implanted such that the peak concentration of the ions occurs at a depth of less than 500 nanometers.

15. The high-resistance substrate includes a GaAs substrate, a SiC substrate, or a high-resistivity silicon substrate. When the high-resistance substrate is a GaAs substrate, the ions include silicon. When the high-resistance substrate is a SiC substrate, the ions include phosphorus, aluminum, or boron. When the high-resistance substrate is a high-resistivity silicon substrate, the ions include phosphorus or boron. The method according to claim 9.

16. The method according to claim 9, wherein the sacrificial layer is used as a hard mask or a transfer layer during a patterning process.

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