Method of manufacturing a silicon carbide semiconductor device

Abstract

To provide a method of manufacturing a silicon carbide semiconductor device, the method enabling a non-defective product rate to be improved .SOLUTION: A method of manufacturing a silicon carbide semiconductor device comprises: a first step of forming a semiconductor wafer having an epitaxial layer on a starting substrate made of silicon carbide; a second step of forming a mark in a scribe line provided on the semiconductor wafer; a third step of inspecting the epitaxial layer with a crystal defect inspection device thereby detecting crystal defects of the epitaxial layer; a fourth step of forming predetermined element structure on the semiconductor wafer; a fifth step of dicing the semiconductor wafer thereby individualizing the same into semiconductor chips; then a six step of selecting the semiconductor chip in which no crystal defect is detected at the third step, as a non-defective product candidate. A distance between an end of the scribe line recognized by the crystal defect inspection device and an end of the mark in a case where there is no deviation of the scribe line, is equal to or more than 10 μm and equal to or less than 25 μm.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This invention relates to a method for manufacturing a silicon carbide semiconductor device.

Background Art

[0002] Conventionally, when evaluating the reliability of a silicon carbide semiconductor device (semiconductor chip) using silicon carbide (SiC) as a semiconductor material, crystal defects on the surface and inside of a semiconductor wafer (SiC wafer) are detected by a crystal defect inspection device (for example, the SiC wafer defect inspection / review device SICA88 manufactured by Lasertec Corporation), and defective chips among a plurality of semiconductor chips cut and separated from the semiconductor wafer are sorted. Semiconductor chips containing crystal defects detected by the crystal defect inspection device are all regarded as defective chips without exception, regardless of the results of electrical characteristic tests or without performing electrical characteristic tests.

[0003] A conventional method for manufacturing a silicon carbide semiconductor device will be described. FIG. 11 is a flowchart showing an outline of a conventional method for manufacturing a silicon carbide semiconductor device. First, a semiconductor wafer (SiC wafer) using silicon carbide as a semiconductor material is prepared (step S101). The semiconductor wafer is an epitaxial wafer formed by epitaxially growing an epitaxial layer on a starting wafer made of silicon carbide. Next, marks for indicating the positions of crystal defects (coordinates in a direction parallel to the wafer surface) of the semiconductor wafer and the alignment of the manufacturing process are formed on the surface (main surface) of the epitaxial layer of the semiconductor wafer (step S102).

[0004] Next, a crystal defect inspection apparatus detects crystal defects in the epitaxial layer of the semiconductor wafer, and acquires position information and the like of the crystal defects based on the marks formed in the process of step S102 (step S103). In the process of step S103, downfalls and large pits caused by foreign matter contamination and carbon (C) inclusion, triangular defects caused by polytype (crystal polymorphism) inclusion, and Frank-type defects and carrot-type defects caused by threading screw dislocations (TSD) that occur during epitaxial growth of the epitaxial layer are detected.

[0005] Next, various processes for forming a predetermined element structure are performed in each chip region (region that becomes a semiconductor chip) of the semiconductor wafer (step S104). Next, the semiconductor wafer is diced to individualize each chip region of the semiconductor wafer into individual semiconductor chips (SiC chips) (step S105). Next, based on the position information acquired in the process of step S103, semiconductor chips that do not completely contain the crystal defects detected in the process of step S103 are selected as good product (good chip) candidates (step S106). Semiconductor chips that contain even one of the crystal defects detected in the process of step S103 are removed as defective chips.

[0006] Next, for each semiconductor chip selected as a good product candidate in the process of step S106, a predetermined energization test is performed to inspect electrical characteristics (step S107), and based on the result of step S107, it is determined whether the acquired good product standard is satisfied (step S108). The good product standard is the limit values of various characteristics that can ensure a predetermined tolerance and predetermined reliability of the silicon carbide semiconductor device, and is acquired in advance. Thereafter, based on the result of step S108, by selecting semiconductor chips that satisfy the good product standard as good products (good chips) (step S109), the evaluation of the silicon carbide semiconductor device is completed.

[0007] As a method for manufacturing a conventional silicon carbide semiconductor device, in visual inspection, when the size of a chip is larger than the field of view size of a camera and the chip is divided into a plurality of parts for imaging, in order to prevent the occurrence of pseudo defects, a method has been proposed in which an inspection image is cut out from the captured image based on the position of an alignment pattern for visual inspection (see, for example, Patent Document 1 below). Further, as a conventional semiconductor wafer, among first and second scribe lines that are orthogonal to each other, the first scribe line is arranged in a direction parallel to the cleavage direction of the substrate crystal, and an accessory pattern is intensively arranged at a position overlapping with the laser irradiation region of stealth dicing, thereby a semiconductor wafer has been proposed that reduces the occurrence of chipping and cracking (see, for example, Patent Document 2 below).

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0009] FIG. 12 is a top view showing a conventional semiconductor wafer. The semiconductor wafer 150 is provided with a scribe line 161 indicating a cutting position when the semiconductor wafer 150 is cut to individualize semiconductor chips. FIG. 13 is a top view showing the scribe line of the conventional semiconductor wafer. FIG. 13 is an enlarged view of part A of FIG. 12.

[0010] FIG. 14 is a top view showing marks in the scribe line of the conventional semiconductor wafer. FIG. 14 is an enlarged view of part B of FIG. 13. The semiconductor wafer 150 is provided with marks 162 indicating the positions of crystal defects and the alignment of the manufacturing process therein. These marks 162 are provided in the scribe line 161.

[0011] When the crystal defect inspection apparatus detects crystal defects, the crystal defect inspection apparatus is set to recognize the position of the scribe line 161 and not perform inspection there. FIG. 15 is a top view showing the scribe line of a conventional semiconductor wafer and the scribe line recognized by the crystal defect inspection apparatus. However, as shown in FIG. 15, the scribe line 161 provided on the semiconductor wafer 150 and the scribe line 161a recognized by the crystal defect inspection apparatus cannot completely coincide, and a deviation occurs.

[0012] FIG. 16 is a top view when marks in the scribe line of a conventional semiconductor wafer are recognized as defects. When a deviation occurs, the crystal defect inspection apparatus mistakes the mark end portion 163a of the mark 162 for a crystal linear defect called an edge line extending in a direction parallel to the orientation flat of the semiconductor wafer 150 because of their similar shapes, and may misrecognize it as a crystal defect.

[0013] As a result, in the above-described conventional method for manufacturing a silicon carbide semiconductor device, due to this misrecognition, a chip that is originally a good product is determined to be a defective product and removed as a defective chip. Therefore, among the semiconductor chips removed as defective chips in the process of step S106, there are semiconductor chips having electrical characteristics that can be used as good products. Since semiconductor chips that can be used as good products are removed as defective chips in this way, the yield rate decreases, leading to an increase in chip cost.

[0014] An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of improving the yield rate in order to solve the problems caused by the above-described conventional technology.

Means for Solving the Problems

[0015] To solve the above problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step of forming a semiconductor wafer by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide is performed. Next, a second step of forming a mark in a 1st scribe line provided in the semiconductor wafer is performed. Next, a third step of inspecting the epitaxial layer by a crystal defect inspection apparatus to detect crystal defects in the epitaxial layer is performed. Next, a fourth step of forming a predetermined element structure in the semiconductor wafer is performed. Next, after the fourth step, a fifth step of dicing the semiconductor wafer into individual semiconductor chips is performed. Next, a sixth step of selecting, as good product candidates, the semiconductor chips in which no crystal defects were detected in the third step is performed. The 2nd scribe line n and the 1st scribe line and When there is no deviation, the distance to the end of the and the end of the second scribe line mark is set to be 10 μm or more and 25 μm or less.

[0016] Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is, in the above-described invention, front the 2nd width of the scribe line is made larger than the width of the 1st scribe line provided in the semiconductor wafer.

[0017] Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is, in the above-described invention, front the 2nd end of the scribe line is located at the channel stopper portion of the semiconductor chip.

[0018] Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is, in the above-described invention, front the 2nd width of the scribe line is the1st It is the same as the width of the scribe line.

[0019] Also, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the 1st scribe lines are provided in a lattice pattern in the <11-20> direction and the <1-100> direction, the second scribe line n and the 1st distance between the end of the scribe line when there is no deviation in the scribe line and the end of the mark is set to be 10 μm or more and 25 μm or less. the end of the second scribe line in the <11-20> direction It is characterized in that.

[0021] According to the above-described invention, the distance between the end of the scribe line recognized by the crystal defect inspection device and the end of the mark when there is no deviation in the scribe line is set to be 10 μm or more and 25 μm or less. For example, the width of the scribe line recognized by the crystal defect inspection device is made wider than the width of the scribe line provided on the semiconductor wafer. For example, the size of the mark is made smaller than the width of the scribe line provided on the semiconductor wafer. Also, the mark is provided only on the scribe line in the <1-100> direction, or the ratio of the mark existing on the scribe line in the <1-100> direction is increased. As a result, even if the scribe line recognized by the crystal defect inspection device is deviated from the scribe line provided on the semiconductor wafer, the crystal defect inspection device does not misrecognize the mark as a crystal defect and remove the semiconductor chip in which the crystal defect is detected as a defective chip. In this way, since the semiconductor chips that have been conventionally made defective due to over-detection can be made non-defective, it is possible to improve the yield rate and reduce the chip cost accordingly.

Advantages of the Invention

[0022] According to the method for manufacturing a silicon carbide semiconductor device according to the present invention, there is an effect that the yield rate can be improved and the chip cost can be reduced.

Brief Description of the Drawings

[0023]

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Figure 16

Embodiments for Carrying Out the Invention

[0024] Hereinafter, with reference to the accompanying drawings, preferred embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in a layer or region preceded by n or p, it means that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layer or region to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. Also, in this specification, in the notation of Miller indices, "-" means a bar attached to the immediately following index, and a negative index is represented by attaching "-" before the index. And the description of the same or equivalent shall include within 5% in consideration of variations in manufacturing.

[0025] (Embodiment 1) The method for manufacturing a silicon carbide semiconductor device according to Embodiment 1 is suitable for, for example, a Schottky Barrier Diode (SBD) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor having an insulating gate composed of a three-layer structure of metal - oxide film - semiconductor), but may also be applied to a pin (p-intrinsic-n) diode or an IGBT (Insulated Gate Bipolar Transistor: an insulated gate type bipolar transistor).

[0026] Here, a vertical n-channel MOSFET with a trench gate structure is shown for a silicon carbide semiconductor device fabricated (manufactured) using silicon carbide (SiC). FIG. 1 is a plan view showing a state of a semiconductor wafer as viewed from the front side according to a manufacturing method of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a plan view showing a layout of a semiconductor chip cut from the semiconductor wafer of FIG. 1 as viewed from the front side. FIG. 2 shows a state after cutting of one chip region 51 of the semiconductor wafer 50 of FIG. 1. FIG. 3 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 1.

[0027] The semiconductor wafer 50 is an n-type starting wafer made of silicon carbide (see FIG. 3, the part that becomes the n-type starting substrate 31 after dicing), and an epitaxial layer (see FIG. 3, the part that becomes the epitaxial layer 35 after dicing) is epitaxially grown thereon. + type starting wafer (see FIG. 3, the part that becomes the n-type starting substrate 31 after dicing), and an epitaxial layer (see FIG. 3, the part that becomes the epitaxial layer 35 after dicing) is epitaxially grown thereon. + type starting wafer (see FIG. 3, the part that becomes the n-type starting substrate 31 after dicing), and an epitaxial layer (see FIG. 3, the part that becomes the epitaxial layer 35 after dicing) is epitaxially grown thereon.

[0028] The semiconductor wafer 50 may have, for example, an orientation flat (a linear notch provided at a part of the edge end) 54 or a notch (a V-shaped notch provided at a part of the edge end: not shown) indicating the plane orientation. Each chip region 51 of the semiconductor wafer 50 is cut (diced) along a scribe line 61 to be separated into individual semiconductor chips 30. All the semiconductor chips 30 separated from the same semiconductor wafer 50 have the same epitaxial layer 35 and p-type epitaxial layer 34 (see FIG. 3), and have the same element structure (here, a trench gate structure: see FIG. 3) formed in the same process.

[0029] The chip regions 51 have a substantially rectangular planar shape and are arranged in a matrix at substantially the center of the semiconductor wafer 50. The scribe lines 61 surround the chip regions 51 in a grid pattern. The scribe lines 61 are linear regions formed on the main surface of the semiconductor wafer 50 (the surface on the epitaxial layer 33 side in FIG. 3). Marks (see FIG. 5) for specifying positions (coordinates) in a direction parallel to the surface of the semiconductor wafer 50 are formed in the scribe lines 61. The marks are reference marks for specifying the positions of the respective chip regions 51 and the positions of crystal defects detected in the process of step S3 in FIG. 4 described later.

[0030] The marks are, for example, convex or concave portions having a predetermined planar shape (e.g., a cross shape) formed by etching on the main surface of the semiconductor wafer 50 within the scribe lines 61. As the marks, alignment marks for aligning the respective parts of the element structure formed in the chip regions 51 may be used.

[0031] The silicon carbide semiconductor device 10 according to Embodiment 1 shown in FIG. 2 is an n-channel vertical MOSFET having a trench gate structure on the front surface side of the semiconductor chip 30 made of silicon carbide, for example, on the (0001) plane (Si plane) in the active region 41. The active region 41 is a region through which the main current (drift current) flows when the MOSFET is in the on state, and a plurality of unit cells (functional units of the element) having the same structure of the MOSFET are arranged adjacent to each other. FIG. 3 shows one unit cell of the MOSFET. The active region 41 is arranged, for example, at substantially the center of the semiconductor chip 30 and is surrounded by the edge termination region 42.

[0032] The edge termination region 42 is the region between the active region 41 and the end of the semiconductor chip 30. The edge termination region 42 has a function of relaxing the electric field on the front side of the semiconductor chip 30 and maintaining the breakdown voltage. A breakdown voltage structure (not shown) such as a field limiting ring (FLR), a junction termination extension (JTE) structure, or a guard ring is disposed in the edge termination region 42. The breakdown voltage is the limit voltage at which the leakage current does not increase excessively and the silicon carbide semiconductor device 10 does not malfunction or break down.

[0033] The trench gate structure is composed of a p-type base region 4, an n + type source region 5, a p ++ type contact region 6, a trench 7, a gate insulating film 8, and a gate electrode 9. The semiconductor chip 30 is formed by epitaxially growing n + type buffer region 2a, an n - type drift region 2b, and p-type base region 4 in this order as epitaxial layers 32 to 34 on the front surface of an n n + type source region 5 type starting substrate 31. The main surface on one side of the semiconductor chip 30 is defined as the front surface, and the main surface on the side of the n + type starting substrate 31 (the back surface of the n+-type starting substrate 31) is defined as the back surface.

[0034] n + type starting substrate 31 is an n + type drain region 1. The n-type buffer region 2a has a function of preventing holes (positive holes) generated at the pn junction interface between the p-type base region 4 and the n - type drift region 2b from recombining in the n-type buffer region 2a and reaching the n + type starting substrate 31. Further, the n-type buffer region 2a has a function of suppressing the expansion of stacking defects in the epitaxial layers 33 and 34 due to the propagation of dislocations from the n + type starting substrate 31 to the epitaxial layer 35. The n-type buffer region 2a may not be provided.

[0035] n - The n-type drift region 2b is provided in contact with these regions between the p-type base region 4 and the n-type buffer region 2a (or the n-type drain region 1 if the n-type buffer region 2a is not provided). Between the p-type base region 4 and the n + -type drift region 2b, an n-type current diffusion region 3 and p - -type regions 21 and 22 may be provided. In this case, the n + -type drift region 2b is the portion of the n - -type epitaxial layer 33 excluding the n-type current diffusion region 3 and the p - -type regions 21 and 22. The n-type current diffusion region 3 and the p + -type regions 21 and 22 are provided at a position deeper than the bottom surface of the trench 7 on the n + -type drain region 1 side. +

[0036] The n-type current diffusion region 3 is a so-called current spreading layer (CSL: Current Spreading Layer) that reduces the spreading resistance of carriers. The p + -type regions 21 and 22 have a function of relaxing the electric field applied to the gate insulating film 8 on the bottom surface of the trench 7. The p + -type region 21 is provided away from the p-type base region 4 and faces the bottom surface of the trench 7 in the depth direction. The p + -type region 21 may reach the bottom surface of the trench 7. The p + -type region 22 is provided between adjacent trenches 7, away from the p + -type region 21 and the trench 7, and is in contact with the p-type base region 4.

[0037] The p-type base region 4 is provided between the front surface of the semiconductor chip 30 and the n - -type drift region 2b. The p-type base region 4 is the portion of the p-type epitaxial layer 34 excluding the n + -type source region 5 and the p ++ -type contact region 6. The n + -type source region 5 and the p ++The p-type contact regions 6 are selectively provided between the front surface of the semiconductor chip 30 and the p-type base region 4, respectively. n + type source regions 5 and p ++ The p-type contact regions 6 are in contact with the p-type base region 4 and make ohmic contact with the ohmic electrode 13 in the contact hole of the interlayer insulating film 11 described later.

[0038] p ++ The p-type contact regions 6 may not be provided. p ++ When the p-type contact regions 6 are not provided, instead of the p-type contact regions 6, the p-type base region 4 makes ohmic contact with the ohmic electrode 13. These n-type current diffusion regions 3, p ++ type regions 21, 22, n + type source regions 5 and p + type contact regions 6 are diffusion regions formed by ion implantation and are selectively provided inside the epitaxial layer 35. The trench 7 penetrates the n ++ type source regions 5 and the p-type base region 4 and reaches the n-type current diffusion region 3 (when the n-type current diffusion region 3 is not provided, the n + type drift region 2b). -

[0039] A gate electrode 9 is provided inside the trench 7 via a gate insulating film 8. The interlayer insulating film 11 is provided on the front surface of the semiconductor chip 30 and covers the gate electrode 9. A barrier metal 12 for preventing the diffusion of metal atoms, for example, from the front surface electrode 14 side to the gate electrode 9 side may be provided on the entire surface between the interlayer insulating film 11 and the front surface electrode 14 described later. The ohmic electrode 13 is a silicide film provided on the front surface of the semiconductor chip 30 in the contact hole of the interlayer insulating film 11. The ohmic electrode 13 is electrically connected to the p-type base region 4, n + type source regions 5 and p ++ type contact regions 6.

[0040] ​The front surface electrode 14 is provided on substantially the entire front surface of the semiconductor chip 30 in the active region 41 so as to fill the contact hole in the interlayer insulating film 11. The front surface electrode 14 is electrically connected to the p-type base region 4, the n + -type source region 5, and the p ++ -type contact region 6 via the ohmic electrode 13. The barrier metal 12, the ohmic electrode 13, and the front surface electrode 14 function as source electrodes. The back surface electrode 15 is provided on the entire back surface of the semiconductor chip 30, for example, the <000-1> plane (C plane), (the back surface of the n + -type starting substrate 31), and is electrically connected to the n + -type drain region 1. The back surface electrode 15 functions as a drain electrode.

[0041] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 1) Next, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 1 will be described. FIG. 4 is a flowchart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to Embodiment 1.

[0042] First, a semiconductor wafer (SiC wafer) 50 using silicon carbide as a semiconductor material is formed (Step S1: First step). The semiconductor wafer 50 is formed by epitaxially growing an epitaxial layer 35 on an n + -type starting substrate 31. In the process of Step S1, a starting wafer 55 made of silicon carbide may be prepared to produce the semiconductor wafer 50, or the semiconductor wafer 50 itself may be purchased.

[0043] Next, a mark is formed in the scribe line on the main surface (the surface on the epitaxial layer 35 side) of the semiconductor wafer 50 (Step S2: Second step). The scribe line, also called a dicing line, is a linear region formed on the main surface of the semiconductor wafer 50 (the surface on the epitaxial layer 35 side in FIG. 3), and indicates the cutting position when individualizing semiconductor chips. For example, the width of the scribe line is about 100 μm.

[0044] Next, the semiconductor wafer is inspected using a crystal defect inspection device. 50 The type, size (length, surface area, etc.) and position information of crystal defects on the surface and inside of the epitaxial layer 35 are detected and obtained (step S3: third process). The crystal defect inspection device is, for example, a SiC wafer defect inspection / review device SICA88 manufactured by Lasertec Corporation. The crystal defects detected in the process of step S3 are foreign matter defects, triangular defects and extended defects formed in the epitaxial layer. The size and position information of these crystal defects are obtained based on the marks formed in the process of step S2, for example.

[0045] Here, Fig. 5 is a top view showing the scribe lines of the semiconductor wafer according to the first embodiment and the scribe lines recognized by the crystal defect inspection device. In Fig. 5, the scribe lines 61 shown by thin lines are the scribe lines provided on the semiconductor wafer 50, the scribe lines 61a shown by dotted lines are the scribe lines recognized by the conventional crystal defect inspection device, and the scribe lines 61b shown by thick lines are the scribe lines recognized by the crystal defect inspection device of the first embodiment (the same applies to Fig. 6).

[0046] Here, since most of the scribe line 61 is cut off by dicing and no current flows through the remaining portion, there is no problem even if crystal defects exist within the scribe line 61. For this reason, the position of the scribe line 61 is set in advance so that the crystal defect inspection device does not inspect for crystal defects within the scribe line 61. The scribe lines 61a and 61b recognized by the crystal defect inspection device are the positions of the scribe lines set in the crystal defect inspection device. Also, the mark 62a indicated by the dashed dotted line is the position of the mark 62 provided on the scribe line 61 in the crystal defect inspection device when there is no misalignment of the scribe line.

[0047] In Embodiment 1, the distance h1 between the end of the scribe line 61b recognized by the crystal defect inspection apparatus and the end of the mark 62a is set to be 10 μm or more and 25 μm or less. The distance h1 between the end of the scribe line 61b recognized by the crystal defect inspection apparatus and the end of the mark 62a is half of the difference between the width of the scribe line 61b and the width of the mark 62. Here, the width of the scribe line 61a recognized by the conventional crystal defect inspection apparatus was the same as the width of the scribe line 61 provided on the semiconductor wafer 50. In Embodiment 1, the width of the scribe line 61b recognized by the crystal defect inspection apparatus is made wider than the width of the scribe line 61 provided on the semiconductor wafer 50, and the distance h1 between the end of the scribe line 61b recognized by the crystal defect inspection apparatus and the end of the mark 62a is set to be 10 μm or more and 25 μm or less.

[0048] For example, by expanding the scribe line 61b by L1 in the outer direction (the direction orthogonal to the scribe line 61b) as indicated by the arrow in FIG. 5, the distance h1 from the end of the scribe line 61b recognized by the crystal defect inspection apparatus to the end of the mark 62a is adjusted. The width of the scribe line 61b recognized by the crystal defect inspection apparatus can be changed according to the settings of the crystal defect inspection apparatus. The distance h1 from the end of the scribe line 61b recognized by the crystal defect inspection apparatus to the end of the mark 62a is, for example, 10 μm or more and 25 μm or less, preferably 15 μm or more and 20 μm or less. This value is based on the fact that the deviation between the scribe line 61 provided on the semiconductor wafer 50 and the scribe line 61b recognized by the crystal defect inspection apparatus is within 10 μm. Also, if it is made larger than 25 μm, the crystal defects that should originally be detected will not be detected.

[0049] Here, in the silicon carbide semiconductor device, a channel stopper portion 43 is provided at the outermost periphery of the edge termination region 42 (see FIG. 2). Since no current flows outside the channel stopper portion 43, even if there are crystal defects, they do not affect the device characteristics such as the on-voltage. Therefore, the position of the end of the scribe line 61b recognized by the crystal defect inspection device may be extended to the channel stopper portion 43. In this case, the end of the scribe line 61b recognized by the crystal defect inspection device is located at the channel stopper portion 43 of the semiconductor chip. The width L1 of the extension to the outside is preferably equal to or less than the distance L2 (see FIG. 2) from the chip end to the end on the active region 41 side of the channel stopper portion 43. This distance L2 includes the distance L3 (not shown) from the chip end to the end on the edge termination region 42 side of the channel stopper portion 43 and the width of the channel stopper portion 43. Therefore, by increasing the distance L3 and the width of the channel stopper portion 43, the distance L2 can be increased, and the width L1 of the extension to the outside can be increased.

[0050] By doing so, even if the scribe line 61b recognized by the crystal defect inspection device is misaligned with the scribe line 61 provided on the semiconductor wafer 50, the mark 62 will enter the scribe line 61b recognized by the crystal defect inspection device. Therefore, it is possible to prevent the crystal defect inspection device from misrecognizing the mark 62 as a crystal defect.

[0051] Also, the scribe line recognized by the crystal defect inspection device may remain the conventional scribe line 61a and the mark 62 may be made smaller. FIG. 6 is a top view showing the mark in the scribe line of the semiconductor wafer according to Embodiment 1. As shown in FIG. 6, by making the mark 62 formed in step S2 smaller than the conventional size, the size of the mark 62 is made smaller than the width of the scribe line 61. In this way, in Embodiment 1, the width of the scribe line 61a recognized by the crystal defect inspection device is made larger than the size of the mark 62.

[0052] For example, if the distance between the scribe line 61 and the end of the mark 62 is h2, the mark 62 is sized to be separated from the end of the scribe line 61 by h2 or more inside. For example, since h2 is within 10 μm, the mark 62 is sized to be separated from the end of the scribe line 61 by 10 μm or more inside. Also, if the mark 62 is made too small, alignment becomes difficult, so it is preferable that the distance from the end of the scribe line 61 to the end of the mark 62 is 25 μm or less.

[0053] By doing so, even if there is a deviation between the scribe line 61 and the scribe line 61a recognized by the crystal defect inspection apparatus, the mark 62 within the scribe line 61 will enter within the scribe line 61a recognized by the crystal defect inspection apparatus. For this reason, even when the width of the scribe line 61a recognized by the crystal defect inspection apparatus is the same as the width of the scribe line 61 provided on the semiconductor wafer 50, it is possible to prevent the crystal defect inspection apparatus from misrecognizing the mark 62 as a crystal defect.

[0054] Also, FIG. 7 is a top view showing the position of the mark within the scribe line of the semiconductor wafer according to Embodiment 1. The scribe line 61 is provided in the <11-20> direction in the direction of the orientation flat 54 and in the <1-100> direction orthogonal to the orientation flat 54. In Embodiment 1, the mark 62 may be provided only on the scribe line 61 in the <1-100> direction (region A in FIG. 7), or the ratio of the mark 62 existing on the scribe line 61 in the <1-100> direction may be increased.

[0055] FIG. 8 is a top view showing marks and linear crystal defects in a scribe line of a semiconductor wafer according to Embodiment 1. The linear crystal defect 64 grows linearly in the <11-20> direction in the direction of the orientation flat 54. For this reason, the crystal defect inspection apparatus recognizes the linearly growing rod-shaped crystal defect 64 as a rod-shaped crystal defect extending in the <11-20> direction. Here, when the scribe line 61 in the <11-20> direction and the scribe line 61b recognized by the crystal defect inspection apparatus are displaced, the mark end portion 63a has a rod-shaped shape extending in the <11-20> direction. Since this shape is similar to the linear crystal defect 64, the crystal defect inspection apparatus misrecognizes it as the linear crystal defect 64. On the other hand, when the scribe line 61 in the <1-100> direction and the scribe line 61b recognized by the crystal defect inspection apparatus are displaced, the mark end portion 63b has a rod-shaped shape extending in the <1-100> direction, and the shape is different from the linear crystal defect 64, so the crystal defect inspection apparatus does not recognize it as a linear crystal defect.

[0056] For this reason, by providing the mark 62 only on the scribe line 61 in the <1-100> direction (region A in FIG. 7) or increasing the ratio of the mark 62 existing on the scribe line 61 in the <1-100> direction, it is possible to reduce the crystal defect inspection apparatus from misrecognizing the mark 62 as a crystal defect. At this time, the configuration in which the mark 62 is provided only on the scribe line 61 in the <1-100> direction includes a configuration in which the mark 62 is provided at the intersection of the scribe line 61 in the <11-20> direction and the scribe line 61 in the <1-100> direction.

[0057] As described above, since the mark 62 in the scribe line 61 in the <1-100> direction is not misrecognized as a crystal defect, as shown in FIG. 5, it is not necessary to widen the width of the scribe line 61b recognized by the crystal defect inspection apparatus. For example, when widening the width of the scribe line 61 provided on the semiconductor wafer 50, only the width of the scribe line 61b recognized by the crystal defect inspection apparatus in the <11-20> direction may be widened to be wider than the width of the scribe line 61 provided on the semiconductor wafer 50.

[0058] In addition, it is also possible to combine making the width of the scribe line 61b recognized by the crystal defect inspection apparatus larger than the size of the mark 62 and making the mark 62 exist only on the scribe line 61 in the <1-100> direction or increasing the ratio of the mark 62 existing on the scribe line 61 in the <1-100> direction. For example, it is possible to arrange the mark 62, which is reduced to a size less than half of the conventional size, only on the scribe line 61 in the <1-100> direction.

[0059] In addition, although the mark 62 has a square shape as shown in FIG. 5 and the like, by making this shape a shape without a line parallel to the scribe line 61 such as a rhombus, false detection by the crystal defect inspection apparatus can be further reduced.

[0060] Next, various processes for forming a predetermined element structure (see FIG. 3) are performed in each chip region of the semiconductor wafer 50 (step S4: fourth step). An outline of the various processes is shown below. First, an n-type epitaxial layer 32, an n - -type epitaxial layer 33, and an n-type current diffusion region 3 are selectively formed in the epitaxial layer 35 by photolithography and ion implantation. Next, epitaxial growth By, p + -type regions 21 and 22 are selectively formed in the n-type current diffusion region 3. Note that the n-type current diffusion region 3 and the p + -type region 22 may be formed by multiple epitaxial growths and ion implantations.

[0061] Next, a p-type base region 4 doped with a p-type impurity such as aluminum is epitaxially grown on the surface of the n-type current diffusion region 3. Next, a process of forming an ion implantation mask by photolithography and etching, ion implantation using this ion implantation mask, and removal of the ion implantation mask is repeated under different ion implantation conditions to form an n + -type source region 5 and a p ++ -type contact region 6 on the surface layer of the p-type base region 4.

[0062] Next, a heat treatment (annealing) is performed to, for example, activate the p + -type regions 21, 22, the n + -type source region 5, and the p ++ -type contact region 6. As described above, each ion implantation region may be activated collectively by a single heat treatment, or each heat treatment may be performed every time ion implantation is carried out for activation.

[0063] Next, on the surface of the p-type base region 4 (i.e., the surface of the n + -type source region 5 and the p ++ -type contact region 6), a trench 7 that penetrates the n from -type source region 5 and the p-type base region 4 and reaches the n-type current diffusion region 3 is formed by photolithography and etching. The bottom of the trench 7 reaches the p + -type region 21. +

[0064] Next, a gate insulating film 8 is formed along the surfaces of the n + -type source region 5 and the p ++ -type contact region 6, the bottom and side walls of the trench 7. Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms (P) is formed on the gate insulating film 8. This polycrystalline silicon layer is formed so as to fill the trench 7. By patterning this polycrystalline silicon layer and leaving it inside the trench 7, a gate electrode 9 is formed.

[0065] Next, an interlayer insulating film 11 is formed so as to cover the gate insulating film 8 and the gate electrode 9. By patterning and selectively removing the interlayer insulating film 11 and the gate insulating film 8, a contact hole is formed to expose the n + -type source region 5 and the p ++ -type contact region 6. Thereafter, a heat treatment (reflow) is performed to planarize the interlayer insulating film 11.

[0066] Next, a conductive film that will become the ohmic electrode 13 is formed within the contact hole and on the interlayer insulating film 11. This conductive film is selectively removed, leaving the ohmic electrode 13 only, for example, within the contact hole.

[0067] Next, an + n-type drain region back surface electrode 15 is formed on the back surface of 1. Next, for example, by sputtering, a front surface electrode 14 is formed so as to cover the ohmic electrode 13 and the interlayer insulating film 11. Also, a barrier metal 12 may be formed between the front surface electrode 14 and the interlayer insulating film 11. Through the above processes, a predetermined element structure is formed in each chip region.

[0068] Next, the semiconductor wafer 50 is cut (diced) to individualize each chip region of the semiconductor wafer 50 into individual semiconductor chips 30 (Step S5: Fifth step). Next, based on the information obtained in the process of Step S3, it is determined whether a crystal defect is detected by inspection with a crystal defect inspection apparatus (Step S6: Sixth step). If no crystal defect is included, it is determined to be normal (Step S6: No). If a crystal defect is included, it is determined to be abnormal (Step S6: Yes) and discarded as a defective chip (Step S9).

[0069] Next, for each semiconductor chip that does not include a crystal defect in the process of Step S6, a predetermined energization test is performed on each to inspect the electrical characteristics (Step S7). In Step S7, in order to compare with the non-defective product standard in the process of Step S8 described later, the same energization test as when the non-defective product standard is obtained is performed to acquire the electrical characteristics. The non-defective product standard is the limit values (upper limit value, lower limit value, or both) of various characteristics that can ensure the predetermined withstand capacity and predetermined reliability of the silicon carbide semiconductor device 10, and is set under the strictest conditions among all the results obtained by performing, for example, one or more tests for measuring the electrical characteristics for withstand capacity evaluation and one or more tests for reliability evaluation as preliminary tests.

[0070] When setting the acceptable product standard with the leakage current value (reverse recovery current Ir in the case of SBD, current value of drain current Idss in the case of MOSFET), the electrical characteristics for the tolerance evaluation are, for example, the forward surge current tolerance (IFSM tolerance), reverse recovery tolerance, avalanche tolerance, reverse bias safety operation area (RBSOA), and the safety operation area at the time of short-circuit current interruption (SCSOA). In this case, the upper limit value of the acceptable product standard is the leakage current value when it is rated.

[0071] Also, when setting the acceptable product standard with the leakage current value, the electrical characteristics for the tolerance evaluation are, for example, the forward surge current tolerance during continuous conduction, continuous conduction life, reverse recovery tolerance during continuous conduction, avalanche tolerance during continuous conduction, RBSOA during continuous conduction, and SCSOA during continuous conduction. In this case, the acceptable product standard is the range of the leakage current value when the variation amount from the design values of these electrical characteristics is equal to or less than a predetermined ratio (for example, 20%). In the case of MOSFET, further, when setting the acceptable product standard with the leakage current value, the electrical characteristics for the tolerance evaluation are the dielectric breakdown tolerance of the gate insulating film.

[0072] The dielectric breakdown tolerance of the gate insulating film is, for example, the time zero dielectric breakdown (TZDB) tolerance, the time-dependent dielectric breakdown (TDDB) tolerance by applying a gate voltage in a state where the drain and source are grounded, and the time-dependent dielectric breakdown (DTDDB) tolerance by applying a predetermined voltage (for example, 1200V) to the drain and applying a gate voltage in a state where the source is grounded. In this case, the acceptable product standard is the range of the leakage current value (current value of drain current Idss) when the variation amount from the design value of the dielectric breakdown tolerance of the gate insulating film 8 is equal to or less than a predetermined ratio (for example, 20%).

[0073] When the acceptable standard is set based on the leakage current value, the tests for reliability evaluation are, for example, a high-temperature and high-voltage application test for evaluating electrical characteristics by applying a high voltage at high temperature, a high-temperature, high-humidity, and high-voltage application test for evaluating electrical characteristics by applying a high voltage under high-temperature and high-humidity conditions, a power cycle test for evaluating the operating life due to thermal fatigue by intermittently energizing and repeatedly alternating self-heating and cooling, and a low-temperature and high-voltage application test for evaluating electrical characteristics by applying a high voltage at low temperature. In this case, the acceptable standard is the range of leakage current values when the amount of variation from the design values of the electrical characteristics obtained in these tests is equal to or less than a predetermined ratio (e.g., 20%).

[0074] Although the explanation is omitted here, in addition to the tests for the above-mentioned tolerance evaluation and reliability evaluation, various other tests are performed to confirm or evaluate conditions that do not affect the tolerance or reliability. If there is no problem in performing these other tests in the state of the semiconductor wafer, they may be performed at the timing after the process of step S5 and before the process of step S6, or may be performed on the semiconductor chip 30 after the process of step S6. In step S7, tests that are difficult to perform in the state of the semiconductor wafer 50 or tests that take a long time to perform in the state of the semiconductor wafer 50, such as when heating or cooling until a predetermined temperature is reached, may be performed.

[0075] Next, based on the result of step S7 and the acceptable standard obtained in advance, the standard determination of the semiconductor chip 30 as a candidate for acceptable products is performed (step S8). In the process of step S8, one acceptable standard is applied to all the semiconductor chips 30 as candidates for acceptable products. Thereby, the manufacturing of the silicon carbide semiconductor device 10 is completed.

[0076] As described above, according to Embodiment 1, the distance between the end of the scribe line and the end of the mark recognized by the crystal defect inspection apparatus is set to be 10 μm or more and 25 μm or less. For example, the width of the scribe line recognized by the crystal defect inspection apparatus is made wider than the width of the scribe line provided on the semiconductor wafer. For example, the size of the mark is made smaller than the width of the scribe line provided on the semiconductor wafer. Further, the mark is provided only on the scribe line in the <1-100> direction or the ratio of the mark existing on the scribe line in the <1-100> direction is increased. Thereby, even if the scribe line recognized by the crystal defect inspection apparatus is displaced from the scribe line provided on the semiconductor wafer, the crystal defect inspection apparatus does not misrecognize the mark as a crystal defect, and a semiconductor chip in which the crystal defect is detected is not removed as a defective chip. In this way, since semiconductor chips that have been conventionally regarded as defective due to over-detection can be made non-defective, it is possible to improve the yield rate and reduce the chip cost accordingly.

[0077] (Embodiment 2) Since the structure of the silicon carbide semiconductor device according to Embodiment 2 is the same as that of Embodiment 1 (FIG. 3), the description thereof is omitted. Further, in the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2, Steps S2 and S3 are different from the flowchart (FIG. 4) showing the outline of the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1. Therefore, only Steps S2 and S3 will be described.

[0078] In Embodiment 2, in Step S2, a mark 62 is formed in a dedicated chip arrangement region or an invalid region 53 on the main surface (the surface on the epitaxial layer 35 side) of the semiconductor wafer 50. FIGS. 9 and 10 are top views showing the positions of the marks in the semiconductor wafer according to Embodiment 2. As shown in FIGS. 9 and 10, in Embodiment 2, the mark 62 is arranged in a region outside the scribe line 61. That is, the mark 62 is not arranged within the scribe line 61.

[0079] FIG. 9 is a top view when the mark 62 is arranged in a dedicated chip placement area. Here, the dedicated chip placement area is an area within the chip area of the semiconductor wafer 50 where the mark 62 is formed and which does not become the semiconductor chip 30. The mark 62 is arranged at least at three positions, preferably five positions, for use in alignment. In FIG. 9, the mark 62 is arranged in a cross shape, but it may also be arranged in a square shape or otherwise.

[0080] Also, on the semiconductor wafer 50, a PCM (Process Control Monitor) is formed in the wafer surface where the device is formed in order to perform management, confirmation, inspection, etc. in each step of the device manufacturing process. Since the area (PCM chip) where the PCM is formed does not become the semiconductor chip 30 to be a product, it is preferable to use the dedicated chip placement area as the PCM chip. By doing so, it is possible to avoid reducing the number of semiconductor chips 30 manufactured from the semiconductor wafer due to the dedicated chip placement area.

[0081] Here, when arranged in the dedicated chip placement area, by preventing the crystal defect inspection device from inspecting the dedicated chip placement area, the crystal defect inspection device can be made not to recognize the mark 62 as a crystal defect. Also, when arranged in the PCM chip, the crystal defect inspection device recognizes the mark 62 as a crystal defect, but since the PCM chip is used to detect the characteristics of the product and does not become a product, there is no problem.

[0082] FIG. 10 is a top view when the mark 62 is arranged in the invalid area 53. The invalid area 53 is a portion between the outermost chip area 51 of the semiconductor wafer 50 and the end of the semiconductor wafer 50 that is not used as the semiconductor chip 30. By arranging the mark 62 in the invalid area 53, it is possible to avoid reducing the number of semiconductor chips 30 manufactured from the semiconductor wafer 50. Also, the dedicated chip placement area within the chip area 51 and the outer peripheral invalid area 53 may be combined and arranged, for example, in an X shape. However, when provided in the outer peripheral invalid area 53, it is necessary not to expose the mark 62 too much to the outside.

[0083] As described above, in the second embodiment, the mark 62 is formed in the dedicated chip placement area or the invalid area 53. Therefore, even if the scribe line 61a recognized by the crystal defect inspection apparatus is displaced from the scribe line 61 provided on the semiconductor wafer 50, the mark 62 will not be misrecognized as a crystal defect. For this reason, the crystal defect inspection apparatus will not misrecognize the mark 62 as a crystal defect and remove it as a defective chip. Thus, chips that were previously over-detected as defective can be made good products, improving the yield rate and reducing the associated chip cost.

[0084] Also, in the second embodiment, in step S2, the inspection can be performed by the crystal defect inspection apparatus without changing the width of the scribe line 61a recognized by the crystal defect inspection apparatus. This is because the mark 62 is not within the scribe line 61. Therefore, there is no need to change the width of the scribe line 61a recognized by the crystal defect inspection apparatus, and it is applicable to a crystal defect inspection apparatus whose width cannot be changed by setting.

[0085] As described above, according to the second embodiment, a mark is formed in the dedicated chip placement area or the invalid area on the main surface of the semiconductor wafer. Thereby, even if the scribe line recognized by the crystal defect inspection apparatus is displaced from the scribe line provided on the semiconductor wafer, the crystal defect inspection apparatus will not misrecognize the mark as a crystal defect and remove it as a defective chip. Thus, chips that were previously over-detected as defective can be made good products, improving the yield rate and reducing the associated chip cost.

[0086] (Effects of Embodiments 1 and 2) As a crystal defect inspection device, when a chip determined to have crystal defects using a SICA device was visually inspected, it was found that crystal defects did not exist in about 30% of the chips. These about 30% of the chips are those in which the SICA device misrecognized the marks as linear crystal defects. Therefore, in the manufacturing method according to the embodiment, since misrecognition by the SICA device can be almost eliminated, about 30% of the chips determined to be defective by the SICA device can be made into non-defective products, and the non-defective product rate can be improved.

[0087] As described above, the present invention can be variously modified without departing from the gist of the present invention. In each of the above-described embodiments, for example, the dimensions, impurity concentrations, etc. of each part are variously set according to required specifications and the like. Further, in each of the above-described embodiments, a MOSFET has been described as an example, but each embodiment is also applicable to an SBD. Further, in each of the above-described embodiments, the case of SiC has been described, but each embodiment is also applicable to GaN. Further, in each embodiment, the first conductivity type is an n-type and the second conductivity type is a p-type, but the present invention also holds true when the first conductivity type is a p-type and the second conductivity type is an n-type.

Industrial Applicability

[0088] As described above, the manufacturing method of the silicon carbide semiconductor device according to the present invention is useful when mass-producing semiconductor chips (silicon carbide semiconductor devices) from 6-inch semiconductor wafers, and is particularly suitable for the manufacture of SBDs and MOSFETs.

Explanation of Reference Numerals

[0089] 1 n + Type drain region 2a n-type buffer region 2b n - Type drift region 3 n-type current diffusion region 4 p-type base region 5 n + Type source region 6 p ++ Type contact region 7 Trench 8 Gate insulating film 9 gate electrode 10 silicon carbide semiconductor device 11 interlayer insulating film 12 barrier metal 13 ohmic electrode 14 front surface electrode 15 back surface electrode 21, 22 p + type region 30 semiconductor chip 31, 55 n + type starting substrate 32 n-type epitaxial layer 33 n - type epitaxial layer 34 p-type epitaxial layer 35 epitaxial layer 41 active region 42 edge termination region 43 channel stopper part 50, 150 semiconductor wafer 51 chip region of semiconductor wafer 53 inactive region of semiconductor wafer 54 orientation flat 61, 161 scribe line 61a, 61b, 161a scribe line recognized by crystal defect inspection device 62, 62a, 162 mark 63a, 63b, 163a mark end part 64 linear crystal defect

Claims

1. A first step of forming a semiconductor wafer by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide; A second step of forming a mark in a first scribe line provided on the semiconductor wafer; A third step of inspecting the epitaxial layer by a crystal defect inspection apparatus to detect crystal defects in the epitaxial layer; A fourth step of forming a predetermined element structure on the semiconductor wafer; A fifth step of dicing the semiconductor wafer into individual semiconductor chips after the fourth step; A sixth step of selecting, as good product candidates, the semiconductor chips in which no crystal defects were detected in the third step; comprising A method for manufacturing a silicon carbide semiconductor device, characterized in that when there is no deviation between a second scribe line recognized by the crystal defect inspection apparatus and the first scribe line, the distance between the end of the second scribe line and the end of the mark is 10 μm or more and 25 μm or less.

2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that the width of the second scribe line is made larger than the width of the first scribe line provided on the semiconductor wafer.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, characterized in that the end of the second scribe line is located at a channel stopper portion of the semiconductor chip.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that the width of the second scribe line is the same as the width of the first scribe line provided on the semiconductor wafer.

5. The first scribe line is provided in a lattice pattern in the <11-20> direction and the <1-100> direction, A method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that when there is no deviation between the second scribe line and the first scribe line, the distance between the end of the second scribe line in the <11-20> direction and the end of the mark is 10 μm or more and 25 μm or less.

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