Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device capable of reducing cost, shortening a manufacturing time, and improving electrical characteristics.SOLUTION: After trench etching and before forming a gate insulating film, heat treatment at a temperature of 1200°C or higher and 1350°C or lower in a mixed gas atmosphere of nitrogen monoxide gas and nitrogen gas for 15 minutes or longer and 60 minutes or shorter and heat treatment for 30 minutes or more and 75 minutes or less in a nitrogen gas atmosphere while maintaining the temperature of this heat treatment are performed successively, and etching damage on the inner wall of the trench is oxidized. The total time during which the predetermined maximum temperature is reached during the total processing time of these heat treatments is 90 minutes or longer. An oxide layer on the inner wall of the trench is removed to expose a clean surface. The luminescence intensity of SiC band edge luminescence determined by CL analysis of the surface region of the inner wall of the trench is greater than or equal to the luminescence intensity of SiC band edge luminescence determined by CL analysis of the surface that has not been dry-etched.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Background Art

[0002] Conventionally, in a trench gate type SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate composed of a three-layer structure of gate - oxide film - semiconductor) using silicon carbide (SiC) as a semiconductor material, etching for forming a trench constituting the trench gate structure (hereinafter referred to as trench etching) is performed by dry etching. Then, after planarizing and cleaning by removing etching damage (damage) on the surface of the inner wall (side wall and bottom surface) of the trench, a gate insulating film is formed along the inner wall of the trench, and a heat treatment (annealing) for baking the gate insulating film is performed.

[0003] Specifically, for trench etching, for example, a plasma etching apparatus is used in which a material gas based on a fluorine-based gas such as sulfur hexafluoride (SF6) gas or methane tetrafluoride (CF4) gas and oxygen (O2) gas is made into a high-density plasma and chemically reacted with a semiconductor (semiconductor substrate), and the volatile reaction products generated are exhausted to the outside to advance the etching. On the inner wall surface of the trench formed by plasma etching, adhesion of fluorine (F) or the like and surface roughness due to ion collision occur. Therefore, after trench etching, the deposits and unevenness on the inner wall surface of the trench are removed by high-temperature heat treatment (hydrogen annealing) in a hydrogen gas (100% H2 gas) atmosphere to planarize the inner wall surface of the trench.

[0004] In addition, due to the surface diffusion effect of silicon (Si) atoms by this hydrogen annealing, the opening-side corners and bottom corners of the trench are appropriately rounded. The opening-side corner of the trench is the boundary between the front surface of the semiconductor substrate and the side wall of the trench, and the bottom corner of the trench is the boundary between the side wall and the bottom surface of the trench. Further, the inner wall surface of the trench is oxidized (sacrificial oxidation) by heat treatment in an oxygen gas atmosphere for a certain period of time, and after removing this oxidized portion (hereinafter referred to as the oxide layer), the inner wall surface of the trench is cleaned, and then a gate insulating film is formed along the inner wall of the trench. Then, after performing heat treatment for densifying the gate insulating film, a polysilicon (poly-Si) layer serving as a gate electrode is embedded in the trench, thereby forming a trench gate structure.

[0005] As a method for forming a gate insulating film, a method has been proposed in which oxygen is obliquely ion-implanted through an oxide film mask serving as a screen oxide film to form an oxygen ion implantation layer in the surface region of the side wall of the trench, and after removing the oxide film mask, a silicon oxide (SiO2) film (hereinafter referred to as an HTO film) serving as a gate insulating film is deposited by high-temperature oxidation (HTO: High Temperature Oxide) (see, for example, Patent Document 1 below). In Patent Document 1 below, excess carbon generated at the initial stage of HTO film deposition and excess carbon in the gate insulating film react with oxygen in the oxygen ion implantation layer to form carbon dioxide and desorb, so the generation of excess carbon is suppressed compared to the case of forming a gate insulating film by thermal oxidation.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In plasma etching, SiC etching is advanced by accelerating ions in the plasma, causing them to collide with the SiC surface and react chemically with SiC. Due to this ion collision, defects such as atomic vacancies, lattice defects (interstitial atoms), dangling bonds (unbonded hands), and impurity (impurities other than dopants) defects occur in the SiC crystal (semiconductor substrate). Also, excessive current flows through the SiC crystal due to the conduction current caused by electrons and ion current in the plasma, or the interatomic bonds of the SiC crystal are broken by high-energy photons generated by ion collision, resulting in the above-mentioned defects.

[0008] These defects caused by plasma etching result in significant etching damage on the SiC surface. In a conventional silicon carbide semiconductor device (SiC-MOSFET), since a channel (n-type inversion layer) is formed along the sidewall of the trench in the p-type base region, when etching damage occurs on the inner wall surface (SiC surface) of the trench by trench etching using plasma etching, it leads to a deterioration of electrical characteristics (such as a decrease in channel mobility and a variation in gate threshold voltage). Therefore, as described above, in the manufacturing method of a conventional silicon carbide semiconductor device, the etching damage on the inner wall surface of the trench is removed by hydrogen annealing.

[0009] Also, it is necessary to remove the source droop that occurs on the sidewall of the trench due to the surface diffusion effect of silicon atoms during this hydrogen annealing. Source droop refers to the n + -type source region flowing on the trench sidewall towards the trench bottom side and drooping to cover the surface of the portion exposed on the trench sidewall of the underlying p-type base region. The source droop on the trench sidewall can be removed by sacrificial oxidation of the inner wall surface of the trench. Therefore, in the manufacturing method of a conventional silicon carbide semiconductor device, after hydrogen annealing to remove the etching damage on the inner wall surface of the trench, it is necessary to perform sacrificial oxidation of the inner wall surface of the trench and removal of the oxide layer formed by the sacrificial oxidation in sequence.

[0010] However, since hydrogen annealing is carried out at a high temperature of 1500°C or higher, an expensive annealing apparatus is required, increasing the manufacturing cost. In addition, both the heating time from room temperature (for example, about 25°C) to a high temperature of 1500°C or higher and the cooling time from the high temperature back to room temperature in the processing furnace of the annealing apparatus are long, so the processing time of hydrogen annealing becomes long. Although the trench inner wall surface can be thinly removed by sacrificial oxidation to obtain a clean surface, it has been found by the inventors' intensive research that damage due to sacrificial oxidation (disorder of the SiC crystal structure, crystal defects) occurs on the trench inner wall.

[0011] It is conceivable to perform trench etching using plasma etching under soft conditions such that etching damage on the trench inner wall surface does not occur or the etching damage on the trench inner wall surface is smaller than that of the conventional method. However, in this case, the etching rate is too slow and trench etching does not proceed. Therefore, even if significant etching damage occurs on the trench inner wall surface by performing trench etching using plasma etching under the same conditions as the conventional method, it is desired to find a method capable of recovering the etching damage on the trench inner wall surface in a subsequent process.

[0012] An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce costs, shorten the manufacturing time, and improve electrical characteristics in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0013] In order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention is a silicon carbide semiconductor device including an insulated gate having a gate-oxide-semiconductor three-layer structure, and has the following features. A semiconductor substrate made of silicon carbide constitutes the semiconductor. A trench having a predetermined depth extending in the depth direction from the first main surface of the semiconductor substrate is provided. A gate insulating film constituting the oxide film is provided along the inner wall of the trench. The gate insulating film contacts the semiconductor substrate at the inner wall of the trench. A gate electrode constituting the gate is provided on the gate insulating film inside the trench. It is a trench gate structure in which a channel is formed in a portion along the side wall of the trench of the semiconductor substrate during turn-on. The emission intensity of the band-edge emission of silicon carbide in the surface region of the inner wall of the trench obtained by using the cathode luminescence method is equal to or higher than the emission intensity of the band-edge emission of silicon carbide in the surface region of the non-dry-etched surface of the semiconductor substrate obtained by using the cathode luminescence method.

[0014] Further, the silicon carbide semiconductor device according to the present invention is the above-described invention, and in the emission intensity distribution of silicon carbide in the surface region of the inner wall of the trench obtained by using the cathode luminescence method, with respect to the emission intensity of the band-edge emission, the ratio of the emission intensity of emission broader than the band-edge emission, which occurs on the longer wavelength side than the peak of the band-edge emission, is less than 35 when the acceleration voltage of the electrons irradiating the inner wall of the trench during analysis by the cathode luminescence method is 2 kV, or is 9 or less when the acceleration voltage of the electrons irradiating the inner wall of the trench during analysis by the cathode luminescence method is 5 kV, or satisfies both of them.

[0015] Further, the silicon carbide semiconductor device according to the present invention is the above-described invention, and the emission intensity of the band-edge emission of silicon carbide on the surface of the inner wall of the trench obtained by using the cathode luminescence method is equal to or higher than the emission intensity of the band-edge emission of silicon carbide on the non-dry-etched surface of the semiconductor substrate obtained by using the cathode luminescence method.

[0016] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the band-edge emission of silicon carbide is characterized in that it is free exciton emission observed near a wavelength of 390 nm.

[0017] In addition, in order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention is a method for manufacturing a silicon carbide semiconductor device including an insulated gate having a three-layer structure of a gate-oxide film-semiconductor, and has the following features. A first step of forming a trench having a predetermined depth extending in the depth direction from the first main surface of a semiconductor substrate made of silicon carbide, which constitutes the semiconductor, by dry etching is performed. After the first step, a second step of performing a first heat treatment in a gas atmosphere containing nitrogen monoxide gas and continuously performing a second heat treatment in a nitrogen gas atmosphere following the first heat treatment is performed. A third step of removing an oxide layer formed on the inner wall of the trench in the second step to expose the inner wall of the trench is performed. After the third step, a fourth step of forming a gate insulating film constituting the oxide film along the inner wall of the trench on the inner wall of the trench is performed. A fifth step of baking the gate insulating film by a third heat treatment is performed. After the fifth step, a trench gate structure in which a channel is formed in a portion along the side wall of the trench of the semiconductor substrate during on-state is formed by forming a gate electrode constituting the gate on the gate insulating film inside the trench. In the second step, the first heat treatment is performed at a temperature in the range of 1200°C or higher and 1350°C or lower, and the second heat treatment is performed by switching to the nitrogen gas atmosphere while maintaining the temperature of the first heat treatment. The total time during which the total treatment time of the first heat treatment and the second heat treatment reaches a predetermined maximum temperature is set to 90 minutes or longer.

[0018] In addition, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the second step, the first heat treatment is performed in the range of 15 minutes or longer and 60 minutes or shorter, and the second heat treatment is performed in the range of 30 minutes or longer and 75 minutes or shorter.

[0019] Also, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the second step, the first heat treatment is performed using the gas atmosphere in which nitric oxide gas is mixed with nitrogen gas at a ratio of 5% or more and 20% or less.

[0020] Also, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the second step, in the first step, the damage layer generated on the inner wall of the trench is oxidized by the first heat treatment to form the oxide layer.

[0021] Also, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the second step, in the first heat treatment, the defects on the inner wall of the trench are terminated with nitrogen contained in nitric oxide gas.

[0022] Also, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the second step, in the second heat treatment, the disorder of the silicon carbide crystal structure of the semiconductor substrate is repaired.

[0023] According to the above-described invention, after the formation of the trench by etching and before the formation of the gate insulating film, by continuously performing the first heat treatment and the second heat treatment, a clean surface is exposed on the inner wall surface of the trench. Thereby, in order to remove the etching damage on the inner wall of the trench, it is not necessary to use a high-temperature hydrogen anneal using an expensive annealing apparatus as in the conventional method. Further, according to the above-described invention, since the maximum temperatures of the first heat treatment and the second heat treatment are lower than the temperature of the hydrogen anneal performed to remove the etching damage on the inner wall of the trench in the conventional method, both the temperature increase time and the temperature decrease time in the heat treatment furnace during the second step can be shortened. Further, according to the above-described invention, it is possible to prevent a decrease in channel mobility and a change in gate threshold voltage.

Effects of the Invention

[0024] According to the silicon carbide semiconductor device and the method of manufacturing the silicon carbide semiconductor device of the present invention, it is possible to reduce costs, shorten the manufacturing time, and improve the electrical characteristics.

Brief Description of the Drawings

[0025]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0026] With reference to the accompanying drawings, preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in a layer or region preceded by n or p, it means that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than a layer or region to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. In this specification, in the notation of Miller indices, "-" means a bar attached to the immediately following index, and a negative index is represented by attaching "-" before the index.

[0027] (Embodiment) The structure of a silicon carbide semiconductor device according to an embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. The silicon carbide semiconductor device 10 according to the embodiment shown in FIG. 1 is a vertical SiC-MOSFET having a trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 30 using silicon carbide (SiC) as a semiconductor material. The semiconductor substrate 30 is an epitaxial substrate formed by laminating an n + -type starting substrate 31 on the front surface, and n - -type drift region 2 and p-type base region 3 in this order, with each epitaxial layer 32, 33 serving as the epitaxial layers.

[0028] The semiconductor substrate 30 has the main surface on the p-type epitaxial layer 33 side as the front surface (first main surface), and the main surface on the n + -type starting substrate 31 side (the back surface of the n + -type starting substrate 31) as the back surface. The crystal structure of the semiconductor substrate 30 may be, for example, a four-layer periodic hexagonal crystal structure (4H-SiC) of silicon carbide. The front surface of the semiconductor substrate 30 may be a (0001) surface, a so-called Si (silicon) surface, or a (000-1) surface, a so-called C (carbon) surface. n + -type starting substrate 31 is an n + -type drain region 1. The n - -type drift region 2 is n- The n-type epitaxial layer 32 + is a portion on the n-type starting substrate 31 side and is adjacent to the n-type starting substrate 31. The p-type base region 3 is provided between the front surface of the semiconductor substrate 30 and the n-type drift region 2. + -

[0029] The trench gate structure is composed of a p-type base region 3, an n-type source region 4, a p-type contact region 5, a trench 6, a gate insulating film 7, and a gate electrode 8. Between the p-type base region 3 and the n-type drift region 2, an n-type current diffusion region 23 and p-type regions 21, 22 are selectively provided at a position deeper than the bottom surface of the trench 6 on the n-type drain region 1 side. + ++ - On the side of the n-type drain region 1 deeper than the bottom surface of the trench 6 between the p-type base region 3 and the n-type drift region 2, an n-type current diffusion region 23 and p-type regions 21, 22 are selectively provided. + + The n-type current diffusion region 23 and the p-type regions 21, 22 are diffusion regions formed inside the n-type epitaxial layer 32 by ion implantation. + - - The portion of the n-type epitaxial layer 32 excluding the n-type current diffusion region 23 and the p-type regions 21, 22 is the n-type drift region 2. + -

[0030] The n-type current diffusion region 23 is a so-called current spreading layer (CSL: Current Spreading Layer) that reduces the spreading resistance of carriers. The n-type current diffusion region 23 contacts the p-type base region 3 and the n-type drift region 2 in the depth direction between adjacent trenches 6, reaches up to the trench 6 in the direction parallel to the front surface of the semiconductor substrate 30, and contacts the gate insulating film 7. The n-type current diffusion region 23 may not be provided. When the n-type current diffusion region 23 is not provided, instead of the n-type current diffusion region 23, the n-type drift region 2 reaches from the n-type drain region 1 side to the p-type base region 3, reaches up to the trench 6 in the direction parallel to the front surface of the semiconductor substrate 30, and contacts the gate insulating film 7. - - +

[0031] ​​​​​​​​​​​​ p + The p-type regions 21 and 22 are fixed to the potential of the source electrode 11 described later, and deplete when the MOSFET (silicon carbide semiconductor device 10) is off (or deplete the n-type current diffusion region 23, or both), and have a function of relaxing the electric field applied to the gate insulating film 7 on the bottom surface of the trench 6. p + The p-type region 21 is provided apart from the p-type base region 3 and faces the bottom surface of the trench 6 in the depth direction. p + The p-type region 21 is partially connected to the p + type region 22 in a part not shown in the figure, or is connected to another p-type region, and is electrically connected to the source electrode 11. p + The p-type region 21 may be in contact with the gate insulating film 7 on the bottom surface of the trench 6, or may be separated from the bottom surface of the trench 6.

[0032] p + The p-type region 21 may also face the bottom corner portion (corner) of the trench 6 in the depth direction. The bottom corner portion of the trench 6 is the boundary between the side wall and the bottom surface of the trench 6. p + When the p-type region 21 faces the bottom corner portion of the trench 6 in the depth direction, the electric field applied to the gate insulating film 7 at the bottom corner portion of the trench 6 is relaxed when the MOSFET is off, so that the electric field relaxation effect near the bottom surface of the trench 6 is enhanced. The p + type regions 22 are provided between adjacent trenches 6, separated from the trenches 6 and the p + type region 21. p + The p-type region 22 is p + in contact with the p-type base region 3 on the surface on the n

[0033] The trench 6 penetrates the p-type epitaxial layer 33 from the front surface of the semiconductor substrate 30 in the depth direction to the n-type current diffusion region 23 (when the n-type current diffusion region 23 is not provided, n -It reaches the p-type drift region 2). The bottom surface of the trench 6 exposes the same crystal plane as the front surface of the semiconductor substrate 30. The side walls of the trench 6 may be, for example, {1-100} planes, so-called m planes. The opening-side corner portions and the bottom-side corner portions of the trench 6 may be appropriately rounded. The opening-side corner portion of the trench 6 is the boundary between the front surface of the semiconductor substrate 30 and the side wall of the trench 6. The surface of the inner wall (side wall and bottom surface) of the trench 6 becomes the bonding interface (hereinafter referred to as the SiC / SiO2 interface) 20 between the semiconductor substrate 30 and the gate insulating film 7.

[0034] The surface of the inner wall of the trench 6 has the etching damage 30a (see FIG. 2) generated during the trench etching (processing in step S3: see FIG. 3) described later recovered by the first NO annealing (processing in step S4: see FIG. 3) described later. As a result, the emission intensity distribution of SiC (see FIG. 9) obtained by the cathodoluminescence (CL) method on the surface and the surface region of the inner wall of the trench 6 satisfies the following conditions. The CL method is a technique used to analyze the crystal structure, impurities, and defect states in the vicinity of the irradiation surface of an object from the emission intensity distribution of photons emitted by irradiating the irradiation surface of the object with electrons accelerated thereto. The higher the acceleration voltage of the electrons (electron beam) irradiated to the object during the analysis by the CL method (hereinafter referred to as CL analysis), the deeper the emission intensity distribution from the irradiation surface can be obtained.

[0035] The emission intensity I1 of the band-edge emission (free exciton emission near the observation wavelength of 390 nm) D1 of SiC by CL analysis of the surface and surface region of the inner wall of the trench 6 is equal to or higher than the emission intensity I1 of the band-edge emission A1 of SiC (see FIG. 5) of the non-dry-etched SiC surface and surface region, respectively. The non-dry-etched SiC surface is a surface not exposed to the material gas for trench etching, and may be a portion of the front surface of the semiconductor substrate 30 covered with a mask for trench etching, the side surface (end portion) and the back surface of the semiconductor substrate 30, or a cross-section exposed by cutting the semiconductor substrate 30 perpendicular to the main surface. In the conventional example described later, the emission intensity I1 of the band-edge emission C1 of SiC (see FIG. 7) of the surface and surface region of the inner wall of the trench is lower than the emission intensity I1 of the band-edge emission A1 of SiC of the non-dry-etched SiC surface and surface region, respectively.

[0036] Also, in the emission intensity distribution of SiC by CL analysis of the surface and surface region of the inner wall of the trench 6, the ratio of the emission intensity I2 of the broad emission D2 on the long wavelength side to the emission intensity I1 of the band-edge emission D1 (= emission intensity I2 of the broad emission D2 on the long wavelength side / emission intensity I1 of the band-edge emission D1) (hereinafter referred to as the emission intensity ratio) is lower than the emission intensity ratio of the broad emission C2 on the long wavelength side of SiC in the conventional example (see FIG. 7), and is, for example, less than about 35 when the acceleration voltage of the electrons in the CL analysis is 2 kV, or less than about 9 when the acceleration voltage of the electrons in the CL analysis is 5 kV, or satisfies both of them (see FIG. 10). The broad emission D2 on the long wavelength side of SiC is a peak broader (wider) than the band-edge emission D1, which occurs on the long wavelength side of the peak (crest) of the band-edge emission D1 of SiC.

[0037] Between adjacent trenches 6, an n + type source region 4 and a p ++ type contact region 5 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 3, respectively. Of the p-type epitaxial layer 33, the n + type source region 4 and the p ++The portion excluding the type- contact region 5 is the p-type base region 3. A channel (n-type inversion layer) is formed in the portion 3a of the p-type base region 3 along the sidewall of the trench 6 when the SiC-MOSFET is turned on. Since the etching damage on the inner wall surface of the trench 6 is recovered by the first NO annealing (processing in step S4: see Fig. 3) described later, it is possible to prevent the electrical characteristics (channel mobility, gate threshold voltage, etc.) of the SiC-MOSFET from degrading.

[0038] n + The n-type source region 4 and the p ++ type contact region 5 is a diffusion region formed inside the p-type epitaxial layer 33 by ion implantation. The n + type source region 4 and the p ++ type contact region 5 is exposed on the front surface of the semiconductor substrate 30. Being exposed on the front surface of the semiconductor substrate 30 means contacting the source electrode 11 described later on the front surface of the semiconductor substrate 30. The n + type source region 4 is the p ++ type contact region 5 is provided closer to the trench 6 side and contacts the gate insulating film 7 at the sidewall of the trench 6. The p ++ type contact region 5 may not be provided. The p ++ type contact region 5 is not provided, the p ++ type contact region 5, instead, the p-type base region 3 reaches the front surface of the semiconductor substrate 30 and is exposed.

[0039] Inside the trench 6, a gate electrode 8 is provided on the gate insulating film 7 so as to fill the trench 6. The gate insulating film 7 is, for example, a silicon oxide (SiO2) film deposited by general HTO (high-temperature oxidation). The gate insulating film 7 is at the inner wall of the trench 6 and the n + type source region 4, p-type base region 3, and n-type current diffusion region 23 (when the n-type current diffusion region 23 is not provided, the n -It is in contact with the type drift region 2). Inside the trench 6, a gate electrode 8 is provided via a gate insulating film 7. In FIG. 1, only one unit cell (the constituent unit of the element) of the MOSFET is shown, but a plurality of unit cells having the same trench gate structure are arranged adjacent to each other on the semiconductor substrate 30.

[0040] The interlayer insulating film 9 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 8. In the contact hole of the interlayer insulating film 9, n + type source region 4 and p ++ type contact region 5 (when the p ++ type contact region 5 is not provided, the p-type base region 3 is exposed. The source electrode 11 makes an ohmic contact with the front surface of the semiconductor substrate 30 at the contact hole of the interlayer insulating film 9, and is electrically connected to the n + type source region 4, p ++ type contact region 5 and the p-type base region 3. A drain electrode 12 is provided on the entire back surface of the semiconductor substrate 30. The drain electrode 12 is in contact with the n + type drain region 1 (n + type starting substrate 31) and is electrically connected to the n + type drain region 1.

[0041] The operation of the silicon carbide semiconductor device 10 according to the embodiment will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 8 in a state where a positive voltage (forward voltage) is applied to the drain electrode 12 with respect to the source electrode 11, a channel (n-type inversion layer) is formed in a portion along the side wall of the trench 6 in the p-type base region 3. As a result, current flows from the n + type drain region 1 through the channel toward the n + type source region 4, and the SiC-MOSFET (silicon carbide semiconductor device 10) turns on.

[0042] On the other hand, when a voltage lower than the gate threshold voltage is applied to the gate electrode 8 in a state where a forward voltage is applied between the source and the drain, p + type regions 21, 22 and the p-type base region 3, and the n-type current diffusion region 23 and n- When the pn junction (main junction) between the n-type drift region 2 and [the other part] is reverse-biased, the current stops flowing, and the SiC-MOSFET maintains the off state. Also, as the depletion layer spreads into the p-type regions 21 and 22 from the pn junction, the electric field applied to the gate insulating film 7 on the bottom surface of the trench 6 is relaxed. +

[0043] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment will be described with reference to FIGS. 1 to 3. FIG. 2 is an enlarged cross-sectional view showing the vicinity of the trench in the state after the process of step S3 in FIG. 3. FIG. 3 is a flowchart showing an outline of the method for manufacturing the semiconductor device according to the embodiment. First, for example, an n-type starting substrate (starting wafer) 31 using 4H-SiC as a semiconductor material is prepared. + + After subjecting the n-type starting substrate 31 to RCA cleaning, an n-type epitaxial layer 32 that will become the n-type drift region 2 is epitaxially grown (deposited) on the front surface of the n-type starting substrate 31 (step S1: part 1). + - - - The impurity concentration of the n-type epitaxial layer 32 is, for example, about 1×10 16 / cm 3 .

[0044] RCA cleaning is a wet cleaning that performs SC-1 cleaning and SC-2 cleaning. In SC-1 cleaning, the semiconductor wafer is immersed in a mixed aqueous solution of ammonium hydroxide (NH4OH), hydrogen chloride (HCl), and hydrogen peroxide (H2O2) for cleaning. In SC-1 cleaning, organic substances and particles on the surface of the semiconductor wafer (the contact surface with the mixed aqueous solution) are removed. SC-2 cleaning is performed after SC-1 cleaning. In SC-2 cleaning, the semiconductor wafer is immersed in a mixed aqueous solution of hydrogen chloride (HCl) and hydrogen peroxide (H2O2) for cleaning. In SC-2 cleaning, metal ion contaminants on the surface of the semiconductor wafer are removed. A rinsing process with pure water (highly purified water: H2O) is performed between SC-1 cleaning and SC-2 cleaning.

[0045] Next, by photolithography and ion implantation of p-type impurities, on the surface region of the n - -type epitaxial layer 32, p + -type regions 21 and the lower part of the p + -type region 22 (the part on the n + -type drain region 1 side) are selectively formed so as to be alternately arranged at intervals from each other. Also, by photolithography and ion implantation of n-type impurities, in the surface region of the n - -type epitaxial layer 32, the lower part of the n-type current diffusion region 23 is formed between the adjacent p + -type region 21 and the p + -type region 22. The part of the n - -type epitaxial layer 32 on the n + -type starting substrate 31 side, which is closer to the n + -type starting substrate 31 than the p - -type regions 21, 22 and the n-type current diffusion region 23, becomes the n

[0046] Next, further epitaxial growth is performed to increase the thickness of the n - -type epitaxial layer 32 to a predetermined thickness (Step S1: Part 2). Next, by photolithography and ion implantation of p-type impurities, on the thickened part of the n - -type epitaxial layer 32, the upper part of the p + -type region 22 (the part on the n + -type source region 4 side) is selectively formed. Also, by photolithography and ion implantation of n-type impurities, on the thickened part of the n - -type epitaxial layer 32, the upper part of the n-type current diffusion region 23 is formed. The upper part of the p + -type region 22 and the upper part of the n-type current diffusion region 23 are formed at positions facing the lower part of the p + -type region 22 and the lower part of the n-type current diffusion region 23 in the depth direction, respectively, and are connected to the lower part of the p + -type region 22 and the lower part of the n-type current diffusion region 23, respectively.

[0047] Next, n -An epitaxial layer 33 that will become the p-type base region 3 is epitaxially grown (deposited) on the type III epitaxial layer 32 (Step S1: Item 3). Through the steps up to this point, a semiconductor substrate (semiconductor wafer) 30 is fabricated (manufactured) with the epitaxial layers 32 and 33 sequentially stacked on the front surface of the n + type starting substrate 31. Next, photolithography and ion implantation are repeatedly performed under different conditions to selectively form an n + type source region 4 and a p ++ type contact region 5 on the surface region of the p-type epitaxial layer 33 (Step S2). The portion of the p-type epitaxial layer 33 on the n + type source region 4 and p ++ type contact region 5 side that is closer to the n - type epitaxial layer 32 becomes the p-type base region 3.

[0048] Next, for all diffusion regions (p + type regions 21 and 22, n-type current diffusion region 23, n + type source region 4, and p ++ type contact region 5) formed by ion implantation, a heat treatment for impurity activation is performed. The heat treatment for impurity activation may be performed each time a diffusion region is formed by ion implantation. Next, as shown in FIG. 2, after the semiconductor substrate 30 is RCA cleaned, a trench 6 is formed by photolithography and etching (hereinafter referred to as trench etching) that penetrates from the front surface of the semiconductor substrate 30 (the surface of the p-type epitaxial layer 33) in the depth direction through the n + type source region 4 and the p-type base region 3 to reach the n-type current diffusion region 23 (Step S3: First step).

[0049] For the trench etching in step S3, for example, a plasma etching apparatus is used in which a material gas based on a fluorine-based gas such as sulfur hexafluoride (SF6) gas or methane tetrafluoride (CF4) gas and oxygen (O2) gas is converted into plasma at high density and chemically reacted with SiC (semiconductor substrate 30), and the volatile reaction products generated are exhausted to the outside to progress the etching. Argon (Ar) gas may be mixed in the material gas for plasma etching. In plasma etching, the trench etching is advanced by accelerating the ions in the plasma and colliding them with the SiC surface to cause a chemical reaction with SiC. On the inner wall surface of the trench 6, adhesion of fluorine (F) etc. in the material gas and etching damage 30a occur.

[0050] Specifically, during the trench etching in step S3, defects such as atomic vacancies, lattice defects (interstitial atoms), dangling bonds (unbonded hands), and impurity (impurities other than dopants) defects are generated in the SiC crystal (semiconductor substrate 30) exposed on the inner wall surface of the trench 6 due to ion collision. Also, excessive current flows through the SiC crystal exposed on the inner wall surface of the trench 6 due to conduction current caused by electrons and ion current in the plasma, or the interatomic bonds of the SiC crystal are broken by high-energy photons generated by ion collision, resulting in the above defects. These defects caused by plasma etching cause etching damage 30a on the inner wall surface of the trench 6. In FIG. 2, the portion where the etching damage 30a occurs is indicated by a thick dashed line.

[0051] Next, the semiconductor substrate 30 is introduced into a heat treatment furnace, and heat treatment is performed in a mixed gas atmosphere in which nitric oxide (NO) gas is mixed with nitrogen (N2) gas at a ratio of, for example, 5% or more and 20% or less (hereinafter referred to as NO / N2 annealing: first heat treatment), and heat treatment in a nitrogen gas atmosphere (hereinafter referred to as N2 annealing: second heat treatment) are continuously performed in the same heat treatment furnace in this order (hereinafter referred to as the first NO annealing) (step S4: second step). By the first NO annealing, the portion (damage layer) where the etching damage 30a on the inner wall surface of the trench 6 has occurred is oxidized, and defects (crystal defects, dangling bonds) near the inner wall surface of the trench 6 are terminated with nitrogen (N) and reduced, and the SiC crystal structure of the semiconductor substrate 30 disturbed by the thermal damage caused by the total processing time at the maximum temperature of the first NO annealing is repaired.

[0052] Specifically, by the NO / N2 annealing of the first NO annealing, the damage layer on the inner wall surface of the trench 6 is oxidized. Further, the defects near the inner wall surface of the trench 6 are terminated and reduced with nitrogen in the NO gas used for the NO / N2 annealing of the first NO annealing. The N2 annealing of the first NO annealing is continuously performed in the same heat treatment furnace as the NO / N2 annealing of the first NO annealing in succession to the NO / N2 annealing. That is, after the semiconductor substrate 30 is introduced into the heat treatment furnace, the semiconductor substrate 30 is taken out from the heat treatment furnace after the NO / N2 annealing and the N2 annealing of the first NO annealing are performed. By the N2 annealing of the first NO annealing, the oxidation of the inner wall surface of the trench 6 advanced by the NO / N2 annealing of the first NO annealing can be stopped. Further, by the N2 annealing of the first NO annealing, the SiC crystal structure disturbed by the thermal damage caused by the total processing time at the maximum temperature of the first NO annealing is repaired.

[0053] For the NO annealing of the first NO anneal, the NO / N2 annealing is carried out at a processing temperature in the range of, for example, 1200 °C or higher and 1350 °C or lower, and the processing time is in the range of about 15 minutes or longer and 60 minutes or shorter. For the N2 annealing of the first NO anneal, the gas supplied to the heat treatment furnace is switched to nitrogen gas (100% N2 gas) while maintaining the temperature of the heat treatment furnace at the processing temperature of the NO / N2 annealing of the first NO anneal, and the processing time is in the range of about 30 minutes or longer and 75 minutes or shorter. During the total processing time of the first NO anneal (= processing time of NO / N2 annealing + processing time of N2 annealing), the total time during which the temperature of the heat treatment furnace reaches a predetermined maximum temperature (total processing time at the predetermined maximum temperature of the first NO anneal) is about 90 minutes or longer.

[0054] The ratio of the processing time of the NO / N2 annealing to the processing time of the N2 annealing of the first NO anneal is appropriately adjusted according to the depth of the etching damage 30a generated on the inner wall surface of the trench 6 (i.e., the trench etching conditions in step S3). Therefore, first, the processing temperature and processing time of the NO / N2 annealing of the first NO anneal are set according to the depth of the damage layer so that the portion (damage layer) where the etching damage 30a reaching a predetermined depth from the inner wall surface of the trench 6 is completely oxidized. Based on the processing time of the NO / N2 annealing of the first NO anneal, the processing time of the N2 annealing of the first NO anneal is set so that the total processing time at the predetermined maximum temperature of the first NO anneal is about 90 minutes or longer.

[0055] In the NO / N2 annealing of the first NO annealing in step S4, when the maximum temperature is set to the lowest temperature (about 1200 °C) within the above-mentioned predetermined temperature range, the NO gas ratio in the mixed gas (NO / N2 gas) is set to the lowest ratio (about 5%), and the treatment time is set to the shortest time (about 15 minutes) (the softest conditions), the oxidation amount of the SiC surface (the thickness of the oxide layer formed on the SiC surface due to the oxidation of the SiC surface) is about 3 nm. Also, in the NO / N2 annealing of the first NO annealing in step S4, when the maximum temperature is set to the highest temperature (about 1350 °C) within the above-mentioned predetermined temperature range, the NO gas ratio in the mixed gas is set to the highest ratio (for example, about 20%), and the treatment time is set to the longest time (for example, 60 minutes) (the conditions under which defects are most recovered), the oxidation amount of the SiC surface is about 20 nm.

[0056] The longer the treatment time of the N2 annealing in the total treatment time of the first NO annealing in step S4, the less the supply amount of the expensive NO gas can be reduced, so the manufacturing cost can be reduced. Also, in the first NO annealing in step S4, by continuously performing the NO / N2 annealing and the N2 annealing, the treatment time of the NO / N2 annealing can be adjusted. Therefore, it is possible to prevent the oxidation of the inner wall surface of the trench 6 from proceeding too much by the NO gas, which is the material gas of the mixed gas atmosphere used for the first NO annealing, and to ensure that the total treatment time at the predetermined maximum temperature of the first NO annealing is about 90 minutes or more.

[0057] In the conventional method, since the temperature of the heat treatment furnace is raised from room temperature (e.g., about 25°C) to a high temperature of 1500°C or higher and then hydrogen annealing is performed, the treatment time of hydrogen annealing becomes several hours. On the other hand, in the present embodiment, for example, in the process of step S4, after the semiconductor substrate 30 is introduced into the heat treatment furnace maintained at a temperature of about 700°C, the temperature inside the heat treatment furnace is raised to the treatment temperature within the above-mentioned predetermined range of NO annealing of NO / N2 annealing of the first NO annealing, and then NO / N2 annealing and N2 annealing are continuously performed. Compared with the hydrogen annealing of the conventional method, the maximum temperature of the first NO annealing in step S4 is low, and both the temperature rising time and the temperature falling time inside the heat treatment furnace during the first NO annealing in step S4 can be shortened.

[0058] The ratio of the treatment time of NO / N2 annealing of the first NO annealing to the treatment time of N2 annealing may be calculated by measuring the depth of the etching damage 30a generated on the inner wall surface of the trench 6 after the process of step S3 and before the process of step S4. Alternatively, the depth of the etching damage 30a generated on the inner wall surface of the trench 6 may be obtained in advance based on the trench etching conditions of step S3 by simulation or the like, and the ratio of the treatment time of NO / N2 annealing of the first NO annealing to the treatment time of N2 annealing may be calculated. By the first NO annealing, the corner portions on the opening side and the bottom corner portions of the trench 6 may be appropriately rounded.

[0059] By the first NO annealing in step S4, the emission intensity I1 of the band edge emission D1 of SiC (see FIG. 9) by CL analysis of the surface and the surface region of the inner wall of the trench 6 is equal to or higher than the emission intensity I1 of the band edge emission A1 of SiC (see FIG. 5) of the SiC surface and the surface region that have not been dry-etched. Further, in the CL analysis of the surface and the surface region of the inner wall of the trench 6, the emission intensity ratio of the broad emission D2 on the long wavelength side of SiC is, for example, less than about 35 when the acceleration voltage of the electrons in the CL analysis is 2 kV, or less than about 9 when the acceleration voltage of the electrons in the CL analysis is 5 kV, or satisfies both of them.

[0060] Next, the temperature inside the heat treatment furnace is decreased to, for example, room temperature, and then the semiconductor substrate 30 is taken out. Next, an oxide layer (silicon oxide (SiO2) layer) formed by oxidizing the damaged layer on the inner wall surface of the trench 6 in the process of step S4 is removed by wet etching using, for example, a solution containing fluorine, to expose the inner wall surface of the trench 6 (step S5: third step). By the wet etching in step S5, a clean surface without damage is exposed on the inner wall surface of the trench 6. The wet etching in step S5 removes only the oxide layer and does not adversely affect the nitrogen termination on the SiC surface. The wet etching in step S5 may use, for example, hydrofluoric acid containing hydrogen fluoride (HF) in a ratio within the range of about 5% or more and 10% or less, or buffered hydrofluoric acid (BHF: Buffered Hydrogen Fluoride). The higher the fluorine concentration, the shorter the processing time in step S5 can be.

[0061] Next, a SiO2 film (HTO film) to be the gate insulating film 7 is deposited (step S6: fourth step). By using the HTO film as the gate insulating film 7, generation of excess carbon (C) at the bonding interface (SiC / SiO2 interface 20) between the semiconductor substrate 30 (inner wall of the trench 6) and the gate insulating film 7 can be suppressed as compared with the case where the gate insulating film 7 is formed by thermal oxidation. Next, heat treatment (post HTO annealing) is performed for about 30 minutes, for example, in a mixed gas atmosphere in which nitric oxide gas is mixed with nitrogen (N2) at a ratio of about 10% (hereinafter referred to as the second NO annealing: third heat treatment) (step S7: fifth step). The second NO annealing promotes the densification of the gate insulating film 7, and the film density of the gate insulating film 7 becomes higher.

[0062] Next, a polysilicon (poly-Si) layer is deposited on the front surface of the semiconductor substrate 30 so as to fill the inside of the trench 6. Then, the polysilicon layer is etched back, for example, to leave only inside the trench 6 to form the gate electrode 8 (step S8: the sixth step). Next, an interlayer insulating film 9 covering the gate electrode 8 is formed on the front surface of the semiconductor substrate 30. Next, surface electrodes serving as the source electrode 11 and the drain electrode 12 are formed on the front surface and the back surface of the semiconductor substrate 30, respectively, by a general method (step S9). Thereafter, the semiconductor wafer (semiconductor substrate 30) is diced (cut) into individual chips, whereby the silicon carbide semiconductor device 10 shown in FIG. 1 is completed.

[0063] Also, in the method for manufacturing the silicon carbide semiconductor device 10 according to the above-described embodiment, after the trench etching in step S3 and before the wet etching in step S5, for example, heat treatment may be performed for about 30 minutes in an argon gas (100% Ar gas) atmosphere at a temperature of about 1500° C. at normal pressure. By this heat treatment in the 100% Ar gas atmosphere, the rearrangement and recrystallization of the SiC crystals in the surface region of the inner wall of the trench 6 can be promoted. Further, since the 100% Ar gas atmosphere is used in this heat treatment, the main surface of the semiconductor substrate 30 and the inner surface of the trench 6 are not oxidized.

[0064] As described above, according to the embodiment, after the trench etching and before the formation of the gate insulating film, NO / N2 annealing at a temperature of 1200° C. or higher and 1350° C. or lower in a gas atmosphere containing nitrogen monoxide gas and N2 annealing in a nitrogen gas atmosphere maintaining the temperature of the NO / N2 annealing are continuously performed to oxidize the etching damage on the inner wall of the trench. The total time during which the total processing time reaches a predetermined maximum temperature during these annealings is set to 90 minutes or more. By removing the oxide layer formed by oxidizing the etching damage on the inner wall of the trench, a clean surface is exposed on the inner wall of the trench.

[0065] According to the embodiment, since NO / N2 annealing and N2 annealing are performed continuously to remove the etching damage on the trench inner wall, it is not necessary to perform high-temperature hydrogen annealing using an expensive annealing apparatus as in the conventional method. Therefore, the manufacturing cost can be reduced. Further, according to the embodiment, since the maximum temperatures of NO / N2 annealing and N2 annealing (the first NO annealing) are lower than the temperature of hydrogen annealing performed to remove the etching damage on the trench inner wall in the conventional method, both the temperature rising time and the temperature falling time in the heat treatment furnace during the first NO annealing can be shortened. Thereby, the manufacturing time can be shortened.

[0066] Also, according to the embodiment, by the first NO annealing, in the surface region of the inner wall of the trench, the etching damage is removed, the defects of the SiC crystal are terminated with nitrogen and reduced, and the SiC crystal structure is repaired. As a result, the emission intensity of the band-edge emission of SiC by CL analysis in the surface region of the inner wall of the trench becomes equal to or higher than the emission intensity of the band-edge emission of SiC by CL analysis of the surface that has not been dry-etched. Thereby, it is possible to prevent a decrease in the electrical characteristics (channel mobility, gate threshold voltage, etc.) of the SiC-MOSFET, and it is possible to improve the electrical characteristics of the SiC-MOSFET as compared with the conventional method.

[0067] (Experimental Example 1) The etching damage 30a (see FIG. 2) on the SiC surface by dry etching (corresponding to the trench etching in step S3: see FIG. 3) was verified. FIG. 4 is a chart showing the band-edge emission intensity ratios of SiC by CL analysis of Comparative Example 1, Comparative Example 2, the conventional example, and the example. In FIG. 4, taking the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1 as a reference (=1.0), the ratios (band-edge emission intensity ratios) of the emission intensity I1 of the band-edge emission of SiC in Comparative Example 2, the conventional example, and the example to the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1 are shown respectively.

[0068] Figures 5 to 7 show the light emission intensity distributions of SiC by CL analysis of Comparative Example 1, Comparative Example 2, and the conventional example, respectively. Figures 8 and 9 show the light emission intensity distributions of SiC by CL analysis of Comparative Example 2 and the example, respectively. Figures 5 to 7 show the CL analysis results with the acceleration voltage of the electron beam set to 5 kV. Figures 4, 8, and 9 show the CL analysis results with the acceleration voltage of the electron beam set to 2 kV. The emission intensities I1 of the band-edge emissions B11 and D1 of SiC in Comparative Example 2 and the example in Figure 4 are calculated with reference to the light emission intensity distributions of SiC in Figures 8 and 9.

[0069] As the example, Comparative Example 1, Comparative Example 2, and the conventional example, on the main surface of a starting substrate made of SiC having an m-plane as the main plane (hereinafter referred to as an m-plane substrate), 1×10 16 / cm 3 of impurity concentration and a thickness of 5 μm, flat epitaxial substrates formed by epitaxially growing an n - -type epitaxial layer were each prepared (corresponding to step S1 (part 1) in Figure 3). In the example, Comparative Example 1, Comparative Example 2, and the conventional example, a predetermined treatment (no treatment in Comparative Example 1) and CL analysis were performed on the main surface (m-plane) on the n - -type epitaxial layer side of the epitaxial substrate.

[0070] Specifically, in the example, the main surface on the n - -type epitaxial layer side of the epitaxial substrate was dry-etched (corresponding to the trench etching in step S3 of Figure 3), and the thickness of the epitaxial substrate (the thickness of the n - -type epitaxial layer) was reduced by a predetermined thickness. On the surface (m-plane) exposed by the dry etching of this epitaxial substrate, according to the manufacturing method of the silicon carbide semiconductor device according to the above-described embodiment, the first NO annealing in step S4 and the wet etching in step S5 were performed.

[0071] The n -The dry etching of the main surface on the epitaxial layer side was performed as plasma etching using a mixed gas of a fluorine-based gas and oxygen gas. As the mixed gas of the fluorine-based gas and oxygen gas, a mixed gas of SF6 gas and O2 gas (SF6 / O2 gas), a mixed gas of CF4 gas and O2 gas (CF4 / O2 gas), a mixed gas of SF6 gas, O2 gas and argon (Ar) gas (SF6 / O2 / Ar gas), or a mixed gas of CF4 gas, O2 gas and Ar gas (CF4 / O2 / Ar gas) is used.

[0072] The first NO annealing in step S4 was performed by carrying out NO / N2 annealing at a temperature of 1300 °C (the maximum temperature of the first NO annealing) for 30 minutes in an atmosphere of a mixed gas (10%NO / N2 gas) in which NO gas was mixed with N2 gas at a ratio of 10%. Then, while maintaining the temperature during NO / N2 annealing (1300 °C), nitrogen gas was introduced into the heat treatment furnace to switch to an atmosphere of nitrogen gas (100%N2 gas) and N2 annealing was carried out for 60 minutes. The wet etching in step S5 was performed using hydrofluoric acid containing HF at a ratio of 5% (dry etching + NO / N2·N2 continuous heat treatment + oxide layer removal).

[0073] Thereafter, CL analysis was performed for the example with the acceleration voltage of the electron beam set to 2 kV and 5 kV respectively, and the emission intensity distribution of SiC on the main surface (SiC surface) on the n- - type epitaxial layer side of the epitaxial substrate was obtained. The emission intensity distribution of SiC by CL analysis with the acceleration voltage of the electron beam set to 2 kV is the emission intensity distribution of SiC in a shallower part (a part closer to the SiC surface) from the main surface on the n- - type epitaxial layer side of the epitaxial substrate than the emission intensity distribution of SiC by CL analysis with the acceleration voltage of the electron beam set to 5 kV.

[0074] The point where Comparative Example 1 differs from the example is that the steps after dry etching are not performed (without dry etching). That is, Comparative Example 1 is an n- on an m-plane substrate. -This is a sample in which only the type epitaxial layer is epitaxially grown. The difference between Comparative Example 2 and the Example is that the processes of Step S4 and Step S5 are not performed (only dry etching). That is, Comparative Example 2 is a sample in which only the main surface on the n-type epitaxial layer side of the epitaxial substrate is dry etched under the same conditions as in the Example. - This is a sample in which only the main surface on the n-type epitaxial layer side of the epitaxial substrate is dry etched.

[0075] The difference between the Conventional Example and the Example is that, instead of the processes of Step S4 and Step S5, sacrificial oxidation of the main surface (m-plane) on the n-type epitaxial layer side of the epitaxial substrate by heat treatment at a temperature of 1150°C for 60 minutes in an oxygen gas atmosphere and removal of the oxide layer formed by the sacrificial oxidation with hydrofluoric acid are performed in sequence (dry etching + sacrificial oxidation + oxide layer removal). For these Comparative Example 1, Comparative Example 2, and Conventional Example, similar to the Example, the emission intensity distribution of SiC by CL analysis was obtained for the main surface on the n-type epitaxial layer side of the epitaxial substrate. - This is a sample in which only the main surface on the n-type epitaxial layer side of the epitaxial substrate is dry etched. - The emission intensity distribution of SiC by CL analysis was obtained for the main surface on the n-type epitaxial layer side of the epitaxial substrate.

[0076] The emission intensity distributions of SiC by CL analysis with the acceleration voltage of the electron beam of 5 kV for Comparative Example 1, Comparative Example 2, and Conventional Example are shown in FIGS. 5 to 7. The emission intensity distributions of SiC by CL analysis with the acceleration voltage of the electron beam of 2 kV for Comparative Example 2 and the Example are shown in FIGS. 8 and 9. The emission intensity distributions of SiC by CL analysis with the acceleration voltage of the electron beam of 2 kV for Comparative Example 1 and Conventional Example and the emission intensity distribution of SiC by CL analysis with the acceleration voltage of the electron beam of 5 kV for Conventional Example are not shown. Peaks (mountains) of interband transition emission (band-edge emission) were observed near the wavelength of 390 nm in all these emission intensity distributions of SiC.

[0077] In addition, in the light intensity distributions of SiC in the examples, Comparative Example 1, Comparative Example 2, and the conventional example, a peak of emission broader than the band-edge emission was observed on the longer-wavelength side than the peak of the band-edge emission. The weaker the emission intensity I1 of the band-edge emission of SiC, the more defects (defects that become non-emitting centers) there are. Therefore, the magnitude of the process damage can be confirmed from the emission intensity I1 of the band-edge emission of SiC. The broad emission on the longer-wavelength side of SiC is emission caused by point defects generated in the n - type epitaxial layer. The broad emission on the longer-wavelength side of SiC will be verified in Experimental Example 2 described later.

[0078] In each of the examples, Comparative Example 1, Comparative Example 2, and the conventional example, the emission intensity I1 of the band-edge emission (free exciton emission near the observed wavelength of 390 nm) of SiC was calculated from the light intensity distribution of SiC by CL analysis with the acceleration voltage of the electron beam set to 2 kV and 5 kV. The method for calculating the emission intensity I1 of the band-edge emission of SiC will be described with reference to, for example, FIG. 5. To the light intensity distribution of SiC, an auxiliary line L1 connecting the valleys (the downward-convex vertex parts under the left and right ends of one wavelength) of the band-edge emission A1 of SiC and a vertical auxiliary line L2 passing through the vertex of the peak of the band-edge emission A1 of SiC (the upward-convex vertex indicating the maximum intensity of one wavelength) are added.

[0079] The amplitude from the intersection of these auxiliary lines L1 and L2 to the vertex of the peak of the band-edge emission A1 of SiC is the emission intensity I1 of the band-edge emission A1 of SiC. For example, the emission intensity I1 of the band-edge emission A1 of SiC by CL analysis with the acceleration voltage of the electron beam of Comparative Example 1 shown in FIG. 5 set to 5 kV is about 29. The emission intensity I1 of the band-edge emission B1 of SiC by CL analysis with the acceleration voltage of the electron beam of Comparative Example 2 shown in FIG. 6 set to 5 kV is about 6. The emission intensity I1 of the band-edge emission C1 of SiC by CL analysis with the acceleration voltage of the electron beam of the conventional example shown in FIG. 7 set to 5 kV is about 11.

[0080] The ratios of the emission intensities I1 of the band-edge emission of SiC in Example, Comparative Example 2, and the conventional example to the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1 were calculated respectively. The band-edge emission intensity ratios of SiC by CL analysis with an acceleration voltage of the electron beam of 2 kV in Example, Comparative Example 1, Comparative Example 2, and the conventional example are shown in FIG. 4. Comparative Example 1 is an n - -type epitaxial layer was only epitaxially grown on the m-plane substrate without any process being performed. Therefore, the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1 is the value when there is no process damage.

[0081] The band-edge emission intensity ratio of SiC in the example is obtained by dividing the emission intensity I1 of the band-edge emission D1 of SiC in the example by the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1. The band-edge emission intensity ratio of SiC in Comparative Example 2 is obtained by dividing the emission intensity I1 of the band-edge emission B11 of SiC in Comparative Example 2 by the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1. The band-edge emission intensity ratio of SiC in the conventional example is obtained by dividing the emission intensity I1 of the band-edge emission of SiC in the conventional example by the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1.

[0082] From the results shown in FIG. 4, in Comparative Example 2, the emission intensity I1 of the band-edge emission B11 of SiC is about 1 / 5 times the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1, and it is confirmed that the emission intensity I1 of the band-edge emission B11 of SiC is weaker than that in Comparative Example 1. In Comparative Example 2, etching damage (process damage) occurred on the SiC surface (the main surface on the n - -type epitaxial layer side of the epitaxial substrate), and it can be seen that the number of defects (defects that become non-emission centers) has increased compared to before dry etching (corresponding to Comparative Example 1).

[0083] Also, from the results shown in FIG. 4, in the conventional example, the emission intensity I1 of the band-edge emission of SiC is about 2 / 5 times that of the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1, and it was confirmed that the emission intensity I1 of the band-edge emission of SiC is slightly stronger than that in Comparative Example 2. In the conventional example, it can be seen that the damage (defects serving as non-emitting centers) on the SiC surface due to dry etching is recovered by sacrificial oxidation, but the recovery amount is small.

[0084] On the other hand, from the results shown in FIG. 4, in the example, it was confirmed that the emission intensity I1 of the band-edge emission D1 of SiC is about 1.35 times that of the emission intensity I1 of the band-edge emission of SiC in Comparative Example 1. It can be seen that the damage on the SiC surface can be reduced by the processes of Steps S4 and S5 compared to the case where dry etching is not performed (Comparative Example 1). Also, in the example, it was confirmed that the emission intensity I1 of the band-edge emission of SiC is stronger than that in Comparative Example 2 and the conventional example. It can be seen that the damage on the SiC surface can be recovered by the processes of Steps S4 and S5 compared to after dry etching (Comparative Example 2) and the conventional method (sacrificial oxidation).

[0085] FIG. 4 shows the CL analysis results with the acceleration voltage of the electron beam set to 2 kV. The CL analysis results with the acceleration voltage of the electron beam set to 5 kV are not shown, but results showing the same tendency as in FIG. 4 are obtained in the CL analysis with the acceleration voltage of the electron beam set to 5 kV.

[0086] Also, the emission intensity I1 of the band-edge emission B11 of SiC by the CL analysis with the acceleration voltage of the electron beam in Comparative Example 2 shown in FIG. 8 each set to 2 kV is confirmed to be much weaker than the emission intensity I1 of the band-edge emission B1 of SiC by the CL analysis with the acceleration voltage of the electron beam in Comparative Example 2 shown in FIG. 6 each set to 5 kV. Although the symbol I1 for the emission intensity is not shown in FIG. 8, the emission intensity I1 is calculated in the same manner as the band-edge emissions A1, B1, C1, D1 of SiC in FIGS. 5 to 7 and 9.

[0087] When the acceleration voltage of the electron beam is 2 kV, the relatively shallow part from the SiC surface is analyzed compared to the case where the acceleration voltage of the electron beam is 5 kV. From the results shown in FIGS. 6 and 8, it was confirmed that the damage due to dry etching is concentrated in the relatively shallow part near the SiC surface. Therefore, it can be seen that if the damage in the relatively shallow part near the SiC surface is recovered, the electrical characteristics of the SiC-MOSFET can be improved.

[0088] The emission intensity I1 of the band-edge emission D1 of SiC by CL analysis with the acceleration voltage of the electron beam of 2 kV in the embodiment shown in FIG. 9 is clearly stronger than the emission intensity I1 of the band-edge emission B11 of SiC by CL analysis with the acceleration voltage of the electron beam of 2 kV in Comparative Example 2 shown in FIG. 8. Therefore, it can be seen that the damage in the relatively shallow part near the SiC surface due to dry etching can be significantly recovered by the processes of steps S4 and S5.

[0089] Therefore, by performing the processes of steps S4 and S5 on the SiC surface (the main surface on the n-type epitaxial layer side of the epitaxial substrate) as in the embodiment, the gate insulating film 7 can be formed on the semiconductor substrate 30 (the inner wall surface of the trench 6) without leaving damage at the interface between the semiconductor substrate 30 and the gate insulating film 7 (SiC / SiO2 interface 20: see FIG. 1). - The broad emission valley on the long-wavelength side of the emission intensity distribution of SiC (the vertex part convex downward under the right end of one wavelength: reference numerals A3, B3, C3, B13, D3 in FIGS. 5 to 9) is a periodic intensity change and is due to the analyzer.

[0090] (Experimental Example 2)

[0091] (Experimental Example 2) Verification was performed on the broad emission on the long-wavelength side of the emission intensity distribution of SiC. The broad emission on the long-wavelength side of SiC (corresponding to symbols A2, B2, C2, B12, D2 in FIGS. 5 to 9) occurs on the long-wavelength side of the peak of the band-edge emission (observation wavelength around 390 nm, corresponding to symbols A1, B1, C1, B11, D1 in FIGS. 5 to 9) in the emission intensity distribution of SiC, and is a peak broader than the band-edge emission D1. The broad emission on the long-wavelength side is not the emission caused by the etching damage due to dry etching, but is the emission caused by point defects in the n - emission caused by point defects in the type epitaxial layer.

[0092] The stronger the emission intensity I2 of the broad emission on the long-wavelength side (see FIGS. 5 to 9), the more - point defects exist in the n-type epitaxial layer. If the emission intensity I2 of the broad emission on the long-wavelength side becomes weaker, the number of point defects in the n - type epitaxial layer decreases, leading to an improvement in the quality of the device. The emission intensity I2 of the broad emission on the long-wavelength side of SiC is the amplitude from the emission intensity = 0 to the peak of the broad emission on the long-wavelength side of SiC (the convex peak indicating the maximum intensity at one wavelength).

[0093] Therefore, it is preferable that the emission intensity I1 of the band-edge emission of SiC is strong and the emission intensity I2 of the broad emission on the long-wavelength side is weak. For example, if the ratio of the emission intensity I2 of the broad emission on the long-wavelength side to the emission intensity I1 of the band-edge emission of SiC (emission intensity ratio = emission intensity I2 of the broad emission on the long-wavelength side / emission intensity I1 of the band-edge emission) is small, the process damage due to dry etching or the like is small, and there are few point defects in the n - type epitaxial layer. The emission intensity ratios of the broad emission on the long-wavelength side of SiC in Comparative Example 1, Comparative Example 2, the conventional example, and the example are shown in FIG. 10.

[0094] FIG. 10 is a chart showing the emission intensity ratio of the broad emission on the long wavelength side of SiC in the examples. FIG. 10 also shows the emission intensity ratios of the broad emission on the long wavelength side of SiC in Comparative Example 1, Comparative Example 2, and the conventional example. In FIG. 10, the emission intensity ratios of the broad emission on the long wavelength side of SiC by CL analysis with the acceleration voltage of the electron beam being 2 kV for Comparative Example 2 and the examples refer to FIGS. 8 and 9, respectively. The emission intensity ratios of the broad emission on the long wavelength side of SiC by CL analysis with the acceleration voltage of the electron beam being 5 kV for Comparative Example 1, Comparative Example 2, and the conventional example refer to FIGS. 5 to 7, respectively.

[0095] From the results shown in FIG. 10, it was confirmed that in the above-described examples, the emission intensity ratio of the broad emission on the long wavelength side of SiC is smaller than that in the above-described Comparative Example 1, Comparative Example 2, and the conventional example. Therefore, by performing the processes of Steps S4 and S5 on the SiC surface (the main surface on the n-type epitaxial layer side of the epitaxial substrate) as in the examples, it is possible to reduce the etching damage caused by dry etching and to reduce the point defects in the n-type epitaxial layer. - type epitaxial layer side of the main surface), it is possible to reduce the etching damage caused by dry etching and to reduce the point defects in the n - type epitaxial layer.

[0096] For example, the emission intensity ratio of the broad emission on the long wavelength side of the conventional example SiC was about 35 in a relatively shallow portion near the SiC surface (when the acceleration voltage of the electron beam for CL analysis was 2 kV), and about 9.1 in a deep portion from the SiC surface (when the acceleration voltage of the electron beam for CL analysis was 5 kV). On the other hand, in the examples, the emission intensity ratio of the broad emission on the long wavelength side of SiC was about 17 in a relatively shallow portion near the SiC surface and about 7.5 in a deep portion from the SiC surface, and it was confirmed that it can be made smaller than the emission intensity ratio of the broad emission on the long wavelength side of the conventional example SiC. That is, in the present embodiment, it was confirmed that the emission intensity ratio of the broad emission on the long wavelength side of SiC can be made less than about 35 in a relatively shallow portion near the SiC surface and about 9 or less in a deep portion from the SiC surface.

[0097] Also, as described above, the higher the acceleration voltage of the electron beam in CL analysis, the more the emission intensity distribution including information from deep parts from the SiC surface can be obtained. The etching damage due to dry etching is large in a relatively shallow part near the SiC surface and becomes smaller as the depth from the SiC surface increases (see FIGS. 6 and 8). When removing the damage on the SiC surface by sacrificial oxidation as in the conventional example, damage occurs from the SiC surface to deep parts (see FIG. 7). Also, the SiC surface is oxidized during sacrificial oxidation. Also, in sacrificial oxidation, the dangling bonds on the SiC surface are not nitrogen-terminated. For this reason, in the conventional example, the amount of recovery of the damage on the SiC surface is small. On the other hand, in the example, it was confirmed that no damage occurred in deep parts from the SiC surface.

[0098] (Experimental Example 3) The channel mobility and gate threshold voltage of the silicon carbide semiconductor device 10 according to the embodiment were verified. FIG. 11 is a chart showing the electrical characteristics (channel mobility and gate threshold voltage) of the example. FIG. 11 also shows the electrical characteristics of Comparative Example 2 and the conventional example. According to the manufacturing method of the silicon carbide semiconductor device 10 according to the above-described embodiment (see FIG. 3), and under the conditions of the above-described example, trench etching in step S3, first NO annealing in step S4, and wet etching in step S5 were performed to fabricate a trench gate type SiC-MOSFET (hereinafter referred to as an example).

[0099] Also, in the manufacturing method of the silicon carbide semiconductor device 10 according to the above-described embodiment, the processes of step S4 and step S5 were omitted (that is, only step S3 was performed under the conditions of Comparative Example 2 described above) to fabricate a trench gate type SiC-MOSFET (hereinafter referred to as Comparative Example 2). Instead of the processes of step S4 and step S5, sacrificial oxidation and removal of the oxide layer by sacrificial oxidation were performed (that is, damage recovery under the conditions of the conventional example described above) to fabricate a trench gate type SiC-MOSFET (hereinafter referred to as the conventional example).

[0100] The results of measuring the channel mobility and gate threshold voltage of Comparative Example 2, the conventional example, and the examples are shown in FIG. 11. From the results shown in FIG. 11, it was confirmed that the examples can achieve a higher channel mobility compared to Comparative Example 2 and the conventional example. For example, the examples can achieve a channel mobility that is about 22% higher than that of the conventional example. Also, it was confirmed that the more damage remains near the SiC surface (see FIG. 4), the lower the channel mobility becomes.

[0101] Therefore, it was confirmed that the etching damage 30a on the inner wall surface of the trench 6 has an adverse effect on the electrical characteristics of the SiC-MOSFET. Also, as in the examples, it was confirmed that the electrical characteristics of the SiC-MOSFET can be improved by controlling and recovering the etching damage 30a on the inner wall surface of the trench 6 generated by the trench etching in Step S3 within an appropriate range.

[0102] In the above-described Experimental Examples 1 and 2, CL analysis is performed by irradiating the main surface (m-plane) of the epitaxial substrate with an electron beam. However, the present invention is not limited to this, and it is also possible to perform CL analysis by irradiating the side wall of a trench that reaches a predetermined depth from the main surface of the epitaxial substrate with an electron beam.

[0103] As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can be applied to a vertical IGBT (Insulated Gate Bipolar Transistor) or a vertical SJ-MOSFET that can adopt a trench gate structure instead of a vertical MOSFET. An SJ-MOSFET is a MOSFET having a super junction (SJ: Super Junction) structure in which a drift layer is a parallel pn layer in which an n-type region and a p-type region with increased impurity concentration are alternately and repeatedly adjacent to each other in a direction parallel to the front surface of the semiconductor substrate.

Industrial Applicability

[0104] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power supply devices such as power conversion devices and various industrial machines.

Explanation of symbols

[0105] 1 n + n-type drain region 2 n - n-type drift region 3 p-type base region 4 n + n-type source region 5 p ++ p-type contact region 6 trench 7 gate insulating film (HTO film) 8 gate electrode 9 interlayer insulating film 10 silicon carbide semiconductor device 11 source electrode 12 drain electrode 20 bonding interface between the inner wall of the trench and the gate insulating film (SiC / SiO2 interface) 21,22 p + p-type region 23 n-type current diffusion region 30 semiconductor substrate 30a etching damage 31 n + n-type starting substrate 32 n - n-type epitaxial layer 33 p-type epitaxial layer

Claims

1. A silicon carbide semiconductor device including an insulated gate having a three-layer structure of gate - oxide film - semiconductor, a semiconductor substrate made of silicon carbide that constitutes the semiconductor, a trench having a predetermined depth extending in the depth direction from the first main surface of the semiconductor substrate, a gate insulating film that constitutes the oxide film and is provided along the inner wall of the trench and contacts the semiconductor substrate at the inner wall of the trench, a gate electrode that constitutes the gate and is provided on the gate insulating film inside the trench, comprising, a trench gate structure in which a channel is formed along the side wall of the trench of the semiconductor substrate during on - state, A silicon carbide semiconductor device characterized in that the emission intensity of the band - edge emission of silicon carbide in the surface region of the inner wall of the trench obtained by using the cathode luminescence method is equal to or greater than the emission intensity of the band - edge emission of silicon carbide in the surface region of the non - dry - etched surface of the semiconductor substrate obtained by using the cathode luminescence method.

2. In the emission intensity distribution of silicon carbide in the surface region of the inner wall of the trench obtained by using the cathode luminescence method, the ratio of the emission intensity of emission broader than the band - edge emission, which occurs on the longer - wavelength side than the peak of the band - edge emission, to the emission intensity of the band - edge emission is less than 35 when the acceleration voltage of the electrons irradiated on the inner wall of the trench during analysis by the cathode luminescence method is 2 kV, or less than 9 when the acceleration voltage of the electrons irradiated on the inner wall of the trench during analysis by the cathode luminescence method is 5 kV, or satisfies both of them. The silicon carbide semiconductor device according to claim 1.

3. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that the emission intensity of the band - edge emission of silicon carbide on the surface of the inner wall of the trench obtained by using the cathode luminescence method is equal to or greater than the emission intensity of the band - edge emission of silicon carbide on the non - dry - etched surface of the semiconductor substrate obtained by using the cathode luminescence method.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that the band - edge emission of silicon carbide is free exciton emission observed near a wavelength of 390 nm.

5. A method for manufacturing a silicon carbide semiconductor device including an insulated gate having a three - layer structure of gate - oxide film - semiconductor, A first step of forming a trench having a predetermined depth extending in the depth direction from the first main surface of a semiconductor substrate made of silicon carbide, which constitutes the semiconductor, by dry etching; A second step of performing a first heat treatment in a gas atmosphere containing nitrogen monoxide gas after the first step, and continuously performing a second heat treatment in a nitrogen gas atmosphere following the first heat treatment; A third step of removing an oxide layer formed on the inner wall of the trench in the second step to expose the inner wall of the trench; A fourth step of forming a gate insulating film constituting the oxide film along the inner wall of the trench on the inner wall of the trench after the third step; A fifth step of annealing the gate insulating film by a third heat treatment; A sixth step of forming a gate electrode constituting the gate on the gate insulating film inside the trench after the fifth step, thereby forming a trench gate structure in which a channel is formed in a portion along the side wall of the trench of the semiconductor substrate during on-state; comprising; In the second step, the first heat treatment is performed at a temperature within the range of 1200 °C or higher and 1350 °C or lower, while maintaining the temperature of the first heat treatment, switching to the nitrogen gas atmosphere to perform the second heat treatment, A method for manufacturing a silicon carbide semiconductor device, characterized in that the total time reaching a predetermined maximum temperature during the total treatment time of the first heat treatment and the second heat treatment is 90 minutes or more.

6. In the second step, the first heat treatment is performed within the range of 15 minutes or more and 60 minutes or less, The method for manufacturing a silicon carbide semiconductor device according to claim 5, characterized in that the second heat treatment is performed within the range of 30 minutes or more and 75 minutes or less.

7. In the second step, the first heat treatment is performed using the gas atmosphere in which nitrogen monoxide gas is mixed with nitrogen gas at a ratio of 5% or more and 20% or less, according to the method for manufacturing a silicon carbide semiconductor device according to claim 5 or 6.

8. In the second step, the damage layer generated on the inner wall of the trench in the first step is oxidized by the first heat treatment to form the oxide layer, according to the method for manufacturing a silicon carbide semiconductor device according to any one of claims 5 to 7.

9. In the second step, in the first heat treatment, defects on the inner wall of the trench are terminated with nitrogen contained in nitrogen monoxide gas, according to the method for manufacturing a silicon carbide semiconductor device according to any one of claims 5 to 8.

10. In the second step, in the second heat treatment, the method for manufacturing a silicon carbide semiconductor device according to any one of claims 5 to 9, wherein the disorder of the silicon carbide crystal structure of the semiconductor substrate is repaired.

Images